Merge tag 'for-linus-5.2-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git/hubca...
[linux-2.6-block.git] / drivers / net / ieee802154 / at86rf230.c
CommitLineData
7b8e19b6 1/*
2 * AT86RF230/RF231 driver
3 *
4 * Copyright (C) 2009-2012 Siemens AG
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
7b8e19b6 15 * Written by:
16 * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
17 * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
01ebd60b 18 * Alexander Aring <aar@pengutronix.de>
7b8e19b6 19 */
20#include <linux/kernel.h>
21#include <linux/module.h>
eb3b435e 22#include <linux/hrtimer.h>
dce481e6 23#include <linux/jiffies.h>
7b8e19b6 24#include <linux/interrupt.h>
4af619ae 25#include <linux/irq.h>
7b8e19b6 26#include <linux/gpio.h>
27#include <linux/delay.h>
7b8e19b6 28#include <linux/spi/spi.h>
29#include <linux/spi/at86rf230.h>
f76014f7 30#include <linux/regmap.h>
7b8e19b6 31#include <linux/skbuff.h>
fa2d3e94 32#include <linux/of_gpio.h>
4ca24aca 33#include <linux/ieee802154.h>
493bc90a 34#include <linux/debugfs.h>
7b8e19b6 35
36#include <net/mac802154.h>
5ad60d36 37#include <net/cfg802154.h>
7b8e19b6 38
7490b008
AA
39#include "at86rf230.h"
40
a53d1f7c
AA
41struct at86rf230_local;
42/* at86rf2xx chip depend data.
43 * All timings are in us.
44 */
45struct at86rf2xx_chip_data {
7a4ef918 46 u16 t_sleep_cycle;
984e0c68 47 u16 t_channel_switch;
09e536cd 48 u16 t_reset_to_off;
2e0571c0
AA
49 u16 t_off_to_aack;
50 u16 t_off_to_tx_on;
e6f7ed9d
AA
51 u16 t_off_to_sleep;
52 u16 t_sleep_to_off;
1d15d6b5
AA
53 u16 t_frame;
54 u16 t_p_ack;
a53d1f7c
AA
55 int rssi_base_val;
56
e37d2ec8 57 int (*set_channel)(struct at86rf230_local *, u8, u8);
6f4da3f8 58 int (*set_txpower)(struct at86rf230_local *, s32);
a53d1f7c
AA
59};
60
ba6d2239
AA
61#define AT86RF2XX_MAX_BUF (127 + 3)
62/* tx retries to access the TX_ON state
63 * if it's above then force change will be started.
64 *
65 * We assume the max_frame_retries (7) value of 802.15.4 here.
66 */
67#define AT86RF2XX_MAX_TX_RETRIES 7
dce481e6
AA
68/* We use the recommended 5 minutes timeout to recalibrate */
69#define AT86RF2XX_CAL_LOOP_TIMEOUT (5 * 60 * HZ)
7b8e19b6 70
1d15d6b5
AA
71struct at86rf230_state_change {
72 struct at86rf230_local *lp;
cca990c8 73 int irq;
7b8e19b6 74
eb3b435e 75 struct hrtimer timer;
1d15d6b5
AA
76 struct spi_message msg;
77 struct spi_transfer trx;
78 u8 buf[AT86RF2XX_MAX_BUF];
79
80 void (*complete)(void *context);
81 u8 from_state;
82 u8 to_state;
97fed795 83
57c1bc7e 84 bool free;
1d15d6b5
AA
85};
86
493bc90a
AA
87struct at86rf230_trac {
88 u64 success;
89 u64 success_data_pending;
90 u64 success_wait_for_ack;
91 u64 channel_access_failure;
92 u64 no_ack;
93 u64 invalid;
94};
95
1d15d6b5
AA
96struct at86rf230_local {
97 struct spi_device *spi;
7b8e19b6 98
5a504397 99 struct ieee802154_hw *hw;
1d15d6b5 100 struct at86rf2xx_chip_data *data;
f76014f7 101 struct regmap *regmap;
d2c8bf51 102 int slp_tr;
cbe62346 103 bool sleep;
7b8e19b6 104
2e0571c0
AA
105 struct completion state_complete;
106 struct at86rf230_state_change state;
107
dce481e6 108 unsigned long cal_timeout;
1d15d6b5 109 bool is_tx;
85009203 110 bool is_tx_from_off;
ba6d2239 111 u8 tx_retry;
1d15d6b5
AA
112 struct sk_buff *tx_skb;
113 struct at86rf230_state_change tx;
493bc90a
AA
114
115 struct at86rf230_trac trac;
7b8e19b6 116};
117
f76014f7
AA
118#define AT86RF2XX_NUMREGS 0x3F
119
97fed795 120static void
1d15d6b5
AA
121at86rf230_async_state_change(struct at86rf230_local *lp,
122 struct at86rf230_state_change *ctx,
57c1bc7e 123 const u8 state, void (*complete)(void *context));
1d15d6b5 124
cbe62346
AA
125static inline void
126at86rf230_sleep(struct at86rf230_local *lp)
127{
128 if (gpio_is_valid(lp->slp_tr)) {
129 gpio_set_value(lp->slp_tr, 1);
130 usleep_range(lp->data->t_off_to_sleep,
131 lp->data->t_off_to_sleep + 10);
132 lp->sleep = true;
133 }
134}
135
136static inline void
137at86rf230_awake(struct at86rf230_local *lp)
138{
139 if (gpio_is_valid(lp->slp_tr)) {
140 gpio_set_value(lp->slp_tr, 0);
141 usleep_range(lp->data->t_sleep_to_off,
142 lp->data->t_sleep_to_off + 100);
143 lp->sleep = false;
144 }
145}
146
f76014f7
AA
147static inline int
148__at86rf230_write(struct at86rf230_local *lp,
149 unsigned int addr, unsigned int data)
150{
cbe62346
AA
151 bool sleep = lp->sleep;
152 int ret;
153
154 /* awake for register setting if sleep */
155 if (sleep)
156 at86rf230_awake(lp);
157
158 ret = regmap_write(lp->regmap, addr, data);
159
160 /* sleep again if was sleeping */
161 if (sleep)
162 at86rf230_sleep(lp);
163
164 return ret;
f76014f7
AA
165}
166
167static inline int
168__at86rf230_read(struct at86rf230_local *lp,
169 unsigned int addr, unsigned int *data)
170{
cbe62346
AA
171 bool sleep = lp->sleep;
172 int ret;
173
174 /* awake for register setting if sleep */
175 if (sleep)
176 at86rf230_awake(lp);
177
178 ret = regmap_read(lp->regmap, addr, data);
179
180 /* sleep again if was sleeping */
181 if (sleep)
182 at86rf230_sleep(lp);
183
184 return ret;
f76014f7
AA
185}
186
187static inline int
188at86rf230_read_subreg(struct at86rf230_local *lp,
189 unsigned int addr, unsigned int mask,
190 unsigned int shift, unsigned int *data)
191{
192 int rc;
193
194 rc = __at86rf230_read(lp, addr, data);
d907c4f0 195 if (!rc)
f76014f7
AA
196 *data = (*data & mask) >> shift;
197
198 return rc;
199}
200
201static inline int
202at86rf230_write_subreg(struct at86rf230_local *lp,
203 unsigned int addr, unsigned int mask,
204 unsigned int shift, unsigned int data)
205{
cbe62346
AA
206 bool sleep = lp->sleep;
207 int ret;
208
209 /* awake for register setting if sleep */
210 if (sleep)
211 at86rf230_awake(lp);
212
213 ret = regmap_update_bits(lp->regmap, addr, mask, data << shift);
214
215 /* sleep again if was sleeping */
216 if (sleep)
217 at86rf230_sleep(lp);
218
219 return ret;
f76014f7
AA
220}
221
d2c8bf51
AA
222static inline void
223at86rf230_slp_tr_rising_edge(struct at86rf230_local *lp)
224{
225 gpio_set_value(lp->slp_tr, 1);
226 udelay(1);
227 gpio_set_value(lp->slp_tr, 0);
228}
229
f76014f7
AA
230static bool
231at86rf230_reg_writeable(struct device *dev, unsigned int reg)
232{
233 switch (reg) {
234 case RG_TRX_STATE:
235 case RG_TRX_CTRL_0:
236 case RG_TRX_CTRL_1:
237 case RG_PHY_TX_PWR:
238 case RG_PHY_ED_LEVEL:
239 case RG_PHY_CC_CCA:
240 case RG_CCA_THRES:
241 case RG_RX_CTRL:
242 case RG_SFD_VALUE:
243 case RG_TRX_CTRL_2:
244 case RG_ANT_DIV:
245 case RG_IRQ_MASK:
246 case RG_VREG_CTRL:
247 case RG_BATMON:
248 case RG_XOSC_CTRL:
249 case RG_RX_SYN:
250 case RG_XAH_CTRL_1:
251 case RG_FTN_CTRL:
252 case RG_PLL_CF:
253 case RG_PLL_DCU:
254 case RG_SHORT_ADDR_0:
255 case RG_SHORT_ADDR_1:
256 case RG_PAN_ID_0:
257 case RG_PAN_ID_1:
258 case RG_IEEE_ADDR_0:
259 case RG_IEEE_ADDR_1:
260 case RG_IEEE_ADDR_2:
261 case RG_IEEE_ADDR_3:
262 case RG_IEEE_ADDR_4:
263 case RG_IEEE_ADDR_5:
264 case RG_IEEE_ADDR_6:
265 case RG_IEEE_ADDR_7:
266 case RG_XAH_CTRL_0:
267 case RG_CSMA_SEED_0:
268 case RG_CSMA_SEED_1:
269 case RG_CSMA_BE:
270 return true;
271 default:
272 return false;
273 }
274}
275
276static bool
277at86rf230_reg_readable(struct device *dev, unsigned int reg)
278{
279 bool rc;
280
281 /* all writeable are also readable */
282 rc = at86rf230_reg_writeable(dev, reg);
283 if (rc)
284 return rc;
285
286 /* readonly regs */
287 switch (reg) {
288 case RG_TRX_STATUS:
289 case RG_PHY_RSSI:
290 case RG_IRQ_STATUS:
291 case RG_PART_NUM:
292 case RG_VERSION_NUM:
293 case RG_MAN_ID_1:
294 case RG_MAN_ID_0:
295 return true;
296 default:
297 return false;
298 }
299}
300
301static bool
302at86rf230_reg_volatile(struct device *dev, unsigned int reg)
303{
304 /* can be changed during runtime */
305 switch (reg) {
306 case RG_TRX_STATUS:
307 case RG_TRX_STATE:
308 case RG_PHY_RSSI:
309 case RG_PHY_ED_LEVEL:
310 case RG_IRQ_STATUS:
311 case RG_VREG_CTRL:
51b3b2cf
AA
312 case RG_PLL_CF:
313 case RG_PLL_DCU:
f76014f7
AA
314 return true;
315 default:
316 return false;
317 }
318}
319
320static bool
321at86rf230_reg_precious(struct device *dev, unsigned int reg)
322{
323 /* don't clear irq line on read */
324 switch (reg) {
325 case RG_IRQ_STATUS:
326 return true;
327 default:
328 return false;
329 }
330}
331
889ee2c7 332static const struct regmap_config at86rf230_regmap_spi_config = {
f76014f7
AA
333 .reg_bits = 8,
334 .val_bits = 8,
335 .write_flag_mask = CMD_REG | CMD_WRITE,
336 .read_flag_mask = CMD_REG,
337 .cache_type = REGCACHE_RBTREE,
338 .max_register = AT86RF2XX_NUMREGS,
339 .writeable_reg = at86rf230_reg_writeable,
340 .readable_reg = at86rf230_reg_readable,
341 .volatile_reg = at86rf230_reg_volatile,
342 .precious_reg = at86rf230_reg_precious,
343};
344
1d15d6b5 345static void
c231c5a4 346at86rf230_async_error_recover_complete(void *context)
1d15d6b5
AA
347{
348 struct at86rf230_state_change *ctx = context;
349 struct at86rf230_local *lp = ctx->lp;
350
57c1bc7e
AA
351 if (ctx->free)
352 kfree(ctx);
c231c5a4
AA
353
354 ieee802154_wake_queue(lp->hw);
355}
356
357static void
358at86rf230_async_error_recover(void *context)
359{
360 struct at86rf230_state_change *ctx = context;
361 struct at86rf230_local *lp = ctx->lp;
362
363 lp->is_tx = 0;
364 at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON,
365 at86rf230_async_error_recover_complete);
1d15d6b5
AA
366}
367
fc50c6e3 368static inline void
1d15d6b5
AA
369at86rf230_async_error(struct at86rf230_local *lp,
370 struct at86rf230_state_change *ctx, int rc)
371{
372 dev_err(&lp->spi->dev, "spi_async error %d\n", rc);
373
374 at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF,
57c1bc7e 375 at86rf230_async_error_recover);
1d15d6b5
AA
376}
377
378/* Generic function to get some register value in async mode */
97fed795 379static void
57c1bc7e 380at86rf230_async_read_reg(struct at86rf230_local *lp, u8 reg,
1d15d6b5 381 struct at86rf230_state_change *ctx,
57c1bc7e 382 void (*complete)(void *context))
7b8e19b6 383{
97fed795
AA
384 int rc;
385
1d15d6b5
AA
386 u8 *tx_buf = ctx->buf;
387
388 tx_buf[0] = (reg & CMD_REG_MASK) | CMD_REG;
1d15d6b5 389 ctx->msg.complete = complete;
97fed795 390 rc = spi_async(lp->spi, &ctx->msg);
57c1bc7e
AA
391 if (rc)
392 at86rf230_async_error(lp, ctx, rc);
393}
97fed795 394
57c1bc7e
AA
395static void
396at86rf230_async_write_reg(struct at86rf230_local *lp, u8 reg, u8 val,
397 struct at86rf230_state_change *ctx,
398 void (*complete)(void *context))
399{
400 int rc;
401
402 ctx->buf[0] = (reg & CMD_REG_MASK) | CMD_REG | CMD_WRITE;
403 ctx->buf[1] = val;
404 ctx->msg.complete = complete;
405 rc = spi_async(lp->spi, &ctx->msg);
406 if (rc)
97fed795 407 at86rf230_async_error(lp, ctx, rc);
1d15d6b5
AA
408}
409
410static void
411at86rf230_async_state_assert(void *context)
412{
413 struct at86rf230_state_change *ctx = context;
414 struct at86rf230_local *lp = ctx->lp;
415 const u8 *buf = ctx->buf;
4748e86e 416 const u8 trx_state = buf[1] & TRX_STATE_MASK;
1d15d6b5
AA
417
418 /* Assert state change */
419 if (trx_state != ctx->to_state) {
420 /* Special handling if transceiver state is in
421 * STATE_BUSY_RX_AACK and a SHR was detected.
422 */
423 if (trx_state == STATE_BUSY_RX_AACK) {
424 /* Undocumented race condition. If we send a state
425 * change to STATE_RX_AACK_ON the transceiver could
426 * change his state automatically to STATE_BUSY_RX_AACK
427 * if a SHR was detected. This is not an error, but we
428 * can't assert this.
429 */
430 if (ctx->to_state == STATE_RX_AACK_ON)
431 goto done;
432
433 /* If we change to STATE_TX_ON without forcing and
434 * transceiver state is STATE_BUSY_RX_AACK, we wait
435 * 'tFrame + tPAck' receiving time. In this time the
436 * PDU should be received. If the transceiver is still
437 * in STATE_BUSY_RX_AACK, we run a force state change
438 * to STATE_TX_ON. This is a timeout handling, if the
439 * transceiver stucks in STATE_BUSY_RX_AACK.
ba6d2239
AA
440 *
441 * Additional we do several retries to try to get into
442 * TX_ON state without forcing. If the retries are
443 * higher or equal than AT86RF2XX_MAX_TX_RETRIES we
444 * will do a force change.
1d15d6b5 445 */
dce481e6
AA
446 if (ctx->to_state == STATE_TX_ON ||
447 ctx->to_state == STATE_TRX_OFF) {
448 u8 state = ctx->to_state;
ba6d2239
AA
449
450 if (lp->tx_retry >= AT86RF2XX_MAX_TX_RETRIES)
ed4a26b0 451 state = STATE_FORCE_TRX_OFF;
ba6d2239
AA
452 lp->tx_retry++;
453
454 at86rf230_async_state_change(lp, ctx, state,
57c1bc7e 455 ctx->complete);
1d15d6b5
AA
456 return;
457 }
458 }
459
1d15d6b5
AA
460 dev_warn(&lp->spi->dev, "unexcept state change from 0x%02x to 0x%02x. Actual state: 0x%02x\n",
461 ctx->from_state, ctx->to_state, trx_state);
462 }
463
464done:
465 if (ctx->complete)
466 ctx->complete(context);
467}
468
eb3b435e
AA
469static enum hrtimer_restart at86rf230_async_state_timer(struct hrtimer *timer)
470{
471 struct at86rf230_state_change *ctx =
472 container_of(timer, struct at86rf230_state_change, timer);
473 struct at86rf230_local *lp = ctx->lp;
474
475 at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
57c1bc7e 476 at86rf230_async_state_assert);
eb3b435e
AA
477
478 return HRTIMER_NORESTART;
479}
480
1d15d6b5
AA
481/* Do state change timing delay. */
482static void
483at86rf230_async_state_delay(void *context)
484{
485 struct at86rf230_state_change *ctx = context;
486 struct at86rf230_local *lp = ctx->lp;
487 struct at86rf2xx_chip_data *c = lp->data;
488 bool force = false;
eb3b435e 489 ktime_t tim;
1d15d6b5
AA
490
491 /* The force state changes are will show as normal states in the
492 * state status subregister. We change the to_state to the
493 * corresponding one and remember if it was a force change, this
494 * differs if we do a state change from STATE_BUSY_RX_AACK.
495 */
496 switch (ctx->to_state) {
497 case STATE_FORCE_TX_ON:
498 ctx->to_state = STATE_TX_ON;
499 force = true;
500 break;
501 case STATE_FORCE_TRX_OFF:
502 ctx->to_state = STATE_TRX_OFF;
503 force = true;
504 break;
505 default:
506 break;
507 }
508
509 switch (ctx->from_state) {
2e0571c0
AA
510 case STATE_TRX_OFF:
511 switch (ctx->to_state) {
512 case STATE_RX_AACK_ON:
8b0e1953 513 tim = c->t_off_to_aack * NSEC_PER_USEC;
2ad33244
AA
514 /* state change from TRX_OFF to RX_AACK_ON to do a
515 * calibration, we need to reset the timeout for the
516 * next one.
517 */
518 lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
2e0571c0 519 goto change;
3b951ca7 520 case STATE_TX_ARET_ON:
2e0571c0 521 case STATE_TX_ON:
8b0e1953 522 tim = c->t_off_to_tx_on * NSEC_PER_USEC;
3b951ca7
AA
523 /* state change from TRX_OFF to TX_ON or ARET_ON to do
524 * a calibration, we need to reset the timeout for the
dce481e6
AA
525 * next one.
526 */
527 lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
2e0571c0
AA
528 goto change;
529 default:
530 break;
531 }
532 break;
1d15d6b5
AA
533 case STATE_BUSY_RX_AACK:
534 switch (ctx->to_state) {
dce481e6 535 case STATE_TRX_OFF:
1d15d6b5
AA
536 case STATE_TX_ON:
537 /* Wait for worst case receiving time if we
538 * didn't make a force change from BUSY_RX_AACK
dce481e6 539 * to TX_ON or TRX_OFF.
1d15d6b5
AA
540 */
541 if (!force) {
8b0e1953 542 tim = (c->t_frame + c->t_p_ack) * NSEC_PER_USEC;
1d15d6b5
AA
543 goto change;
544 }
545 break;
546 default:
547 break;
548 }
549 break;
09e536cd
AA
550 /* Default value, means RESET state */
551 case STATE_P_ON:
552 switch (ctx->to_state) {
553 case STATE_TRX_OFF:
8b0e1953 554 tim = c->t_reset_to_off * NSEC_PER_USEC;
09e536cd
AA
555 goto change;
556 default:
557 break;
558 }
559 break;
1d15d6b5
AA
560 default:
561 break;
562 }
563
564 /* Default delay is 1us in the most cases */
8b44f0dd
AA
565 udelay(1);
566 at86rf230_async_state_timer(&ctx->timer);
567 return;
1d15d6b5
AA
568
569change:
eb3b435e 570 hrtimer_start(&ctx->timer, tim, HRTIMER_MODE_REL);
1d15d6b5
AA
571}
572
573static void
574at86rf230_async_state_change_start(void *context)
575{
576 struct at86rf230_state_change *ctx = context;
577 struct at86rf230_local *lp = ctx->lp;
578 u8 *buf = ctx->buf;
4748e86e 579 const u8 trx_state = buf[1] & TRX_STATE_MASK;
1d15d6b5
AA
580
581 /* Check for "possible" STATE_TRANSITION_IN_PROGRESS */
582 if (trx_state == STATE_TRANSITION_IN_PROGRESS) {
583 udelay(1);
97fed795 584 at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
57c1bc7e 585 at86rf230_async_state_change_start);
1d15d6b5
AA
586 return;
587 }
588
589 /* Check if we already are in the state which we change in */
590 if (trx_state == ctx->to_state) {
591 if (ctx->complete)
592 ctx->complete(context);
593 return;
594 }
595
596 /* Set current state to the context of state change */
597 ctx->from_state = trx_state;
598
599 /* Going into the next step for a state change which do a timing
600 * relevant delay.
601 */
57c1bc7e
AA
602 at86rf230_async_write_reg(lp, RG_TRX_STATE, ctx->to_state, ctx,
603 at86rf230_async_state_delay);
7b8e19b6 604}
605
97fed795 606static void
1d15d6b5
AA
607at86rf230_async_state_change(struct at86rf230_local *lp,
608 struct at86rf230_state_change *ctx,
57c1bc7e 609 const u8 state, void (*complete)(void *context))
7b8e19b6 610{
1d15d6b5
AA
611 /* Initialization for the state change context */
612 ctx->to_state = state;
613 ctx->complete = complete;
97fed795 614 at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
57c1bc7e 615 at86rf230_async_state_change_start);
1d15d6b5 616}
7b8e19b6 617
2e0571c0
AA
618static void
619at86rf230_sync_state_change_complete(void *context)
620{
621 struct at86rf230_state_change *ctx = context;
622 struct at86rf230_local *lp = ctx->lp;
623
624 complete(&lp->state_complete);
625}
626
627/* This function do a sync framework above the async state change.
628 * Some callbacks of the IEEE 802.15.4 driver interface need to be
629 * handled synchronously.
630 */
631static int
632at86rf230_sync_state_change(struct at86rf230_local *lp, unsigned int state)
633{
3e544ef9 634 unsigned long rc;
2e0571c0 635
97fed795 636 at86rf230_async_state_change(lp, &lp->state, state,
57c1bc7e 637 at86rf230_sync_state_change_complete);
2e0571c0
AA
638
639 rc = wait_for_completion_timeout(&lp->state_complete,
640 msecs_to_jiffies(100));
d06c2199
AA
641 if (!rc) {
642 at86rf230_async_error(lp, &lp->state, -ETIMEDOUT);
2e0571c0 643 return -ETIMEDOUT;
d06c2199 644 }
2e0571c0
AA
645
646 return 0;
647}
648
1d15d6b5
AA
649static void
650at86rf230_tx_complete(void *context)
651{
652 struct at86rf230_state_change *ctx = context;
653 struct at86rf230_local *lp = ctx->lp;
654
fc0719e6 655 ieee802154_xmit_complete(lp->hw, lp->tx_skb, false);
57c1bc7e 656 kfree(ctx);
1d15d6b5
AA
657}
658
659static void
660at86rf230_tx_on(void *context)
661{
662 struct at86rf230_state_change *ctx = context;
663 struct at86rf230_local *lp = ctx->lp;
1d15d6b5 664
31fa7434 665 at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON,
57c1bc7e 666 at86rf230_tx_complete);
1d15d6b5
AA
667}
668
1d15d6b5
AA
669static void
670at86rf230_tx_trac_check(void *context)
671{
672 struct at86rf230_state_change *ctx = context;
673 struct at86rf230_local *lp = ctx->lp;
1d15d6b5 674
493bc90a
AA
675 if (IS_ENABLED(CONFIG_IEEE802154_AT86RF230_DEBUGFS)) {
676 u8 trac = TRAC_MASK(ctx->buf[1]);
677
678 switch (trac) {
679 case TRAC_SUCCESS:
680 lp->trac.success++;
681 break;
682 case TRAC_SUCCESS_DATA_PENDING:
683 lp->trac.success_data_pending++;
684 break;
685 case TRAC_CHANNEL_ACCESS_FAILURE:
686 lp->trac.channel_access_failure++;
687 break;
688 case TRAC_NO_ACK:
689 lp->trac.no_ack++;
690 break;
691 case TRAC_INVALID:
692 lp->trac.invalid++;
693 break;
694 default:
695 WARN_ONCE(1, "received tx trac status %d\n", trac);
696 break;
697 }
698 }
699
57c1bc7e 700 at86rf230_async_state_change(lp, ctx, STATE_TX_ON, at86rf230_tx_on);
1d15d6b5
AA
701}
702
703static void
74de4c80 704at86rf230_rx_read_frame_complete(void *context)
1d15d6b5 705{
74de4c80
AA
706 struct at86rf230_state_change *ctx = context;
707 struct at86rf230_local *lp = ctx->lp;
31fa7434 708 const u8 *buf = ctx->buf;
74de4c80
AA
709 struct sk_buff *skb;
710 u8 len, lqi;
1d15d6b5 711
74de4c80
AA
712 len = buf[1];
713 if (!ieee802154_is_valid_psdu_len(len)) {
714 dev_vdbg(&lp->spi->dev, "corrupted frame received\n");
715 len = IEEE802154_MTU;
716 }
717 lqi = buf[2 + len];
718
61a22814 719 skb = dev_alloc_skb(IEEE802154_MTU);
1d15d6b5
AA
720 if (!skb) {
721 dev_vdbg(&lp->spi->dev, "failed to allocate sk_buff\n");
57c1bc7e 722 kfree(ctx);
1d15d6b5
AA
723 return;
724 }
725
59ae1d12 726 skb_put_data(skb, buf + 2, len);
b89c3341 727 ieee802154_rx_irqsafe(lp->hw, skb, lqi);
57c1bc7e 728 kfree(ctx);
1d15d6b5 729}
7b8e19b6 730
97fed795 731static void
493bc90a 732at86rf230_rx_trac_check(void *context)
1d15d6b5 733{
cca990c8
AA
734 struct at86rf230_state_change *ctx = context;
735 struct at86rf230_local *lp = ctx->lp;
31fa7434 736 u8 *buf = ctx->buf;
97fed795
AA
737 int rc;
738
493bc90a
AA
739 if (IS_ENABLED(CONFIG_IEEE802154_AT86RF230_DEBUGFS)) {
740 u8 trac = TRAC_MASK(buf[1]);
741
742 switch (trac) {
743 case TRAC_SUCCESS:
744 lp->trac.success++;
745 break;
746 case TRAC_SUCCESS_WAIT_FOR_ACK:
747 lp->trac.success_wait_for_ack++;
748 break;
749 case TRAC_INVALID:
750 lp->trac.invalid++;
751 break;
752 default:
753 WARN_ONCE(1, "received rx trac status %d\n", trac);
754 break;
755 }
756 }
757
7b8e19b6 758 buf[0] = CMD_FB;
31fa7434
AA
759 ctx->trx.len = AT86RF2XX_MAX_BUF;
760 ctx->msg.complete = at86rf230_rx_read_frame_complete;
761 rc = spi_async(lp->spi, &ctx->msg);
97fed795 762 if (rc) {
263be332 763 ctx->trx.len = 2;
31fa7434 764 at86rf230_async_error(lp, ctx, rc);
97fed795 765 }
1d15d6b5
AA
766}
767
97fed795 768static void
57c1bc7e 769at86rf230_irq_trx_end(void *context)
1d15d6b5 770{
57c1bc7e
AA
771 struct at86rf230_state_change *ctx = context;
772 struct at86rf230_local *lp = ctx->lp;
773
1d15d6b5
AA
774 if (lp->is_tx) {
775 lp->is_tx = 0;
57c1bc7e
AA
776 at86rf230_async_read_reg(lp, RG_TRX_STATE, ctx,
777 at86rf230_tx_trac_check);
1d15d6b5 778 } else {
57c1bc7e
AA
779 at86rf230_async_read_reg(lp, RG_TRX_STATE, ctx,
780 at86rf230_rx_trac_check);
1d15d6b5
AA
781 }
782}
783
784static void
785at86rf230_irq_status(void *context)
786{
787 struct at86rf230_state_change *ctx = context;
788 struct at86rf230_local *lp = ctx->lp;
31fa7434 789 const u8 *buf = ctx->buf;
57c1bc7e
AA
790 u8 irq = buf[1];
791
792 enable_irq(lp->spi->irq);
1d15d6b5
AA
793
794 if (irq & IRQ_TRX_END) {
57c1bc7e 795 at86rf230_irq_trx_end(ctx);
1d15d6b5 796 } else {
1d15d6b5
AA
797 dev_err(&lp->spi->dev, "not supported irq %02x received\n",
798 irq);
57c1bc7e 799 kfree(ctx);
1d15d6b5
AA
800 }
801}
802
57c1bc7e
AA
803static void
804at86rf230_setup_spi_messages(struct at86rf230_local *lp,
805 struct at86rf230_state_change *state)
806{
807 state->lp = lp;
808 state->irq = lp->spi->irq;
809 spi_message_init(&state->msg);
810 state->msg.context = state;
811 state->trx.len = 2;
812 state->trx.tx_buf = state->buf;
813 state->trx.rx_buf = state->buf;
814 spi_message_add_tail(&state->trx, &state->msg);
815 hrtimer_init(&state->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
816 state->timer.function = at86rf230_async_state_timer;
817}
818
1d15d6b5
AA
819static irqreturn_t at86rf230_isr(int irq, void *data)
820{
821 struct at86rf230_local *lp = data;
57c1bc7e 822 struct at86rf230_state_change *ctx;
1d15d6b5
AA
823 int rc;
824
90566363 825 disable_irq_nosync(irq);
1d15d6b5 826
57c1bc7e
AA
827 ctx = kzalloc(sizeof(*ctx), GFP_ATOMIC);
828 if (!ctx) {
829 enable_irq(irq);
830 return IRQ_NONE;
831 }
832
833 at86rf230_setup_spi_messages(lp, ctx);
834 /* tell on error handling to free ctx */
835 ctx->free = true;
836
837 ctx->buf[0] = (RG_IRQ_STATUS & CMD_REG_MASK) | CMD_REG;
1d15d6b5
AA
838 ctx->msg.complete = at86rf230_irq_status;
839 rc = spi_async(lp->spi, &ctx->msg);
840 if (rc) {
841 at86rf230_async_error(lp, ctx, rc);
57c1bc7e 842 enable_irq(irq);
1d15d6b5
AA
843 return IRQ_NONE;
844 }
845
846 return IRQ_HANDLED;
847}
848
849static void
850at86rf230_write_frame_complete(void *context)
851{
852 struct at86rf230_state_change *ctx = context;
853 struct at86rf230_local *lp = ctx->lp;
1d15d6b5 854
1d15d6b5 855 ctx->trx.len = 2;
d2c8bf51 856
57c1bc7e 857 if (gpio_is_valid(lp->slp_tr))
d2c8bf51 858 at86rf230_slp_tr_rising_edge(lp);
57c1bc7e
AA
859 else
860 at86rf230_async_write_reg(lp, RG_TRX_STATE, STATE_BUSY_TX, ctx,
861 NULL);
1d15d6b5
AA
862}
863
864static void
865at86rf230_write_frame(void *context)
866{
867 struct at86rf230_state_change *ctx = context;
868 struct at86rf230_local *lp = ctx->lp;
869 struct sk_buff *skb = lp->tx_skb;
31fa7434 870 u8 *buf = ctx->buf;
1d15d6b5
AA
871 int rc;
872
1d15d6b5 873 lp->is_tx = 1;
1d15d6b5
AA
874
875 buf[0] = CMD_FB | CMD_WRITE;
876 buf[1] = skb->len + 2;
877 memcpy(buf + 2, skb->data, skb->len);
31fa7434
AA
878 ctx->trx.len = skb->len + 2;
879 ctx->msg.complete = at86rf230_write_frame_complete;
880 rc = spi_async(lp->spi, &ctx->msg);
263be332
AA
881 if (rc) {
882 ctx->trx.len = 2;
1d15d6b5 883 at86rf230_async_error(lp, ctx, rc);
263be332 884 }
1d15d6b5
AA
885}
886
887static void
888at86rf230_xmit_tx_on(void *context)
889{
890 struct at86rf230_state_change *ctx = context;
891 struct at86rf230_local *lp = ctx->lp;
7b8e19b6 892
97fed795 893 at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON,
57c1bc7e 894 at86rf230_write_frame);
1d15d6b5
AA
895}
896
dce481e6
AA
897static void
898at86rf230_xmit_start(void *context)
1d15d6b5 899{
dce481e6
AA
900 struct at86rf230_state_change *ctx = context;
901 struct at86rf230_local *lp = ctx->lp;
7b8e19b6 902
fc0719e6 903 /* check if we change from off state */
d981b5b5 904 if (lp->is_tx_from_off)
fc0719e6 905 at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON,
57c1bc7e 906 at86rf230_write_frame);
d981b5b5 907 else
dce481e6 908 at86rf230_async_state_change(lp, ctx, STATE_TX_ON,
57c1bc7e 909 at86rf230_xmit_tx_on);
dce481e6
AA
910}
911
912static int
913at86rf230_xmit(struct ieee802154_hw *hw, struct sk_buff *skb)
914{
915 struct at86rf230_local *lp = hw->priv;
916 struct at86rf230_state_change *ctx = &lp->tx;
7b8e19b6 917
dce481e6 918 lp->tx_skb = skb;
ba6d2239 919 lp->tx_retry = 0;
dce481e6
AA
920
921 /* After 5 minutes in PLL and the same frequency we run again the
922 * calibration loops which is recommended by at86rf2xx datasheets.
923 *
924 * The calibration is initiate by a state change from TRX_OFF
925 * to TX_ON, the lp->cal_timeout should be reinit by state_delay
926 * function then to start in the next 5 minutes.
927 */
85009203
AA
928 if (time_is_before_jiffies(lp->cal_timeout)) {
929 lp->is_tx_from_off = true;
dce481e6 930 at86rf230_async_state_change(lp, ctx, STATE_TRX_OFF,
57c1bc7e 931 at86rf230_xmit_start);
85009203 932 } else {
d981b5b5 933 lp->is_tx_from_off = false;
dce481e6 934 at86rf230_xmit_start(ctx);
85009203 935 }
97fed795 936
1d15d6b5 937 return 0;
7b8e19b6 938}
939
940static int
5a504397 941at86rf230_ed(struct ieee802154_hw *hw, u8 *level)
7b8e19b6 942{
20f33045 943 WARN_ON(!level);
7b8e19b6 944 *level = 0xbe;
945 return 0;
946}
947
7b8e19b6 948static int
5a504397 949at86rf230_start(struct ieee802154_hw *hw)
7b8e19b6 950{
e6f7ed9d
AA
951 struct at86rf230_local *lp = hw->priv;
952
493bc90a
AA
953 /* reset trac stats on start */
954 if (IS_ENABLED(CONFIG_IEEE802154_AT86RF230_DEBUGFS))
955 memset(&lp->trac, 0, sizeof(struct at86rf230_trac));
956
cbe62346 957 at86rf230_awake(lp);
e6f7ed9d
AA
958 enable_irq(lp->spi->irq);
959
30811fa6 960 return at86rf230_sync_state_change(lp, STATE_RX_AACK_ON);
7b8e19b6 961}
962
963static void
5a504397 964at86rf230_stop(struct ieee802154_hw *hw)
7b8e19b6 965{
e6f7ed9d 966 struct at86rf230_local *lp = hw->priv;
74ed9d98 967 u8 csma_seed[2];
e6f7ed9d 968
30811fa6 969 at86rf230_sync_state_change(lp, STATE_FORCE_TRX_OFF);
e6f7ed9d
AA
970
971 disable_irq(lp->spi->irq);
74ed9d98
AA
972
973 /* It's recommended to set random new csma_seeds before sleep state.
974 * Makes only sense in the stop callback, not doing this inside of
975 * at86rf230_sleep, this is also used when we don't transmit afterwards
976 * when calling start callback again.
977 */
978 get_random_bytes(csma_seed, ARRAY_SIZE(csma_seed));
979 at86rf230_write_subreg(lp, SR_CSMA_SEED_0, csma_seed[0]);
980 at86rf230_write_subreg(lp, SR_CSMA_SEED_1, csma_seed[1]);
981
cbe62346 982 at86rf230_sleep(lp);
7b8e19b6 983}
984
8fad346f 985static int
e37d2ec8 986at86rf23x_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
8fad346f
PB
987{
988 return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
989}
990
2d9fe7ab 991#define AT86RF2XX_MAX_ED_LEVELS 0xF
4d7101d7
AA
992static const s32 at86rf233_ed_levels[AT86RF2XX_MAX_ED_LEVELS + 1] = {
993 -9400, -9200, -9000, -8800, -8600, -8400, -8200, -8000, -7800, -7600,
994 -7400, -7200, -7000, -6800, -6600, -6400,
995};
996
997static const s32 at86rf231_ed_levels[AT86RF2XX_MAX_ED_LEVELS + 1] = {
2d9fe7ab
AA
998 -9100, -8900, -8700, -8500, -8300, -8100, -7900, -7700, -7500, -7300,
999 -7100, -6900, -6700, -6500, -6300, -6100,
1000};
1001
1002static const s32 at86rf212_ed_levels_100[AT86RF2XX_MAX_ED_LEVELS + 1] = {
1003 -10000, -9800, -9600, -9400, -9200, -9000, -8800, -8600, -8400, -8200,
179655fc 1004 -8000, -7800, -7600, -7400, -7200, -7000,
2d9fe7ab
AA
1005};
1006
1007static const s32 at86rf212_ed_levels_98[AT86RF2XX_MAX_ED_LEVELS + 1] = {
1008 -9800, -9600, -9400, -9200, -9000, -8800, -8600, -8400, -8200, -8000,
179655fc 1009 -7800, -7600, -7400, -7200, -7000, -6800,
2d9fe7ab
AA
1010};
1011
1012static inline int
1013at86rf212_update_cca_ed_level(struct at86rf230_local *lp, int rssi_base_val)
1014{
1015 unsigned int cca_ed_thres;
1016 int rc;
1017
1018 rc = at86rf230_read_subreg(lp, SR_CCA_ED_THRES, &cca_ed_thres);
1019 if (rc < 0)
1020 return rc;
1021
1022 switch (rssi_base_val) {
1023 case -98:
1024 lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_98;
1025 lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_98);
1026 lp->hw->phy->cca_ed_level = at86rf212_ed_levels_98[cca_ed_thres];
1027 break;
1028 case -100:
1029 lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_100;
1030 lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_100);
1031 lp->hw->phy->cca_ed_level = at86rf212_ed_levels_100[cca_ed_thres];
1032 break;
1033 default:
1034 WARN_ON(1);
1035 }
1036
1037 return 0;
1038}
1039
8fad346f 1040static int
e37d2ec8 1041at86rf212_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
8fad346f
PB
1042{
1043 int rc;
1044
1045 if (channel == 0)
1046 rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 0);
1047 else
1048 rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 1);
1049 if (rc < 0)
1050 return rc;
1051
6ca00197 1052 if (page == 0) {
643e53c2 1053 rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 0);
a53d1f7c 1054 lp->data->rssi_base_val = -100;
6ca00197 1055 } else {
643e53c2 1056 rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 1);
a53d1f7c 1057 lp->data->rssi_base_val = -98;
6ca00197 1058 }
643e53c2
PB
1059 if (rc < 0)
1060 return rc;
1061
2d9fe7ab
AA
1062 rc = at86rf212_update_cca_ed_level(lp, lp->data->rssi_base_val);
1063 if (rc < 0)
1064 return rc;
1065
24ccb9f4
AA
1066 /* This sets the symbol_duration according frequency on the 212.
1067 * TODO move this handling while set channel and page in cfg802154.
1068 * We can do that, this timings are according 802.15.4 standard.
1069 * If we do that in cfg802154, this is a more generic calculation.
1070 *
1071 * This should also protected from ifs_timer. Means cancel timer and
1072 * init with a new value. For now, this is okay.
1073 */
1074 if (channel == 0) {
1075 if (page == 0) {
1076 /* SUB:0 and BPSK:0 -> BPSK-20 */
1077 lp->hw->phy->symbol_duration = 50;
1078 } else {
1079 /* SUB:1 and BPSK:0 -> BPSK-40 */
1080 lp->hw->phy->symbol_duration = 25;
1081 }
1082 } else {
1083 if (page == 0)
2d6dde29 1084 /* SUB:0 and BPSK:1 -> OQPSK-100/200/400 */
24ccb9f4
AA
1085 lp->hw->phy->symbol_duration = 40;
1086 else
2d6dde29 1087 /* SUB:1 and BPSK:1 -> OQPSK-250/500/1000 */
24ccb9f4
AA
1088 lp->hw->phy->symbol_duration = 16;
1089 }
1090
1091 lp->hw->phy->lifs_period = IEEE802154_LIFS_PERIOD *
1092 lp->hw->phy->symbol_duration;
1093 lp->hw->phy->sifs_period = IEEE802154_SIFS_PERIOD *
1094 lp->hw->phy->symbol_duration;
1095
8fad346f
PB
1096 return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
1097}
1098
7b8e19b6 1099static int
e37d2ec8 1100at86rf230_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
7b8e19b6 1101{
5a504397 1102 struct at86rf230_local *lp = hw->priv;
7b8e19b6 1103 int rc;
1104
a53d1f7c 1105 rc = lp->data->set_channel(lp, page, channel);
984e0c68
AA
1106 /* Wait for PLL */
1107 usleep_range(lp->data->t_channel_switch,
1108 lp->data->t_channel_switch + 10);
dce481e6
AA
1109
1110 lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
820bd66f 1111 return rc;
7b8e19b6 1112}
1113
1486774d 1114static int
5a504397 1115at86rf230_set_hw_addr_filt(struct ieee802154_hw *hw,
1486774d 1116 struct ieee802154_hw_addr_filt *filt,
1117 unsigned long changed)
1118{
5a504397 1119 struct at86rf230_local *lp = hw->priv;
1486774d 1120
57205c14 1121 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
b70ab2e8
PB
1122 u16 addr = le16_to_cpu(filt->short_addr);
1123
8a81388e 1124 dev_vdbg(&lp->spi->dev, "%s called for saddr\n", __func__);
b70ab2e8
PB
1125 __at86rf230_write(lp, RG_SHORT_ADDR_0, addr);
1126 __at86rf230_write(lp, RG_SHORT_ADDR_1, addr >> 8);
1486774d 1127 }
1128
57205c14 1129 if (changed & IEEE802154_AFILT_PANID_CHANGED) {
b70ab2e8
PB
1130 u16 pan = le16_to_cpu(filt->pan_id);
1131
8a81388e 1132 dev_vdbg(&lp->spi->dev, "%s called for pan id\n", __func__);
b70ab2e8
PB
1133 __at86rf230_write(lp, RG_PAN_ID_0, pan);
1134 __at86rf230_write(lp, RG_PAN_ID_1, pan >> 8);
1486774d 1135 }
1136
57205c14 1137 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
b70ab2e8
PB
1138 u8 i, addr[8];
1139
1140 memcpy(addr, &filt->ieee_addr, 8);
8a81388e 1141 dev_vdbg(&lp->spi->dev, "%s called for IEEE addr\n", __func__);
b70ab2e8
PB
1142 for (i = 0; i < 8; i++)
1143 __at86rf230_write(lp, RG_IEEE_ADDR_0 + i, addr[i]);
1486774d 1144 }
1145
57205c14 1146 if (changed & IEEE802154_AFILT_PANC_CHANGED) {
8a81388e 1147 dev_vdbg(&lp->spi->dev, "%s called for panc change\n", __func__);
1486774d 1148 if (filt->pan_coord)
1149 at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 1);
1150 else
1151 at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 0);
1152 }
1153
1154 return 0;
1155}
1156
6f4da3f8
AA
1157#define AT86RF23X_MAX_TX_POWERS 0xF
1158static const s32 at86rf233_powers[AT86RF23X_MAX_TX_POWERS + 1] = {
1159 400, 370, 340, 300, 250, 200, 100, 0, -100, -200, -300, -400, -600,
1160 -800, -1200, -1700,
1161};
1162
1163static const s32 at86rf231_powers[AT86RF23X_MAX_TX_POWERS + 1] = {
1164 300, 280, 230, 180, 130, 70, 0, -100, -200, -300, -400, -500, -700,
1165 -900, -1200, -1700,
1166};
1167
1168#define AT86RF212_MAX_TX_POWERS 0x1F
1169static const s32 at86rf212_powers[AT86RF212_MAX_TX_POWERS + 1] = {
1170 500, 400, 300, 200, 100, 0, -100, -200, -300, -400, -500, -600, -700,
1171 -800, -900, -1000, -1100, -1200, -1300, -1400, -1500, -1600, -1700,
1172 -1800, -1900, -2000, -2100, -2200, -2300, -2400, -2500, -2600,
1173};
1174
9b2777d6 1175static int
6f4da3f8 1176at86rf23x_set_txpower(struct at86rf230_local *lp, s32 mbm)
9b2777d6 1177{
6f4da3f8 1178 u32 i;
9b2777d6 1179
6f4da3f8
AA
1180 for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
1181 if (lp->hw->phy->supported.tx_powers[i] == mbm)
1182 return at86rf230_write_subreg(lp, SR_TX_PWR_23X, i);
1183 }
1184
1185 return -EINVAL;
1186}
1187
1188static int
1189at86rf212_set_txpower(struct at86rf230_local *lp, s32 mbm)
1190{
1191 u32 i;
1192
1193 for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
1194 if (lp->hw->phy->supported.tx_powers[i] == mbm)
1195 return at86rf230_write_subreg(lp, SR_TX_PWR_212, i);
1196 }
9b2777d6 1197
6f4da3f8
AA
1198 return -EINVAL;
1199}
1200
1201static int
1202at86rf230_set_txpower(struct ieee802154_hw *hw, s32 mbm)
1203{
1204 struct at86rf230_local *lp = hw->priv;
9b2777d6 1205
6f4da3f8 1206 return lp->data->set_txpower(lp, mbm);
9b2777d6
PB
1207}
1208
84dda3c6 1209static int
5a504397 1210at86rf230_set_lbt(struct ieee802154_hw *hw, bool on)
84dda3c6 1211{
5a504397 1212 struct at86rf230_local *lp = hw->priv;
84dda3c6
PB
1213
1214 return at86rf230_write_subreg(lp, SR_CSMA_LBT_MODE, on);
1215}
1216
ba08fea5 1217static int
7fe9a388
AA
1218at86rf230_set_cca_mode(struct ieee802154_hw *hw,
1219 const struct wpan_phy_cca *cca)
ba08fea5 1220{
5a504397 1221 struct at86rf230_local *lp = hw->priv;
7fe9a388 1222 u8 val;
ba08fea5 1223
7fe9a388
AA
1224 /* mapping 802.15.4 to driver spec */
1225 switch (cca->mode) {
1226 case NL802154_CCA_ENERGY:
1227 val = 1;
1228 break;
1229 case NL802154_CCA_CARRIER:
1230 val = 2;
1231 break;
1232 case NL802154_CCA_ENERGY_CARRIER:
1233 switch (cca->opt) {
1234 case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
1235 val = 3;
1236 break;
1237 case NL802154_CCA_OPT_ENERGY_CARRIER_OR:
1238 val = 0;
1239 break;
1240 default:
1241 return -EINVAL;
1242 }
1243 break;
1244 default:
1245 return -EINVAL;
1246 }
1247
1248 return at86rf230_write_subreg(lp, SR_CCA_MODE, val);
ba08fea5
PB
1249}
1250
6ca00197 1251static int
32b23550 1252at86rf230_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
6ca00197 1253{
5a504397 1254 struct at86rf230_local *lp = hw->priv;
2d9fe7ab 1255 u32 i;
6ca00197 1256
2d9fe7ab
AA
1257 for (i = 0; i < hw->phy->supported.cca_ed_levels_size; i++) {
1258 if (hw->phy->supported.cca_ed_levels[i] == mbm)
1259 return at86rf230_write_subreg(lp, SR_CCA_ED_THRES, i);
1260 }
6ca00197 1261
2d9fe7ab 1262 return -EINVAL;
6ca00197
PB
1263}
1264
f2fdd67c 1265static int
5a504397 1266at86rf230_set_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
f2fdd67c
PB
1267 u8 retries)
1268{
5a504397 1269 struct at86rf230_local *lp = hw->priv;
f2fdd67c
PB
1270 int rc;
1271
f2fdd67c
PB
1272 rc = at86rf230_write_subreg(lp, SR_MIN_BE, min_be);
1273 if (rc)
1274 return rc;
1275
1276 rc = at86rf230_write_subreg(lp, SR_MAX_BE, max_be);
1277 if (rc)
1278 return rc;
1279
39d7f320 1280 return at86rf230_write_subreg(lp, SR_MAX_CSMA_RETRIES, retries);
f2fdd67c
PB
1281}
1282
1283static int
5a504397 1284at86rf230_set_frame_retries(struct ieee802154_hw *hw, s8 retries)
f2fdd67c 1285{
5a504397 1286 struct at86rf230_local *lp = hw->priv;
f2fdd67c 1287
fc0719e6 1288 return at86rf230_write_subreg(lp, SR_MAX_FRAME_RETRIES, retries);
f2fdd67c
PB
1289}
1290
92f45f54
AA
1291static int
1292at86rf230_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on)
1293{
1294 struct at86rf230_local *lp = hw->priv;
1295 int rc;
1296
1297 if (on) {
1298 rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 1);
1299 if (rc < 0)
1300 return rc;
1301
1302 rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 1);
1303 if (rc < 0)
1304 return rc;
1305 } else {
1306 rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 0);
1307 if (rc < 0)
1308 return rc;
1309
1310 rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 0);
1311 if (rc < 0)
1312 return rc;
1313 }
1314
1315 return 0;
1316}
1317
16301861 1318static const struct ieee802154_ops at86rf230_ops = {
7b8e19b6 1319 .owner = THIS_MODULE,
955aee8b 1320 .xmit_async = at86rf230_xmit,
7b8e19b6 1321 .ed = at86rf230_ed,
1322 .set_channel = at86rf230_channel,
1323 .start = at86rf230_start,
1324 .stop = at86rf230_stop,
1486774d 1325 .set_hw_addr_filt = at86rf230_set_hw_addr_filt,
640985ec
AA
1326 .set_txpower = at86rf230_set_txpower,
1327 .set_lbt = at86rf230_set_lbt,
1328 .set_cca_mode = at86rf230_set_cca_mode,
1329 .set_cca_ed_level = at86rf230_set_cca_ed_level,
1330 .set_csma_params = at86rf230_set_csma_params,
1331 .set_frame_retries = at86rf230_set_frame_retries,
92f45f54 1332 .set_promiscuous_mode = at86rf230_set_promiscuous_mode,
8fad346f
PB
1333};
1334
a53d1f7c 1335static struct at86rf2xx_chip_data at86rf233_data = {
7a4ef918 1336 .t_sleep_cycle = 330,
984e0c68 1337 .t_channel_switch = 11,
09e536cd 1338 .t_reset_to_off = 26,
2e0571c0
AA
1339 .t_off_to_aack = 80,
1340 .t_off_to_tx_on = 80,
e6f7ed9d 1341 .t_off_to_sleep = 35,
60f5f5d3 1342 .t_sleep_to_off = 1000,
1d15d6b5
AA
1343 .t_frame = 4096,
1344 .t_p_ack = 545,
4d7101d7 1345 .rssi_base_val = -94,
a53d1f7c 1346 .set_channel = at86rf23x_set_channel,
6f4da3f8 1347 .set_txpower = at86rf23x_set_txpower,
a53d1f7c
AA
1348};
1349
1350static struct at86rf2xx_chip_data at86rf231_data = {
7a4ef918 1351 .t_sleep_cycle = 330,
984e0c68 1352 .t_channel_switch = 24,
09e536cd 1353 .t_reset_to_off = 37,
2e0571c0
AA
1354 .t_off_to_aack = 110,
1355 .t_off_to_tx_on = 110,
e6f7ed9d 1356 .t_off_to_sleep = 35,
60f5f5d3 1357 .t_sleep_to_off = 1000,
1d15d6b5
AA
1358 .t_frame = 4096,
1359 .t_p_ack = 545,
a53d1f7c
AA
1360 .rssi_base_val = -91,
1361 .set_channel = at86rf23x_set_channel,
6f4da3f8 1362 .set_txpower = at86rf23x_set_txpower,
a53d1f7c
AA
1363};
1364
1365static struct at86rf2xx_chip_data at86rf212_data = {
7a4ef918 1366 .t_sleep_cycle = 330,
984e0c68 1367 .t_channel_switch = 11,
09e536cd 1368 .t_reset_to_off = 26,
2e0571c0
AA
1369 .t_off_to_aack = 200,
1370 .t_off_to_tx_on = 200,
e6f7ed9d 1371 .t_off_to_sleep = 35,
60f5f5d3 1372 .t_sleep_to_off = 1000,
1d15d6b5
AA
1373 .t_frame = 4096,
1374 .t_p_ack = 545,
a53d1f7c
AA
1375 .rssi_base_val = -100,
1376 .set_channel = at86rf212_set_channel,
6f4da3f8 1377 .set_txpower = at86rf212_set_txpower,
a53d1f7c
AA
1378};
1379
ccdaeb2b 1380static int at86rf230_hw_init(struct at86rf230_local *lp, u8 xtal_trim)
7b8e19b6 1381{
1db0558e 1382 int rc, irq_type, irq_pol = IRQ_ACTIVE_HIGH;
f76014f7 1383 unsigned int dvdd;
f2fdd67c 1384 u8 csma_seed[2];
7b8e19b6 1385
09e536cd 1386 rc = at86rf230_sync_state_change(lp, STATE_FORCE_TRX_OFF);
7dcbd22a
PB
1387 if (rc)
1388 return rc;
7b8e19b6 1389
4af619ae 1390 irq_type = irq_get_trigger_type(lp->spi->irq);
702d211c
AA
1391 if (irq_type == IRQ_TYPE_EDGE_FALLING ||
1392 irq_type == IRQ_TYPE_LEVEL_LOW)
43b5abe0 1393 irq_pol = IRQ_ACTIVE_LOW;
43b5abe0 1394
18c65049 1395 rc = at86rf230_write_subreg(lp, SR_IRQ_POLARITY, irq_pol);
43b5abe0
SH
1396 if (rc)
1397 return rc;
1398
6bd2b132
AA
1399 rc = at86rf230_write_subreg(lp, SR_RX_SAFE_MODE, 1);
1400 if (rc)
1401 return rc;
1402
057dad6f 1403 rc = at86rf230_write_subreg(lp, SR_IRQ_MASK, IRQ_TRX_END);
7b8e19b6 1404 if (rc)
1405 return rc;
1406
be64f076
AA
1407 /* reset values differs in at86rf231 and at86rf233 */
1408 rc = at86rf230_write_subreg(lp, SR_IRQ_MASK_MODE, 0);
1409 if (rc)
1410 return rc;
1411
f2fdd67c
PB
1412 get_random_bytes(csma_seed, ARRAY_SIZE(csma_seed));
1413 rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_0, csma_seed[0]);
1414 if (rc)
1415 return rc;
1416 rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_1, csma_seed[1]);
1417 if (rc)
1418 return rc;
1419
7b8e19b6 1420 /* CLKM changes are applied immediately */
1421 rc = at86rf230_write_subreg(lp, SR_CLKM_SHA_SEL, 0x00);
1422 if (rc)
1423 return rc;
1424
1425 /* Turn CLKM Off */
1426 rc = at86rf230_write_subreg(lp, SR_CLKM_CTRL, 0x00);
1427 if (rc)
1428 return rc;
1429 /* Wait the next SLEEP cycle */
7a4ef918
AA
1430 usleep_range(lp->data->t_sleep_cycle,
1431 lp->data->t_sleep_cycle + 100);
7b8e19b6 1432
ccdaeb2b
AA
1433 /* xtal_trim value is calculated by:
1434 * CL = 0.5 * (CX + CTRIM + CPAR)
1435 *
1436 * whereas:
1437 * CL = capacitor of used crystal
1438 * CX = connected capacitors at xtal pins
1439 * CPAR = in all at86rf2xx datasheets this is a constant value 3 pF,
1440 * but this is different on each board setup. You need to fine
1441 * tuning this value via CTRIM.
1442 * CTRIM = variable capacitor setting. Resolution is 0.3 pF range is
1443 * 0 pF upto 4.5 pF.
1444 *
1445 * Examples:
1446 * atben transceiver:
1447 *
1448 * CL = 8 pF
1449 * CX = 12 pF
1450 * CPAR = 3 pF (We assume the magic constant from datasheet)
1451 * CTRIM = 0.9 pF
1452 *
1453 * (12+0.9+3)/2 = 7.95 which is nearly at 8 pF
1454 *
1455 * xtal_trim = 0x3
1456 *
1457 * openlabs transceiver:
1458 *
1459 * CL = 16 pF
1460 * CX = 22 pF
1461 * CPAR = 3 pF (We assume the magic constant from datasheet)
1462 * CTRIM = 4.5 pF
1463 *
1464 * (22+4.5+3)/2 = 14.75 which is the nearest value to 16 pF
1465 *
1466 * xtal_trim = 0xf
1467 */
1468 rc = at86rf230_write_subreg(lp, SR_XTAL_TRIM, xtal_trim);
1469 if (rc)
1470 return rc;
1471
1cc9fc53 1472 rc = at86rf230_read_subreg(lp, SR_DVDD_OK, &dvdd);
7b8e19b6 1473 if (rc)
1474 return rc;
1cc9fc53 1475 if (!dvdd) {
7b8e19b6 1476 dev_err(&lp->spi->dev, "DVDD error\n");
1477 return -EINVAL;
1478 }
1479
05e3f2f3
AA
1480 /* Force setting slotted operation bit to 0. Sometimes the atben
1481 * sets this bit and I don't know why. We set this always force
1482 * to zero while probing.
1483 */
6cc6399c 1484 return at86rf230_write_subreg(lp, SR_SLOTTED_OPERATION, 0);
7b8e19b6 1485}
1486
aaa1c4d2 1487static int
ccdaeb2b
AA
1488at86rf230_get_pdata(struct spi_device *spi, int *rstn, int *slp_tr,
1489 u8 *xtal_trim)
fa2d3e94 1490{
aaa1c4d2 1491 struct at86rf230_platform_data *pdata = spi->dev.platform_data;
ccdaeb2b 1492 int ret;
fa2d3e94 1493
aaa1c4d2
AA
1494 if (!IS_ENABLED(CONFIG_OF) || !spi->dev.of_node) {
1495 if (!pdata)
1496 return -ENOENT;
fa2d3e94 1497
aaa1c4d2
AA
1498 *rstn = pdata->rstn;
1499 *slp_tr = pdata->slp_tr;
ccdaeb2b 1500 *xtal_trim = pdata->xtal_trim;
aaa1c4d2
AA
1501 return 0;
1502 }
fa2d3e94 1503
aaa1c4d2
AA
1504 *rstn = of_get_named_gpio(spi->dev.of_node, "reset-gpio", 0);
1505 *slp_tr = of_get_named_gpio(spi->dev.of_node, "sleep-gpio", 0);
ccdaeb2b
AA
1506 ret = of_property_read_u8(spi->dev.of_node, "xtal-trim", xtal_trim);
1507 if (ret < 0 && ret != -EINVAL)
1508 return ret;
fa2d3e94 1509
aaa1c4d2 1510 return 0;
fa2d3e94
AA
1511}
1512
c8ee0f56
AA
1513static int
1514at86rf230_detect_device(struct at86rf230_local *lp)
1515{
1516 unsigned int part, version, val;
1517 u16 man_id = 0;
1518 const char *chip;
1519 int rc;
1520
1521 rc = __at86rf230_read(lp, RG_MAN_ID_0, &val);
1522 if (rc)
1523 return rc;
1524 man_id |= val;
1525
1526 rc = __at86rf230_read(lp, RG_MAN_ID_1, &val);
1527 if (rc)
1528 return rc;
1529 man_id |= (val << 8);
1530
1531 rc = __at86rf230_read(lp, RG_PART_NUM, &part);
1532 if (rc)
1533 return rc;
1534
7598968d 1535 rc = __at86rf230_read(lp, RG_VERSION_NUM, &version);
c8ee0f56
AA
1536 if (rc)
1537 return rc;
1538
1539 if (man_id != 0x001f) {
1540 dev_err(&lp->spi->dev, "Non-Atmel dev found (MAN_ID %02x %02x)\n",
1541 man_id >> 8, man_id & 0xFF);
1542 return -EINVAL;
1543 }
1544
f265be3d 1545 lp->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM |
edea8f7c
AA
1546 IEEE802154_HW_CSMA_PARAMS |
1547 IEEE802154_HW_FRAME_RETRIES | IEEE802154_HW_AFILT |
1548 IEEE802154_HW_PROMISCUOUS;
1549
1550 lp->hw->phy->flags = WPAN_PHY_FLAG_TXPOWER |
1551 WPAN_PHY_FLAG_CCA_ED_LEVEL |
1552 WPAN_PHY_FLAG_CCA_MODE;
c8ee0f56 1553
8377d22c
AA
1554 lp->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
1555 BIT(NL802154_CCA_CARRIER) | BIT(NL802154_CCA_ENERGY_CARRIER);
1556 lp->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND) |
1557 BIT(NL802154_CCA_OPT_ENERGY_CARRIER_OR);
1558
b48a7c18
AA
1559 lp->hw->phy->cca.mode = NL802154_CCA_ENERGY;
1560
c8ee0f56
AA
1561 switch (part) {
1562 case 2:
1563 chip = "at86rf230";
1564 rc = -ENOTSUPP;
cc643496 1565 goto not_supp;
c8ee0f56
AA
1566 case 3:
1567 chip = "at86rf231";
a53d1f7c 1568 lp->data = &at86rf231_data;
72f655e4 1569 lp->hw->phy->supported.channels[0] = 0x7FFF800;
fe58d016 1570 lp->hw->phy->current_channel = 11;
24ccb9f4 1571 lp->hw->phy->symbol_duration = 16;
6f4da3f8
AA
1572 lp->hw->phy->supported.tx_powers = at86rf231_powers;
1573 lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf231_powers);
4d7101d7
AA
1574 lp->hw->phy->supported.cca_ed_levels = at86rf231_ed_levels;
1575 lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf231_ed_levels);
c8ee0f56
AA
1576 break;
1577 case 7:
1578 chip = "at86rf212";
4ecc8a55
AY
1579 lp->data = &at86rf212_data;
1580 lp->hw->flags |= IEEE802154_HW_LBT;
72f655e4
AA
1581 lp->hw->phy->supported.channels[0] = 0x00007FF;
1582 lp->hw->phy->supported.channels[2] = 0x00007FF;
4ecc8a55
AY
1583 lp->hw->phy->current_channel = 5;
1584 lp->hw->phy->symbol_duration = 25;
8377d22c 1585 lp->hw->phy->supported.lbt = NL802154_SUPPORTED_BOOL_BOTH;
6f4da3f8
AA
1586 lp->hw->phy->supported.tx_powers = at86rf212_powers;
1587 lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf212_powers);
2d9fe7ab
AA
1588 lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_100;
1589 lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_100);
c8ee0f56
AA
1590 break;
1591 case 11:
1592 chip = "at86rf233";
a53d1f7c 1593 lp->data = &at86rf233_data;
72f655e4 1594 lp->hw->phy->supported.channels[0] = 0x7FFF800;
fe58d016 1595 lp->hw->phy->current_channel = 13;
24ccb9f4 1596 lp->hw->phy->symbol_duration = 16;
6f4da3f8
AA
1597 lp->hw->phy->supported.tx_powers = at86rf233_powers;
1598 lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf233_powers);
4d7101d7
AA
1599 lp->hw->phy->supported.cca_ed_levels = at86rf233_ed_levels;
1600 lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf233_ed_levels);
c8ee0f56
AA
1601 break;
1602 default:
2b8b7e29 1603 chip = "unknown";
c8ee0f56 1604 rc = -ENOTSUPP;
cc643496 1605 goto not_supp;
c8ee0f56
AA
1606 }
1607
cc643496 1608 lp->hw->phy->cca_ed_level = lp->hw->phy->supported.cca_ed_levels[7];
392f4e67 1609 lp->hw->phy->transmit_power = lp->hw->phy->supported.tx_powers[0];
cc643496
AA
1610
1611not_supp:
c8ee0f56
AA
1612 dev_info(&lp->spi->dev, "Detected %s chip version %d\n", chip, version);
1613
1614 return rc;
1615}
1616
493bc90a
AA
1617#ifdef CONFIG_IEEE802154_AT86RF230_DEBUGFS
1618static struct dentry *at86rf230_debugfs_root;
1619
1620static int at86rf230_stats_show(struct seq_file *file, void *offset)
1621{
1622 struct at86rf230_local *lp = file->private;
493bc90a 1623
97170ea1
SR
1624 seq_printf(file, "SUCCESS:\t\t%8llu\n", lp->trac.success);
1625 seq_printf(file, "SUCCESS_DATA_PENDING:\t%8llu\n",
1626 lp->trac.success_data_pending);
1627 seq_printf(file, "SUCCESS_WAIT_FOR_ACK:\t%8llu\n",
1628 lp->trac.success_wait_for_ack);
1629 seq_printf(file, "CHANNEL_ACCESS_FAILURE:\t%8llu\n",
1630 lp->trac.channel_access_failure);
1631 seq_printf(file, "NO_ACK:\t\t\t%8llu\n", lp->trac.no_ack);
1632 seq_printf(file, "INVALID:\t\t%8llu\n", lp->trac.invalid);
1633 return 0;
493bc90a 1634}
f578e676 1635DEFINE_SHOW_ATTRIBUTE(at86rf230_stats);
493bc90a
AA
1636
1637static int at86rf230_debugfs_init(struct at86rf230_local *lp)
1638{
1639 char debugfs_dir_name[DNAME_INLINE_LEN + 1] = "at86rf230-";
1640 struct dentry *stats;
1641
1642 strncat(debugfs_dir_name, dev_name(&lp->spi->dev), DNAME_INLINE_LEN);
1643
1644 at86rf230_debugfs_root = debugfs_create_dir(debugfs_dir_name, NULL);
1645 if (!at86rf230_debugfs_root)
1646 return -ENOMEM;
1647
d61e4038 1648 stats = debugfs_create_file("trac_stats", 0444,
493bc90a
AA
1649 at86rf230_debugfs_root, lp,
1650 &at86rf230_stats_fops);
1651 if (!stats)
1652 return -ENOMEM;
1653
1654 return 0;
1655}
1656
1657static void at86rf230_debugfs_remove(void)
1658{
1659 debugfs_remove_recursive(at86rf230_debugfs_root);
1660}
1661#else
1662static int at86rf230_debugfs_init(struct at86rf230_local *lp) { return 0; }
1663static void at86rf230_debugfs_remove(void) { }
1664#endif
1665
bb1f4606 1666static int at86rf230_probe(struct spi_device *spi)
7b8e19b6 1667{
5a504397 1668 struct ieee802154_hw *hw;
7b8e19b6 1669 struct at86rf230_local *lp;
f76014f7 1670 unsigned int status;
aaa1c4d2 1671 int rc, irq_type, rstn, slp_tr;
e3721749 1672 u8 xtal_trim = 0;
7b8e19b6 1673
1674 if (!spi->irq) {
1675 dev_err(&spi->dev, "no IRQ specified\n");
1676 return -EINVAL;
1677 }
1678
ccdaeb2b 1679 rc = at86rf230_get_pdata(spi, &rstn, &slp_tr, &xtal_trim);
aaa1c4d2
AA
1680 if (rc < 0) {
1681 dev_err(&spi->dev, "failed to parse platform_data: %d\n", rc);
1682 return rc;
43b5abe0
SH
1683 }
1684
aaa1c4d2
AA
1685 if (gpio_is_valid(rstn)) {
1686 rc = devm_gpio_request_one(&spi->dev, rstn,
0679e29b 1687 GPIOF_OUT_INIT_HIGH, "rstn");
3fa27571
AA
1688 if (rc)
1689 return rc;
1690 }
7b8e19b6 1691
aaa1c4d2
AA
1692 if (gpio_is_valid(slp_tr)) {
1693 rc = devm_gpio_request_one(&spi->dev, slp_tr,
0679e29b 1694 GPIOF_OUT_INIT_LOW, "slp_tr");
7b8e19b6 1695 if (rc)
0679e29b 1696 return rc;
7b8e19b6 1697 }
1698
1699 /* Reset */
aaa1c4d2 1700 if (gpio_is_valid(rstn)) {
3fa27571 1701 udelay(1);
f3016069 1702 gpio_set_value_cansleep(rstn, 0);
3fa27571 1703 udelay(1);
f3016069 1704 gpio_set_value_cansleep(rstn, 1);
3fa27571
AA
1705 usleep_range(120, 240);
1706 }
7b8e19b6 1707
5a504397
AA
1708 hw = ieee802154_alloc_hw(sizeof(*lp), &at86rf230_ops);
1709 if (!hw)
640985ec
AA
1710 return -ENOMEM;
1711
5a504397
AA
1712 lp = hw->priv;
1713 lp->hw = hw;
640985ec 1714 lp->spi = spi;
d2c8bf51 1715 lp->slp_tr = slp_tr;
5a504397 1716 hw->parent = &spi->dev;
f6f4e86a 1717 ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
8fad346f 1718
f76014f7
AA
1719 lp->regmap = devm_regmap_init_spi(spi, &at86rf230_regmap_spi_config);
1720 if (IS_ERR(lp->regmap)) {
1721 rc = PTR_ERR(lp->regmap);
1722 dev_err(&spi->dev, "Failed to allocate register map: %d\n",
1723 rc);
1724 goto free_dev;
1725 }
1726
57c1bc7e
AA
1727 at86rf230_setup_spi_messages(lp, &lp->state);
1728 at86rf230_setup_spi_messages(lp, &lp->tx);
1d15d6b5 1729
c8ee0f56
AA
1730 rc = at86rf230_detect_device(lp);
1731 if (rc < 0)
1732 goto free_dev;
1733
2e0571c0 1734 init_completion(&lp->state_complete);
8fad346f
PB
1735
1736 spi_set_drvdata(spi, lp);
1737
ccdaeb2b 1738 rc = at86rf230_hw_init(lp, xtal_trim);
7b8e19b6 1739 if (rc)
1d15d6b5 1740 goto free_dev;
7b8e19b6 1741
19626946
AA
1742 /* Read irq status register to reset irq line */
1743 rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &status);
7b8e19b6 1744 if (rc)
1d15d6b5 1745 goto free_dev;
7b8e19b6 1746
1d15d6b5
AA
1747 irq_type = irq_get_trigger_type(spi->irq);
1748 if (!irq_type)
9ff19e6f 1749 irq_type = IRQF_TRIGGER_HIGH;
1d15d6b5
AA
1750
1751 rc = devm_request_irq(&spi->dev, spi->irq, at86rf230_isr,
1752 IRQF_SHARED | irq_type, dev_name(&spi->dev), lp);
057dad6f 1753 if (rc)
1d15d6b5 1754 goto free_dev;
057dad6f 1755
e6f7ed9d
AA
1756 /* disable_irq by default and wait for starting hardware */
1757 disable_irq(spi->irq);
1758
1759 /* going into sleep by default */
cbe62346 1760 at86rf230_sleep(lp);
e6f7ed9d 1761
493bc90a 1762 rc = at86rf230_debugfs_init(lp);
7b8e19b6 1763 if (rc)
1d15d6b5 1764 goto free_dev;
7b8e19b6 1765
493bc90a
AA
1766 rc = ieee802154_register_hw(lp->hw);
1767 if (rc)
1768 goto free_debugfs;
1769
7b8e19b6 1770 return rc;
1771
493bc90a
AA
1772free_debugfs:
1773 at86rf230_debugfs_remove();
640985ec 1774free_dev:
5a504397 1775 ieee802154_free_hw(lp->hw);
8fad346f 1776
7b8e19b6 1777 return rc;
1778}
1779
bb1f4606 1780static int at86rf230_remove(struct spi_device *spi)
7b8e19b6 1781{
1782 struct at86rf230_local *lp = spi_get_drvdata(spi);
1783
17e84a92
AA
1784 /* mask all at86rf230 irq's */
1785 at86rf230_write_subreg(lp, SR_IRQ_MASK, 0);
5a504397
AA
1786 ieee802154_unregister_hw(lp->hw);
1787 ieee802154_free_hw(lp->hw);
493bc90a 1788 at86rf230_debugfs_remove();
7b8e19b6 1789 dev_dbg(&spi->dev, "unregistered at86rf230\n");
0679e29b 1790
7b8e19b6 1791 return 0;
1792}
1793
1086b4f6 1794static const struct of_device_id at86rf230_of_match[] = {
fa2d3e94
AA
1795 { .compatible = "atmel,at86rf230", },
1796 { .compatible = "atmel,at86rf231", },
1797 { .compatible = "atmel,at86rf233", },
1798 { .compatible = "atmel,at86rf212", },
1799 { },
1800};
835cb7d2 1801MODULE_DEVICE_TABLE(of, at86rf230_of_match);
fa2d3e94 1802
90b15520
AA
1803static const struct spi_device_id at86rf230_device_id[] = {
1804 { .name = "at86rf230", },
1805 { .name = "at86rf231", },
1806 { .name = "at86rf233", },
1807 { .name = "at86rf212", },
1808 { },
1809};
1810MODULE_DEVICE_TABLE(spi, at86rf230_device_id);
1811
7b8e19b6 1812static struct spi_driver at86rf230_driver = {
90b15520 1813 .id_table = at86rf230_device_id,
7b8e19b6 1814 .driver = {
fa2d3e94 1815 .of_match_table = of_match_ptr(at86rf230_of_match),
7b8e19b6 1816 .name = "at86rf230",
7b8e19b6 1817 },
1818 .probe = at86rf230_probe,
bb1f4606 1819 .remove = at86rf230_remove,
7b8e19b6 1820};
1821
395a5738 1822module_spi_driver(at86rf230_driver);
7b8e19b6 1823
1824MODULE_DESCRIPTION("AT86RF230 Transceiver Driver");
1825MODULE_LICENSE("GPL v2");