projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
netdev: Remove redundant checks for CAP_NET_ADMIN in MDIO implementations
[linux-2.6-block.git] / drivers / net / ibm_newemac / core.c
CommitLineData
1d3bb996
DG		 1/*
2 * drivers/net/ibm_newemac/core.c
3 *
4 * Driver for PowerPC 4xx on-chip ethernet controller.
5 *
17cf803a
BH		 6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
7 * <benh@kernel.crashing.org>
8 *
9 * Based on the arch/ppc version of the driver:
10 *
1d3bb996
DG		 11 * Copyright (c) 2004, 2005 Zultys Technologies.
12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
13 *
14 * Based on original work by
15 * Matt Porter <mporter@kernel.crashing.org>
16 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
17 * Armin Kuster <akuster@mvista.com>
18 * Johnnie Peters <jpeters@mvista.com>
19 *
20 * This program is free software; you can redistribute it and/or modify it
21 * under the terms of the GNU General Public License as published by the
22 * Free Software Foundation; either version 2 of the License, or (at your
23 * option) any later version.
24 *
25 */
26
27#include <linux/sched.h>
28#include <linux/string.h>
29#include <linux/errno.h>
30#include <linux/delay.h>
31#include <linux/types.h>
32#include <linux/pci.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/crc32.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
38#include <linux/bitops.h>
39#include <linux/workqueue.h>
283029d1 40#include <linux/of.h>
1d3bb996
DG		 41
42#include <asm/processor.h>
43#include <asm/io.h>
44#include <asm/dma.h>
45#include <asm/uaccess.h>
0925ab5d
VB		 46#include <asm/dcr.h>
47#include <asm/dcr-regs.h>
1d3bb996
DG		 48
49#include "core.h"
50
51/*
52 * Lack of dma_unmap_???? calls is intentional.
53 *
54 * API-correct usage requires additional support state information to be
55 * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
56 * EMAC design (e.g. TX buffer passed from network stack can be split into
57 * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
58 * maintaining such information will add additional overhead.
59 * Current DMA API implementation for 4xx processors only ensures cache coherency
60 * and dma_unmap_???? routines are empty and are likely to stay this way.
61 * I decided to omit dma_unmap_??? calls because I don't want to add additional
62 * complexity just for the sake of following some abstract API, when it doesn't
63 * add any real benefit to the driver. I understand that this decision maybe
64 * controversial, but I really tried to make code API-correct and efficient
65 * at the same time and didn't come up with code I liked :(. --ebs
66 */
67
68#define DRV_NAME "emac"
69#define DRV_VERSION "3.54"
70#define DRV_DESC "PPC 4xx OCP EMAC driver"
71
72MODULE_DESCRIPTION(DRV_DESC);
73MODULE_AUTHOR
74 ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
75MODULE_LICENSE("GPL");
76
77/*
78 * PPC64 doesn't (yet) have a cacheable_memcpy
79 */
80#ifdef CONFIG_PPC64
81#define cacheable_memcpy(d,s,n) memcpy((d),(s),(n))
82#endif
83
84/* minimum number of free TX descriptors required to wake up TX process */
85#define EMAC_TX_WAKEUP_THRESH (NUM_TX_BUFF / 4)
86
87/* If packet size is less than this number, we allocate small skb and copy packet
88 * contents into it instead of just sending original big skb up
89 */
90#define EMAC_RX_COPY_THRESH CONFIG_IBM_NEW_EMAC_RX_COPY_THRESHOLD
91
92/* Since multiple EMACs share MDIO lines in various ways, we need
93 * to avoid re-using the same PHY ID in cases where the arch didn't
94 * setup precise phy_map entries
95 *
96 * XXX This is something that needs to be reworked as we can have multiple
97 * EMAC "sets" (multiple ASICs containing several EMACs) though we can
98 * probably require in that case to have explicit PHY IDs in the device-tree
99 */
100static u32 busy_phy_map;
101static DEFINE_MUTEX(emac_phy_map_lock);
102
103/* This is the wait queue used to wait on any event related to probe, that
104 * is discovery of MALs, other EMACs, ZMII/RGMIIs, etc...
105 */
106static DECLARE_WAIT_QUEUE_HEAD(emac_probe_wait);
107
108/* Having stable interface names is a doomed idea. However, it would be nice
109 * if we didn't have completely random interface names at boot too :-) It's
110 * just a matter of making everybody's life easier. Since we are doing
111 * threaded probing, it's a bit harder though. The base idea here is that
112 * we make up a list of all emacs in the device-tree before we register the
113 * driver. Every emac will then wait for the previous one in the list to
114 * initialize before itself. We should also keep that list ordered by
115 * cell_index.
116 * That list is only 4 entries long, meaning that additional EMACs don't
117 * get ordering guarantees unless EMAC_BOOT_LIST_SIZE is increased.
118 */
119
120#define EMAC_BOOT_LIST_SIZE 4
121static struct device_node *emac_boot_list[EMAC_BOOT_LIST_SIZE];
122
123/* How long should I wait for dependent devices ? */
124#define EMAC_PROBE_DEP_TIMEOUT (HZ * 5)
125
126/* I don't want to litter system log with timeout errors
127 * when we have brain-damaged PHY.
128 */
129static inline void emac_report_timeout_error(struct emac_instance *dev,
130 const char *error)
131{
11121e30 132 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
9e3cb294 133 EMAC_FTR_460EX_PHY_CLK_FIX |
11121e30
VB		 134 EMAC_FTR_440EP_PHY_CLK_FIX))
135 DBG(dev, "%s" NL, error);
136 else if (net_ratelimit())
62f0c338 137 printk(KERN_ERR "%s: %s\n", dev->ofdev->node->full_name, error);
1d3bb996
DG		 138}
139
11121e30
VB		 140/* EMAC PHY clock workaround:
141 * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX,
142 * which allows controlling each EMAC clock
143 */
144static inline void emac_rx_clk_tx(struct emac_instance *dev)
145{
146#ifdef CONFIG_PPC_DCR_NATIVE
147 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
148 dcri_clrset(SDR0, SDR0_MFR,
149 0, SDR0_MFR_ECS >> dev->cell_index);
150#endif
151}
152
153static inline void emac_rx_clk_default(struct emac_instance *dev)
154{
155#ifdef CONFIG_PPC_DCR_NATIVE
156 if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
157 dcri_clrset(SDR0, SDR0_MFR,
158 SDR0_MFR_ECS >> dev->cell_index, 0);
159#endif
160}
161
1d3bb996
DG		 162/* PHY polling intervals */
163#define PHY_POLL_LINK_ON HZ
164#define PHY_POLL_LINK_OFF (HZ / 5)
165
166/* Graceful stop timeouts in us.
167 * We should allow up to 1 frame time (full-duplex, ignoring collisions)
168 */
169#define STOP_TIMEOUT_10 1230
170#define STOP_TIMEOUT_100 124
171#define STOP_TIMEOUT_1000 13
172#define STOP_TIMEOUT_1000_JUMBO 73
173
4373c932
PB		 174static unsigned char default_mcast_addr[] = {
175 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01
176};
177
1d3bb996
DG		 178/* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
179static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
180 "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
181 "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
182 "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
183 "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
184 "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
185 "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
186 "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
187 "rx_bad_packet", "rx_runt_packet", "rx_short_event",
188 "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
189 "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
190 "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
191 "tx_bd_excessive_collisions", "tx_bd_late_collision",
192 "tx_bd_multple_collisions", "tx_bd_single_collision",
193 "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
194 "tx_errors"
195};
196
197static irqreturn_t emac_irq(int irq, void *dev_instance);
198static void emac_clean_tx_ring(struct emac_instance *dev);
199static void __emac_set_multicast_list(struct emac_instance *dev);
200
201static inline int emac_phy_supports_gige(int phy_mode)
202{
203 return phy_mode == PHY_MODE_GMII ||
204 phy_mode == PHY_MODE_RGMII ||
9e3cb294 205 phy_mode == PHY_MODE_SGMII ||
1d3bb996
DG		 206 phy_mode == PHY_MODE_TBI ||
207 phy_mode == PHY_MODE_RTBI;
208}
209
210static inline int emac_phy_gpcs(int phy_mode)
211{
9e3cb294
VG		 212 return phy_mode == PHY_MODE_SGMII ||
213 phy_mode == PHY_MODE_TBI ||
1d3bb996
DG		 214 phy_mode == PHY_MODE_RTBI;
215}
216
217static inline void emac_tx_enable(struct emac_instance *dev)
218{
219 struct emac_regs __iomem *p = dev->emacp;
220 u32 r;
221
222 DBG(dev, "tx_enable" NL);
223
224 r = in_be32(&p->mr0);
225 if (!(r & EMAC_MR0_TXE))
226 out_be32(&p->mr0, r | EMAC_MR0_TXE);
227}
228
229static void emac_tx_disable(struct emac_instance *dev)
230{
231 struct emac_regs __iomem *p = dev->emacp;
232 u32 r;
233
234 DBG(dev, "tx_disable" NL);
235
236 r = in_be32(&p->mr0);
237 if (r & EMAC_MR0_TXE) {
238 int n = dev->stop_timeout;
239 out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
240 while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n) {
241 udelay(1);
242 --n;
243 }
244 if (unlikely(!n))
245 emac_report_timeout_error(dev, "TX disable timeout");
246 }
247}
248
249static void emac_rx_enable(struct emac_instance *dev)
250{
251 struct emac_regs __iomem *p = dev->emacp;
252 u32 r;
253
254 if (unlikely(test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags)))
255 goto out;
256
257 DBG(dev, "rx_enable" NL);
258
259 r = in_be32(&p->mr0);
260 if (!(r & EMAC_MR0_RXE)) {
261 if (unlikely(!(r & EMAC_MR0_RXI))) {
262 /* Wait if previous async disable is still in progress */
263 int n = dev->stop_timeout;
264 while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
265 udelay(1);
266 --n;
267 }
268 if (unlikely(!n))
269 emac_report_timeout_error(dev,
270 "RX disable timeout");
271 }
272 out_be32(&p->mr0, r | EMAC_MR0_RXE);
273 }
274 out:
275 ;
276}
277
278static void emac_rx_disable(struct emac_instance *dev)
279{
280 struct emac_regs __iomem *p = dev->emacp;
281 u32 r;
282
283 DBG(dev, "rx_disable" NL);
284
285 r = in_be32(&p->mr0);
286 if (r & EMAC_MR0_RXE) {
287 int n = dev->stop_timeout;
288 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
289 while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n) {
290 udelay(1);
291 --n;
292 }
293 if (unlikely(!n))
294 emac_report_timeout_error(dev, "RX disable timeout");
295 }
296}
297
298static inline void emac_netif_stop(struct emac_instance *dev)
299{
300 netif_tx_lock_bh(dev->ndev);
e308a5d8 301 netif_addr_lock(dev->ndev);
1d3bb996 302 dev->no_mcast = 1;
e308a5d8 303 netif_addr_unlock(dev->ndev);
1d3bb996
DG		 304 netif_tx_unlock_bh(dev->ndev);
305 dev->ndev->trans_start = jiffies; /* prevent tx timeout */
306 mal_poll_disable(dev->mal, &dev->commac);
307 netif_tx_disable(dev->ndev);
308}
309
310static inline void emac_netif_start(struct emac_instance *dev)
311{
312 netif_tx_lock_bh(dev->ndev);
e308a5d8 313 netif_addr_lock(dev->ndev);
1d3bb996
DG		 314 dev->no_mcast = 0;
315 if (dev->mcast_pending && netif_running(dev->ndev))
316 __emac_set_multicast_list(dev);
e308a5d8 317 netif_addr_unlock(dev->ndev);
1d3bb996
DG		 318 netif_tx_unlock_bh(dev->ndev);
319
320 netif_wake_queue(dev->ndev);
321
322 /* NOTE: unconditional netif_wake_queue is only appropriate
323 * so long as all callers are assured to have free tx slots
324 * (taken from tg3... though the case where that is wrong is
325 * not terribly harmful)
326 */
327 mal_poll_enable(dev->mal, &dev->commac);
328}
329
330static inline void emac_rx_disable_async(struct emac_instance *dev)
331{
332 struct emac_regs __iomem *p = dev->emacp;
333 u32 r;
334
335 DBG(dev, "rx_disable_async" NL);
336
337 r = in_be32(&p->mr0);
338 if (r & EMAC_MR0_RXE)
339 out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
340}
341
342static int emac_reset(struct emac_instance *dev)
343{
344 struct emac_regs __iomem *p = dev->emacp;
345 int n = 20;
346
347 DBG(dev, "reset" NL);
348
349 if (!dev->reset_failed) {
350 /* 40x erratum suggests stopping RX channel before reset,
351 * we stop TX as well
352 */
353 emac_rx_disable(dev);
354 emac_tx_disable(dev);
355 }
356
9e3cb294
VG		 357#ifdef CONFIG_PPC_DCR_NATIVE
358 /* Enable internal clock source */
359 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
360 dcri_clrset(SDR0, SDR0_ETH_CFG,
361 0, SDR0_ETH_CFG_ECS << dev->cell_index);
362#endif
363
1d3bb996
DG		 364 out_be32(&p->mr0, EMAC_MR0_SRST);
365 while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
366 --n;
367
9e3cb294
VG		 368#ifdef CONFIG_PPC_DCR_NATIVE
369 /* Enable external clock source */
370 if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
371 dcri_clrset(SDR0, SDR0_ETH_CFG,
372 SDR0_ETH_CFG_ECS << dev->cell_index, 0);
373#endif
374
1d3bb996
DG		 375 if (n) {
376 dev->reset_failed = 0;
377 return 0;
378 } else {
379 emac_report_timeout_error(dev, "reset timeout");
380 dev->reset_failed = 1;
381 return -ETIMEDOUT;
382 }
383}
384
385static void emac_hash_mc(struct emac_instance *dev)
386{
05781ccd
GE		 387 const int regs = EMAC_XAHT_REGS(dev);
388 u32 *gaht_base = emac_gaht_base(dev);
389 u32 gaht_temp[regs];
1d3bb996 390 struct dev_mc_list *dmi;
05781ccd 391 int i;
1d3bb996
DG		 392
393 DBG(dev, "hash_mc %d" NL, dev->ndev->mc_count);
394
05781ccd
GE		 395 memset(gaht_temp, 0, sizeof (gaht_temp));
396
1d3bb996 397 for (dmi = dev->ndev->mc_list; dmi; dmi = dmi->next) {
05781ccd 398 int slot, reg, mask;
7c510e4b 399 DBG2(dev, "mc %pM" NL, dmi->dmi_addr);
1d3bb996 400
05781ccd
GE		 401 slot = EMAC_XAHT_CRC_TO_SLOT(dev, ether_crc(ETH_ALEN, dmi->dmi_addr));
402 reg = EMAC_XAHT_SLOT_TO_REG(dev, slot);
403 mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot);
404
405 gaht_temp[reg] |= mask;
1d3bb996 406 }
05781ccd
GE		 407
408 for (i = 0; i < regs; i++)
409 out_be32(gaht_base + i, gaht_temp[i]);
1d3bb996
DG		 410}
411
412static inline u32 emac_iff2rmr(struct net_device *ndev)
413{
414 struct emac_instance *dev = netdev_priv(ndev);
415 u32 r;
416
417 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE;
418
419 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
420 r |= EMAC4_RMR_BASE;
421 else
422 r |= EMAC_RMR_BASE;
423
424 if (ndev->flags & IFF_PROMISC)
425 r |= EMAC_RMR_PME;
05781ccd
GE		 426 else if (ndev->flags & IFF_ALLMULTI ||
427 (ndev->mc_count > EMAC_XAHT_SLOTS(dev)))
1d3bb996
DG		 428 r |= EMAC_RMR_PMME;
429 else if (ndev->mc_count > 0)
430 r |= EMAC_RMR_MAE;
431
432 return r;
433}
434
435static u32 __emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
436{
437 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC_MR1_TR0_MULT;
438
439 DBG2(dev, "__emac_calc_base_mr1" NL);
440
441 switch(tx_size) {
442 case 2048:
443 ret |= EMAC_MR1_TFS_2K;
444 break;
445 default:
446 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
447 dev->ndev->name, tx_size);
448 }
449
450 switch(rx_size) {
451 case 16384:
452 ret |= EMAC_MR1_RFS_16K;
453 break;
454 case 4096:
455 ret |= EMAC_MR1_RFS_4K;
456 break;
457 default:
458 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
459 dev->ndev->name, rx_size);
460 }
461
462 return ret;
463}
464
465static u32 __emac4_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
466{
467 u32 ret = EMAC_MR1_VLE | EMAC_MR1_IST | EMAC4_MR1_TR |
4696c3c4 468 EMAC4_MR1_OBCI(dev->opb_bus_freq / 1000000);
1d3bb996
DG		 469
470 DBG2(dev, "__emac4_calc_base_mr1" NL);
471
472 switch(tx_size) {
473 case 4096:
474 ret |= EMAC4_MR1_TFS_4K;
475 break;
476 case 2048:
477 ret |= EMAC4_MR1_TFS_2K;
478 break;
479 default:
480 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
481 dev->ndev->name, tx_size);
482 }
483
484 switch(rx_size) {
485 case 16384:
486 ret |= EMAC4_MR1_RFS_16K;
487 break;
488 case 4096:
489 ret |= EMAC4_MR1_RFS_4K;
490 break;
491 case 2048:
492 ret |= EMAC4_MR1_RFS_2K;
493 break;
494 default:
495 printk(KERN_WARNING "%s: Unknown Rx FIFO size %d\n",
496 dev->ndev->name, rx_size);
497 }
498
499 return ret;
500}
501
502static u32 emac_calc_base_mr1(struct emac_instance *dev, int tx_size, int rx_size)
503{
504 return emac_has_feature(dev, EMAC_FTR_EMAC4) ?
505 __emac4_calc_base_mr1(dev, tx_size, rx_size) :
506 __emac_calc_base_mr1(dev, tx_size, rx_size);
507}
508
509static inline u32 emac_calc_trtr(struct emac_instance *dev, unsigned int size)
510{
511 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
512 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT_EMAC4;
513 else
514 return ((size >> 6) - 1) << EMAC_TRTR_SHIFT;
515}
516
517static inline u32 emac_calc_rwmr(struct emac_instance *dev,
518 unsigned int low, unsigned int high)
519{
520 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
521 return (low << 22) | ( (high & 0x3ff) << 6);
522 else
523 return (low << 23) | ( (high & 0x1ff) << 7);
524}
525
526static int emac_configure(struct emac_instance *dev)
527{
528 struct emac_regs __iomem *p = dev->emacp;
529 struct net_device *ndev = dev->ndev;
911b237d 530 int tx_size, rx_size, link = netif_carrier_ok(dev->ndev);
1d3bb996
DG		 531 u32 r, mr1 = 0;
532
533 DBG(dev, "configure" NL);
534
911b237d
BH		 535 if (!link) {
536 out_be32(&p->mr1, in_be32(&p->mr1)
537 | EMAC_MR1_FDE | EMAC_MR1_ILE);
538 udelay(100);
539 } else if (emac_reset(dev) < 0)
1d3bb996
DG		 540 return -ETIMEDOUT;
541
542 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
543 tah_reset(dev->tah_dev);
544
911b237d
BH		 545 DBG(dev, " link = %d duplex = %d, pause = %d, asym_pause = %d\n",
546 link, dev->phy.duplex, dev->phy.pause, dev->phy.asym_pause);
1d3bb996
DG		 547
548 /* Default fifo sizes */
549 tx_size = dev->tx_fifo_size;
550 rx_size = dev->rx_fifo_size;
551
911b237d
BH		 552 /* No link, force loopback */
553 if (!link)
554 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE;
555
1d3bb996 556 /* Check for full duplex */
911b237d 557 else if (dev->phy.duplex == DUPLEX_FULL)
1d3bb996
DG		 558 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001;
559
560 /* Adjust fifo sizes, mr1 and timeouts based on link speed */
561 dev->stop_timeout = STOP_TIMEOUT_10;
562 switch (dev->phy.speed) {
563 case SPEED_1000:
564 if (emac_phy_gpcs(dev->phy.mode)) {
9e3cb294
VG		 565 mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA(
566 (dev->phy.gpcs_address != 0xffffffff) ?
567 dev->phy.gpcs_address : dev->phy.address);
1d3bb996
DG		 568
569 /* Put some arbitrary OUI, Manuf & Rev IDs so we can
570 * identify this GPCS PHY later.
571 */
05781ccd 572 out_be32(&p->u1.emac4.ipcr, 0xdeadbeef);
1d3bb996
DG		 573 } else
574 mr1 |= EMAC_MR1_MF_1000;
575
576 /* Extended fifo sizes */
577 tx_size = dev->tx_fifo_size_gige;
578 rx_size = dev->rx_fifo_size_gige;
579
580 if (dev->ndev->mtu > ETH_DATA_LEN) {
f34ebab6
SR		 581 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
582 mr1 |= EMAC4_MR1_JPSM;
583 else
584 mr1 |= EMAC_MR1_JPSM;
1d3bb996
DG		 585 dev->stop_timeout = STOP_TIMEOUT_1000_JUMBO;
586 } else
587 dev->stop_timeout = STOP_TIMEOUT_1000;
588 break;
589 case SPEED_100:
590 mr1 |= EMAC_MR1_MF_100;
591 dev->stop_timeout = STOP_TIMEOUT_100;
592 break;
593 default: /* make gcc happy */
594 break;
595 }
596
597 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
598 rgmii_set_speed(dev->rgmii_dev, dev->rgmii_port,
599 dev->phy.speed);
600 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
601 zmii_set_speed(dev->zmii_dev, dev->zmii_port, dev->phy.speed);
602
603 /* on 40x erratum forces us to NOT use integrated flow control,
604 * let's hope it works on 44x ;)
605 */
606 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x) &&
607 dev->phy.duplex == DUPLEX_FULL) {
608 if (dev->phy.pause)
609 mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP;
610 else if (dev->phy.asym_pause)
611 mr1 |= EMAC_MR1_APP;
612 }
613
614 /* Add base settings & fifo sizes & program MR1 */
615 mr1 |= emac_calc_base_mr1(dev, tx_size, rx_size);
616 out_be32(&p->mr1, mr1);
617
618 /* Set individual MAC address */
619 out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
620 out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
621 (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
622 ndev->dev_addr[5]);
623
624 /* VLAN Tag Protocol ID */
625 out_be32(&p->vtpid, 0x8100);
626
627 /* Receive mode register */
628 r = emac_iff2rmr(ndev);
629 if (r & EMAC_RMR_MAE)
630 emac_hash_mc(dev);
631 out_be32(&p->rmr, r);
632
633 /* FIFOs thresholds */
634 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
635 r = EMAC4_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
636 tx_size / 2 / dev->fifo_entry_size);
637 else
638 r = EMAC_TMR1((dev->mal_burst_size / dev->fifo_entry_size) + 1,
639 tx_size / 2 / dev->fifo_entry_size);
640 out_be32(&p->tmr1, r);
641 out_be32(&p->trtr, emac_calc_trtr(dev, tx_size / 2));
642
643 /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
644 there should be still enough space in FIFO to allow the our link
645 partner time to process this frame and also time to send PAUSE
646 frame itself.
647
648 Here is the worst case scenario for the RX FIFO "headroom"
649 (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
650
651 1) One maximum-length frame on TX 1522 bytes
652 2) One PAUSE frame time 64 bytes
653 3) PAUSE frame decode time allowance 64 bytes
654 4) One maximum-length frame on RX 1522 bytes
655 5) Round-trip propagation delay of the link (100Mb) 15 bytes
656 ----------
657 3187 bytes
658
659 I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
660 low-water mark to RX_FIFO_SIZE / 8 (512 bytes)
661 */
662 r = emac_calc_rwmr(dev, rx_size / 8 / dev->fifo_entry_size,
663 rx_size / 4 / dev->fifo_entry_size);
664 out_be32(&p->rwmr, r);
665
666 /* Set PAUSE timer to the maximum */
667 out_be32(&p->ptr, 0xffff);
668
669 /* IRQ sources */
670 r = EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
671 EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
672 EMAC_ISR_IRE | EMAC_ISR_TE;
673 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
674 r |= EMAC4_ISR_TXPE | EMAC4_ISR_RXPE /* | EMAC4_ISR_TXUE |
675 EMAC4_ISR_RXOE | */;
676 out_be32(&p->iser, r);
677
678 /* We need to take GPCS PHY out of isolate mode after EMAC reset */
9e3cb294
VG		 679 if (emac_phy_gpcs(dev->phy.mode)) {
680 if (dev->phy.gpcs_address != 0xffffffff)
681 emac_mii_reset_gpcs(&dev->phy);
682 else
683 emac_mii_reset_phy(&dev->phy);
684 }
1d3bb996
DG		 685
686 return 0;
687}
688
689static void emac_reinitialize(struct emac_instance *dev)
690{
691 DBG(dev, "reinitialize" NL);
692
693 emac_netif_stop(dev);
694 if (!emac_configure(dev)) {
695 emac_tx_enable(dev);
696 emac_rx_enable(dev);
697 }
698 emac_netif_start(dev);
699}
700
701static void emac_full_tx_reset(struct emac_instance *dev)
702{
703 DBG(dev, "full_tx_reset" NL);
704
705 emac_tx_disable(dev);
706 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
707 emac_clean_tx_ring(dev);
708 dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
709
710 emac_configure(dev);
711
712 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
713 emac_tx_enable(dev);
714 emac_rx_enable(dev);
715}
716
717static void emac_reset_work(struct work_struct *work)
718{
719 struct emac_instance *dev = container_of(work, struct emac_instance, reset_work);
720
721 DBG(dev, "reset_work" NL);
722
723 mutex_lock(&dev->link_lock);
61dbcece
BH		 724 if (dev->opened) {
725 emac_netif_stop(dev);
726 emac_full_tx_reset(dev);
727 emac_netif_start(dev);
728 }
1d3bb996
DG		 729 mutex_unlock(&dev->link_lock);
730}
731
732static void emac_tx_timeout(struct net_device *ndev)
733{
734 struct emac_instance *dev = netdev_priv(ndev);
735
736 DBG(dev, "tx_timeout" NL);
737
738 schedule_work(&dev->reset_work);
739}
740
741
742static inline int emac_phy_done(struct emac_instance *dev, u32 stacr)
743{
744 int done = !!(stacr & EMAC_STACR_OC);
745
746 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
747 done = !done;
748
749 return done;
750};
751
752static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg)
753{
754 struct emac_regs __iomem *p = dev->emacp;
755 u32 r = 0;
756 int n, err = -ETIMEDOUT;
757
758 mutex_lock(&dev->mdio_lock);
759
760 DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg);
761
762 /* Enable proper MDIO port */
763 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
764 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
765 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
766 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
767
768 /* Wait for management interface to become idle */
cca87c18 769 n = 20;
1d3bb996
DG		 770 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
771 udelay(1);
772 if (!--n) {
773 DBG2(dev, " -> timeout wait idle\n");
774 goto bail;
775 }
776 }
777
778 /* Issue read command */
779 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
780 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
781 else
782 r = EMAC_STACR_BASE(dev->opb_bus_freq);
783 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
784 r |= EMAC_STACR_OC;
bff713b5 785 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
1d3bb996
DG		 786 r |= EMACX_STACR_STAC_READ;
787 else
788 r |= EMAC_STACR_STAC_READ;
789 r |= (reg & EMAC_STACR_PRA_MASK)
790 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT);
791 out_be32(&p->stacr, r);
792
793 /* Wait for read to complete */
cca87c18 794 n = 200;
1d3bb996
DG		 795 while (!emac_phy_done(dev, (r = in_be32(&p->stacr)))) {
796 udelay(1);
797 if (!--n) {
798 DBG2(dev, " -> timeout wait complete\n");
799 goto bail;
800 }
801 }
802
803 if (unlikely(r & EMAC_STACR_PHYE)) {
804 DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg);
805 err = -EREMOTEIO;
806 goto bail;
807 }
808
809 r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
810
811 DBG2(dev, "mdio_read -> %04x" NL, r);
812 err = 0;
813 bail:
814 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
815 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
816 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
817 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
818 mutex_unlock(&dev->mdio_lock);
819
820 return err == 0 ? r : err;
821}
822
823static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg,
824 u16 val)
825{
826 struct emac_regs __iomem *p = dev->emacp;
827 u32 r = 0;
828 int n, err = -ETIMEDOUT;
829
830 mutex_lock(&dev->mdio_lock);
831
832 DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val);
833
834 /* Enable proper MDIO port */
835 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
836 zmii_get_mdio(dev->zmii_dev, dev->zmii_port);
837 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
838 rgmii_get_mdio(dev->rgmii_dev, dev->rgmii_port);
839
840 /* Wait for management interface to be idle */
cca87c18 841 n = 20;
1d3bb996
DG		 842 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
843 udelay(1);
844 if (!--n) {
845 DBG2(dev, " -> timeout wait idle\n");
846 goto bail;
847 }
848 }
849
850 /* Issue write command */
851 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
852 r = EMAC4_STACR_BASE(dev->opb_bus_freq);
853 else
854 r = EMAC_STACR_BASE(dev->opb_bus_freq);
855 if (emac_has_feature(dev, EMAC_FTR_STACR_OC_INVERT))
856 r |= EMAC_STACR_OC;
bff713b5 857 if (emac_has_feature(dev, EMAC_FTR_HAS_NEW_STACR))
1d3bb996
DG		 858 r |= EMACX_STACR_STAC_WRITE;
859 else
860 r |= EMAC_STACR_STAC_WRITE;
861 r |= (reg & EMAC_STACR_PRA_MASK) |
862 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
863 (val << EMAC_STACR_PHYD_SHIFT);
864 out_be32(&p->stacr, r);
865
866 /* Wait for write to complete */
cca87c18 867 n = 200;
1d3bb996
DG		 868 while (!emac_phy_done(dev, in_be32(&p->stacr))) {
869 udelay(1);
870 if (!--n) {
871 DBG2(dev, " -> timeout wait complete\n");
872 goto bail;
873 }
874 }
875 err = 0;
876 bail:
877 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
878 rgmii_put_mdio(dev->rgmii_dev, dev->rgmii_port);
879 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
880 zmii_put_mdio(dev->zmii_dev, dev->zmii_port);
881 mutex_unlock(&dev->mdio_lock);
882}
883
884static int emac_mdio_read(struct net_device *ndev, int id, int reg)
885{
886 struct emac_instance *dev = netdev_priv(ndev);
887 int res;
888
9e3cb294
VG		 889 res = __emac_mdio_read((dev->mdio_instance &&
890 dev->phy.gpcs_address != id) ?
891 dev->mdio_instance : dev,
1d3bb996
DG		 892 (u8) id, (u8) reg);
893 return res;
894}
895
896static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
897{
898 struct emac_instance *dev = netdev_priv(ndev);
899
9e3cb294
VG		 900 __emac_mdio_write((dev->mdio_instance &&
901 dev->phy.gpcs_address != id) ?
902 dev->mdio_instance : dev,
1d3bb996
DG		 903 (u8) id, (u8) reg, (u16) val);
904}
905
906/* Tx lock BH */
907static void __emac_set_multicast_list(struct emac_instance *dev)
908{
909 struct emac_regs __iomem *p = dev->emacp;
910 u32 rmr = emac_iff2rmr(dev->ndev);
911
912 DBG(dev, "__multicast %08x" NL, rmr);
913
914 /* I decided to relax register access rules here to avoid
915 * full EMAC reset.
916 *
917 * There is a real problem with EMAC4 core if we use MWSW_001 bit
918 * in MR1 register and do a full EMAC reset.
919 * One TX BD status update is delayed and, after EMAC reset, it
920 * never happens, resulting in TX hung (it'll be recovered by TX
921 * timeout handler eventually, but this is just gross).
922 * So we either have to do full TX reset or try to cheat here :)
923 *
924 * The only required change is to RX mode register, so I *think* all
925 * we need is just to stop RX channel. This seems to work on all
926 * tested SoCs. --ebs
927 *
928 * If we need the full reset, we might just trigger the workqueue
929 * and do it async... a bit nasty but should work --BenH
930 */
931 dev->mcast_pending = 0;
932 emac_rx_disable(dev);
933 if (rmr & EMAC_RMR_MAE)
934 emac_hash_mc(dev);
935 out_be32(&p->rmr, rmr);
936 emac_rx_enable(dev);
937}
938
939/* Tx lock BH */
940static void emac_set_multicast_list(struct net_device *ndev)
941{
942 struct emac_instance *dev = netdev_priv(ndev);
943
944 DBG(dev, "multicast" NL);
945
946 BUG_ON(!netif_running(dev->ndev));
947
948 if (dev->no_mcast) {
949 dev->mcast_pending = 1;
950 return;
951 }
952 __emac_set_multicast_list(dev);
953}
954
955static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
956{
957 int rx_sync_size = emac_rx_sync_size(new_mtu);
958 int rx_skb_size = emac_rx_skb_size(new_mtu);
959 int i, ret = 0;
960
961 mutex_lock(&dev->link_lock);
962 emac_netif_stop(dev);
963 emac_rx_disable(dev);
964 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
965
966 if (dev->rx_sg_skb) {
967 ++dev->estats.rx_dropped_resize;
968 dev_kfree_skb(dev->rx_sg_skb);
969 dev->rx_sg_skb = NULL;
970 }
971
972 /* Make a first pass over RX ring and mark BDs ready, dropping
973 * non-processed packets on the way. We need this as a separate pass
974 * to simplify error recovery in the case of allocation failure later.
975 */
976 for (i = 0; i < NUM_RX_BUFF; ++i) {
977 if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
978 ++dev->estats.rx_dropped_resize;
979
980 dev->rx_desc[i].data_len = 0;
981 dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
982 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
983 }
984
985 /* Reallocate RX ring only if bigger skb buffers are required */
986 if (rx_skb_size <= dev->rx_skb_size)
987 goto skip;
988
989 /* Second pass, allocate new skbs */
990 for (i = 0; i < NUM_RX_BUFF; ++i) {
991 struct sk_buff *skb = alloc_skb(rx_skb_size, GFP_ATOMIC);
992 if (!skb) {
993 ret = -ENOMEM;
994 goto oom;
995 }
996
997 BUG_ON(!dev->rx_skb[i]);
998 dev_kfree_skb(dev->rx_skb[i]);
999
1000 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1001 dev->rx_desc[i].data_ptr =
1002 dma_map_single(&dev->ofdev->dev, skb->data - 2, rx_sync_size,
1003 DMA_FROM_DEVICE) + 2;
1004 dev->rx_skb[i] = skb;
1005 }
1006 skip:
1007 /* Check if we need to change "Jumbo" bit in MR1 */
1008 if ((new_mtu > ETH_DATA_LEN) ^ (dev->ndev->mtu > ETH_DATA_LEN)) {
1009 /* This is to prevent starting RX channel in emac_rx_enable() */
1010 set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1011
1012 dev->ndev->mtu = new_mtu;
1013 emac_full_tx_reset(dev);
1014 }
1015
1016 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(new_mtu));
1017 oom:
1018 /* Restart RX */
1019 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1020 dev->rx_slot = 0;
1021 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1022 emac_rx_enable(dev);
1023 emac_netif_start(dev);
1024 mutex_unlock(&dev->link_lock);
1025
1026 return ret;
1027}
1028
1029/* Process ctx, rtnl_lock semaphore */
1030static int emac_change_mtu(struct net_device *ndev, int new_mtu)
1031{
1032 struct emac_instance *dev = netdev_priv(ndev);
1033 int ret = 0;
1034
1035 if (new_mtu < EMAC_MIN_MTU || new_mtu > dev->max_mtu)
1036 return -EINVAL;
1037
1038 DBG(dev, "change_mtu(%d)" NL, new_mtu);
1039
1040 if (netif_running(ndev)) {
1041 /* Check if we really need to reinitalize RX ring */
1042 if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
1043 ret = emac_resize_rx_ring(dev, new_mtu);
1044 }
1045
1046 if (!ret) {
1047 ndev->mtu = new_mtu;
1048 dev->rx_skb_size = emac_rx_skb_size(new_mtu);
1049 dev->rx_sync_size = emac_rx_sync_size(new_mtu);
1050 }
1051
1052 return ret;
1053}
1054
1055static void emac_clean_tx_ring(struct emac_instance *dev)
1056{
1057 int i;
1058
1059 for (i = 0; i < NUM_TX_BUFF; ++i) {
1060 if (dev->tx_skb[i]) {
1061 dev_kfree_skb(dev->tx_skb[i]);
1062 dev->tx_skb[i] = NULL;
1063 if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
1064 ++dev->estats.tx_dropped;
1065 }
1066 dev->tx_desc[i].ctrl = 0;
1067 dev->tx_desc[i].data_ptr = 0;
1068 }
1069}
1070
1071static void emac_clean_rx_ring(struct emac_instance *dev)
1072{
1073 int i;
1074
1075 for (i = 0; i < NUM_RX_BUFF; ++i)
1076 if (dev->rx_skb[i]) {
1077 dev->rx_desc[i].ctrl = 0;
1078 dev_kfree_skb(dev->rx_skb[i]);
1079 dev->rx_skb[i] = NULL;
1080 dev->rx_desc[i].data_ptr = 0;
1081 }
1082
1083 if (dev->rx_sg_skb) {
1084 dev_kfree_skb(dev->rx_sg_skb);
1085 dev->rx_sg_skb = NULL;
1086 }
1087}
1088
1089static inline int emac_alloc_rx_skb(struct emac_instance *dev, int slot,
1090 gfp_t flags)
1091{
1092 struct sk_buff *skb = alloc_skb(dev->rx_skb_size, flags);
1093 if (unlikely(!skb))
1094 return -ENOMEM;
1095
1096 dev->rx_skb[slot] = skb;
1097 dev->rx_desc[slot].data_len = 0;
1098
1099 skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
1100 dev->rx_desc[slot].data_ptr =
1101 dma_map_single(&dev->ofdev->dev, skb->data - 2, dev->rx_sync_size,
1102 DMA_FROM_DEVICE) + 2;
1103 wmb();
1104 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1105 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1106
1107 return 0;
1108}
1109
1110static void emac_print_link_status(struct emac_instance *dev)
1111{
1112 if (netif_carrier_ok(dev->ndev))
1113 printk(KERN_INFO "%s: link is up, %d %s%s\n",
1114 dev->ndev->name, dev->phy.speed,
1115 dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
1116 dev->phy.pause ? ", pause enabled" :
1117 dev->phy.asym_pause ? ", asymmetric pause enabled" : "");
1118 else
1119 printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
1120}
1121
1122/* Process ctx, rtnl_lock semaphore */
1123static int emac_open(struct net_device *ndev)
1124{
1125 struct emac_instance *dev = netdev_priv(ndev);
1126 int err, i;
1127
1128 DBG(dev, "open" NL);
1129
1130 /* Setup error IRQ handler */
1131 err = request_irq(dev->emac_irq, emac_irq, 0, "EMAC", dev);
1132 if (err) {
1133 printk(KERN_ERR "%s: failed to request IRQ %d\n",
1134 ndev->name, dev->emac_irq);
1135 return err;
1136 }
1137
1138 /* Allocate RX ring */
1139 for (i = 0; i < NUM_RX_BUFF; ++i)
1140 if (emac_alloc_rx_skb(dev, i, GFP_KERNEL)) {
1141 printk(KERN_ERR "%s: failed to allocate RX ring\n",
1142 ndev->name);
1143 goto oom;
1144 }
1145
1146 dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot = 0;
1147 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1148 dev->rx_sg_skb = NULL;
1149
1150 mutex_lock(&dev->link_lock);
61dbcece 1151 dev->opened = 1;
1d3bb996 1152
61dbcece 1153 /* Start PHY polling now.
1d3bb996
DG		 1154 */
1155 if (dev->phy.address >= 0) {
1156 int link_poll_interval;
1157 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1158 dev->phy.def->ops->read_link(&dev->phy);
11121e30 1159 emac_rx_clk_default(dev);
1d3bb996
DG		 1160 netif_carrier_on(dev->ndev);
1161 link_poll_interval = PHY_POLL_LINK_ON;
1162 } else {
11121e30 1163 emac_rx_clk_tx(dev);
1d3bb996
DG		 1164 netif_carrier_off(dev->ndev);
1165 link_poll_interval = PHY_POLL_LINK_OFF;
1166 }
1167 dev->link_polling = 1;
1168 wmb();
1169 schedule_delayed_work(&dev->link_work, link_poll_interval);
1170 emac_print_link_status(dev);
1171 } else
1172 netif_carrier_on(dev->ndev);
1173
e8296582
BH		 1174 /* Required for Pause packet support in EMAC */
1175 dev_mc_add(ndev, default_mcast_addr, sizeof(default_mcast_addr), 1);
1176
1d3bb996
DG		 1177 emac_configure(dev);
1178 mal_poll_add(dev->mal, &dev->commac);
1179 mal_enable_tx_channel(dev->mal, dev->mal_tx_chan);
1180 mal_set_rcbs(dev->mal, dev->mal_rx_chan, emac_rx_size(ndev->mtu));
1181 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1182 emac_tx_enable(dev);
1183 emac_rx_enable(dev);
1184 emac_netif_start(dev);
1185
1186 mutex_unlock(&dev->link_lock);
1187
1188 return 0;
1189 oom:
1190 emac_clean_rx_ring(dev);
1191 free_irq(dev->emac_irq, dev);
1192
1193 return -ENOMEM;
1194}
1195
1196/* BHs disabled */
1197#if 0
1198static int emac_link_differs(struct emac_instance *dev)
1199{
1200 u32 r = in_be32(&dev->emacp->mr1);
1201
1202 int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
1203 int speed, pause, asym_pause;
1204
1205 if (r & EMAC_MR1_MF_1000)
1206 speed = SPEED_1000;
1207 else if (r & EMAC_MR1_MF_100)
1208 speed = SPEED_100;
1209 else
1210 speed = SPEED_10;
1211
1212 switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
1213 case (EMAC_MR1_EIFC | EMAC_MR1_APP):
1214 pause = 1;
1215 asym_pause = 0;
1216 break;
1217 case EMAC_MR1_APP:
1218 pause = 0;
1219 asym_pause = 1;
1220 break;
1221 default:
1222 pause = asym_pause = 0;
1223 }
1224 return speed != dev->phy.speed || duplex != dev->phy.duplex ||
1225 pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
1226}
1227#endif
1228
1229static void emac_link_timer(struct work_struct *work)
1230{
1231 struct emac_instance *dev =
10fd9d7e 1232 container_of(to_delayed_work(work),
1d3bb996
DG		 1233 struct emac_instance, link_work);
1234 int link_poll_interval;
1235
1236 mutex_lock(&dev->link_lock);
1d3bb996
DG		 1237 DBG2(dev, "link timer" NL);
1238
61dbcece
BH		 1239 if (!dev->opened)
1240 goto bail;
1241
1d3bb996
DG		 1242 if (dev->phy.def->ops->poll_link(&dev->phy)) {
1243 if (!netif_carrier_ok(dev->ndev)) {
11121e30 1244 emac_rx_clk_default(dev);
1d3bb996
DG		 1245 /* Get new link parameters */
1246 dev->phy.def->ops->read_link(&dev->phy);
1247
1248 netif_carrier_on(dev->ndev);
1249 emac_netif_stop(dev);
1250 emac_full_tx_reset(dev);
1251 emac_netif_start(dev);
1252 emac_print_link_status(dev);
1253 }
1254 link_poll_interval = PHY_POLL_LINK_ON;
1255 } else {
1256 if (netif_carrier_ok(dev->ndev)) {
11121e30 1257 emac_rx_clk_tx(dev);
1d3bb996
DG		 1258 netif_carrier_off(dev->ndev);
1259 netif_tx_disable(dev->ndev);
911b237d 1260 emac_reinitialize(dev);
1d3bb996
DG		 1261 emac_print_link_status(dev);
1262 }
1263 link_poll_interval = PHY_POLL_LINK_OFF;
1264 }
1265 schedule_delayed_work(&dev->link_work, link_poll_interval);
61dbcece 1266 bail:
1d3bb996
DG		 1267 mutex_unlock(&dev->link_lock);
1268}
1269
1270static void emac_force_link_update(struct emac_instance *dev)
1271{
1272 netif_carrier_off(dev->ndev);
61dbcece 1273 smp_rmb();
1d3bb996
DG		 1274 if (dev->link_polling) {
1275 cancel_rearming_delayed_work(&dev->link_work);
1276 if (dev->link_polling)
1277 schedule_delayed_work(&dev->link_work, PHY_POLL_LINK_OFF);
1278 }
1279}
1280
1281/* Process ctx, rtnl_lock semaphore */
1282static int emac_close(struct net_device *ndev)
1283{
1284 struct emac_instance *dev = netdev_priv(ndev);
1285
1286 DBG(dev, "close" NL);
1287
61dbcece
BH		 1288 if (dev->phy.address >= 0) {
1289 dev->link_polling = 0;
1d3bb996 1290 cancel_rearming_delayed_work(&dev->link_work);
61dbcece
BH		 1291 }
1292 mutex_lock(&dev->link_lock);
1d3bb996 1293 emac_netif_stop(dev);
61dbcece
BH		 1294 dev->opened = 0;
1295 mutex_unlock(&dev->link_lock);
1d3bb996
DG		 1296
1297 emac_rx_disable(dev);
1298 emac_tx_disable(dev);
1299 mal_disable_rx_channel(dev->mal, dev->mal_rx_chan);
1300 mal_disable_tx_channel(dev->mal, dev->mal_tx_chan);
1301 mal_poll_del(dev->mal, &dev->commac);
1302
1303 emac_clean_tx_ring(dev);
1304 emac_clean_rx_ring(dev);
1305
1306 free_irq(dev->emac_irq, dev);
1307
d3b325f9
PG		 1308 netif_carrier_off(ndev);
1309
1d3bb996
DG		 1310 return 0;
1311}
1312
1313static inline u16 emac_tx_csum(struct emac_instance *dev,
1314 struct sk_buff *skb)
1315{
e66f4168
VB		 1316 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
1317 (skb->ip_summed == CHECKSUM_PARTIAL)) {
1d3bb996
DG		 1318 ++dev->stats.tx_packets_csum;
1319 return EMAC_TX_CTRL_TAH_CSUM;
1320 }
1321 return 0;
1322}
1323
1324static inline int emac_xmit_finish(struct emac_instance *dev, int len)
1325{
1326 struct emac_regs __iomem *p = dev->emacp;
1327 struct net_device *ndev = dev->ndev;
1328
1329 /* Send the packet out. If the if makes a significant perf
1330 * difference, then we can store the TMR0 value in "dev"
1331 * instead
1332 */
1333 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
1d3bb996 1334 out_be32(&p->tmr0, EMAC4_TMR0_XMIT);
07c2c76e 1335 else
1336 out_be32(&p->tmr0, EMAC_TMR0_XMIT);
1d3bb996
DG		 1337
1338 if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
1339 netif_stop_queue(ndev);
1340 DBG2(dev, "stopped TX queue" NL);
1341 }
1342
1343 ndev->trans_start = jiffies;
1344 ++dev->stats.tx_packets;
1345 dev->stats.tx_bytes += len;
1346
ec634fe3 1347 return NETDEV_TX_OK;
1d3bb996
DG		 1348}
1349
1350/* Tx lock BH */
1351static int emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1352{
1353 struct emac_instance *dev = netdev_priv(ndev);
1354 unsigned int len = skb->len;
1355 int slot;
1356
1357 u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1358 MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
1359
1360 slot = dev->tx_slot++;
1361 if (dev->tx_slot == NUM_TX_BUFF) {
1362 dev->tx_slot = 0;
1363 ctrl |= MAL_TX_CTRL_WRAP;
1364 }
1365
1366 DBG2(dev, "xmit(%u) %d" NL, len, slot);
1367
1368 dev->tx_skb[slot] = skb;
1369 dev->tx_desc[slot].data_ptr = dma_map_single(&dev->ofdev->dev,
1370 skb->data, len,
1371 DMA_TO_DEVICE);
1372 dev->tx_desc[slot].data_len = (u16) len;
1373 wmb();
1374 dev->tx_desc[slot].ctrl = ctrl;
1375
1376 return emac_xmit_finish(dev, len);
1377}
1378
1d3bb996
DG		 1379static inline int emac_xmit_split(struct emac_instance *dev, int slot,
1380 u32 pd, int len, int last, u16 base_ctrl)
1381{
1382 while (1) {
1383 u16 ctrl = base_ctrl;
1384 int chunk = min(len, MAL_MAX_TX_SIZE);
1385 len -= chunk;
1386
1387 slot = (slot + 1) % NUM_TX_BUFF;
1388
1389 if (last && !len)
1390 ctrl |= MAL_TX_CTRL_LAST;
1391 if (slot == NUM_TX_BUFF - 1)
1392 ctrl |= MAL_TX_CTRL_WRAP;
1393
1394 dev->tx_skb[slot] = NULL;
1395 dev->tx_desc[slot].data_ptr = pd;
1396 dev->tx_desc[slot].data_len = (u16) chunk;
1397 dev->tx_desc[slot].ctrl = ctrl;
1398 ++dev->tx_cnt;
1399
1400 if (!len)
1401 break;
1402
1403 pd += chunk;
1404 }
1405 return slot;
1406}
1407
1408/* Tx lock BH disabled (SG version for TAH equipped EMACs) */
1409static int emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
1410{
1411 struct emac_instance *dev = netdev_priv(ndev);
1412 int nr_frags = skb_shinfo(skb)->nr_frags;
1413 int len = skb->len, chunk;
1414 int slot, i;
1415 u16 ctrl;
1416 u32 pd;
1417
1418 /* This is common "fast" path */
1419 if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
1420 return emac_start_xmit(skb, ndev);
1421
1422 len -= skb->data_len;
1423
1424 /* Note, this is only an *estimation*, we can still run out of empty
1425 * slots because of the additional fragmentation into
1426 * MAL_MAX_TX_SIZE-sized chunks
1427 */
1428 if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
1429 goto stop_queue;
1430
1431 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
1432 emac_tx_csum(dev, skb);
1433 slot = dev->tx_slot;
1434
1435 /* skb data */
1436 dev->tx_skb[slot] = NULL;
1437 chunk = min(len, MAL_MAX_TX_SIZE);
1438 dev->tx_desc[slot].data_ptr = pd =
1439 dma_map_single(&dev->ofdev->dev, skb->data, len, DMA_TO_DEVICE);
1440 dev->tx_desc[slot].data_len = (u16) chunk;
1441 len -= chunk;
1442 if (unlikely(len))
1443 slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
1444 ctrl);
1445 /* skb fragments */
1446 for (i = 0; i < nr_frags; ++i) {
1447 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
1448 len = frag->size;
1449
1450 if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
1451 goto undo_frame;
1452
1453 pd = dma_map_page(&dev->ofdev->dev, frag->page, frag->page_offset, len,
1454 DMA_TO_DEVICE);
1455
1456 slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
1457 ctrl);
1458 }
1459
1460 DBG2(dev, "xmit_sg(%u) %d - %d" NL, skb->len, dev->tx_slot, slot);
1461
1462 /* Attach skb to the last slot so we don't release it too early */
1463 dev->tx_skb[slot] = skb;
1464
1465 /* Send the packet out */
1466 if (dev->tx_slot == NUM_TX_BUFF - 1)
1467 ctrl |= MAL_TX_CTRL_WRAP;
1468 wmb();
1469 dev->tx_desc[dev->tx_slot].ctrl = ctrl;
1470 dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
1471
1472 return emac_xmit_finish(dev, skb->len);
1473
1474 undo_frame:
1475 /* Well, too bad. Our previous estimation was overly optimistic.
1476 * Undo everything.
1477 */
1478 while (slot != dev->tx_slot) {
1479 dev->tx_desc[slot].ctrl = 0;
1480 --dev->tx_cnt;
1481 if (--slot < 0)
1482 slot = NUM_TX_BUFF - 1;
1483 }
1484 ++dev->estats.tx_undo;
1485
1486 stop_queue:
1487 netif_stop_queue(ndev);
1488 DBG2(dev, "stopped TX queue" NL);
5b548140 1489 return NETDEV_TX_BUSY;
1d3bb996 1490}
1d3bb996
DG		 1491
1492/* Tx lock BHs */
1493static void emac_parse_tx_error(struct emac_instance *dev, u16 ctrl)
1494{
1495 struct emac_error_stats *st = &dev->estats;
1496
1497 DBG(dev, "BD TX error %04x" NL, ctrl);
1498
1499 ++st->tx_bd_errors;
1500 if (ctrl & EMAC_TX_ST_BFCS)
1501 ++st->tx_bd_bad_fcs;
1502 if (ctrl & EMAC_TX_ST_LCS)
1503 ++st->tx_bd_carrier_loss;
1504 if (ctrl & EMAC_TX_ST_ED)
1505 ++st->tx_bd_excessive_deferral;
1506 if (ctrl & EMAC_TX_ST_EC)
1507 ++st->tx_bd_excessive_collisions;
1508 if (ctrl & EMAC_TX_ST_LC)
1509 ++st->tx_bd_late_collision;
1510 if (ctrl & EMAC_TX_ST_MC)
1511 ++st->tx_bd_multple_collisions;
1512 if (ctrl & EMAC_TX_ST_SC)
1513 ++st->tx_bd_single_collision;
1514 if (ctrl & EMAC_TX_ST_UR)
1515 ++st->tx_bd_underrun;
1516 if (ctrl & EMAC_TX_ST_SQE)
1517 ++st->tx_bd_sqe;
1518}
1519
1520static void emac_poll_tx(void *param)
1521{
1522 struct emac_instance *dev = param;
1523 u32 bad_mask;
1524
1525 DBG2(dev, "poll_tx, %d %d" NL, dev->tx_cnt, dev->ack_slot);
1526
1527 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
1528 bad_mask = EMAC_IS_BAD_TX_TAH;
1529 else
1530 bad_mask = EMAC_IS_BAD_TX;
1531
1532 netif_tx_lock_bh(dev->ndev);
1533 if (dev->tx_cnt) {
1534 u16 ctrl;
1535 int slot = dev->ack_slot, n = 0;
1536 again:
1537 ctrl = dev->tx_desc[slot].ctrl;
1538 if (!(ctrl & MAL_TX_CTRL_READY)) {
1539 struct sk_buff *skb = dev->tx_skb[slot];
1540 ++n;
1541
1542 if (skb) {
1543 dev_kfree_skb(skb);
1544 dev->tx_skb[slot] = NULL;
1545 }
1546 slot = (slot + 1) % NUM_TX_BUFF;
1547
1548 if (unlikely(ctrl & bad_mask))
1549 emac_parse_tx_error(dev, ctrl);
1550
1551 if (--dev->tx_cnt)
1552 goto again;
1553 }
1554 if (n) {
1555 dev->ack_slot = slot;
1556 if (netif_queue_stopped(dev->ndev) &&
1557 dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
1558 netif_wake_queue(dev->ndev);
1559
1560 DBG2(dev, "tx %d pkts" NL, n);
1561 }
1562 }
1563 netif_tx_unlock_bh(dev->ndev);
1564}
1565
1566static inline void emac_recycle_rx_skb(struct emac_instance *dev, int slot,
1567 int len)
1568{
1569 struct sk_buff *skb = dev->rx_skb[slot];
1570
1571 DBG2(dev, "recycle %d %d" NL, slot, len);
1572
1573 if (len)
1574 dma_map_single(&dev->ofdev->dev, skb->data - 2,
1575 EMAC_DMA_ALIGN(len + 2), DMA_FROM_DEVICE);
1576
1577 dev->rx_desc[slot].data_len = 0;
1578 wmb();
1579 dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
1580 (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
1581}
1582
1583static void emac_parse_rx_error(struct emac_instance *dev, u16 ctrl)
1584{
1585 struct emac_error_stats *st = &dev->estats;
1586
1587 DBG(dev, "BD RX error %04x" NL, ctrl);
1588
1589 ++st->rx_bd_errors;
1590 if (ctrl & EMAC_RX_ST_OE)
1591 ++st->rx_bd_overrun;
1592 if (ctrl & EMAC_RX_ST_BP)
1593 ++st->rx_bd_bad_packet;
1594 if (ctrl & EMAC_RX_ST_RP)
1595 ++st->rx_bd_runt_packet;
1596 if (ctrl & EMAC_RX_ST_SE)
1597 ++st->rx_bd_short_event;
1598 if (ctrl & EMAC_RX_ST_AE)
1599 ++st->rx_bd_alignment_error;
1600 if (ctrl & EMAC_RX_ST_BFCS)
1601 ++st->rx_bd_bad_fcs;
1602 if (ctrl & EMAC_RX_ST_PTL)
1603 ++st->rx_bd_packet_too_long;
1604 if (ctrl & EMAC_RX_ST_ORE)
1605 ++st->rx_bd_out_of_range;
1606 if (ctrl & EMAC_RX_ST_IRE)
1607 ++st->rx_bd_in_range;
1608}
1609
1610static inline void emac_rx_csum(struct emac_instance *dev,
1611 struct sk_buff *skb, u16 ctrl)
1612{
1613#ifdef CONFIG_IBM_NEW_EMAC_TAH
1614 if (!ctrl && dev->tah_dev) {
1615 skb->ip_summed = CHECKSUM_UNNECESSARY;
1616 ++dev->stats.rx_packets_csum;
1617 }
1618#endif
1619}
1620
1621static inline int emac_rx_sg_append(struct emac_instance *dev, int slot)
1622{
1623 if (likely(dev->rx_sg_skb != NULL)) {
1624 int len = dev->rx_desc[slot].data_len;
1625 int tot_len = dev->rx_sg_skb->len + len;
1626
1627 if (unlikely(tot_len + 2 > dev->rx_skb_size)) {
1628 ++dev->estats.rx_dropped_mtu;
1629 dev_kfree_skb(dev->rx_sg_skb);
1630 dev->rx_sg_skb = NULL;
1631 } else {
bef1bc95 1632 cacheable_memcpy(skb_tail_pointer(dev->rx_sg_skb),
1d3bb996
DG		 1633 dev->rx_skb[slot]->data, len);
1634 skb_put(dev->rx_sg_skb, len);
1635 emac_recycle_rx_skb(dev, slot, len);
1636 return 0;
1637 }
1638 }
1639 emac_recycle_rx_skb(dev, slot, 0);
1640 return -1;
1641}
1642
1643/* NAPI poll context */
1644static int emac_poll_rx(void *param, int budget)
1645{
1646 struct emac_instance *dev = param;
1647 int slot = dev->rx_slot, received = 0;
1648
1649 DBG2(dev, "poll_rx(%d)" NL, budget);
1650
1651 again:
1652 while (budget > 0) {
1653 int len;
1654 struct sk_buff *skb;
1655 u16 ctrl = dev->rx_desc[slot].ctrl;
1656
1657 if (ctrl & MAL_RX_CTRL_EMPTY)
1658 break;
1659
1660 skb = dev->rx_skb[slot];
1661 mb();
1662 len = dev->rx_desc[slot].data_len;
1663
1664 if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
1665 goto sg;
1666
1667 ctrl &= EMAC_BAD_RX_MASK;
1668 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1669 emac_parse_rx_error(dev, ctrl);
1670 ++dev->estats.rx_dropped_error;
1671 emac_recycle_rx_skb(dev, slot, 0);
1672 len = 0;
1673 goto next;
1674 }
6c688f42
SN		 1675
1676 if (len < ETH_HLEN) {
1677 ++dev->estats.rx_dropped_stack;
1678 emac_recycle_rx_skb(dev, slot, len);
1679 goto next;
1680 }
1d3bb996
DG		 1681
1682 if (len && len < EMAC_RX_COPY_THRESH) {
1683 struct sk_buff *copy_skb =
1684 alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC);
1685 if (unlikely(!copy_skb))
1686 goto oom;
1687
1688 skb_reserve(copy_skb, EMAC_RX_SKB_HEADROOM + 2);
1689 cacheable_memcpy(copy_skb->data - 2, skb->data - 2,
1690 len + 2);
1691 emac_recycle_rx_skb(dev, slot, len);
1692 skb = copy_skb;
1693 } else if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC)))
1694 goto oom;
1695
1696 skb_put(skb, len);
1697 push_packet:
1698 skb->dev = dev->ndev;
1699 skb->protocol = eth_type_trans(skb, dev->ndev);
1700 emac_rx_csum(dev, skb, ctrl);
1701
1702 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
1703 ++dev->estats.rx_dropped_stack;
1704 next:
1705 ++dev->stats.rx_packets;
1706 skip:
1707 dev->stats.rx_bytes += len;
1708 slot = (slot + 1) % NUM_RX_BUFF;
1709 --budget;
1710 ++received;
1711 continue;
1712 sg:
1713 if (ctrl & MAL_RX_CTRL_FIRST) {
1714 BUG_ON(dev->rx_sg_skb);
1715 if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC))) {
1716 DBG(dev, "rx OOM %d" NL, slot);
1717 ++dev->estats.rx_dropped_oom;
1718 emac_recycle_rx_skb(dev, slot, 0);
1719 } else {
1720 dev->rx_sg_skb = skb;
1721 skb_put(skb, len);
1722 }
1723 } else if (!emac_rx_sg_append(dev, slot) &&
1724 (ctrl & MAL_RX_CTRL_LAST)) {
1725
1726 skb = dev->rx_sg_skb;
1727 dev->rx_sg_skb = NULL;
1728
1729 ctrl &= EMAC_BAD_RX_MASK;
1730 if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
1731 emac_parse_rx_error(dev, ctrl);
1732 ++dev->estats.rx_dropped_error;
1733 dev_kfree_skb(skb);
1734 len = 0;
1735 } else
1736 goto push_packet;
1737 }
1738 goto skip;
1739 oom:
1740 DBG(dev, "rx OOM %d" NL, slot);
1741 /* Drop the packet and recycle skb */
1742 ++dev->estats.rx_dropped_oom;
1743 emac_recycle_rx_skb(dev, slot, 0);
1744 goto next;
1745 }
1746
1747 if (received) {
1748 DBG2(dev, "rx %d BDs" NL, received);
1749 dev->rx_slot = slot;
1750 }
1751
1752 if (unlikely(budget && test_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags))) {
1753 mb();
1754 if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
1755 DBG2(dev, "rx restart" NL);
1756 received = 0;
1757 goto again;
1758 }
1759
1760 if (dev->rx_sg_skb) {
1761 DBG2(dev, "dropping partial rx packet" NL);
1762 ++dev->estats.rx_dropped_error;
1763 dev_kfree_skb(dev->rx_sg_skb);
1764 dev->rx_sg_skb = NULL;
1765 }
1766
1767 clear_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
1768 mal_enable_rx_channel(dev->mal, dev->mal_rx_chan);
1769 emac_rx_enable(dev);
1770 dev->rx_slot = 0;
1771 }
1772 return received;
1773}
1774
1775/* NAPI poll context */
1776static int emac_peek_rx(void *param)
1777{
1778 struct emac_instance *dev = param;
1779
1780 return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
1781}
1782
1783/* NAPI poll context */
1784static int emac_peek_rx_sg(void *param)
1785{
1786 struct emac_instance *dev = param;
1787
1788 int slot = dev->rx_slot;
1789 while (1) {
1790 u16 ctrl = dev->rx_desc[slot].ctrl;
1791 if (ctrl & MAL_RX_CTRL_EMPTY)
1792 return 0;
1793 else if (ctrl & MAL_RX_CTRL_LAST)
1794 return 1;
1795
1796 slot = (slot + 1) % NUM_RX_BUFF;
1797
1798 /* I'm just being paranoid here :) */
1799 if (unlikely(slot == dev->rx_slot))
1800 return 0;
1801 }
1802}
1803
1804/* Hard IRQ */
1805static void emac_rxde(void *param)
1806{
1807 struct emac_instance *dev = param;
1808
1809 ++dev->estats.rx_stopped;
1810 emac_rx_disable_async(dev);
1811}
1812
1813/* Hard IRQ */
1814static irqreturn_t emac_irq(int irq, void *dev_instance)
1815{
1816 struct emac_instance *dev = dev_instance;
1817 struct emac_regs __iomem *p = dev->emacp;
1818 struct emac_error_stats *st = &dev->estats;
1819 u32 isr;
1820
1821 spin_lock(&dev->lock);
1822
1823 isr = in_be32(&p->isr);
1824 out_be32(&p->isr, isr);
1825
1826 DBG(dev, "isr = %08x" NL, isr);
1827
1828 if (isr & EMAC4_ISR_TXPE)
1829 ++st->tx_parity;
1830 if (isr & EMAC4_ISR_RXPE)
1831 ++st->rx_parity;
1832 if (isr & EMAC4_ISR_TXUE)
1833 ++st->tx_underrun;
1834 if (isr & EMAC4_ISR_RXOE)
1835 ++st->rx_fifo_overrun;
1836 if (isr & EMAC_ISR_OVR)
1837 ++st->rx_overrun;
1838 if (isr & EMAC_ISR_BP)
1839 ++st->rx_bad_packet;
1840 if (isr & EMAC_ISR_RP)
1841 ++st->rx_runt_packet;
1842 if (isr & EMAC_ISR_SE)
1843 ++st->rx_short_event;
1844 if (isr & EMAC_ISR_ALE)
1845 ++st->rx_alignment_error;
1846 if (isr & EMAC_ISR_BFCS)
1847 ++st->rx_bad_fcs;
1848 if (isr & EMAC_ISR_PTLE)
1849 ++st->rx_packet_too_long;
1850 if (isr & EMAC_ISR_ORE)
1851 ++st->rx_out_of_range;
1852 if (isr & EMAC_ISR_IRE)
1853 ++st->rx_in_range;
1854 if (isr & EMAC_ISR_SQE)
1855 ++st->tx_sqe;
1856 if (isr & EMAC_ISR_TE)
1857 ++st->tx_errors;
1858
1859 spin_unlock(&dev->lock);
1860
1861 return IRQ_HANDLED;
1862}
1863
1864static struct net_device_stats *emac_stats(struct net_device *ndev)
1865{
1866 struct emac_instance *dev = netdev_priv(ndev);
1867 struct emac_stats *st = &dev->stats;
1868 struct emac_error_stats *est = &dev->estats;
1869 struct net_device_stats *nst = &dev->nstats;
1870 unsigned long flags;
1871
1872 DBG2(dev, "stats" NL);
1873
1874 /* Compute "legacy" statistics */
1875 spin_lock_irqsave(&dev->lock, flags);
1876 nst->rx_packets = (unsigned long)st->rx_packets;
1877 nst->rx_bytes = (unsigned long)st->rx_bytes;
1878 nst->tx_packets = (unsigned long)st->tx_packets;
1879 nst->tx_bytes = (unsigned long)st->tx_bytes;
1880 nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
1881 est->rx_dropped_error +
1882 est->rx_dropped_resize +
1883 est->rx_dropped_mtu);
1884 nst->tx_dropped = (unsigned long)est->tx_dropped;
1885
1886 nst->rx_errors = (unsigned long)est->rx_bd_errors;
1887 nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
1888 est->rx_fifo_overrun +
1889 est->rx_overrun);
1890 nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
1891 est->rx_alignment_error);
1892 nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
1893 est->rx_bad_fcs);
1894 nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
1895 est->rx_bd_short_event +
1896 est->rx_bd_packet_too_long +
1897 est->rx_bd_out_of_range +
1898 est->rx_bd_in_range +
1899 est->rx_runt_packet +
1900 est->rx_short_event +
1901 est->rx_packet_too_long +
1902 est->rx_out_of_range +
1903 est->rx_in_range);
1904
1905 nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
1906 nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
1907 est->tx_underrun);
1908 nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
1909 nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
1910 est->tx_bd_excessive_collisions +
1911 est->tx_bd_late_collision +
1912 est->tx_bd_multple_collisions);
1913 spin_unlock_irqrestore(&dev->lock, flags);
1914 return nst;
1915}
1916
1917static struct mal_commac_ops emac_commac_ops = {
1918 .poll_tx = &emac_poll_tx,
1919 .poll_rx = &emac_poll_rx,
1920 .peek_rx = &emac_peek_rx,
1921 .rxde = &emac_rxde,
1922};
1923
1924static struct mal_commac_ops emac_commac_sg_ops = {
1925 .poll_tx = &emac_poll_tx,
1926 .poll_rx = &emac_poll_rx,
1927 .peek_rx = &emac_peek_rx_sg,
1928 .rxde = &emac_rxde,
1929};
1930
1931/* Ethtool support */
1932static int emac_ethtool_get_settings(struct net_device *ndev,
1933 struct ethtool_cmd *cmd)
1934{
1935 struct emac_instance *dev = netdev_priv(ndev);
1936
1937 cmd->supported = dev->phy.features;
1938 cmd->port = PORT_MII;
1939 cmd->phy_address = dev->phy.address;
1940 cmd->transceiver =
1941 dev->phy.address >= 0 ? XCVR_EXTERNAL : XCVR_INTERNAL;
1942
1943 mutex_lock(&dev->link_lock);
1944 cmd->advertising = dev->phy.advertising;
1945 cmd->autoneg = dev->phy.autoneg;
1946 cmd->speed = dev->phy.speed;
1947 cmd->duplex = dev->phy.duplex;
1948 mutex_unlock(&dev->link_lock);
1949
1950 return 0;
1951}
1952
1953static int emac_ethtool_set_settings(struct net_device *ndev,
1954 struct ethtool_cmd *cmd)
1955{
1956 struct emac_instance *dev = netdev_priv(ndev);
1957 u32 f = dev->phy.features;
1958
1959 DBG(dev, "set_settings(%d, %d, %d, 0x%08x)" NL,
1960 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1961
1962 /* Basic sanity checks */
1963 if (dev->phy.address < 0)
1964 return -EOPNOTSUPP;
1965 if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
1966 return -EINVAL;
1967 if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
1968 return -EINVAL;
1969 if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
1970 return -EINVAL;
1971
1972 if (cmd->autoneg == AUTONEG_DISABLE) {
1973 switch (cmd->speed) {
1974 case SPEED_10:
1975 if (cmd->duplex == DUPLEX_HALF
1976 && !(f & SUPPORTED_10baseT_Half))
1977 return -EINVAL;
1978 if (cmd->duplex == DUPLEX_FULL
1979 && !(f & SUPPORTED_10baseT_Full))
1980 return -EINVAL;
1981 break;
1982 case SPEED_100:
1983 if (cmd->duplex == DUPLEX_HALF
1984 && !(f & SUPPORTED_100baseT_Half))
1985 return -EINVAL;
1986 if (cmd->duplex == DUPLEX_FULL
1987 && !(f & SUPPORTED_100baseT_Full))
1988 return -EINVAL;
1989 break;
1990 case SPEED_1000:
1991 if (cmd->duplex == DUPLEX_HALF
1992 && !(f & SUPPORTED_1000baseT_Half))
1993 return -EINVAL;
1994 if (cmd->duplex == DUPLEX_FULL
1995 && !(f & SUPPORTED_1000baseT_Full))
1996 return -EINVAL;
1997 break;
1998 default:
1999 return -EINVAL;
2000 }
2001
2002 mutex_lock(&dev->link_lock);
2003 dev->phy.def->ops->setup_forced(&dev->phy, cmd->speed,
2004 cmd->duplex);
2005 mutex_unlock(&dev->link_lock);
2006
2007 } else {
2008 if (!(f & SUPPORTED_Autoneg))
2009 return -EINVAL;
2010
2011 mutex_lock(&dev->link_lock);
2012 dev->phy.def->ops->setup_aneg(&dev->phy,
2013 (cmd->advertising & f) |
2014 (dev->phy.advertising &
2015 (ADVERTISED_Pause |
2016 ADVERTISED_Asym_Pause)));
2017 mutex_unlock(&dev->link_lock);
2018 }
2019 emac_force_link_update(dev);
2020
2021 return 0;
2022}
2023
2024static void emac_ethtool_get_ringparam(struct net_device *ndev,
2025 struct ethtool_ringparam *rp)
2026{
2027 rp->rx_max_pending = rp->rx_pending = NUM_RX_BUFF;
2028 rp->tx_max_pending = rp->tx_pending = NUM_TX_BUFF;
2029}
2030
2031static void emac_ethtool_get_pauseparam(struct net_device *ndev,
2032 struct ethtool_pauseparam *pp)
2033{
2034 struct emac_instance *dev = netdev_priv(ndev);
2035
2036 mutex_lock(&dev->link_lock);
2037 if ((dev->phy.features & SUPPORTED_Autoneg) &&
2038 (dev->phy.advertising & (ADVERTISED_Pause | ADVERTISED_Asym_Pause)))
2039 pp->autoneg = 1;
2040
2041 if (dev->phy.duplex == DUPLEX_FULL) {
2042 if (dev->phy.pause)
2043 pp->rx_pause = pp->tx_pause = 1;
2044 else if (dev->phy.asym_pause)
2045 pp->tx_pause = 1;
2046 }
2047 mutex_unlock(&dev->link_lock);
2048}
2049
2050static u32 emac_ethtool_get_rx_csum(struct net_device *ndev)
2051{
2052 struct emac_instance *dev = netdev_priv(ndev);
2053
eb4d84f1 2054 return dev->tah_dev != NULL;
1d3bb996
DG		 2055}
2056
2057static int emac_get_regs_len(struct emac_instance *dev)
2058{
2059 if (emac_has_feature(dev, EMAC_FTR_EMAC4))
2060 return sizeof(struct emac_ethtool_regs_subhdr) +
05781ccd 2061 EMAC4_ETHTOOL_REGS_SIZE(dev);
1d3bb996
DG		 2062 else
2063 return sizeof(struct emac_ethtool_regs_subhdr) +
05781ccd 2064 EMAC_ETHTOOL_REGS_SIZE(dev);
1d3bb996
DG		 2065}
2066
2067static int emac_ethtool_get_regs_len(struct net_device *ndev)
2068{
2069 struct emac_instance *dev = netdev_priv(ndev);
2070 int size;
2071
2072 size = sizeof(struct emac_ethtool_regs_hdr) +
2073 emac_get_regs_len(dev) + mal_get_regs_len(dev->mal);
2074 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2075 size += zmii_get_regs_len(dev->zmii_dev);
2076 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2077 size += rgmii_get_regs_len(dev->rgmii_dev);
2078 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2079 size += tah_get_regs_len(dev->tah_dev);
2080
2081 return size;
2082}
2083
2084static void *emac_dump_regs(struct emac_instance *dev, void *buf)
2085{
2086 struct emac_ethtool_regs_subhdr *hdr = buf;
2087
2088 hdr->index = dev->cell_index;
2089 if (emac_has_feature(dev, EMAC_FTR_EMAC4)) {
2090 hdr->version = EMAC4_ETHTOOL_REGS_VER;
05781ccd
GE		 2091 memcpy_fromio(hdr + 1, dev->emacp, EMAC4_ETHTOOL_REGS_SIZE(dev));
2092 return ((void *)(hdr + 1) + EMAC4_ETHTOOL_REGS_SIZE(dev));
1d3bb996
DG		 2093 } else {
2094 hdr->version = EMAC_ETHTOOL_REGS_VER;
05781ccd
GE		 2095 memcpy_fromio(hdr + 1, dev->emacp, EMAC_ETHTOOL_REGS_SIZE(dev));
2096 return ((void *)(hdr + 1) + EMAC_ETHTOOL_REGS_SIZE(dev));
1d3bb996
DG		 2097 }
2098}
2099
2100static void emac_ethtool_get_regs(struct net_device *ndev,
2101 struct ethtool_regs *regs, void *buf)
2102{
2103 struct emac_instance *dev = netdev_priv(ndev);
2104 struct emac_ethtool_regs_hdr *hdr = buf;
2105
2106 hdr->components = 0;
2107 buf = hdr + 1;
2108
2109 buf = mal_dump_regs(dev->mal, buf);
2110 buf = emac_dump_regs(dev, buf);
2111 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII)) {
2112 hdr->components |= EMAC_ETHTOOL_REGS_ZMII;
2113 buf = zmii_dump_regs(dev->zmii_dev, buf);
2114 }
2115 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII)) {
2116 hdr->components |= EMAC_ETHTOOL_REGS_RGMII;
2117 buf = rgmii_dump_regs(dev->rgmii_dev, buf);
2118 }
2119 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH)) {
2120 hdr->components |= EMAC_ETHTOOL_REGS_TAH;
2121 buf = tah_dump_regs(dev->tah_dev, buf);
2122 }
2123}
2124
2125static int emac_ethtool_nway_reset(struct net_device *ndev)
2126{
2127 struct emac_instance *dev = netdev_priv(ndev);
2128 int res = 0;
2129
2130 DBG(dev, "nway_reset" NL);
2131
2132 if (dev->phy.address < 0)
2133 return -EOPNOTSUPP;
2134
2135 mutex_lock(&dev->link_lock);
2136 if (!dev->phy.autoneg) {
2137 res = -EINVAL;
2138 goto out;
2139 }
2140
2141 dev->phy.def->ops->setup_aneg(&dev->phy, dev->phy.advertising);
2142 out:
2143 mutex_unlock(&dev->link_lock);
2144 emac_force_link_update(dev);
2145 return res;
2146}
2147
2148static int emac_ethtool_get_stats_count(struct net_device *ndev)
2149{
2150 return EMAC_ETHTOOL_STATS_COUNT;
2151}
2152
2153static void emac_ethtool_get_strings(struct net_device *ndev, u32 stringset,
2154 u8 * buf)
2155{
2156 if (stringset == ETH_SS_STATS)
2157 memcpy(buf, &emac_stats_keys, sizeof(emac_stats_keys));
2158}
2159
2160static void emac_ethtool_get_ethtool_stats(struct net_device *ndev,
2161 struct ethtool_stats *estats,
2162 u64 * tmp_stats)
2163{
2164 struct emac_instance *dev = netdev_priv(ndev);
2165
2166 memcpy(tmp_stats, &dev->stats, sizeof(dev->stats));
2167 tmp_stats += sizeof(dev->stats) / sizeof(u64);
2168 memcpy(tmp_stats, &dev->estats, sizeof(dev->estats));
2169}
2170
2171static void emac_ethtool_get_drvinfo(struct net_device *ndev,
2172 struct ethtool_drvinfo *info)
2173{
2174 struct emac_instance *dev = netdev_priv(ndev);
2175
2176 strcpy(info->driver, "ibm_emac");
2177 strcpy(info->version, DRV_VERSION);
2178 info->fw_version[0] = '\0';
2179 sprintf(info->bus_info, "PPC 4xx EMAC-%d %s",
2180 dev->cell_index, dev->ofdev->node->full_name);
2181 info->n_stats = emac_ethtool_get_stats_count(ndev);
2182 info->regdump_len = emac_ethtool_get_regs_len(ndev);
2183}
2184
2185static const struct ethtool_ops emac_ethtool_ops = {
2186 .get_settings = emac_ethtool_get_settings,
2187 .set_settings = emac_ethtool_set_settings,
2188 .get_drvinfo = emac_ethtool_get_drvinfo,
2189
2190 .get_regs_len = emac_ethtool_get_regs_len,
2191 .get_regs = emac_ethtool_get_regs,
2192
2193 .nway_reset = emac_ethtool_nway_reset,
2194
2195 .get_ringparam = emac_ethtool_get_ringparam,
2196 .get_pauseparam = emac_ethtool_get_pauseparam,
2197
2198 .get_rx_csum = emac_ethtool_get_rx_csum,
2199
2200 .get_strings = emac_ethtool_get_strings,
2201 .get_stats_count = emac_ethtool_get_stats_count,
2202 .get_ethtool_stats = emac_ethtool_get_ethtool_stats,
2203
2204 .get_link = ethtool_op_get_link,
2205 .get_tx_csum = ethtool_op_get_tx_csum,
2206 .get_sg = ethtool_op_get_sg,
2207};
2208
2209static int emac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2210{
2211 struct emac_instance *dev = netdev_priv(ndev);
2212 uint16_t *data = (uint16_t *) & rq->ifr_ifru;
2213
2214 DBG(dev, "ioctl %08x" NL, cmd);
2215
2216 if (dev->phy.address < 0)
2217 return -EOPNOTSUPP;
2218
2219 switch (cmd) {
2220 case SIOCGMIIPHY:
1d3bb996
DG		 2221 data[0] = dev->phy.address;
2222 /* Fall through */
2223 case SIOCGMIIREG:
1d3bb996
DG		 2224 data[3] = emac_mdio_read(ndev, dev->phy.address, data[1]);
2225 return 0;
2226
2227 case SIOCSMIIREG:
1d3bb996
DG		 2228 emac_mdio_write(ndev, dev->phy.address, data[1], data[2]);
2229 return 0;
2230 default:
2231 return -EOPNOTSUPP;
2232 }
2233}
2234
2235struct emac_depentry {
2236 u32 phandle;
2237 struct device_node *node;
2238 struct of_device *ofdev;
2239 void *drvdata;
2240};
2241
2242#define EMAC_DEP_MAL_IDX 0
2243#define EMAC_DEP_ZMII_IDX 1
2244#define EMAC_DEP_RGMII_IDX 2
2245#define EMAC_DEP_TAH_IDX 3
2246#define EMAC_DEP_MDIO_IDX 4
2247#define EMAC_DEP_PREV_IDX 5
2248#define EMAC_DEP_COUNT 6
2249
2250static int __devinit emac_check_deps(struct emac_instance *dev,
2251 struct emac_depentry *deps)
2252{
2253 int i, there = 0;
2254 struct device_node *np;
2255
2256 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2257 /* no dependency on that item, allright */
2258 if (deps[i].phandle == 0) {
2259 there++;
2260 continue;
2261 }
2262 /* special case for blist as the dependency might go away */
2263 if (i == EMAC_DEP_PREV_IDX) {
2264 np = *(dev->blist - 1);
2265 if (np == NULL) {
2266 deps[i].phandle = 0;
2267 there++;
2268 continue;
2269 }
2270 if (deps[i].node == NULL)
2271 deps[i].node = of_node_get(np);
2272 }
2273 if (deps[i].node == NULL)
2274 deps[i].node = of_find_node_by_phandle(deps[i].phandle);
2275 if (deps[i].node == NULL)
2276 continue;
2277 if (deps[i].ofdev == NULL)
2278 deps[i].ofdev = of_find_device_by_node(deps[i].node);
2279 if (deps[i].ofdev == NULL)
2280 continue;
2281 if (deps[i].drvdata == NULL)
2282 deps[i].drvdata = dev_get_drvdata(&deps[i].ofdev->dev);
2283 if (deps[i].drvdata != NULL)
2284 there++;
2285 }
2286 return (there == EMAC_DEP_COUNT);
2287}
2288
2289static void emac_put_deps(struct emac_instance *dev)
2290{
2291 if (dev->mal_dev)
2292 of_dev_put(dev->mal_dev);
2293 if (dev->zmii_dev)
2294 of_dev_put(dev->zmii_dev);
2295 if (dev->rgmii_dev)
2296 of_dev_put(dev->rgmii_dev);
2297 if (dev->mdio_dev)
2298 of_dev_put(dev->mdio_dev);
2299 if (dev->tah_dev)
2300 of_dev_put(dev->tah_dev);
2301}
2302
2303static int __devinit emac_of_bus_notify(struct notifier_block *nb,
2304 unsigned long action, void *data)
2305{
2306 /* We are only intereted in device addition */
2307 if (action == BUS_NOTIFY_BOUND_DRIVER)
2308 wake_up_all(&emac_probe_wait);
2309 return 0;
2310}
2311
51d4a1cc 2312static struct notifier_block emac_of_bus_notifier __devinitdata = {
1d3bb996
DG		 2313 .notifier_call = emac_of_bus_notify
2314};
2315
2316static int __devinit emac_wait_deps(struct emac_instance *dev)
2317{
2318 struct emac_depentry deps[EMAC_DEP_COUNT];
2319 int i, err;
2320
2321 memset(&deps, 0, sizeof(deps));
2322
2323 deps[EMAC_DEP_MAL_IDX].phandle = dev->mal_ph;
2324 deps[EMAC_DEP_ZMII_IDX].phandle = dev->zmii_ph;
2325 deps[EMAC_DEP_RGMII_IDX].phandle = dev->rgmii_ph;
2326 if (dev->tah_ph)
2327 deps[EMAC_DEP_TAH_IDX].phandle = dev->tah_ph;
2328 if (dev->mdio_ph)
2329 deps[EMAC_DEP_MDIO_IDX].phandle = dev->mdio_ph;
2330 if (dev->blist && dev->blist > emac_boot_list)
2331 deps[EMAC_DEP_PREV_IDX].phandle = 0xffffffffu;
2332 bus_register_notifier(&of_platform_bus_type, &emac_of_bus_notifier);
2333 wait_event_timeout(emac_probe_wait,
2334 emac_check_deps(dev, deps),
2335 EMAC_PROBE_DEP_TIMEOUT);
2336 bus_unregister_notifier(&of_platform_bus_type, &emac_of_bus_notifier);
2337 err = emac_check_deps(dev, deps) ? 0 : -ENODEV;
2338 for (i = 0; i < EMAC_DEP_COUNT; i++) {
2339 if (deps[i].node)
2340 of_node_put(deps[i].node);
2341 if (err && deps[i].ofdev)
2342 of_dev_put(deps[i].ofdev);
2343 }
2344 if (err == 0) {
2345 dev->mal_dev = deps[EMAC_DEP_MAL_IDX].ofdev;
2346 dev->zmii_dev = deps[EMAC_DEP_ZMII_IDX].ofdev;
2347 dev->rgmii_dev = deps[EMAC_DEP_RGMII_IDX].ofdev;
2348 dev->tah_dev = deps[EMAC_DEP_TAH_IDX].ofdev;
2349 dev->mdio_dev = deps[EMAC_DEP_MDIO_IDX].ofdev;
2350 }
2351 if (deps[EMAC_DEP_PREV_IDX].ofdev)
2352 of_dev_put(deps[EMAC_DEP_PREV_IDX].ofdev);
2353 return err;
2354}
2355
2356static int __devinit emac_read_uint_prop(struct device_node *np, const char *name,
2357 u32 *val, int fatal)
2358{
2359 int len;
2360 const u32 *prop = of_get_property(np, name, &len);
2361 if (prop == NULL || len < sizeof(u32)) {
2362 if (fatal)
2363 printk(KERN_ERR "%s: missing %s property\n",
2364 np->full_name, name);
2365 return -ENODEV;
2366 }
2367 *val = *prop;
2368 return 0;
2369}
2370
2371static int __devinit emac_init_phy(struct emac_instance *dev)
2372{
2373 struct device_node *np = dev->ofdev->node;
2374 struct net_device *ndev = dev->ndev;
2375 u32 phy_map, adv;
2376 int i;
2377
2378 dev->phy.dev = ndev;
2379 dev->phy.mode = dev->phy_mode;
2380
2381 /* PHY-less configuration.
2382 * XXX I probably should move these settings to the dev tree
2383 */
2384 if (dev->phy_address == 0xffffffff && dev->phy_map == 0xffffffff) {
2385 emac_reset(dev);
2386
2387 /* PHY-less configuration.
2388 * XXX I probably should move these settings to the dev tree
2389 */
2390 dev->phy.address = -1;
9e3cb294
VG		 2391 dev->phy.features = SUPPORTED_MII;
2392 if (emac_phy_supports_gige(dev->phy_mode))
2393 dev->phy.features |= SUPPORTED_1000baseT_Full;
2394 else
2395 dev->phy.features |= SUPPORTED_100baseT_Full;
1d3bb996
DG		 2396 dev->phy.pause = 1;
2397
2398 return 0;
2399 }
2400
2401 mutex_lock(&emac_phy_map_lock);
2402 phy_map = dev->phy_map | busy_phy_map;
2403
2404 DBG(dev, "PHY maps %08x %08x" NL, dev->phy_map, busy_phy_map);
2405
2406 dev->phy.mdio_read = emac_mdio_read;
2407 dev->phy.mdio_write = emac_mdio_write;
2408
0925ab5d
VB		 2409 /* Enable internal clock source */
2410#ifdef CONFIG_PPC_DCR_NATIVE
2411 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2412 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
11121e30
VB		 2413#endif
2414 /* PHY clock workaround */
2415 emac_rx_clk_tx(dev);
2416
2417 /* Enable internal clock source on 440GX*/
2418#ifdef CONFIG_PPC_DCR_NATIVE
2419 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2420 dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
0925ab5d 2421#endif
1d3bb996
DG		 2422 /* Configure EMAC with defaults so we can at least use MDIO
2423 * This is needed mostly for 440GX
2424 */
2425 if (emac_phy_gpcs(dev->phy.mode)) {
2426 /* XXX
2427 * Make GPCS PHY address equal to EMAC index.
2428 * We probably should take into account busy_phy_map
2429 * and/or phy_map here.
2430 *
2431 * Note that the busy_phy_map is currently global
2432 * while it should probably be per-ASIC...
2433 */
9e3cb294
VG		 2434 dev->phy.gpcs_address = dev->gpcs_address;
2435 if (dev->phy.gpcs_address == 0xffffffff)
2436 dev->phy.address = dev->cell_index;
1d3bb996
DG		 2437 }
2438
2439 emac_configure(dev);
2440
2441 if (dev->phy_address != 0xffffffff)
2442 phy_map = ~(1 << dev->phy_address);
2443
2444 for (i = 0; i < 0x20; phy_map >>= 1, ++i)
2445 if (!(phy_map & 1)) {
2446 int r;
2447 busy_phy_map |= 1 << i;
2448
2449 /* Quick check if there is a PHY at the address */
2450 r = emac_mdio_read(dev->ndev, i, MII_BMCR);
2451 if (r == 0xffff || r < 0)
2452 continue;
2453 if (!emac_mii_phy_probe(&dev->phy, i))
2454 break;
2455 }
0925ab5d
VB		 2456
2457 /* Enable external clock source */
2458#ifdef CONFIG_PPC_DCR_NATIVE
2459 if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
2460 dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0);
2461#endif
1d3bb996
DG		 2462 mutex_unlock(&emac_phy_map_lock);
2463 if (i == 0x20) {
2464 printk(KERN_WARNING "%s: can't find PHY!\n", np->full_name);
2465 return -ENXIO;
2466 }
2467
2468 /* Init PHY */
2469 if (dev->phy.def->ops->init)
2470 dev->phy.def->ops->init(&dev->phy);
2471
2472 /* Disable any PHY features not supported by the platform */
2473 dev->phy.def->features &= ~dev->phy_feat_exc;
2474
2475 /* Setup initial link parameters */
2476 if (dev->phy.features & SUPPORTED_Autoneg) {
2477 adv = dev->phy.features;
2478 if (!emac_has_feature(dev, EMAC_FTR_NO_FLOW_CONTROL_40x))
2479 adv |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
2480 /* Restart autonegotiation */
2481 dev->phy.def->ops->setup_aneg(&dev->phy, adv);
2482 } else {
2483 u32 f = dev->phy.def->features;
2484 int speed = SPEED_10, fd = DUPLEX_HALF;
2485
2486 /* Select highest supported speed/duplex */
2487 if (f & SUPPORTED_1000baseT_Full) {
2488 speed = SPEED_1000;
2489 fd = DUPLEX_FULL;
2490 } else if (f & SUPPORTED_1000baseT_Half)
2491 speed = SPEED_1000;
2492 else if (f & SUPPORTED_100baseT_Full) {
2493 speed = SPEED_100;
2494 fd = DUPLEX_FULL;
2495 } else if (f & SUPPORTED_100baseT_Half)
2496 speed = SPEED_100;
2497 else if (f & SUPPORTED_10baseT_Full)
2498 fd = DUPLEX_FULL;
2499
2500 /* Force link parameters */
2501 dev->phy.def->ops->setup_forced(&dev->phy, speed, fd);
2502 }
2503 return 0;
2504}
2505
2506static int __devinit emac_init_config(struct emac_instance *dev)
2507{
2508 struct device_node *np = dev->ofdev->node;
2509 const void *p;
2510 unsigned int plen;
2511 const char *pm, *phy_modes[] = {
2512 [PHY_MODE_NA] = "",
2513 [PHY_MODE_MII] = "mii",
2514 [PHY_MODE_RMII] = "rmii",
2515 [PHY_MODE_SMII] = "smii",
2516 [PHY_MODE_RGMII] = "rgmii",
2517 [PHY_MODE_TBI] = "tbi",
2518 [PHY_MODE_GMII] = "gmii",
2519 [PHY_MODE_RTBI] = "rtbi",
2520 [PHY_MODE_SGMII] = "sgmii",
2521 };
2522
2523 /* Read config from device-tree */
2524 if (emac_read_uint_prop(np, "mal-device", &dev->mal_ph, 1))
2525 return -ENXIO;
2526 if (emac_read_uint_prop(np, "mal-tx-channel", &dev->mal_tx_chan, 1))
2527 return -ENXIO;
2528 if (emac_read_uint_prop(np, "mal-rx-channel", &dev->mal_rx_chan, 1))
2529 return -ENXIO;
2530 if (emac_read_uint_prop(np, "cell-index", &dev->cell_index, 1))
2531 return -ENXIO;
2532 if (emac_read_uint_prop(np, "max-frame-size", &dev->max_mtu, 0))
2533 dev->max_mtu = 1500;
2534 if (emac_read_uint_prop(np, "rx-fifo-size", &dev->rx_fifo_size, 0))
2535 dev->rx_fifo_size = 2048;
2536 if (emac_read_uint_prop(np, "tx-fifo-size", &dev->tx_fifo_size, 0))
2537 dev->tx_fifo_size = 2048;
2538 if (emac_read_uint_prop(np, "rx-fifo-size-gige", &dev->rx_fifo_size_gige, 0))
2539 dev->rx_fifo_size_gige = dev->rx_fifo_size;
2540 if (emac_read_uint_prop(np, "tx-fifo-size-gige", &dev->tx_fifo_size_gige, 0))
2541 dev->tx_fifo_size_gige = dev->tx_fifo_size;
2542 if (emac_read_uint_prop(np, "phy-address", &dev->phy_address, 0))
2543 dev->phy_address = 0xffffffff;
2544 if (emac_read_uint_prop(np, "phy-map", &dev->phy_map, 0))
2545 dev->phy_map = 0xffffffff;
9e3cb294
VG		 2546 if (emac_read_uint_prop(np, "gpcs-address", &dev->gpcs_address, 0))
2547 dev->gpcs_address = 0xffffffff;
1d3bb996
DG		 2548 if (emac_read_uint_prop(np->parent, "clock-frequency", &dev->opb_bus_freq, 1))
2549 return -ENXIO;
2550 if (emac_read_uint_prop(np, "tah-device", &dev->tah_ph, 0))
2551 dev->tah_ph = 0;
2552 if (emac_read_uint_prop(np, "tah-channel", &dev->tah_port, 0))
63b6cad7 2553 dev->tah_port = 0;
1d3bb996
DG		 2554 if (emac_read_uint_prop(np, "mdio-device", &dev->mdio_ph, 0))
2555 dev->mdio_ph = 0;
2556 if (emac_read_uint_prop(np, "zmii-device", &dev->zmii_ph, 0))
2557 dev->zmii_ph = 0;;
2558 if (emac_read_uint_prop(np, "zmii-channel", &dev->zmii_port, 0))
2559 dev->zmii_port = 0xffffffff;;
2560 if (emac_read_uint_prop(np, "rgmii-device", &dev->rgmii_ph, 0))
2561 dev->rgmii_ph = 0;;
2562 if (emac_read_uint_prop(np, "rgmii-channel", &dev->rgmii_port, 0))
2563 dev->rgmii_port = 0xffffffff;;
2564 if (emac_read_uint_prop(np, "fifo-entry-size", &dev->fifo_entry_size, 0))
2565 dev->fifo_entry_size = 16;
2566 if (emac_read_uint_prop(np, "mal-burst-size", &dev->mal_burst_size, 0))
2567 dev->mal_burst_size = 256;
2568
2569 /* PHY mode needs some decoding */
2570 dev->phy_mode = PHY_MODE_NA;
2571 pm = of_get_property(np, "phy-mode", &plen);
2572 if (pm != NULL) {
2573 int i;
2574 for (i = 0; i < ARRAY_SIZE(phy_modes); i++)
2575 if (!strcasecmp(pm, phy_modes[i])) {
2576 dev->phy_mode = i;
2577 break;
2578 }
2579 }
2580
2581 /* Backward compat with non-final DT */
2582 if (dev->phy_mode == PHY_MODE_NA && pm != NULL && plen == 4) {
2583 u32 nmode = *(const u32 *)pm;
2584 if (nmode > PHY_MODE_NA && nmode <= PHY_MODE_SGMII)
2585 dev->phy_mode = nmode;
2586 }
2587
2588 /* Check EMAC version */
05781ccd
GE		 2589 if (of_device_is_compatible(np, "ibm,emac4sync")) {
2590 dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC);
9e3cb294
VG		 2591 if (of_device_is_compatible(np, "ibm,emac-460ex") ||
2592 of_device_is_compatible(np, "ibm,emac-460gt"))
2593 dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
9616a755
BH		 2594 if (of_device_is_compatible(np, "ibm,emac-405ex") ||
2595 of_device_is_compatible(np, "ibm,emac-405exr"))
2596 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
05781ccd 2597 } else if (of_device_is_compatible(np, "ibm,emac4")) {
1d3bb996 2598 dev->features |= EMAC_FTR_EMAC4;
0925ab5d
VB		 2599 if (of_device_is_compatible(np, "ibm,emac-440gx"))
2600 dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
11121e30
VB		 2601 } else {
2602 if (of_device_is_compatible(np, "ibm,emac-440ep") ||
2603 of_device_is_compatible(np, "ibm,emac-440gr"))
2604 dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
1ff0fcfc 2605 if (of_device_is_compatible(np, "ibm,emac-405ez")) {
c778e11d 2606#ifdef CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL
b68d185a 2607 dev->features |= EMAC_FTR_NO_FLOW_CONTROL_40x;
1ff0fcfc
JB		 2608#else
2609 printk(KERN_ERR "%s: Flow control not disabled!\n",
2610 np->full_name);
2611 return -ENXIO;
2612#endif
2613 }
2614
0925ab5d 2615 }
bff713b5
BH		 2616
2617 /* Fixup some feature bits based on the device tree */
2618 if (of_get_property(np, "has-inverted-stacr-oc", NULL))
1d3bb996 2619 dev->features |= EMAC_FTR_STACR_OC_INVERT;
bff713b5
BH		 2620 if (of_get_property(np, "has-new-stacr-staopc", NULL))
2621 dev->features |= EMAC_FTR_HAS_NEW_STACR;
1d3bb996 2622
bff713b5
BH		 2623 /* CAB lacks the appropriate properties */
2624 if (of_device_is_compatible(np, "ibm,emac-axon"))
2625 dev->features |= EMAC_FTR_HAS_NEW_STACR |
2626 EMAC_FTR_STACR_OC_INVERT;
2627
2628 /* Enable TAH/ZMII/RGMII features as found */
1d3bb996
DG		 2629 if (dev->tah_ph != 0) {
2630#ifdef CONFIG_IBM_NEW_EMAC_TAH
2631 dev->features |= EMAC_FTR_HAS_TAH;
2632#else
2633 printk(KERN_ERR "%s: TAH support not enabled !\n",
2634 np->full_name);
2635 return -ENXIO;
2636#endif
2637 }
2638
2639 if (dev->zmii_ph != 0) {
2640#ifdef CONFIG_IBM_NEW_EMAC_ZMII
2641 dev->features |= EMAC_FTR_HAS_ZMII;
2642#else
2643 printk(KERN_ERR "%s: ZMII support not enabled !\n",
2644 np->full_name);
2645 return -ENXIO;
2646#endif
2647 }
2648
2649 if (dev->rgmii_ph != 0) {
2650#ifdef CONFIG_IBM_NEW_EMAC_RGMII
2651 dev->features |= EMAC_FTR_HAS_RGMII;
2652#else
2653 printk(KERN_ERR "%s: RGMII support not enabled !\n",
2654 np->full_name);
2655 return -ENXIO;
2656#endif
2657 }
2658
2659 /* Read MAC-address */
2660 p = of_get_property(np, "local-mac-address", NULL);
2661 if (p == NULL) {
2662 printk(KERN_ERR "%s: Can't find local-mac-address property\n",
2663 np->full_name);
2664 return -ENXIO;
2665 }
2666 memcpy(dev->ndev->dev_addr, p, 6);
2667
05781ccd
GE		 2668 /* IAHT and GAHT filter parameterization */
2669 if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC)) {
2670 dev->xaht_slots_shift = EMAC4SYNC_XAHT_SLOTS_SHIFT;
2671 dev->xaht_width_shift = EMAC4SYNC_XAHT_WIDTH_SHIFT;
2672 } else {
2673 dev->xaht_slots_shift = EMAC4_XAHT_SLOTS_SHIFT;
2674 dev->xaht_width_shift = EMAC4_XAHT_WIDTH_SHIFT;
2675 }
2676
1d3bb996
DG		 2677 DBG(dev, "features : 0x%08x / 0x%08x\n", dev->features, EMAC_FTRS_POSSIBLE);
2678 DBG(dev, "tx_fifo_size : %d (%d gige)\n", dev->tx_fifo_size, dev->tx_fifo_size_gige);
2679 DBG(dev, "rx_fifo_size : %d (%d gige)\n", dev->rx_fifo_size, dev->rx_fifo_size_gige);
2680 DBG(dev, "max_mtu : %d\n", dev->max_mtu);
2681 DBG(dev, "OPB freq : %d\n", dev->opb_bus_freq);
2682
2683 return 0;
2684}
2685
15efc02b
AB		 2686static const struct net_device_ops emac_netdev_ops = {
2687 .ndo_open = emac_open,
2688 .ndo_stop = emac_close,
2689 .ndo_get_stats = emac_stats,
2690 .ndo_set_multicast_list = emac_set_multicast_list,
2691 .ndo_do_ioctl = emac_ioctl,
2692 .ndo_tx_timeout = emac_tx_timeout,
2693 .ndo_validate_addr = eth_validate_addr,
2694 .ndo_set_mac_address = eth_mac_addr,
2695 .ndo_start_xmit = emac_start_xmit,
2696 .ndo_change_mtu = eth_change_mtu,
2697};
2698
2699static const struct net_device_ops emac_gige_netdev_ops = {
2700 .ndo_open = emac_open,
2701 .ndo_stop = emac_close,
2702 .ndo_get_stats = emac_stats,
2703 .ndo_set_multicast_list = emac_set_multicast_list,
2704 .ndo_do_ioctl = emac_ioctl,
2705 .ndo_tx_timeout = emac_tx_timeout,
2706 .ndo_validate_addr = eth_validate_addr,
2707 .ndo_set_mac_address = eth_mac_addr,
2708 .ndo_start_xmit = emac_start_xmit_sg,
2709 .ndo_change_mtu = emac_change_mtu,
2710};
2711
1d3bb996
DG		 2712static int __devinit emac_probe(struct of_device *ofdev,
2713 const struct of_device_id *match)
2714{
2715 struct net_device *ndev;
2716 struct emac_instance *dev;
2717 struct device_node *np = ofdev->node;
2718 struct device_node **blist = NULL;
2719 int err, i;
2720
be63c09a
JB		 2721 /* Skip unused/unwired EMACS. We leave the check for an unused
2722 * property here for now, but new flat device trees should set a
2723 * status property to "disabled" instead.
2724 */
2725 if (of_get_property(np, "unused", NULL) || !of_device_is_available(np))
3d722562
HB		 2726 return -ENODEV;
2727
1d3bb996
DG		 2728 /* Find ourselves in the bootlist if we are there */
2729 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
2730 if (emac_boot_list[i] == np)
2731 blist = &emac_boot_list[i];
2732
2733 /* Allocate our net_device structure */
2734 err = -ENOMEM;
2735 ndev = alloc_etherdev(sizeof(struct emac_instance));
2736 if (!ndev) {
2737 printk(KERN_ERR "%s: could not allocate ethernet device!\n",
2738 np->full_name);
2739 goto err_gone;
2740 }
2741 dev = netdev_priv(ndev);
2742 dev->ndev = ndev;
2743 dev->ofdev = ofdev;
2744 dev->blist = blist;
1d3bb996
DG		 2745 SET_NETDEV_DEV(ndev, &ofdev->dev);
2746
2747 /* Initialize some embedded data structures */
2748 mutex_init(&dev->mdio_lock);
2749 mutex_init(&dev->link_lock);
2750 spin_lock_init(&dev->lock);
2751 INIT_WORK(&dev->reset_work, emac_reset_work);
2752
2753 /* Init various config data based on device-tree */
2754 err = emac_init_config(dev);
2755 if (err != 0)
2756 goto err_free;
2757
2758 /* Get interrupts. EMAC irq is mandatory, WOL irq is optional */
2759 dev->emac_irq = irq_of_parse_and_map(np, 0);
2760 dev->wol_irq = irq_of_parse_and_map(np, 1);
2761 if (dev->emac_irq == NO_IRQ) {
2762 printk(KERN_ERR "%s: Can't map main interrupt\n", np->full_name);
2763 goto err_free;
2764 }
2765 ndev->irq = dev->emac_irq;
2766
2767 /* Map EMAC regs */
2768 if (of_address_to_resource(np, 0, &dev->rsrc_regs)) {
2769 printk(KERN_ERR "%s: Can't get registers address\n",
2770 np->full_name);
2771 goto err_irq_unmap;
2772 }
2773 // TODO : request_mem_region
05781ccd
GE		 2774 dev->emacp = ioremap(dev->rsrc_regs.start,
2775 dev->rsrc_regs.end - dev->rsrc_regs.start + 1);
1d3bb996
DG		 2776 if (dev->emacp == NULL) {
2777 printk(KERN_ERR "%s: Can't map device registers!\n",
2778 np->full_name);
2779 err = -ENOMEM;
2780 goto err_irq_unmap;
2781 }
2782
2783 /* Wait for dependent devices */
2784 err = emac_wait_deps(dev);
2785 if (err) {
2786 printk(KERN_ERR
2787 "%s: Timeout waiting for dependent devices\n",
2788 np->full_name);
2789 /* display more info about what's missing ? */
2790 goto err_reg_unmap;
2791 }
2792 dev->mal = dev_get_drvdata(&dev->mal_dev->dev);
2793 if (dev->mdio_dev != NULL)
2794 dev->mdio_instance = dev_get_drvdata(&dev->mdio_dev->dev);
2795
2796 /* Register with MAL */
2797 dev->commac.ops = &emac_commac_ops;
2798 dev->commac.dev = dev;
2799 dev->commac.tx_chan_mask = MAL_CHAN_MASK(dev->mal_tx_chan);
2800 dev->commac.rx_chan_mask = MAL_CHAN_MASK(dev->mal_rx_chan);
2801 err = mal_register_commac(dev->mal, &dev->commac);
2802 if (err) {
2803 printk(KERN_ERR "%s: failed to register with mal %s!\n",
2804 np->full_name, dev->mal_dev->node->full_name);
2805 goto err_rel_deps;
2806 }
2807 dev->rx_skb_size = emac_rx_skb_size(ndev->mtu);
2808 dev->rx_sync_size = emac_rx_sync_size(ndev->mtu);
2809
2810 /* Get pointers to BD rings */
2811 dev->tx_desc =
2812 dev->mal->bd_virt + mal_tx_bd_offset(dev->mal, dev->mal_tx_chan);
2813 dev->rx_desc =
2814 dev->mal->bd_virt + mal_rx_bd_offset(dev->mal, dev->mal_rx_chan);
2815
2816 DBG(dev, "tx_desc %p" NL, dev->tx_desc);
2817 DBG(dev, "rx_desc %p" NL, dev->rx_desc);
2818
2819 /* Clean rings */
2820 memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
2821 memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
ab9b30cc
SN		 2822 memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *));
2823 memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *));
1d3bb996
DG		 2824
2825 /* Attach to ZMII, if needed */
2826 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) &&
2827 (err = zmii_attach(dev->zmii_dev, dev->zmii_port, &dev->phy_mode)) != 0)
2828 goto err_unreg_commac;
2829
2830 /* Attach to RGMII, if needed */
2831 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII) &&
2832 (err = rgmii_attach(dev->rgmii_dev, dev->rgmii_port, dev->phy_mode)) != 0)
2833 goto err_detach_zmii;
2834
2835 /* Attach to TAH, if needed */
2836 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
2837 (err = tah_attach(dev->tah_dev, dev->tah_port)) != 0)
2838 goto err_detach_rgmii;
2839
2840 /* Set some link defaults before we can find out real parameters */
2841 dev->phy.speed = SPEED_100;
2842 dev->phy.duplex = DUPLEX_FULL;
2843 dev->phy.autoneg = AUTONEG_DISABLE;
2844 dev->phy.pause = dev->phy.asym_pause = 0;
2845 dev->stop_timeout = STOP_TIMEOUT_100;
2846 INIT_DELAYED_WORK(&dev->link_work, emac_link_timer);
2847
2848 /* Find PHY if any */
2849 err = emac_init_phy(dev);
2850 if (err != 0)
2851 goto err_detach_tah;
2852
ee63d22b 2853 if (dev->tah_dev)
1d3bb996 2854 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1d3bb996 2855 ndev->watchdog_timeo = 5 * HZ;
1d3bb996 2856 if (emac_phy_supports_gige(dev->phy_mode)) {
15efc02b 2857 ndev->netdev_ops = &emac_gige_netdev_ops;
1d3bb996 2858 dev->commac.ops = &emac_commac_sg_ops;
15efc02b
AB		 2859 } else
2860 ndev->netdev_ops = &emac_netdev_ops;
1d3bb996
DG		 2861 SET_ETHTOOL_OPS(ndev, &emac_ethtool_ops);
2862
2863 netif_carrier_off(ndev);
2864 netif_stop_queue(ndev);
2865
2866 err = register_netdev(ndev);
2867 if (err) {
2868 printk(KERN_ERR "%s: failed to register net device (%d)!\n",
2869 np->full_name, err);
2870 goto err_detach_tah;
2871 }
2872
2873 /* Set our drvdata last as we don't want them visible until we are
2874 * fully initialized
2875 */
2876 wmb();
2877 dev_set_drvdata(&ofdev->dev, dev);
2878
2879 /* There's a new kid in town ! Let's tell everybody */
2880 wake_up_all(&emac_probe_wait);
2881
2882
7c510e4b
JB		 2883 printk(KERN_INFO "%s: EMAC-%d %s, MAC %pM\n",
2884 ndev->name, dev->cell_index, np->full_name, ndev->dev_addr);
1d3bb996 2885
9e3cb294
VG		 2886 if (dev->phy_mode == PHY_MODE_SGMII)
2887 printk(KERN_NOTICE "%s: in SGMII mode\n", ndev->name);
2888
1d3bb996
DG		 2889 if (dev->phy.address >= 0)
2890 printk("%s: found %s PHY (0x%02x)\n", ndev->name,
2891 dev->phy.def->name, dev->phy.address);
2892
2893 emac_dbg_register(dev);
2894
2895 /* Life is good */
2896 return 0;
2897
2898 /* I have a bad feeling about this ... */
2899
2900 err_detach_tah:
2901 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2902 tah_detach(dev->tah_dev, dev->tah_port);
2903 err_detach_rgmii:
2904 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2905 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
2906 err_detach_zmii:
2907 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2908 zmii_detach(dev->zmii_dev, dev->zmii_port);
2909 err_unreg_commac:
2910 mal_unregister_commac(dev->mal, &dev->commac);
2911 err_rel_deps:
2912 emac_put_deps(dev);
2913 err_reg_unmap:
2914 iounmap(dev->emacp);
2915 err_irq_unmap:
2916 if (dev->wol_irq != NO_IRQ)
2917 irq_dispose_mapping(dev->wol_irq);
2918 if (dev->emac_irq != NO_IRQ)
2919 irq_dispose_mapping(dev->emac_irq);
2920 err_free:
2921 kfree(ndev);
2922 err_gone:
2923 /* if we were on the bootlist, remove us as we won't show up and
2924 * wake up all waiters to notify them in case they were waiting
2925 * on us
2926 */
2927 if (blist) {
2928 *blist = NULL;
2929 wake_up_all(&emac_probe_wait);
2930 }
2931 return err;
2932}
2933
2934static int __devexit emac_remove(struct of_device *ofdev)
2935{
2936 struct emac_instance *dev = dev_get_drvdata(&ofdev->dev);
2937
2938 DBG(dev, "remove" NL);
2939
2940 dev_set_drvdata(&ofdev->dev, NULL);
2941
2942 unregister_netdev(dev->ndev);
2943
61dbcece
BH		 2944 flush_scheduled_work();
2945
1d3bb996
DG		 2946 if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
2947 tah_detach(dev->tah_dev, dev->tah_port);
2948 if (emac_has_feature(dev, EMAC_FTR_HAS_RGMII))
2949 rgmii_detach(dev->rgmii_dev, dev->rgmii_port);
2950 if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII))
2951 zmii_detach(dev->zmii_dev, dev->zmii_port);
2952
2953 mal_unregister_commac(dev->mal, &dev->commac);
2954 emac_put_deps(dev);
2955
2956 emac_dbg_unregister(dev);
2957 iounmap(dev->emacp);
2958
2959 if (dev->wol_irq != NO_IRQ)
2960 irq_dispose_mapping(dev->wol_irq);
2961 if (dev->emac_irq != NO_IRQ)
2962 irq_dispose_mapping(dev->emac_irq);
2963
2964 kfree(dev->ndev);
2965
2966 return 0;
2967}
2968
2969/* XXX Features in here should be replaced by properties... */
2970static struct of_device_id emac_match[] =
2971{
2972 {
2973 .type = "network",
2974 .compatible = "ibm,emac",
2975 },
2976 {
2977 .type = "network",
2978 .compatible = "ibm,emac4",
2979 },
05781ccd
GE		 2980 {
2981 .type = "network",
2982 .compatible = "ibm,emac4sync",
2983 },
1d3bb996
DG		 2984 {},
2985};
2986
2987static struct of_platform_driver emac_driver = {
2988 .name = "emac",
2989 .match_table = emac_match,
2990
2991 .probe = emac_probe,
2992 .remove = emac_remove,
2993};
2994
2995static void __init emac_make_bootlist(void)
2996{
2997 struct device_node *np = NULL;
2998 int j, max, i = 0, k;
2999 int cell_indices[EMAC_BOOT_LIST_SIZE];
3000
3001 /* Collect EMACs */
3002 while((np = of_find_all_nodes(np)) != NULL) {
3003 const u32 *idx;
3004
3005 if (of_match_node(emac_match, np) == NULL)
3006 continue;
3007 if (of_get_property(np, "unused", NULL))
3008 continue;
3009 idx = of_get_property(np, "cell-index", NULL);
3010 if (idx == NULL)
3011 continue;
3012 cell_indices[i] = *idx;
3013 emac_boot_list[i++] = of_node_get(np);
3014 if (i >= EMAC_BOOT_LIST_SIZE) {
3015 of_node_put(np);
3016 break;
3017 }
3018 }
3019 max = i;
3020
3021 /* Bubble sort them (doh, what a creative algorithm :-) */
3022 for (i = 0; max > 1 && (i < (max - 1)); i++)
3023 for (j = i; j < max; j++) {
3024 if (cell_indices[i] > cell_indices[j]) {
3025 np = emac_boot_list[i];
3026 emac_boot_list[i] = emac_boot_list[j];
3027 emac_boot_list[j] = np;
3028 k = cell_indices[i];
3029 cell_indices[i] = cell_indices[j];
3030 cell_indices[j] = k;
3031 }
3032 }
3033}
3034
3035static int __init emac_init(void)
3036{
3037 int rc;
3038
3039 printk(KERN_INFO DRV_DESC ", version " DRV_VERSION "\n");
3040
3041 /* Init debug stuff */
3042 emac_init_debug();
3043
3044 /* Build EMAC boot list */
3045 emac_make_bootlist();
3046
3047 /* Init submodules */
3048 rc = mal_init();
3049 if (rc)
3050 goto err;
3051 rc = zmii_init();
3052 if (rc)
3053 goto err_mal;
3054 rc = rgmii_init();
3055 if (rc)
3056 goto err_zmii;
3057 rc = tah_init();
3058 if (rc)
3059 goto err_rgmii;
3060 rc = of_register_platform_driver(&emac_driver);
3061 if (rc)
3062 goto err_tah;
3063
3064 return 0;
3065
3066 err_tah:
3067 tah_exit();
3068 err_rgmii:
3069 rgmii_exit();
3070 err_zmii:
3071 zmii_exit();
3072 err_mal:
3073 mal_exit();
3074 err:
3075 return rc;
3076}
3077
3078static void __exit emac_exit(void)
3079{
3080 int i;
3081
3082 of_unregister_platform_driver(&emac_driver);
3083
3084 tah_exit();
3085 rgmii_exit();
3086 zmii_exit();
3087 mal_exit();
3088 emac_fini_debug();
3089
3090 /* Destroy EMAC boot list */
3091 for (i = 0; i < EMAC_BOOT_LIST_SIZE; i++)
3092 if (emac_boot_list[i])
3093 of_node_put(emac_boot_list[i]);
3094}
3095
3096module_init(emac_init);
3097module_exit(emac_exit);
Linux 6.x block layer and io_uring tree(s)