Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
37448f7d | 2 | * drivers/net/ibm_emac/ibm_emac_phy.c |
1da177e4 | 3 | * |
37448f7d ES |
4 | * Driver for PowerPC 4xx on-chip ethernet controller, PHY support. |
5 | * Borrowed from sungem_phy.c, though I only kept the generic MII | |
1da177e4 LT |
6 | * driver for now. |
7 | * | |
8 | * This file should be shared with other drivers or eventually | |
9 | * merged as the "low level" part of miilib | |
10 | * | |
11 | * (c) 2003, Benjamin Herrenscmidt (benh@kernel.crashing.org) | |
37448f7d | 12 | * (c) 2004-2005, Eugene Surovegin <ebs@ebshome.net> |
1da177e4 LT |
13 | * |
14 | */ | |
1da177e4 | 15 | #include <linux/config.h> |
1da177e4 | 16 | #include <linux/module.h> |
1da177e4 | 17 | #include <linux/kernel.h> |
1da177e4 LT |
18 | #include <linux/types.h> |
19 | #include <linux/netdevice.h> | |
1da177e4 LT |
20 | #include <linux/mii.h> |
21 | #include <linux/ethtool.h> | |
22 | #include <linux/delay.h> | |
23 | ||
37448f7d ES |
24 | #include <asm/ocp.h> |
25 | ||
1da177e4 LT |
26 | #include "ibm_emac_phy.h" |
27 | ||
37448f7d ES |
28 | static inline int phy_read(struct mii_phy *phy, int reg) |
29 | { | |
30 | return phy->mdio_read(phy->dev, phy->address, reg); | |
31 | } | |
32 | ||
33 | static inline void phy_write(struct mii_phy *phy, int reg, int val) | |
1da177e4 | 34 | { |
37448f7d ES |
35 | phy->mdio_write(phy->dev, phy->address, reg, val); |
36 | } | |
37 | ||
38 | int mii_reset_phy(struct mii_phy *phy) | |
39 | { | |
40 | int val; | |
1da177e4 LT |
41 | int limit = 10000; |
42 | ||
37448f7d | 43 | val = phy_read(phy, MII_BMCR); |
1da177e4 LT |
44 | val &= ~BMCR_ISOLATE; |
45 | val |= BMCR_RESET; | |
37448f7d | 46 | phy_write(phy, MII_BMCR, val); |
1da177e4 | 47 | |
37448f7d | 48 | udelay(300); |
1da177e4 LT |
49 | |
50 | while (limit--) { | |
37448f7d ES |
51 | val = phy_read(phy, MII_BMCR); |
52 | if (val >= 0 && (val & BMCR_RESET) == 0) | |
1da177e4 LT |
53 | break; |
54 | udelay(10); | |
55 | } | |
56 | if ((val & BMCR_ISOLATE) && limit > 0) | |
37448f7d | 57 | phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); |
1da177e4 | 58 | |
37448f7d | 59 | return limit <= 0; |
1da177e4 LT |
60 | } |
61 | ||
62 | static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise) | |
63 | { | |
37448f7d | 64 | int ctl, adv; |
1da177e4 | 65 | |
37448f7d | 66 | phy->autoneg = AUTONEG_ENABLE; |
1da177e4 LT |
67 | phy->speed = SPEED_10; |
68 | phy->duplex = DUPLEX_HALF; | |
37448f7d | 69 | phy->pause = phy->asym_pause = 0; |
1da177e4 LT |
70 | phy->advertising = advertise; |
71 | ||
72 | /* Setup standard advertise */ | |
73 | adv = phy_read(phy, MII_ADVERTISE); | |
37448f7d ES |
74 | if (adv < 0) |
75 | return adv; | |
76 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | | |
77 | ADVERTISE_PAUSE_ASYM); | |
1da177e4 LT |
78 | if (advertise & ADVERTISED_10baseT_Half) |
79 | adv |= ADVERTISE_10HALF; | |
80 | if (advertise & ADVERTISED_10baseT_Full) | |
81 | adv |= ADVERTISE_10FULL; | |
82 | if (advertise & ADVERTISED_100baseT_Half) | |
83 | adv |= ADVERTISE_100HALF; | |
84 | if (advertise & ADVERTISED_100baseT_Full) | |
85 | adv |= ADVERTISE_100FULL; | |
37448f7d ES |
86 | if (advertise & ADVERTISED_Pause) |
87 | adv |= ADVERTISE_PAUSE_CAP; | |
88 | if (advertise & ADVERTISED_Asym_Pause) | |
89 | adv |= ADVERTISE_PAUSE_ASYM; | |
1da177e4 LT |
90 | phy_write(phy, MII_ADVERTISE, adv); |
91 | ||
37448f7d ES |
92 | if (phy->features & |
93 | (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) { | |
94 | adv = phy_read(phy, MII_CTRL1000); | |
95 | if (adv < 0) | |
96 | return adv; | |
97 | adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
98 | if (advertise & ADVERTISED_1000baseT_Full) | |
99 | adv |= ADVERTISE_1000FULL; | |
100 | if (advertise & ADVERTISED_1000baseT_Half) | |
101 | adv |= ADVERTISE_1000HALF; | |
102 | phy_write(phy, MII_CTRL1000, adv); | |
103 | } | |
104 | ||
1da177e4 LT |
105 | /* Start/Restart aneg */ |
106 | ctl = phy_read(phy, MII_BMCR); | |
107 | ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
108 | phy_write(phy, MII_BMCR, ctl); | |
109 | ||
110 | return 0; | |
111 | } | |
112 | ||
113 | static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd) | |
114 | { | |
37448f7d | 115 | int ctl; |
1da177e4 | 116 | |
37448f7d | 117 | phy->autoneg = AUTONEG_DISABLE; |
1da177e4 LT |
118 | phy->speed = speed; |
119 | phy->duplex = fd; | |
37448f7d | 120 | phy->pause = phy->asym_pause = 0; |
1da177e4 LT |
121 | |
122 | ctl = phy_read(phy, MII_BMCR); | |
37448f7d ES |
123 | if (ctl < 0) |
124 | return ctl; | |
1da177e4 LT |
125 | ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_ANENABLE); |
126 | ||
127 | /* First reset the PHY */ | |
128 | phy_write(phy, MII_BMCR, ctl | BMCR_RESET); | |
129 | ||
130 | /* Select speed & duplex */ | |
131 | switch (speed) { | |
132 | case SPEED_10: | |
133 | break; | |
134 | case SPEED_100: | |
135 | ctl |= BMCR_SPEED100; | |
136 | break; | |
137 | case SPEED_1000: | |
37448f7d ES |
138 | ctl |= BMCR_SPEED1000; |
139 | break; | |
1da177e4 LT |
140 | default: |
141 | return -EINVAL; | |
142 | } | |
143 | if (fd == DUPLEX_FULL) | |
144 | ctl |= BMCR_FULLDPLX; | |
145 | phy_write(phy, MII_BMCR, ctl); | |
146 | ||
147 | return 0; | |
148 | } | |
149 | ||
150 | static int genmii_poll_link(struct mii_phy *phy) | |
151 | { | |
37448f7d | 152 | int status; |
1da177e4 | 153 | |
37448f7d ES |
154 | /* Clear latched value with dummy read */ |
155 | phy_read(phy, MII_BMSR); | |
1da177e4 | 156 | status = phy_read(phy, MII_BMSR); |
37448f7d | 157 | if (status < 0 || (status & BMSR_LSTATUS) == 0) |
1da177e4 | 158 | return 0; |
37448f7d | 159 | if (phy->autoneg == AUTONEG_ENABLE && !(status & BMSR_ANEGCOMPLETE)) |
1da177e4 LT |
160 | return 0; |
161 | return 1; | |
162 | } | |
163 | ||
37448f7d | 164 | static int genmii_read_link(struct mii_phy *phy) |
1da177e4 | 165 | { |
37448f7d ES |
166 | if (phy->autoneg == AUTONEG_ENABLE) { |
167 | int glpa = 0; | |
168 | int lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE); | |
169 | if (lpa < 0) | |
170 | return lpa; | |
171 | ||
172 | if (phy->features & | |
173 | (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) { | |
174 | int adv = phy_read(phy, MII_CTRL1000); | |
175 | glpa = phy_read(phy, MII_STAT1000); | |
176 | ||
177 | if (glpa < 0 || adv < 0) | |
178 | return adv; | |
179 | ||
180 | glpa &= adv << 2; | |
181 | } | |
182 | ||
183 | phy->speed = SPEED_10; | |
184 | phy->duplex = DUPLEX_HALF; | |
185 | phy->pause = phy->asym_pause = 0; | |
186 | ||
187 | if (glpa & (LPA_1000FULL | LPA_1000HALF)) { | |
188 | phy->speed = SPEED_1000; | |
189 | if (glpa & LPA_1000FULL) | |
190 | phy->duplex = DUPLEX_FULL; | |
191 | } else if (lpa & (LPA_100FULL | LPA_100HALF)) { | |
192 | phy->speed = SPEED_100; | |
193 | if (lpa & LPA_100FULL) | |
194 | phy->duplex = DUPLEX_FULL; | |
195 | } else if (lpa & LPA_10FULL) | |
196 | phy->duplex = DUPLEX_FULL; | |
1da177e4 | 197 | |
37448f7d ES |
198 | if (phy->duplex == DUPLEX_FULL) { |
199 | phy->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; | |
200 | phy->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; | |
201 | } | |
202 | } else { | |
203 | int bmcr = phy_read(phy, MII_BMCR); | |
204 | if (bmcr < 0) | |
205 | return bmcr; | |
1da177e4 | 206 | |
37448f7d | 207 | if (bmcr & BMCR_FULLDPLX) |
1da177e4 LT |
208 | phy->duplex = DUPLEX_FULL; |
209 | else | |
210 | phy->duplex = DUPLEX_HALF; | |
37448f7d | 211 | if (bmcr & BMCR_SPEED1000) |
1da177e4 | 212 | phy->speed = SPEED_1000; |
37448f7d | 213 | else if (bmcr & BMCR_SPEED100) |
1da177e4 LT |
214 | phy->speed = SPEED_100; |
215 | else | |
216 | phy->speed = SPEED_10; | |
1da177e4 | 217 | |
37448f7d ES |
218 | phy->pause = phy->asym_pause = 0; |
219 | } | |
1da177e4 LT |
220 | return 0; |
221 | } | |
222 | ||
37448f7d ES |
223 | /* Generic implementation for most 10/100/1000 PHYs */ |
224 | static struct mii_phy_ops generic_phy_ops = { | |
225 | .setup_aneg = genmii_setup_aneg, | |
226 | .setup_forced = genmii_setup_forced, | |
227 | .poll_link = genmii_poll_link, | |
228 | .read_link = genmii_read_link | |
229 | }; | |
230 | ||
231 | static struct mii_phy_def genmii_phy_def = { | |
232 | .phy_id = 0x00000000, | |
233 | .phy_id_mask = 0x00000000, | |
234 | .name = "Generic MII", | |
235 | .ops = &generic_phy_ops | |
236 | }; | |
237 | ||
238 | /* CIS8201 */ | |
239 | #define MII_CIS8201_EPCR 0x17 | |
240 | #define EPCR_MODE_MASK 0x3000 | |
241 | #define EPCR_GMII_MODE 0x0000 | |
242 | #define EPCR_RGMII_MODE 0x1000 | |
243 | #define EPCR_TBI_MODE 0x2000 | |
244 | #define EPCR_RTBI_MODE 0x3000 | |
245 | ||
246 | static int cis8201_init(struct mii_phy *phy) | |
1da177e4 | 247 | { |
37448f7d | 248 | int epcr; |
1da177e4 | 249 | |
37448f7d ES |
250 | epcr = phy_read(phy, MII_CIS8201_EPCR); |
251 | if (epcr < 0) | |
252 | return epcr; | |
1da177e4 | 253 | |
37448f7d | 254 | epcr &= ~EPCR_MODE_MASK; |
1da177e4 | 255 | |
37448f7d ES |
256 | switch (phy->mode) { |
257 | case PHY_MODE_TBI: | |
258 | epcr |= EPCR_TBI_MODE; | |
259 | break; | |
260 | case PHY_MODE_RTBI: | |
261 | epcr |= EPCR_RTBI_MODE; | |
262 | break; | |
263 | case PHY_MODE_GMII: | |
264 | epcr |= EPCR_GMII_MODE; | |
265 | break; | |
266 | case PHY_MODE_RGMII: | |
267 | default: | |
268 | epcr |= EPCR_RGMII_MODE; | |
1da177e4 | 269 | } |
37448f7d ES |
270 | |
271 | phy_write(phy, MII_CIS8201_EPCR, epcr); | |
1da177e4 LT |
272 | |
273 | return 0; | |
274 | } | |
275 | ||
1da177e4 | 276 | static struct mii_phy_ops cis8201_phy_ops = { |
37448f7d ES |
277 | .init = cis8201_init, |
278 | .setup_aneg = genmii_setup_aneg, | |
279 | .setup_forced = genmii_setup_forced, | |
280 | .poll_link = genmii_poll_link, | |
281 | .read_link = genmii_read_link | |
1da177e4 LT |
282 | }; |
283 | ||
284 | static struct mii_phy_def cis8201_phy_def = { | |
37448f7d ES |
285 | .phy_id = 0x000fc410, |
286 | .phy_id_mask = 0x000ffff0, | |
287 | .name = "CIS8201 Gigabit Ethernet", | |
288 | .ops = &cis8201_phy_ops | |
1da177e4 LT |
289 | }; |
290 | ||
291 | static struct mii_phy_def *mii_phy_table[] = { | |
292 | &cis8201_phy_def, | |
293 | &genmii_phy_def, | |
294 | NULL | |
295 | }; | |
296 | ||
37448f7d | 297 | int mii_phy_probe(struct mii_phy *phy, int address) |
1da177e4 | 298 | { |
1da177e4 LT |
299 | struct mii_phy_def *def; |
300 | int i; | |
37448f7d | 301 | u32 id; |
1da177e4 | 302 | |
37448f7d | 303 | phy->autoneg = AUTONEG_DISABLE; |
1da177e4 | 304 | phy->advertising = 0; |
37448f7d ES |
305 | phy->address = address; |
306 | phy->speed = SPEED_10; | |
307 | phy->duplex = DUPLEX_HALF; | |
308 | phy->pause = phy->asym_pause = 0; | |
309 | ||
310 | /* Take PHY out of isolate mode and reset it. */ | |
311 | if (mii_reset_phy(phy)) | |
1da177e4 LT |
312 | return -ENODEV; |
313 | ||
314 | /* Read ID and find matching entry */ | |
37448f7d | 315 | id = (phy_read(phy, MII_PHYSID1) << 16) | phy_read(phy, MII_PHYSID2); |
1da177e4 LT |
316 | for (i = 0; (def = mii_phy_table[i]) != NULL; i++) |
317 | if ((id & def->phy_id_mask) == def->phy_id) | |
318 | break; | |
319 | /* Should never be NULL (we have a generic entry), but... */ | |
37448f7d | 320 | if (!def) |
1da177e4 LT |
321 | return -ENODEV; |
322 | ||
323 | phy->def = def; | |
324 | ||
37448f7d ES |
325 | /* Determine PHY features if needed */ |
326 | phy->features = def->features; | |
327 | if (!phy->features) { | |
328 | u16 bmsr = phy_read(phy, MII_BMSR); | |
329 | if (bmsr & BMSR_ANEGCAPABLE) | |
330 | phy->features |= SUPPORTED_Autoneg; | |
331 | if (bmsr & BMSR_10HALF) | |
332 | phy->features |= SUPPORTED_10baseT_Half; | |
333 | if (bmsr & BMSR_10FULL) | |
334 | phy->features |= SUPPORTED_10baseT_Full; | |
335 | if (bmsr & BMSR_100HALF) | |
336 | phy->features |= SUPPORTED_100baseT_Half; | |
337 | if (bmsr & BMSR_100FULL) | |
338 | phy->features |= SUPPORTED_100baseT_Full; | |
339 | if (bmsr & BMSR_ESTATEN) { | |
340 | u16 esr = phy_read(phy, MII_ESTATUS); | |
341 | if (esr & ESTATUS_1000_TFULL) | |
342 | phy->features |= SUPPORTED_1000baseT_Full; | |
343 | if (esr & ESTATUS_1000_THALF) | |
344 | phy->features |= SUPPORTED_1000baseT_Half; | |
345 | } | |
346 | phy->features |= SUPPORTED_MII; | |
347 | } | |
348 | ||
1da177e4 | 349 | /* Setup default advertising */ |
37448f7d | 350 | phy->advertising = phy->features; |
1da177e4 LT |
351 | |
352 | return 0; | |
353 | } | |
354 | ||
355 | MODULE_LICENSE("GPL"); |