Merge commit 'v2.6.32-rc5' into perf/probes
[linux-2.6-block.git] / drivers / net / hamachi.c
CommitLineData
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1/* hamachi.c: A Packet Engines GNIC-II Gigabit Ethernet driver for Linux. */
2/*
3 Written 1998-2000 by Donald Becker.
4 Updates 2000 by Keith Underwood.
5
6aa20a22 6 This software may be used and distributed according to the terms of
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7 the GNU General Public License (GPL), incorporated herein by reference.
8 Drivers based on or derived from this code fall under the GPL and must
9 retain the authorship, copyright and license notice. This file is not
10 a complete program and may only be used when the entire operating
11 system is licensed under the GPL.
12
13 The author may be reached as becker@scyld.com, or C/O
14 Scyld Computing Corporation
15 410 Severn Ave., Suite 210
16 Annapolis MD 21403
17
18 This driver is for the Packet Engines GNIC-II PCI Gigabit Ethernet
19 adapter.
20
21 Support and updates available at
22 http://www.scyld.com/network/hamachi.html
03a8c661 23 [link no longer provides useful info -jgarzik]
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24 or
25 http://www.parl.clemson.edu/~keithu/hamachi.html
26
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27*/
28
29#define DRV_NAME "hamachi"
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30#define DRV_VERSION "2.1"
31#define DRV_RELDATE "Sept 11, 2006"
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32
33
34/* A few user-configurable values. */
35
36static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
37#define final_version
38#define hamachi_debug debug
39/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
40static int max_interrupt_work = 40;
41static int mtu;
42/* Default values selected by testing on a dual processor PIII-450 */
43/* These six interrupt control parameters may be set directly when loading the
44 * module, or through the rx_params and tx_params variables
45 */
46static int max_rx_latency = 0x11;
47static int max_rx_gap = 0x05;
48static int min_rx_pkt = 0x18;
6aa20a22 49static int max_tx_latency = 0x00;
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50static int max_tx_gap = 0x00;
51static int min_tx_pkt = 0x30;
52
53/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
54 -Setting to > 1518 causes all frames to be copied
55 -Setting to 0 disables copies
56*/
57static int rx_copybreak;
58
59/* An override for the hardware detection of bus width.
60 Set to 1 to force 32 bit PCI bus detection. Set to 4 to force 64 bit.
61 Add 2 to disable parity detection.
62*/
63static int force32;
64
65
66/* Used to pass the media type, etc.
67 These exist for driver interoperability.
68 No media types are currently defined.
69 - The lower 4 bits are reserved for the media type.
70 - The next three bits may be set to one of the following:
71 0x00000000 : Autodetect PCI bus
72 0x00000010 : Force 32 bit PCI bus
73 0x00000020 : Disable parity detection
74 0x00000040 : Force 64 bit PCI bus
75 Default is autodetect
76 - The next bit can be used to force half-duplex. This is a bad
77 idea since no known implementations implement half-duplex, and,
78 in general, half-duplex for gigabit ethernet is a bad idea.
6aa20a22 79 0x00000080 : Force half-duplex
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80 Default is full-duplex.
81 - In the original driver, the ninth bit could be used to force
82 full-duplex. Maintain that for compatibility
83 0x00000200 : Force full-duplex
84*/
85#define MAX_UNITS 8 /* More are supported, limit only on options */
86static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
87static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
88/* The Hamachi chipset supports 3 parameters each for Rx and Tx
89 * interruput management. Parameters will be loaded as specified into
6aa20a22 90 * the TxIntControl and RxIntControl registers.
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91 *
92 * The registers are arranged as follows:
93 * 23 - 16 15 - 8 7 - 0
94 * _________________________________
95 * | min_pkt | max_gap | max_latency |
96 * ---------------------------------
97 * min_pkt : The minimum number of packets processed between
6aa20a22 98 * interrupts.
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99 * max_gap : The maximum inter-packet gap in units of 8.192 us
100 * max_latency : The absolute time between interrupts in units of 8.192 us
6aa20a22 101 *
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102 */
103static int rx_params[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
104static int tx_params[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
105
106/* Operational parameters that are set at compile time. */
107
108/* Keep the ring sizes a power of two for compile efficiency.
109 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
110 Making the Tx ring too large decreases the effectiveness of channel
111 bonding and packet priority.
112 There are no ill effects from too-large receive rings, except for
113 excessive memory usage */
114/* Empirically it appears that the Tx ring needs to be a little bigger
115 for these Gbit adapters or you get into an overrun condition really
116 easily. Also, things appear to work a bit better in back-to-back
117 configurations if the Rx ring is 8 times the size of the Tx ring
118*/
119#define TX_RING_SIZE 64
120#define RX_RING_SIZE 512
121#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct hamachi_desc)
122#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct hamachi_desc)
123
124/*
125 * Enable netdev_ioctl. Added interrupt coalescing parameter adjustment.
126 * 2/19/99 Pete Wyckoff <wyckoff@ca.sandia.gov>
127 */
128
129/* play with 64-bit addrlen; seems to be a teensy bit slower --pw */
130/* #define ADDRLEN 64 */
131
132/*
133 * RX_CHECKSUM turns on card-generated receive checksum generation for
134 * TCP and UDP packets. Otherwise the upper layers do the calculation.
135 * TX_CHECKSUM won't do anything too useful, even if it works. There's no
136 * easy mechanism by which to tell the TCP/UDP stack that it need not
137 * generate checksums for this device. But if somebody can find a way
138 * to get that to work, most of the card work is in here already.
139 * 3/10/1999 Pete Wyckoff <wyckoff@ca.sandia.gov>
140 */
141#undef TX_CHECKSUM
142#define RX_CHECKSUM
143
144/* Operational parameters that usually are not changed. */
145/* Time in jiffies before concluding the transmitter is hung. */
146#define TX_TIMEOUT (5*HZ)
147
d43c36dc 148#include <linux/capability.h>
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149#include <linux/module.h>
150#include <linux/kernel.h>
151#include <linux/string.h>
152#include <linux/timer.h>
153#include <linux/time.h>
154#include <linux/errno.h>
155#include <linux/ioport.h>
156#include <linux/slab.h>
157#include <linux/interrupt.h>
158#include <linux/pci.h>
159#include <linux/init.h>
160#include <linux/ethtool.h>
161#include <linux/mii.h>
162#include <linux/netdevice.h>
163#include <linux/etherdevice.h>
164#include <linux/skbuff.h>
165#include <linux/ip.h>
166#include <linux/delay.h>
167#include <linux/bitops.h>
168
169#include <asm/uaccess.h>
170#include <asm/processor.h> /* Processor type for cache alignment. */
171#include <asm/io.h>
172#include <asm/unaligned.h>
173#include <asm/cache.h>
174
98683956 175static const char version[] __devinitconst =
1da177e4 176KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n"
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177" Some modifications by Eric kasten <kasten@nscl.msu.edu>\n"
178" Further modifications by Keith Underwood <keithu@parl.clemson.edu>\n";
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179
180
181/* IP_MF appears to be only defined in <netinet/ip.h>, however,
182 we need it for hardware checksumming support. FYI... some of
183 the definitions in <netinet/ip.h> conflict/duplicate those in
184 other linux headers causing many compiler warnings.
185*/
186#ifndef IP_MF
6aa20a22 187 #define IP_MF 0x2000 /* IP more frags from <netinet/ip.h> */
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188#endif
189
190/* Define IP_OFFSET to be IPOPT_OFFSET */
191#ifndef IP_OFFSET
192 #ifdef IPOPT_OFFSET
193 #define IP_OFFSET IPOPT_OFFSET
194 #else
195 #define IP_OFFSET 2
196 #endif
197#endif
198
199#define RUN_AT(x) (jiffies + (x))
200
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201#ifndef ADDRLEN
202#define ADDRLEN 32
203#endif
204
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205/* Condensed bus+endian portability operations. */
206#if ADDRLEN == 64
207#define cpu_to_leXX(addr) cpu_to_le64(addr)
8e985918 208#define leXX_to_cpu(addr) le64_to_cpu(addr)
6aa20a22 209#else
1da177e4 210#define cpu_to_leXX(addr) cpu_to_le32(addr)
8e985918 211#define leXX_to_cpu(addr) le32_to_cpu(addr)
6aa20a22 212#endif
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213
214
215/*
216 Theory of Operation
217
218I. Board Compatibility
219
220This device driver is designed for the Packet Engines "Hamachi"
221Gigabit Ethernet chip. The only PCA currently supported is the GNIC-II 64-bit
22266Mhz PCI card.
223
224II. Board-specific settings
225
226No jumpers exist on the board. The chip supports software correction of
227various motherboard wiring errors, however this driver does not support
228that feature.
229
230III. Driver operation
231
232IIIa. Ring buffers
233
234The Hamachi uses a typical descriptor based bus-master architecture.
235The descriptor list is similar to that used by the Digital Tulip.
236This driver uses two statically allocated fixed-size descriptor lists
237formed into rings by a branch from the final descriptor to the beginning of
238the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
239
240This driver uses a zero-copy receive and transmit scheme similar my other
241network drivers.
242The driver allocates full frame size skbuffs for the Rx ring buffers at
243open() time and passes the skb->data field to the Hamachi as receive data
244buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
245a fresh skbuff is allocated and the frame is copied to the new skbuff.
246When the incoming frame is larger, the skbuff is passed directly up the
247protocol stack and replaced by a newly allocated skbuff.
248
249The RX_COPYBREAK value is chosen to trade-off the memory wasted by
250using a full-sized skbuff for small frames vs. the copying costs of larger
251frames. Gigabit cards are typically used on generously configured machines
252and the underfilled buffers have negligible impact compared to the benefit of
253a single allocation size, so the default value of zero results in never
254copying packets.
255
256IIIb/c. Transmit/Receive Structure
257
258The Rx and Tx descriptor structure are straight-forward, with no historical
259baggage that must be explained. Unlike the awkward DBDMA structure, there
260are no unused fields or option bits that had only one allowable setting.
261
262Two details should be noted about the descriptors: The chip supports both 32
263bit and 64 bit address structures, and the length field is overwritten on
264the receive descriptors. The descriptor length is set in the control word
265for each channel. The development driver uses 32 bit addresses only, however
26664 bit addresses may be enabled for 64 bit architectures e.g. the Alpha.
267
268IIId. Synchronization
269
270This driver is very similar to my other network drivers.
271The driver runs as two independent, single-threaded flows of control. One
272is the send-packet routine, which enforces single-threaded use by the
273dev->tbusy flag. The other thread is the interrupt handler, which is single
274threaded by the hardware and other software.
275
276The send packet thread has partial control over the Tx ring and 'dev->tbusy'
277flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
278queue slot is empty, it clears the tbusy flag when finished otherwise it sets
279the 'hmp->tx_full' flag.
280
281The interrupt handler has exclusive control over the Rx ring and records stats
282from the Tx ring. After reaping the stats, it marks the Tx queue entry as
283empty by incrementing the dirty_tx mark. Iff the 'hmp->tx_full' flag is set, it
284clears both the tx_full and tbusy flags.
285
286IV. Notes
287
288Thanks to Kim Stearns of Packet Engines for providing a pair of GNIC-II boards.
289
290IVb. References
291
292Hamachi Engineering Design Specification, 5/15/97
293(Note: This version was marked "Confidential".)
294
295IVc. Errata
296
6aa20a22 297None noted.
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298
299V. Recent Changes
300
6aa20a22 30101/15/1999 EPK Enlargement of the TX and RX ring sizes. This appears
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302 to help avoid some stall conditions -- this needs further research.
303
6aa20a22 30401/15/1999 EPK Creation of the hamachi_tx function. This function cleans
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305 the Tx ring and is called from hamachi_start_xmit (this used to be
306 called from hamachi_interrupt but it tends to delay execution of the
307 interrupt handler and thus reduce bandwidth by reducing the latency
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JG
308 between hamachi_rx()'s). Notably, some modification has been made so
309 that the cleaning loop checks only to make sure that the DescOwn bit
310 isn't set in the status flag since the card is not required
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311 to set the entire flag to zero after processing.
312
6aa20a22 31301/15/1999 EPK In the hamachi_start_tx function, the Tx ring full flag is
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314 checked before attempting to add a buffer to the ring. If the ring is full
315 an attempt is made to free any dirty buffers and thus find space for
316 the new buffer or the function returns non-zero which should case the
317 scheduler to reschedule the buffer later.
318
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JG
31901/15/1999 EPK Some adjustments were made to the chip initialization.
320 End-to-end flow control should now be fully active and the interrupt
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321 algorithm vars have been changed. These could probably use further tuning.
322
32301/15/1999 EPK Added the max_{rx,tx}_latency options. These are used to
324 set the rx and tx latencies for the Hamachi interrupts. If you're having
325 problems with network stalls, try setting these to higher values.
326 Valid values are 0x00 through 0xff.
327
6aa20a22 32801/15/1999 EPK In general, the overall bandwidth has increased and
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329 latencies are better (sometimes by a factor of 2). Stalls are rare at
330 this point, however there still appears to be a bug somewhere between the
331 hardware and driver. TCP checksum errors under load also appear to be
332 eliminated at this point.
333
33401/18/1999 EPK Ensured that the DescEndRing bit was being set on both the
335 Rx and Tx rings. This appears to have been affecting whether a particular
336 peer-to-peer connection would hang under high load. I believe the Rx
337 rings was typically getting set correctly, but the Tx ring wasn't getting
338 the DescEndRing bit set during initialization. ??? Does this mean the
339 hamachi card is using the DescEndRing in processing even if a particular
6aa20a22 340 slot isn't in use -- hypothetically, the card might be searching the
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341 entire Tx ring for slots with the DescOwn bit set and then processing
342 them. If the DescEndRing bit isn't set, then it might just wander off
343 through memory until it hits a chunk of data with that bit set
344 and then looping back.
345
6aa20a22 34602/09/1999 EPK Added Michel Mueller's TxDMA Interrupt and Tx-timeout
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347 problem (TxCmd and RxCmd need only to be set when idle or stopped.
348
34902/09/1999 EPK Added code to check/reset dev->tbusy in hamachi_interrupt.
6aa20a22 350 (Michel Mueller pointed out the ``permanently busy'' potential
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351 problem here).
352
6aa20a22 35302/22/1999 EPK Added Pete Wyckoff's ioctl to control the Tx/Rx latencies.
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354
35502/23/1999 EPK Verified that the interrupt status field bits for Tx were
356 incorrectly defined and corrected (as per Michel Mueller).
357
35802/23/1999 EPK Corrected the Tx full check to check that at least 4 slots
359 were available before reseting the tbusy and tx_full flags
360 (as per Michel Mueller).
361
36203/11/1999 EPK Added Pete Wyckoff's hardware checksumming support.
363
36412/31/1999 KDU Cleaned up assorted things and added Don's code to force
36532 bit.
366
36702/20/2000 KDU Some of the control was just plain odd. Cleaned up the
368hamachi_start_xmit() and hamachi_interrupt() code. There is still some
6aa20a22 369re-structuring I would like to do.
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370
37103/01/2000 KDU Experimenting with a WIDE range of interrupt mitigation
372parameters on a dual P3-450 setup yielded the new default interrupt
373mitigation parameters. Tx should interrupt VERY infrequently due to
374Eric's scheme. Rx should be more often...
375
37603/13/2000 KDU Added a patch to make the Rx Checksum code interact
6aa20a22 377nicely with non-linux machines.
1da177e4 378
6aa20a22 37903/13/2000 KDU Experimented with some of the configuration values:
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380
381 -It seems that enabling PCI performance commands for descriptors
6aa20a22
JG
382 (changing RxDMACtrl and TxDMACtrl lower nibble from 5 to D) has minimal
383 performance impact for any of my tests. (ttcp, netpipe, netperf) I will
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384 leave them that way until I hear further feedback.
385
6aa20a22 386 -Increasing the PCI_LATENCY_TIMER to 130
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387 (2 + (burst size of 128 * (0 wait states + 1))) seems to slightly
388 degrade performance. Leaving default at 64 pending further information.
389
6aa20a22 39003/14/2000 KDU Further tuning:
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391
392 -adjusted boguscnt in hamachi_rx() to depend on interrupt
393 mitigation parameters chosen.
394
6aa20a22 395 -Selected a set of interrupt parameters based on some extensive testing.
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396 These may change with more testing.
397
398TO DO:
399
400-Consider borrowing from the acenic driver code to check PCI_COMMAND for
401PCI_COMMAND_INVALIDATE. Set maximum burst size to cache line size in
402that case.
403
6aa20a22 404-fix the reset procedure. It doesn't quite work.
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405*/
406
407/* A few values that may be tweaked. */
408/* Size of each temporary Rx buffer, calculated as:
409 * 1518 bytes (ethernet packet) + 2 bytes (to get 8 byte alignment for
410 * the card) + 8 bytes of status info + 8 bytes for the Rx Checksum +
6aa20a22 411 * 2 more because we use skb_reserve.
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412 */
413#define PKT_BUF_SZ 1538
414
415/* For now, this is going to be set to the maximum size of an ethernet
416 * packet. Eventually, we may want to make it a variable that is
417 * related to the MTU
418 */
419#define MAX_FRAME_SIZE 1518
420
421/* The rest of these values should never change. */
422
423static void hamachi_timer(unsigned long data);
424
425enum capability_flags {CanHaveMII=1, };
f71e1309 426static const struct chip_info {
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427 u16 vendor_id, device_id, device_id_mask, pad;
428 const char *name;
429 void (*media_timer)(unsigned long data);
430 int flags;
431} chip_tbl[] = {
432 {0x1318, 0x0911, 0xffff, 0, "Hamachi GNIC-II", hamachi_timer, 0},
433 {0,},
434};
435
436/* Offsets to the Hamachi registers. Various sizes. */
437enum hamachi_offsets {
438 TxDMACtrl=0x00, TxCmd=0x04, TxStatus=0x06, TxPtr=0x08, TxCurPtr=0x10,
439 RxDMACtrl=0x20, RxCmd=0x24, RxStatus=0x26, RxPtr=0x28, RxCurPtr=0x30,
440 PCIClkMeas=0x060, MiscStatus=0x066, ChipRev=0x68, ChipReset=0x06B,
441 LEDCtrl=0x06C, VirtualJumpers=0x06D, GPIO=0x6E,
442 TxChecksum=0x074, RxChecksum=0x076,
443 TxIntrCtrl=0x078, RxIntrCtrl=0x07C,
444 InterruptEnable=0x080, InterruptClear=0x084, IntrStatus=0x088,
445 EventStatus=0x08C,
446 MACCnfg=0x0A0, FrameGap0=0x0A2, FrameGap1=0x0A4,
447 /* See enum MII_offsets below. */
448 MACCnfg2=0x0B0, RxDepth=0x0B8, FlowCtrl=0x0BC, MaxFrameSize=0x0CE,
449 AddrMode=0x0D0, StationAddr=0x0D2,
450 /* Gigabit AutoNegotiation. */
451 ANCtrl=0x0E0, ANStatus=0x0E2, ANXchngCtrl=0x0E4, ANAdvertise=0x0E8,
452 ANLinkPartnerAbility=0x0EA,
453 EECmdStatus=0x0F0, EEData=0x0F1, EEAddr=0x0F2,
454 FIFOcfg=0x0F8,
455};
456
457/* Offsets to the MII-mode registers. */
458enum MII_offsets {
459 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
460 MII_Status=0xAE,
461};
462
463/* Bits in the interrupt status/mask registers. */
464enum intr_status_bits {
465 IntrRxDone=0x01, IntrRxPCIFault=0x02, IntrRxPCIErr=0x04,
466 IntrTxDone=0x100, IntrTxPCIFault=0x200, IntrTxPCIErr=0x400,
467 LinkChange=0x10000, NegotiationChange=0x20000, StatsMax=0x40000, };
468
469/* The Hamachi Rx and Tx buffer descriptors. */
470struct hamachi_desc {
8e985918 471 __le32 status_n_length;
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472#if ADDRLEN == 64
473 u32 pad;
8e985918 474 __le64 addr;
1da177e4 475#else
8e985918 476 __le32 addr;
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477#endif
478};
479
480/* Bits in hamachi_desc.status_n_length */
481enum desc_status_bits {
6aa20a22 482 DescOwn=0x80000000, DescEndPacket=0x40000000, DescEndRing=0x20000000,
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483 DescIntr=0x10000000,
484};
485
486#define PRIV_ALIGN 15 /* Required alignment mask */
487#define MII_CNT 4
488struct hamachi_private {
489 /* Descriptor rings first for alignment. Tx requires a second descriptor
490 for status. */
491 struct hamachi_desc *rx_ring;
492 struct hamachi_desc *tx_ring;
493 struct sk_buff* rx_skbuff[RX_RING_SIZE];
494 struct sk_buff* tx_skbuff[TX_RING_SIZE];
495 dma_addr_t tx_ring_dma;
496 dma_addr_t rx_ring_dma;
497 struct net_device_stats stats;
498 struct timer_list timer; /* Media selection timer. */
499 /* Frequently used and paired value: keep adjacent for cache effect. */
500 spinlock_t lock;
501 int chip_id;
502 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
503 unsigned int cur_tx, dirty_tx;
504 unsigned int rx_buf_sz; /* Based on MTU+slack. */
505 unsigned int tx_full:1; /* The Tx queue is full. */
506 unsigned int duplex_lock:1;
507 unsigned int default_port:4; /* Last dev->if_port value. */
508 /* MII transceiver section. */
509 int mii_cnt; /* MII device addresses. */
510 struct mii_if_info mii_if; /* MII lib hooks/info */
511 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
512 u32 rx_int_var, tx_int_var; /* interrupt control variables */
513 u32 option; /* Hold on to a copy of the options */
514 struct pci_dev *pci_dev;
515 void __iomem *base;
516};
517
518MODULE_AUTHOR("Donald Becker <becker@scyld.com>, Eric Kasten <kasten@nscl.msu.edu>, Keith Underwood <keithu@parl.clemson.edu>");
519MODULE_DESCRIPTION("Packet Engines 'Hamachi' GNIC-II Gigabit Ethernet driver");
520MODULE_LICENSE("GPL");
521
522module_param(max_interrupt_work, int, 0);
523module_param(mtu, int, 0);
524module_param(debug, int, 0);
525module_param(min_rx_pkt, int, 0);
526module_param(max_rx_gap, int, 0);
527module_param(max_rx_latency, int, 0);
528module_param(min_tx_pkt, int, 0);
529module_param(max_tx_gap, int, 0);
530module_param(max_tx_latency, int, 0);
531module_param(rx_copybreak, int, 0);
532module_param_array(rx_params, int, NULL, 0);
533module_param_array(tx_params, int, NULL, 0);
534module_param_array(options, int, NULL, 0);
535module_param_array(full_duplex, int, NULL, 0);
536module_param(force32, int, 0);
537MODULE_PARM_DESC(max_interrupt_work, "GNIC-II maximum events handled per interrupt");
538MODULE_PARM_DESC(mtu, "GNIC-II MTU (all boards)");
539MODULE_PARM_DESC(debug, "GNIC-II debug level (0-7)");
540MODULE_PARM_DESC(min_rx_pkt, "GNIC-II minimum Rx packets processed between interrupts");
541MODULE_PARM_DESC(max_rx_gap, "GNIC-II maximum Rx inter-packet gap in 8.192 microsecond units");
542MODULE_PARM_DESC(max_rx_latency, "GNIC-II time between Rx interrupts in 8.192 microsecond units");
543MODULE_PARM_DESC(min_tx_pkt, "GNIC-II minimum Tx packets processed between interrupts");
544MODULE_PARM_DESC(max_tx_gap, "GNIC-II maximum Tx inter-packet gap in 8.192 microsecond units");
545MODULE_PARM_DESC(max_tx_latency, "GNIC-II time between Tx interrupts in 8.192 microsecond units");
546MODULE_PARM_DESC(rx_copybreak, "GNIC-II copy breakpoint for copy-only-tiny-frames");
547MODULE_PARM_DESC(rx_params, "GNIC-II min_rx_pkt+max_rx_gap+max_rx_latency");
548MODULE_PARM_DESC(tx_params, "GNIC-II min_tx_pkt+max_tx_gap+max_tx_latency");
549MODULE_PARM_DESC(options, "GNIC-II Bits 0-3: media type, bits 4-6: as force32, bit 7: half duplex, bit 9 full duplex");
550MODULE_PARM_DESC(full_duplex, "GNIC-II full duplex setting(s) (1)");
551MODULE_PARM_DESC(force32, "GNIC-II: Bit 0: 32 bit PCI, bit 1: disable parity, bit 2: 64 bit PCI (all boards)");
6aa20a22 552
1da177e4
LT
553static int read_eeprom(void __iomem *ioaddr, int location);
554static int mdio_read(struct net_device *dev, int phy_id, int location);
555static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
556static int hamachi_open(struct net_device *dev);
557static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
558static void hamachi_timer(unsigned long data);
559static void hamachi_tx_timeout(struct net_device *dev);
560static void hamachi_init_ring(struct net_device *dev);
61357325
SH
561static netdev_tx_t hamachi_start_xmit(struct sk_buff *skb,
562 struct net_device *dev);
7d12e780 563static irqreturn_t hamachi_interrupt(int irq, void *dev_instance);
1da177e4
LT
564static int hamachi_rx(struct net_device *dev);
565static inline int hamachi_tx(struct net_device *dev);
566static void hamachi_error(struct net_device *dev, int intr_status);
567static int hamachi_close(struct net_device *dev);
568static struct net_device_stats *hamachi_get_stats(struct net_device *dev);
569static void set_rx_mode(struct net_device *dev);
7282d491
JG
570static const struct ethtool_ops ethtool_ops;
571static const struct ethtool_ops ethtool_ops_no_mii;
1da177e4 572
a8652d23
SH
573static const struct net_device_ops hamachi_netdev_ops = {
574 .ndo_open = hamachi_open,
575 .ndo_stop = hamachi_close,
576 .ndo_start_xmit = hamachi_start_xmit,
577 .ndo_get_stats = hamachi_get_stats,
578 .ndo_set_multicast_list = set_rx_mode,
579 .ndo_change_mtu = eth_change_mtu,
580 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 581 .ndo_set_mac_address = eth_mac_addr,
a8652d23
SH
582 .ndo_tx_timeout = hamachi_tx_timeout,
583 .ndo_do_ioctl = netdev_ioctl,
584};
585
586
1da177e4
LT
587static int __devinit hamachi_init_one (struct pci_dev *pdev,
588 const struct pci_device_id *ent)
589{
590 struct hamachi_private *hmp;
591 int option, i, rx_int_var, tx_int_var, boguscnt;
592 int chip_id = ent->driver_data;
593 int irq;
594 void __iomem *ioaddr;
595 unsigned long base;
596 static int card_idx;
597 struct net_device *dev;
598 void *ring_space;
599 dma_addr_t ring_dma;
600 int ret = -ENOMEM;
601
602/* when built into the kernel, we only print version if device is found */
603#ifndef MODULE
604 static int printed_version;
605 if (!printed_version++)
606 printk(version);
607#endif
608
609 if (pci_enable_device(pdev)) {
610 ret = -EIO;
611 goto err_out;
612 }
613
614 base = pci_resource_start(pdev, 0);
615#ifdef __alpha__ /* Really "64 bit addrs" */
616 base |= (pci_resource_start(pdev, 1) << 32);
617#endif
618
619 pci_set_master(pdev);
620
621 i = pci_request_regions(pdev, DRV_NAME);
2e8a538d
JG
622 if (i)
623 return i;
1da177e4
LT
624
625 irq = pdev->irq;
626 ioaddr = ioremap(base, 0x400);
627 if (!ioaddr)
628 goto err_out_release;
629
630 dev = alloc_etherdev(sizeof(struct hamachi_private));
631 if (!dev)
632 goto err_out_iounmap;
633
1da177e4
LT
634 SET_NETDEV_DEV(dev, &pdev->dev);
635
636#ifdef TX_CHECKSUM
637 printk("check that skbcopy in ip_queue_xmit isn't happening\n");
638 dev->hard_header_len += 8; /* for cksum tag */
639#endif
640
641 for (i = 0; i < 6; i++)
642 dev->dev_addr[i] = 1 ? read_eeprom(ioaddr, 4 + i)
643 : readb(ioaddr + StationAddr + i);
644
645#if ! defined(final_version)
646 if (hamachi_debug > 4)
647 for (i = 0; i < 0x10; i++)
648 printk("%2.2x%s",
649 read_eeprom(ioaddr, i), i % 16 != 15 ? " " : "\n");
650#endif
651
652 hmp = netdev_priv(dev);
653 spin_lock_init(&hmp->lock);
654
655 hmp->mii_if.dev = dev;
656 hmp->mii_if.mdio_read = mdio_read;
657 hmp->mii_if.mdio_write = mdio_write;
658 hmp->mii_if.phy_id_mask = 0x1f;
659 hmp->mii_if.reg_num_mask = 0x1f;
660
661 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
662 if (!ring_space)
663 goto err_out_cleardev;
664 hmp->tx_ring = (struct hamachi_desc *)ring_space;
665 hmp->tx_ring_dma = ring_dma;
666
667 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
668 if (!ring_space)
669 goto err_out_unmap_tx;
670 hmp->rx_ring = (struct hamachi_desc *)ring_space;
671 hmp->rx_ring_dma = ring_dma;
672
673 /* Check for options being passed in */
674 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
675 if (dev->mem_start)
676 option = dev->mem_start;
677
678 /* If the bus size is misidentified, do the following. */
6aa20a22 679 force32 = force32 ? force32 :
1da177e4
LT
680 ((option >= 0) ? ((option & 0x00000070) >> 4) : 0 );
681 if (force32)
682 writeb(force32, ioaddr + VirtualJumpers);
683
684 /* Hmmm, do we really need to reset the chip???. */
685 writeb(0x01, ioaddr + ChipReset);
686
687 /* After a reset, the clock speed measurement of the PCI bus will not
688 * be valid for a moment. Wait for a little while until it is. If
689 * it takes more than 10ms, forget it.
690 */
6aa20a22 691 udelay(10);
1da177e4
LT
692 i = readb(ioaddr + PCIClkMeas);
693 for (boguscnt = 0; (!(i & 0x080)) && boguscnt < 1000; boguscnt++){
6aa20a22
JG
694 udelay(10);
695 i = readb(ioaddr + PCIClkMeas);
1da177e4
LT
696 }
697
698 hmp->base = ioaddr;
699 dev->base_addr = (unsigned long)ioaddr;
700 dev->irq = irq;
701 pci_set_drvdata(pdev, dev);
702
703 hmp->chip_id = chip_id;
704 hmp->pci_dev = pdev;
705
706 /* The lower four bits are the media type. */
707 if (option > 0) {
708 hmp->option = option;
709 if (option & 0x200)
710 hmp->mii_if.full_duplex = 1;
711 else if (option & 0x080)
712 hmp->mii_if.full_duplex = 0;
713 hmp->default_port = option & 15;
714 if (hmp->default_port)
715 hmp->mii_if.force_media = 1;
716 }
717 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
718 hmp->mii_if.full_duplex = 1;
719
720 /* lock the duplex mode if someone specified a value */
721 if (hmp->mii_if.full_duplex || (option & 0x080))
722 hmp->duplex_lock = 1;
723
724 /* Set interrupt tuning parameters */
725 max_rx_latency = max_rx_latency & 0x00ff;
726 max_rx_gap = max_rx_gap & 0x00ff;
727 min_rx_pkt = min_rx_pkt & 0x00ff;
728 max_tx_latency = max_tx_latency & 0x00ff;
729 max_tx_gap = max_tx_gap & 0x00ff;
730 min_tx_pkt = min_tx_pkt & 0x00ff;
731
732 rx_int_var = card_idx < MAX_UNITS ? rx_params[card_idx] : -1;
733 tx_int_var = card_idx < MAX_UNITS ? tx_params[card_idx] : -1;
6aa20a22 734 hmp->rx_int_var = rx_int_var >= 0 ? rx_int_var :
1da177e4 735 (min_rx_pkt << 16 | max_rx_gap << 8 | max_rx_latency);
6aa20a22 736 hmp->tx_int_var = tx_int_var >= 0 ? tx_int_var :
1da177e4
LT
737 (min_tx_pkt << 16 | max_tx_gap << 8 | max_tx_latency);
738
739
740 /* The Hamachi-specific entries in the device structure. */
a8652d23 741 dev->netdev_ops = &hamachi_netdev_ops;
1da177e4
LT
742 if (chip_tbl[hmp->chip_id].flags & CanHaveMII)
743 SET_ETHTOOL_OPS(dev, &ethtool_ops);
744 else
745 SET_ETHTOOL_OPS(dev, &ethtool_ops_no_mii);
1da177e4
LT
746 dev->watchdog_timeo = TX_TIMEOUT;
747 if (mtu)
748 dev->mtu = mtu;
749
750 i = register_netdev(dev);
751 if (i) {
752 ret = i;
753 goto err_out_unmap_rx;
754 }
755
e174961c 756 printk(KERN_INFO "%s: %s type %x at %p, %pM, IRQ %d.\n",
1da177e4 757 dev->name, chip_tbl[chip_id].name, readl(ioaddr + ChipRev),
e174961c 758 ioaddr, dev->dev_addr, irq);
1da177e4
LT
759 i = readb(ioaddr + PCIClkMeas);
760 printk(KERN_INFO "%s: %d-bit %d Mhz PCI bus (%d), Virtual Jumpers "
761 "%2.2x, LPA %4.4x.\n",
762 dev->name, readw(ioaddr + MiscStatus) & 1 ? 64 : 32,
763 i ? 2000/(i&0x7f) : 0, i&0x7f, (int)readb(ioaddr + VirtualJumpers),
764 readw(ioaddr + ANLinkPartnerAbility));
765
766 if (chip_tbl[hmp->chip_id].flags & CanHaveMII) {
767 int phy, phy_idx = 0;
768 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
769 int mii_status = mdio_read(dev, phy, MII_BMSR);
770 if (mii_status != 0xffff &&
771 mii_status != 0x0000) {
772 hmp->phys[phy_idx++] = phy;
773 hmp->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
774 printk(KERN_INFO "%s: MII PHY found at address %d, status "
775 "0x%4.4x advertising %4.4x.\n",
776 dev->name, phy, mii_status, hmp->mii_if.advertising);
777 }
778 }
779 hmp->mii_cnt = phy_idx;
780 if (hmp->mii_cnt > 0)
781 hmp->mii_if.phy_id = hmp->phys[0];
782 else
783 memset(&hmp->mii_if, 0, sizeof(hmp->mii_if));
784 }
785 /* Configure gigabit autonegotiation. */
786 writew(0x0400, ioaddr + ANXchngCtrl); /* Enable legacy links. */
787 writew(0x08e0, ioaddr + ANAdvertise); /* Set our advertise word. */
788 writew(0x1000, ioaddr + ANCtrl); /* Enable negotiation */
789
790 card_idx++;
791 return 0;
792
793err_out_unmap_rx:
6aa20a22 794 pci_free_consistent(pdev, RX_TOTAL_SIZE, hmp->rx_ring,
1da177e4
LT
795 hmp->rx_ring_dma);
796err_out_unmap_tx:
6aa20a22 797 pci_free_consistent(pdev, TX_TOTAL_SIZE, hmp->tx_ring,
1da177e4
LT
798 hmp->tx_ring_dma);
799err_out_cleardev:
800 free_netdev (dev);
801err_out_iounmap:
802 iounmap(ioaddr);
803err_out_release:
804 pci_release_regions(pdev);
805err_out:
806 return ret;
807}
808
809static int __devinit read_eeprom(void __iomem *ioaddr, int location)
810{
811 int bogus_cnt = 1000;
812
813 /* We should check busy first - per docs -KDU */
814 while ((readb(ioaddr + EECmdStatus) & 0x40) && --bogus_cnt > 0);
815 writew(location, ioaddr + EEAddr);
816 writeb(0x02, ioaddr + EECmdStatus);
817 bogus_cnt = 1000;
818 while ((readb(ioaddr + EECmdStatus) & 0x40) && --bogus_cnt > 0);
819 if (hamachi_debug > 5)
820 printk(" EEPROM status is %2.2x after %d ticks.\n",
821 (int)readb(ioaddr + EECmdStatus), 1000- bogus_cnt);
822 return readb(ioaddr + EEData);
823}
824
825/* MII Managemen Data I/O accesses.
826 These routines assume the MDIO controller is idle, and do not exit until
827 the command is finished. */
828
829static int mdio_read(struct net_device *dev, int phy_id, int location)
830{
831 struct hamachi_private *hmp = netdev_priv(dev);
832 void __iomem *ioaddr = hmp->base;
833 int i;
834
835 /* We should check busy first - per docs -KDU */
836 for (i = 10000; i >= 0; i--)
837 if ((readw(ioaddr + MII_Status) & 1) == 0)
838 break;
839 writew((phy_id<<8) + location, ioaddr + MII_Addr);
840 writew(0x0001, ioaddr + MII_Cmd);
841 for (i = 10000; i >= 0; i--)
842 if ((readw(ioaddr + MII_Status) & 1) == 0)
843 break;
844 return readw(ioaddr + MII_Rd_Data);
845}
846
847static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
848{
849 struct hamachi_private *hmp = netdev_priv(dev);
850 void __iomem *ioaddr = hmp->base;
851 int i;
852
853 /* We should check busy first - per docs -KDU */
854 for (i = 10000; i >= 0; i--)
855 if ((readw(ioaddr + MII_Status) & 1) == 0)
856 break;
857 writew((phy_id<<8) + location, ioaddr + MII_Addr);
858 writew(value, ioaddr + MII_Wr_Data);
859
860 /* Wait for the command to finish. */
861 for (i = 10000; i >= 0; i--)
862 if ((readw(ioaddr + MII_Status) & 1) == 0)
863 break;
864 return;
865}
866
6aa20a22 867
1da177e4
LT
868static int hamachi_open(struct net_device *dev)
869{
870 struct hamachi_private *hmp = netdev_priv(dev);
871 void __iomem *ioaddr = hmp->base;
872 int i;
873 u32 rx_int_var, tx_int_var;
874 u16 fifo_info;
875
1fb9df5d 876 i = request_irq(dev->irq, &hamachi_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT
877 if (i)
878 return i;
879
880 if (hamachi_debug > 1)
881 printk(KERN_DEBUG "%s: hamachi_open() irq %d.\n",
882 dev->name, dev->irq);
883
884 hamachi_init_ring(dev);
885
886#if ADDRLEN == 64
887 /* writellll anyone ? */
8e985918
AV
888 writel(hmp->rx_ring_dma, ioaddr + RxPtr);
889 writel(hmp->rx_ring_dma >> 32, ioaddr + RxPtr + 4);
890 writel(hmp->tx_ring_dma, ioaddr + TxPtr);
891 writel(hmp->tx_ring_dma >> 32, ioaddr + TxPtr + 4);
1da177e4 892#else
8e985918
AV
893 writel(hmp->rx_ring_dma, ioaddr + RxPtr);
894 writel(hmp->tx_ring_dma, ioaddr + TxPtr);
1da177e4
LT
895#endif
896
6aa20a22 897 /* TODO: It would make sense to organize this as words since the card
1da177e4
LT
898 * documentation does. -KDU
899 */
900 for (i = 0; i < 6; i++)
901 writeb(dev->dev_addr[i], ioaddr + StationAddr + i);
902
903 /* Initialize other registers: with so many this eventually this will
904 converted to an offset/value list. */
905
906 /* Configure the FIFO */
907 fifo_info = (readw(ioaddr + GPIO) & 0x00C0) >> 6;
908 switch (fifo_info){
6aa20a22 909 case 0 :
1da177e4
LT
910 /* No FIFO */
911 writew(0x0000, ioaddr + FIFOcfg);
912 break;
6aa20a22 913 case 1 :
1da177e4
LT
914 /* Configure the FIFO for 512K external, 16K used for Tx. */
915 writew(0x0028, ioaddr + FIFOcfg);
916 break;
6aa20a22 917 case 2 :
1da177e4
LT
918 /* Configure the FIFO for 1024 external, 32K used for Tx. */
919 writew(0x004C, ioaddr + FIFOcfg);
920 break;
6aa20a22 921 case 3 :
1da177e4
LT
922 /* Configure the FIFO for 2048 external, 32K used for Tx. */
923 writew(0x006C, ioaddr + FIFOcfg);
924 break;
6aa20a22 925 default :
1da177e4
LT
926 printk(KERN_WARNING "%s: Unsupported external memory config!\n",
927 dev->name);
928 /* Default to no FIFO */
929 writew(0x0000, ioaddr + FIFOcfg);
930 break;
931 }
6aa20a22 932
1da177e4
LT
933 if (dev->if_port == 0)
934 dev->if_port = hmp->default_port;
935
936
937 /* Setting the Rx mode will start the Rx process. */
6aa20a22 938 /* If someone didn't choose a duplex, default to full-duplex */
1da177e4
LT
939 if (hmp->duplex_lock != 1)
940 hmp->mii_if.full_duplex = 1;
941
942 /* always 1, takes no more time to do it */
943 writew(0x0001, ioaddr + RxChecksum);
944#ifdef TX_CHECKSUM
945 writew(0x0001, ioaddr + TxChecksum);
946#else
947 writew(0x0000, ioaddr + TxChecksum);
948#endif
949 writew(0x8000, ioaddr + MACCnfg); /* Soft reset the MAC */
950 writew(0x215F, ioaddr + MACCnfg);
6aa20a22 951 writew(0x000C, ioaddr + FrameGap0);
1da177e4
LT
952 /* WHAT?!?!? Why isn't this documented somewhere? -KDU */
953 writew(0x1018, ioaddr + FrameGap1);
954 /* Why do we enable receives/transmits here? -KDU */
955 writew(0x0780, ioaddr + MACCnfg2); /* Upper 16 bits control LEDs. */
956 /* Enable automatic generation of flow control frames, period 0xffff. */
957 writel(0x0030FFFF, ioaddr + FlowCtrl);
958 writew(MAX_FRAME_SIZE, ioaddr + MaxFrameSize); /* dev->mtu+14 ??? */
959
960 /* Enable legacy links. */
961 writew(0x0400, ioaddr + ANXchngCtrl); /* Enable legacy links. */
962 /* Initial Link LED to blinking red. */
963 writeb(0x03, ioaddr + LEDCtrl);
964
965 /* Configure interrupt mitigation. This has a great effect on
966 performance, so systems tuning should start here!. */
967
968 rx_int_var = hmp->rx_int_var;
969 tx_int_var = hmp->tx_int_var;
970
971 if (hamachi_debug > 1) {
972 printk("max_tx_latency: %d, max_tx_gap: %d, min_tx_pkt: %d\n",
6aa20a22 973 tx_int_var & 0x00ff, (tx_int_var & 0x00ff00) >> 8,
1da177e4
LT
974 (tx_int_var & 0x00ff0000) >> 16);
975 printk("max_rx_latency: %d, max_rx_gap: %d, min_rx_pkt: %d\n",
6aa20a22 976 rx_int_var & 0x00ff, (rx_int_var & 0x00ff00) >> 8,
1da177e4
LT
977 (rx_int_var & 0x00ff0000) >> 16);
978 printk("rx_int_var: %x, tx_int_var: %x\n", rx_int_var, tx_int_var);
979 }
980
6aa20a22
JG
981 writel(tx_int_var, ioaddr + TxIntrCtrl);
982 writel(rx_int_var, ioaddr + RxIntrCtrl);
1da177e4
LT
983
984 set_rx_mode(dev);
985
986 netif_start_queue(dev);
987
988 /* Enable interrupts by setting the interrupt mask. */
989 writel(0x80878787, ioaddr + InterruptEnable);
990 writew(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
991
992 /* Configure and start the DMA channels. */
993 /* Burst sizes are in the low three bits: size = 4<<(val&7) */
994#if ADDRLEN == 64
995 writew(0x005D, ioaddr + RxDMACtrl); /* 128 dword bursts */
996 writew(0x005D, ioaddr + TxDMACtrl);
997#else
998 writew(0x001D, ioaddr + RxDMACtrl);
999 writew(0x001D, ioaddr + TxDMACtrl);
1000#endif
1001 writew(0x0001, ioaddr + RxCmd);
1002
1003 if (hamachi_debug > 2) {
1004 printk(KERN_DEBUG "%s: Done hamachi_open(), status: Rx %x Tx %x.\n",
1005 dev->name, readw(ioaddr + RxStatus), readw(ioaddr + TxStatus));
1006 }
1007 /* Set the timer to check for link beat. */
1008 init_timer(&hmp->timer);
1009 hmp->timer.expires = RUN_AT((24*HZ)/10); /* 2.4 sec. */
1010 hmp->timer.data = (unsigned long)dev;
1011 hmp->timer.function = &hamachi_timer; /* timer handler */
1012 add_timer(&hmp->timer);
1013
1014 return 0;
1015}
1016
1017static inline int hamachi_tx(struct net_device *dev)
1018{
1019 struct hamachi_private *hmp = netdev_priv(dev);
1020
1021 /* Update the dirty pointer until we find an entry that is
1022 still owned by the card */
1023 for (; hmp->cur_tx - hmp->dirty_tx > 0; hmp->dirty_tx++) {
1024 int entry = hmp->dirty_tx % TX_RING_SIZE;
1025 struct sk_buff *skb;
1026
6aa20a22 1027 if (hmp->tx_ring[entry].status_n_length & cpu_to_le32(DescOwn))
1da177e4
LT
1028 break;
1029 /* Free the original skb. */
1030 skb = hmp->tx_skbuff[entry];
ddfce6bb 1031 if (skb) {
6aa20a22 1032 pci_unmap_single(hmp->pci_dev,
8e985918
AV
1033 leXX_to_cpu(hmp->tx_ring[entry].addr),
1034 skb->len, PCI_DMA_TODEVICE);
1da177e4
LT
1035 dev_kfree_skb(skb);
1036 hmp->tx_skbuff[entry] = NULL;
1037 }
1038 hmp->tx_ring[entry].status_n_length = 0;
6aa20a22 1039 if (entry >= TX_RING_SIZE-1)
1da177e4 1040 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |=
6aa20a22 1041 cpu_to_le32(DescEndRing);
1da177e4
LT
1042 hmp->stats.tx_packets++;
1043 }
1044
1045 return 0;
1046}
1047
1048static void hamachi_timer(unsigned long data)
1049{
1050 struct net_device *dev = (struct net_device *)data;
1051 struct hamachi_private *hmp = netdev_priv(dev);
1052 void __iomem *ioaddr = hmp->base;
1053 int next_tick = 10*HZ;
1054
1055 if (hamachi_debug > 2) {
1056 printk(KERN_INFO "%s: Hamachi Autonegotiation status %4.4x, LPA "
1057 "%4.4x.\n", dev->name, readw(ioaddr + ANStatus),
1058 readw(ioaddr + ANLinkPartnerAbility));
1059 printk(KERN_INFO "%s: Autonegotiation regs %4.4x %4.4x %4.4x "
1060 "%4.4x %4.4x %4.4x.\n", dev->name,
1061 readw(ioaddr + 0x0e0),
1062 readw(ioaddr + 0x0e2),
1063 readw(ioaddr + 0x0e4),
1064 readw(ioaddr + 0x0e6),
1065 readw(ioaddr + 0x0e8),
1066 readw(ioaddr + 0x0eA));
1067 }
1068 /* We could do something here... nah. */
1069 hmp->timer.expires = RUN_AT(next_tick);
1070 add_timer(&hmp->timer);
1071}
1072
1073static void hamachi_tx_timeout(struct net_device *dev)
1074{
1075 int i;
1076 struct hamachi_private *hmp = netdev_priv(dev);
1077 void __iomem *ioaddr = hmp->base;
1078
1079 printk(KERN_WARNING "%s: Hamachi transmit timed out, status %8.8x,"
1080 " resetting...\n", dev->name, (int)readw(ioaddr + TxStatus));
1081
1082 {
1da177e4
LT
1083 printk(KERN_DEBUG " Rx ring %p: ", hmp->rx_ring);
1084 for (i = 0; i < RX_RING_SIZE; i++)
ad361c98
JP
1085 printk(KERN_CONT " %8.8x",
1086 le32_to_cpu(hmp->rx_ring[i].status_n_length));
1087 printk(KERN_CONT "\n");
1088 printk(KERN_DEBUG" Tx ring %p: ", hmp->tx_ring);
1da177e4 1089 for (i = 0; i < TX_RING_SIZE; i++)
ad361c98
JP
1090 printk(KERN_CONT " %4.4x",
1091 le32_to_cpu(hmp->tx_ring[i].status_n_length));
1092 printk(KERN_CONT "\n");
1da177e4
LT
1093 }
1094
6aa20a22 1095 /* Reinit the hardware and make sure the Rx and Tx processes
1da177e4
LT
1096 are up and running.
1097 */
1098 dev->if_port = 0;
1099 /* The right way to do Reset. -KDU
1100 * -Clear OWN bit in all Rx/Tx descriptors
1101 * -Wait 50 uS for channels to go idle
1102 * -Turn off MAC receiver
1103 * -Issue Reset
1104 */
6aa20a22 1105
1da177e4
LT
1106 for (i = 0; i < RX_RING_SIZE; i++)
1107 hmp->rx_ring[i].status_n_length &= cpu_to_le32(~DescOwn);
1108
1109 /* Presume that all packets in the Tx queue are gone if we have to
1110 * re-init the hardware.
1111 */
1112 for (i = 0; i < TX_RING_SIZE; i++){
1113 struct sk_buff *skb;
1114
1115 if (i >= TX_RING_SIZE - 1)
8e985918
AV
1116 hmp->tx_ring[i].status_n_length =
1117 cpu_to_le32(DescEndRing) |
1118 (hmp->tx_ring[i].status_n_length &
1119 cpu_to_le32(0x0000ffff));
6aa20a22 1120 else
8e985918 1121 hmp->tx_ring[i].status_n_length &= cpu_to_le32(0x0000ffff);
1da177e4
LT
1122 skb = hmp->tx_skbuff[i];
1123 if (skb){
8e985918 1124 pci_unmap_single(hmp->pci_dev, leXX_to_cpu(hmp->tx_ring[i].addr),
1da177e4
LT
1125 skb->len, PCI_DMA_TODEVICE);
1126 dev_kfree_skb(skb);
1127 hmp->tx_skbuff[i] = NULL;
1128 }
1129 }
1130
1131 udelay(60); /* Sleep 60 us just for safety sake */
1132 writew(0x0002, ioaddr + RxCmd); /* STOP Rx */
6aa20a22
JG
1133
1134 writeb(0x01, ioaddr + ChipReset); /* Reinit the hardware */
1da177e4
LT
1135
1136 hmp->tx_full = 0;
1137 hmp->cur_rx = hmp->cur_tx = 0;
1138 hmp->dirty_rx = hmp->dirty_tx = 0;
1139 /* Rx packets are also presumed lost; however, we need to make sure a
1140 * ring of buffers is in tact. -KDU
6aa20a22 1141 */
1da177e4
LT
1142 for (i = 0; i < RX_RING_SIZE; i++){
1143 struct sk_buff *skb = hmp->rx_skbuff[i];
1144
1145 if (skb){
8e985918
AV
1146 pci_unmap_single(hmp->pci_dev,
1147 leXX_to_cpu(hmp->rx_ring[i].addr),
1da177e4
LT
1148 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1149 dev_kfree_skb(skb);
1150 hmp->rx_skbuff[i] = NULL;
1151 }
1152 }
1153 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1154 for (i = 0; i < RX_RING_SIZE; i++) {
8eb60131 1155 struct sk_buff *skb = netdev_alloc_skb(dev, hmp->rx_buf_sz);
1da177e4
LT
1156 hmp->rx_skbuff[i] = skb;
1157 if (skb == NULL)
1158 break;
8eb60131 1159
1da177e4 1160 skb_reserve(skb, 2); /* 16 byte align the IP header. */
6aa20a22 1161 hmp->rx_ring[i].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
689be439 1162 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
6aa20a22 1163 hmp->rx_ring[i].status_n_length = cpu_to_le32(DescOwn |
1da177e4
LT
1164 DescEndPacket | DescIntr | (hmp->rx_buf_sz - 2));
1165 }
1166 hmp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1167 /* Mark the last entry as wrapping the ring. */
1168 hmp->rx_ring[RX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1169
1170 /* Trigger an immediate transmit demand. */
cdd0db05 1171 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT
1172 hmp->stats.tx_errors++;
1173
1174 /* Restart the chip's Tx/Rx processes . */
1175 writew(0x0002, ioaddr + TxCmd); /* STOP Tx */
1176 writew(0x0001, ioaddr + TxCmd); /* START Tx */
1177 writew(0x0001, ioaddr + RxCmd); /* START Rx */
1178
1179 netif_wake_queue(dev);
1180}
1181
1182
1183/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1184static void hamachi_init_ring(struct net_device *dev)
1185{
1186 struct hamachi_private *hmp = netdev_priv(dev);
1187 int i;
1188
1189 hmp->tx_full = 0;
1190 hmp->cur_rx = hmp->cur_tx = 0;
1191 hmp->dirty_rx = hmp->dirty_tx = 0;
1192
1da177e4 1193 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
6aa20a22
JG
1194 * card needs room to do 8 byte alignment, +2 so we can reserve
1195 * the first 2 bytes, and +16 gets room for the status word from the
1da177e4
LT
1196 * card. -KDU
1197 */
6aa20a22 1198 hmp->rx_buf_sz = (dev->mtu <= 1492 ? PKT_BUF_SZ :
1da177e4
LT
1199 (((dev->mtu+26+7) & ~7) + 2 + 16));
1200
1201 /* Initialize all Rx descriptors. */
1202 for (i = 0; i < RX_RING_SIZE; i++) {
1203 hmp->rx_ring[i].status_n_length = 0;
1204 hmp->rx_skbuff[i] = NULL;
1205 }
1206 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1207 for (i = 0; i < RX_RING_SIZE; i++) {
1208 struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz);
1209 hmp->rx_skbuff[i] = skb;
1210 if (skb == NULL)
1211 break;
1212 skb->dev = dev; /* Mark as being used by this device. */
1213 skb_reserve(skb, 2); /* 16 byte align the IP header. */
6aa20a22 1214 hmp->rx_ring[i].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
689be439 1215 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4 1216 /* -2 because it doesn't REALLY have that first 2 bytes -KDU */
6aa20a22 1217 hmp->rx_ring[i].status_n_length = cpu_to_le32(DescOwn |
1da177e4
LT
1218 DescEndPacket | DescIntr | (hmp->rx_buf_sz -2));
1219 }
1220 hmp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1221 hmp->rx_ring[RX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1222
1223 for (i = 0; i < TX_RING_SIZE; i++) {
1224 hmp->tx_skbuff[i] = NULL;
1225 hmp->tx_ring[i].status_n_length = 0;
1226 }
1227 /* Mark the last entry of the ring */
1228 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |= cpu_to_le32(DescEndRing);
1229
1230 return;
1231}
1232
1233
1234#ifdef TX_CHECKSUM
1235#define csum_add(it, val) \
1236do { \
1237 it += (u16) (val); \
1238 if (it & 0xffff0000) { \
1239 it &= 0xffff; \
1240 ++it; \
1241 } \
1242} while (0)
1243 /* printk("add %04x --> %04x\n", val, it); \ */
1244
1245/* uh->len already network format, do not swap */
1246#define pseudo_csum_udp(sum,ih,uh) do { \
1247 sum = 0; \
1248 csum_add(sum, (ih)->saddr >> 16); \
1249 csum_add(sum, (ih)->saddr & 0xffff); \
1250 csum_add(sum, (ih)->daddr >> 16); \
1251 csum_add(sum, (ih)->daddr & 0xffff); \
09640e63 1252 csum_add(sum, cpu_to_be16(IPPROTO_UDP)); \
1da177e4
LT
1253 csum_add(sum, (uh)->len); \
1254} while (0)
1255
1256/* swap len */
1257#define pseudo_csum_tcp(sum,ih,len) do { \
1258 sum = 0; \
1259 csum_add(sum, (ih)->saddr >> 16); \
1260 csum_add(sum, (ih)->saddr & 0xffff); \
1261 csum_add(sum, (ih)->daddr >> 16); \
1262 csum_add(sum, (ih)->daddr & 0xffff); \
09640e63 1263 csum_add(sum, cpu_to_be16(IPPROTO_TCP)); \
1da177e4
LT
1264 csum_add(sum, htons(len)); \
1265} while (0)
1266#endif
1267
61357325
SH
1268static netdev_tx_t hamachi_start_xmit(struct sk_buff *skb,
1269 struct net_device *dev)
1da177e4
LT
1270{
1271 struct hamachi_private *hmp = netdev_priv(dev);
1272 unsigned entry;
1273 u16 status;
1274
6aa20a22 1275 /* Ok, now make sure that the queue has space before trying to
1da177e4
LT
1276 add another skbuff. if we return non-zero the scheduler
1277 should interpret this as a queue full and requeue the buffer
1278 for later.
1279 */
1280 if (hmp->tx_full) {
1281 /* We should NEVER reach this point -KDU */
1282 printk(KERN_WARNING "%s: Hamachi transmit queue full at slot %d.\n",dev->name, hmp->cur_tx);
1283
1284 /* Wake the potentially-idle transmit channel. */
1285 /* If we don't need to read status, DON'T -KDU */
1286 status=readw(hmp->base + TxStatus);
1287 if( !(status & 0x0001) || (status & 0x0002))
1288 writew(0x0001, hmp->base + TxCmd);
5b548140 1289 return NETDEV_TX_BUSY;
6aa20a22 1290 }
1da177e4
LT
1291
1292 /* Caution: the write order is important here, set the field
1293 with the "ownership" bits last. */
1294
1295 /* Calculate the next Tx descriptor entry. */
1296 entry = hmp->cur_tx % TX_RING_SIZE;
1297
1298 hmp->tx_skbuff[entry] = skb;
1299
1300#ifdef TX_CHECKSUM
1301 {
1302 /* tack on checksum tag */
1303 u32 tagval = 0;
1304 struct ethhdr *eh = (struct ethhdr *)skb->data;
09640e63 1305 if (eh->h_proto == cpu_to_be16(ETH_P_IP)) {
1da177e4
LT
1306 struct iphdr *ih = (struct iphdr *)((char *)eh + ETH_HLEN);
1307 if (ih->protocol == IPPROTO_UDP) {
1308 struct udphdr *uh
1309 = (struct udphdr *)((char *)ih + ih->ihl*4);
1310 u32 offset = ((unsigned char *)uh + 6) - skb->data;
1311 u32 pseudo;
1312 pseudo_csum_udp(pseudo, ih, uh);
1313 pseudo = htons(pseudo);
1314 printk("udp cksum was %04x, sending pseudo %04x\n",
1315 uh->check, pseudo);
1316 uh->check = 0; /* zero out uh->check before card calc */
1317 /*
1318 * start at 14 (skip ethhdr), store at offset (uh->check),
1319 * use pseudo value given.
1320 */
1321 tagval = (14 << 24) | (offset << 16) | pseudo;
1322 } else if (ih->protocol == IPPROTO_TCP) {
1323 printk("tcp, no auto cksum\n");
1324 }
1325 }
1326 *(u32 *)skb_push(skb, 8) = tagval;
1327 }
1328#endif
1329
6aa20a22 1330 hmp->tx_ring[entry].addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
1da177e4 1331 skb->data, skb->len, PCI_DMA_TODEVICE));
6aa20a22 1332
1da177e4
LT
1333 /* Hmmmm, could probably put a DescIntr on these, but the way
1334 the driver is currently coded makes Tx interrupts unnecessary
1335 since the clearing of the Tx ring is handled by the start_xmit
1336 routine. This organization helps mitigate the interrupts a
1337 bit and probably renders the max_tx_latency param useless.
6aa20a22 1338
1da177e4
LT
1339 Update: Putting a DescIntr bit on all of the descriptors and
1340 mitigating interrupt frequency with the tx_min_pkt parameter. -KDU
1341 */
1342 if (entry >= TX_RING_SIZE-1) /* Wrap ring */
1343 hmp->tx_ring[entry].status_n_length = cpu_to_le32(DescOwn |
1344 DescEndPacket | DescEndRing | DescIntr | skb->len);
1345 else
1346 hmp->tx_ring[entry].status_n_length = cpu_to_le32(DescOwn |
1347 DescEndPacket | DescIntr | skb->len);
1348 hmp->cur_tx++;
1349
1350 /* Non-x86 Todo: explicitly flush cache lines here. */
1351
1352 /* Wake the potentially-idle transmit channel. */
1353 /* If we don't need to read status, DON'T -KDU */
1354 status=readw(hmp->base + TxStatus);
1355 if( !(status & 0x0001) || (status & 0x0002))
1356 writew(0x0001, hmp->base + TxCmd);
1357
1358 /* Immediately before returning, let's clear as many entries as we can. */
1359 hamachi_tx(dev);
1360
1361 /* We should kick the bottom half here, since we are not accepting
1362 * interrupts with every packet. i.e. realize that Gigabit ethernet
1363 * can transmit faster than ordinary machines can load packets;
1364 * hence, any packet that got put off because we were in the transmit
1365 * routine should IMMEDIATELY get a chance to be re-queued. -KDU
1366 */
6aa20a22 1367 if ((hmp->cur_tx - hmp->dirty_tx) < (TX_RING_SIZE - 4))
1da177e4
LT
1368 netif_wake_queue(dev); /* Typical path */
1369 else {
1370 hmp->tx_full = 1;
1371 netif_stop_queue(dev);
1372 }
1da177e4
LT
1373
1374 if (hamachi_debug > 4) {
1375 printk(KERN_DEBUG "%s: Hamachi transmit frame #%d queued in slot %d.\n",
1376 dev->name, hmp->cur_tx, entry);
1377 }
6ed10654 1378 return NETDEV_TX_OK;
1da177e4
LT
1379}
1380
1381/* The interrupt handler does all of the Rx thread work and cleans up
1382 after the Tx thread. */
7d12e780 1383static irqreturn_t hamachi_interrupt(int irq, void *dev_instance)
1da177e4
LT
1384{
1385 struct net_device *dev = dev_instance;
1386 struct hamachi_private *hmp = netdev_priv(dev);
1387 void __iomem *ioaddr = hmp->base;
1388 long boguscnt = max_interrupt_work;
1389 int handled = 0;
1390
1391#ifndef final_version /* Can never occur. */
1392 if (dev == NULL) {
1393 printk (KERN_ERR "hamachi_interrupt(): irq %d for unknown device.\n", irq);
1394 return IRQ_NONE;
1395 }
1396#endif
1397
1398 spin_lock(&hmp->lock);
1399
1400 do {
1401 u32 intr_status = readl(ioaddr + InterruptClear);
1402
1403 if (hamachi_debug > 4)
1404 printk(KERN_DEBUG "%s: Hamachi interrupt, status %4.4x.\n",
1405 dev->name, intr_status);
1406
1407 if (intr_status == 0)
1408 break;
1409
1410 handled = 1;
1411
1412 if (intr_status & IntrRxDone)
1413 hamachi_rx(dev);
1414
1415 if (intr_status & IntrTxDone){
1416 /* This code should RARELY need to execute. After all, this is
1417 * a gigabit link, it should consume packets as fast as we put
1418 * them in AND we clear the Tx ring in hamachi_start_xmit().
6aa20a22 1419 */
1da177e4
LT
1420 if (hmp->tx_full){
1421 for (; hmp->cur_tx - hmp->dirty_tx > 0; hmp->dirty_tx++){
1422 int entry = hmp->dirty_tx % TX_RING_SIZE;
1423 struct sk_buff *skb;
1424
6aa20a22 1425 if (hmp->tx_ring[entry].status_n_length & cpu_to_le32(DescOwn))
1da177e4
LT
1426 break;
1427 skb = hmp->tx_skbuff[entry];
1428 /* Free the original skb. */
1429 if (skb){
6aa20a22 1430 pci_unmap_single(hmp->pci_dev,
8e985918 1431 leXX_to_cpu(hmp->tx_ring[entry].addr),
1da177e4
LT
1432 skb->len,
1433 PCI_DMA_TODEVICE);
1434 dev_kfree_skb_irq(skb);
1435 hmp->tx_skbuff[entry] = NULL;
1436 }
1437 hmp->tx_ring[entry].status_n_length = 0;
6aa20a22
JG
1438 if (entry >= TX_RING_SIZE-1)
1439 hmp->tx_ring[TX_RING_SIZE-1].status_n_length |=
1da177e4
LT
1440 cpu_to_le32(DescEndRing);
1441 hmp->stats.tx_packets++;
1442 }
1443 if (hmp->cur_tx - hmp->dirty_tx < TX_RING_SIZE - 4){
1444 /* The ring is no longer full */
1445 hmp->tx_full = 0;
1446 netif_wake_queue(dev);
1447 }
1448 } else {
1449 netif_wake_queue(dev);
1450 }
1451 }
1452
1453
1454 /* Abnormal error summary/uncommon events handlers. */
1455 if (intr_status &
1456 (IntrTxPCIFault | IntrTxPCIErr | IntrRxPCIFault | IntrRxPCIErr |
1457 LinkChange | NegotiationChange | StatsMax))
1458 hamachi_error(dev, intr_status);
1459
1460 if (--boguscnt < 0) {
1461 printk(KERN_WARNING "%s: Too much work at interrupt, status=0x%4.4x.\n",
1462 dev->name, intr_status);
1463 break;
1464 }
1465 } while (1);
1466
1467 if (hamachi_debug > 3)
1468 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1469 dev->name, readl(ioaddr + IntrStatus));
1470
1471#ifndef final_version
1472 /* Code that should never be run! Perhaps remove after testing.. */
1473 {
1474 static int stopit = 10;
1475 if (dev->start == 0 && --stopit < 0) {
1476 printk(KERN_ERR "%s: Emergency stop, looping startup interrupt.\n",
1477 dev->name);
1478 free_irq(irq, dev);
1479 }
1480 }
1481#endif
1482
1483 spin_unlock(&hmp->lock);
1484 return IRQ_RETVAL(handled);
1485}
1486
1487/* This routine is logically part of the interrupt handler, but separated
1488 for clarity and better register allocation. */
1489static int hamachi_rx(struct net_device *dev)
1490{
1491 struct hamachi_private *hmp = netdev_priv(dev);
1492 int entry = hmp->cur_rx % RX_RING_SIZE;
1493 int boguscnt = (hmp->dirty_rx + RX_RING_SIZE) - hmp->cur_rx;
1494
1495 if (hamachi_debug > 4) {
1496 printk(KERN_DEBUG " In hamachi_rx(), entry %d status %4.4x.\n",
1497 entry, hmp->rx_ring[entry].status_n_length);
1498 }
1499
1500 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1501 while (1) {
1502 struct hamachi_desc *desc = &(hmp->rx_ring[entry]);
1503 u32 desc_status = le32_to_cpu(desc->status_n_length);
1504 u16 data_size = desc_status; /* Implicit truncate */
6aa20a22 1505 u8 *buf_addr;
1da177e4 1506 s32 frame_status;
6aa20a22 1507
1da177e4
LT
1508 if (desc_status & DescOwn)
1509 break;
1510 pci_dma_sync_single_for_cpu(hmp->pci_dev,
8e985918 1511 leXX_to_cpu(desc->addr),
1da177e4
LT
1512 hmp->rx_buf_sz,
1513 PCI_DMA_FROMDEVICE);
689be439 1514 buf_addr = (u8 *) hmp->rx_skbuff[entry]->data;
6caf52a4 1515 frame_status = get_unaligned_le32(&(buf_addr[data_size - 12]));
1da177e4
LT
1516 if (hamachi_debug > 4)
1517 printk(KERN_DEBUG " hamachi_rx() status was %8.8x.\n",
1518 frame_status);
1519 if (--boguscnt < 0)
1520 break;
1521 if ( ! (desc_status & DescEndPacket)) {
1522 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1523 "multiple buffers, entry %#x length %d status %4.4x!\n",
1524 dev->name, hmp->cur_rx, data_size, desc_status);
1525 printk(KERN_WARNING "%s: Oversized Ethernet frame %p vs %p.\n",
1526 dev->name, desc, &hmp->rx_ring[hmp->cur_rx % RX_RING_SIZE]);
1527 printk(KERN_WARNING "%s: Oversized Ethernet frame -- next status %x/%x last status %x.\n",
1528 dev->name,
8e985918
AV
1529 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx+1) % RX_RING_SIZE].status_n_length) & 0xffff0000,
1530 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx+1) % RX_RING_SIZE].status_n_length) & 0x0000ffff,
1531 le32_to_cpu(hmp->rx_ring[(hmp->cur_rx-1) % RX_RING_SIZE].status_n_length));
1da177e4
LT
1532 hmp->stats.rx_length_errors++;
1533 } /* else Omit for prototype errata??? */
1534 if (frame_status & 0x00380000) {
1535 /* There was an error. */
1536 if (hamachi_debug > 2)
1537 printk(KERN_DEBUG " hamachi_rx() Rx error was %8.8x.\n",
1538 frame_status);
1539 hmp->stats.rx_errors++;
1540 if (frame_status & 0x00600000) hmp->stats.rx_length_errors++;
1541 if (frame_status & 0x00080000) hmp->stats.rx_frame_errors++;
1542 if (frame_status & 0x00100000) hmp->stats.rx_crc_errors++;
1543 if (frame_status < 0) hmp->stats.rx_dropped++;
1544 } else {
1545 struct sk_buff *skb;
1546 /* Omit CRC */
6aa20a22 1547 u16 pkt_len = (frame_status & 0x07ff) - 4;
1da177e4
LT
1548#ifdef RX_CHECKSUM
1549 u32 pfck = *(u32 *) &buf_addr[data_size - 8];
1550#endif
1551
1552
1553#ifndef final_version
1554 if (hamachi_debug > 4)
1555 printk(KERN_DEBUG " hamachi_rx() normal Rx pkt length %d"
1556 " of %d, bogus_cnt %d.\n",
1557 pkt_len, data_size, boguscnt);
1558 if (hamachi_debug > 5)
1559 printk(KERN_DEBUG"%s: rx status %8.8x %8.8x %8.8x %8.8x %8.8x.\n",
1560 dev->name,
1561 *(s32*)&(buf_addr[data_size - 20]),
1562 *(s32*)&(buf_addr[data_size - 16]),
1563 *(s32*)&(buf_addr[data_size - 12]),
1564 *(s32*)&(buf_addr[data_size - 8]),
1565 *(s32*)&(buf_addr[data_size - 4]));
1566#endif
1567 /* Check if the packet is long enough to accept without copying
1568 to a minimally-sized skbuff. */
1569 if (pkt_len < rx_copybreak
1570 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1571#ifdef RX_CHECKSUM
1572 printk(KERN_ERR "%s: rx_copybreak non-zero "
1573 "not good with RX_CHECKSUM\n", dev->name);
1574#endif
1da177e4
LT
1575 skb_reserve(skb, 2); /* 16 byte align the IP header */
1576 pci_dma_sync_single_for_cpu(hmp->pci_dev,
8e985918 1577 leXX_to_cpu(hmp->rx_ring[entry].addr),
1da177e4
LT
1578 hmp->rx_buf_sz,
1579 PCI_DMA_FROMDEVICE);
1580 /* Call copy + cksum if available. */
1581#if 1 || USE_IP_COPYSUM
8c7b7faa
DM
1582 skb_copy_to_linear_data(skb,
1583 hmp->rx_skbuff[entry]->data, pkt_len);
1da177e4
LT
1584 skb_put(skb, pkt_len);
1585#else
1586 memcpy(skb_put(skb, pkt_len), hmp->rx_ring_dma
1587 + entry*sizeof(*desc), pkt_len);
1588#endif
1589 pci_dma_sync_single_for_device(hmp->pci_dev,
8e985918 1590 leXX_to_cpu(hmp->rx_ring[entry].addr),
1da177e4
LT
1591 hmp->rx_buf_sz,
1592 PCI_DMA_FROMDEVICE);
1593 } else {
6aa20a22 1594 pci_unmap_single(hmp->pci_dev,
8e985918 1595 leXX_to_cpu(hmp->rx_ring[entry].addr),
1da177e4
LT
1596 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1597 skb_put(skb = hmp->rx_skbuff[entry], pkt_len);
1598 hmp->rx_skbuff[entry] = NULL;
1599 }
1600 skb->protocol = eth_type_trans(skb, dev);
1601
1602
1603#ifdef RX_CHECKSUM
1604 /* TCP or UDP on ipv4, DIX encoding */
1605 if (pfck>>24 == 0x91 || pfck>>24 == 0x51) {
1606 struct iphdr *ih = (struct iphdr *) skb->data;
1607 /* Check that IP packet is at least 46 bytes, otherwise,
1608 * there may be pad bytes included in the hardware checksum.
1609 * This wouldn't happen if everyone padded with 0.
1610 */
1611 if (ntohs(ih->tot_len) >= 46){
1612 /* don't worry about frags */
09640e63 1613 if (!(ih->frag_off & cpu_to_be16(IP_MF|IP_OFFSET))) {
1da177e4
LT
1614 u32 inv = *(u32 *) &buf_addr[data_size - 16];
1615 u32 *p = (u32 *) &buf_addr[data_size - 20];
1616 register u32 crc, p_r, p_r1;
1617
1618 if (inv & 4) {
1619 inv &= ~4;
1620 --p;
1621 }
1622 p_r = *p;
1623 p_r1 = *(p-1);
1624 switch (inv) {
6aa20a22 1625 case 0:
1da177e4
LT
1626 crc = (p_r & 0xffff) + (p_r >> 16);
1627 break;
6aa20a22 1628 case 1:
1da177e4 1629 crc = (p_r >> 16) + (p_r & 0xffff)
6aa20a22 1630 + (p_r1 >> 16 & 0xff00);
1da177e4 1631 break;
6aa20a22
JG
1632 case 2:
1633 crc = p_r + (p_r1 >> 16);
1da177e4 1634 break;
6aa20a22
JG
1635 case 3:
1636 crc = p_r + (p_r1 & 0xff00) + (p_r1 >> 16);
1da177e4
LT
1637 break;
1638 default: /*NOTREACHED*/ crc = 0;
1639 }
1640 if (crc & 0xffff0000) {
1641 crc &= 0xffff;
1642 ++crc;
1643 }
1644 /* tcp/udp will add in pseudo */
1645 skb->csum = ntohs(pfck & 0xffff);
1646 if (skb->csum > crc)
1647 skb->csum -= crc;
1648 else
1649 skb->csum += (~crc & 0xffff);
1650 /*
1651 * could do the pseudo myself and return
1652 * CHECKSUM_UNNECESSARY
1653 */
84fa7933 1654 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4 1655 }
6aa20a22 1656 }
1da177e4
LT
1657 }
1658#endif /* RX_CHECKSUM */
1659
1660 netif_rx(skb);
1da177e4
LT
1661 hmp->stats.rx_packets++;
1662 }
1663 entry = (++hmp->cur_rx) % RX_RING_SIZE;
1664 }
1665
1666 /* Refill the Rx ring buffers. */
1667 for (; hmp->cur_rx - hmp->dirty_rx > 0; hmp->dirty_rx++) {
1668 struct hamachi_desc *desc;
1669
1670 entry = hmp->dirty_rx % RX_RING_SIZE;
1671 desc = &(hmp->rx_ring[entry]);
1672 if (hmp->rx_skbuff[entry] == NULL) {
1673 struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz);
1674
1675 hmp->rx_skbuff[entry] = skb;
1676 if (skb == NULL)
1677 break; /* Better luck next round. */
1678 skb->dev = dev; /* Mark as being used by this device. */
1679 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
6aa20a22 1680 desc->addr = cpu_to_leXX(pci_map_single(hmp->pci_dev,
689be439 1681 skb->data, hmp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4
LT
1682 }
1683 desc->status_n_length = cpu_to_le32(hmp->rx_buf_sz);
1684 if (entry >= RX_RING_SIZE-1)
6aa20a22 1685 desc->status_n_length |= cpu_to_le32(DescOwn |
1da177e4
LT
1686 DescEndPacket | DescEndRing | DescIntr);
1687 else
6aa20a22 1688 desc->status_n_length |= cpu_to_le32(DescOwn |
1da177e4
LT
1689 DescEndPacket | DescIntr);
1690 }
1691
1692 /* Restart Rx engine if stopped. */
1693 /* If we don't need to check status, don't. -KDU */
1694 if (readw(hmp->base + RxStatus) & 0x0002)
1695 writew(0x0001, hmp->base + RxCmd);
1696
1697 return 0;
1698}
1699
1700/* This is more properly named "uncommon interrupt events", as it covers more
1701 than just errors. */
1702static void hamachi_error(struct net_device *dev, int intr_status)
1703{
1704 struct hamachi_private *hmp = netdev_priv(dev);
1705 void __iomem *ioaddr = hmp->base;
1706
1707 if (intr_status & (LinkChange|NegotiationChange)) {
1708 if (hamachi_debug > 1)
1709 printk(KERN_INFO "%s: Link changed: AutoNegotiation Ctrl"
1710 " %4.4x, Status %4.4x %4.4x Intr status %4.4x.\n",
1711 dev->name, readw(ioaddr + 0x0E0), readw(ioaddr + 0x0E2),
1712 readw(ioaddr + ANLinkPartnerAbility),
1713 readl(ioaddr + IntrStatus));
1714 if (readw(ioaddr + ANStatus) & 0x20)
1715 writeb(0x01, ioaddr + LEDCtrl);
1716 else
1717 writeb(0x03, ioaddr + LEDCtrl);
1718 }
1719 if (intr_status & StatsMax) {
1720 hamachi_get_stats(dev);
1721 /* Read the overflow bits to clear. */
1722 readl(ioaddr + 0x370);
1723 readl(ioaddr + 0x3F0);
1724 }
1725 if ((intr_status & ~(LinkChange|StatsMax|NegotiationChange|IntrRxDone|IntrTxDone))
1726 && hamachi_debug)
1727 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1728 dev->name, intr_status);
1729 /* Hmmmmm, it's not clear how to recover from PCI faults. */
1730 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1731 hmp->stats.tx_fifo_errors++;
1732 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1733 hmp->stats.rx_fifo_errors++;
1734}
1735
1736static int hamachi_close(struct net_device *dev)
1737{
1738 struct hamachi_private *hmp = netdev_priv(dev);
1739 void __iomem *ioaddr = hmp->base;
1740 struct sk_buff *skb;
1741 int i;
1742
1743 netif_stop_queue(dev);
1744
1745 if (hamachi_debug > 1) {
1746 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x Rx %4.4x Int %2.2x.\n",
1747 dev->name, readw(ioaddr + TxStatus),
1748 readw(ioaddr + RxStatus), readl(ioaddr + IntrStatus));
1749 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1750 dev->name, hmp->cur_tx, hmp->dirty_tx, hmp->cur_rx, hmp->dirty_rx);
1751 }
1752
1753 /* Disable interrupts by clearing the interrupt mask. */
1754 writel(0x0000, ioaddr + InterruptEnable);
1755
1756 /* Stop the chip's Tx and Rx processes. */
1757 writel(2, ioaddr + RxCmd);
1758 writew(2, ioaddr + TxCmd);
1759
1760#ifdef __i386__
1761 if (hamachi_debug > 2) {
ad361c98 1762 printk(KERN_DEBUG " Tx ring at %8.8x:\n",
1da177e4
LT
1763 (int)hmp->tx_ring_dma);
1764 for (i = 0; i < TX_RING_SIZE; i++)
ad361c98 1765 printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x.\n",
1da177e4
LT
1766 readl(ioaddr + TxCurPtr) == (long)&hmp->tx_ring[i] ? '>' : ' ',
1767 i, hmp->tx_ring[i].status_n_length, hmp->tx_ring[i].addr);
ad361c98 1768 printk(KERN_DEBUG " Rx ring %8.8x:\n",
1da177e4
LT
1769 (int)hmp->rx_ring_dma);
1770 for (i = 0; i < RX_RING_SIZE; i++) {
1771 printk(KERN_DEBUG " %c #%d desc. %4.4x %8.8x\n",
1772 readl(ioaddr + RxCurPtr) == (long)&hmp->rx_ring[i] ? '>' : ' ',
1773 i, hmp->rx_ring[i].status_n_length, hmp->rx_ring[i].addr);
1774 if (hamachi_debug > 6) {
689be439 1775 if (*(u8*)hmp->rx_skbuff[i]->data != 0x69) {
1da177e4 1776 u16 *addr = (u16 *)
689be439 1777 hmp->rx_skbuff[i]->data;
1da177e4 1778 int j;
ad361c98 1779 printk(KERN_DEBUG "Addr: ");
1da177e4
LT
1780 for (j = 0; j < 0x50; j++)
1781 printk(" %4.4x", addr[j]);
1782 printk("\n");
1783 }
1784 }
1785 }
1786 }
1787#endif /* __i386__ debugging only */
1788
1789 free_irq(dev->irq, dev);
1790
1791 del_timer_sync(&hmp->timer);
1792
1793 /* Free all the skbuffs in the Rx queue. */
1794 for (i = 0; i < RX_RING_SIZE; i++) {
1795 skb = hmp->rx_skbuff[i];
1796 hmp->rx_ring[i].status_n_length = 0;
1da177e4 1797 if (skb) {
6aa20a22 1798 pci_unmap_single(hmp->pci_dev,
8e985918
AV
1799 leXX_to_cpu(hmp->rx_ring[i].addr),
1800 hmp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1da177e4
LT
1801 dev_kfree_skb(skb);
1802 hmp->rx_skbuff[i] = NULL;
1803 }
8e985918 1804 hmp->rx_ring[i].addr = cpu_to_leXX(0xBADF00D0); /* An invalid address. */
1da177e4
LT
1805 }
1806 for (i = 0; i < TX_RING_SIZE; i++) {
1807 skb = hmp->tx_skbuff[i];
1808 if (skb) {
6aa20a22 1809 pci_unmap_single(hmp->pci_dev,
8e985918
AV
1810 leXX_to_cpu(hmp->tx_ring[i].addr),
1811 skb->len, PCI_DMA_TODEVICE);
1da177e4
LT
1812 dev_kfree_skb(skb);
1813 hmp->tx_skbuff[i] = NULL;
1814 }
1815 }
1816
1817 writeb(0x00, ioaddr + LEDCtrl);
1818
1819 return 0;
1820}
1821
1822static struct net_device_stats *hamachi_get_stats(struct net_device *dev)
1823{
1824 struct hamachi_private *hmp = netdev_priv(dev);
1825 void __iomem *ioaddr = hmp->base;
1826
1827 /* We should lock this segment of code for SMP eventually, although
1828 the vulnerability window is very small and statistics are
1829 non-critical. */
1830 /* Ok, what goes here? This appears to be stuck at 21 packets
1831 according to ifconfig. It does get incremented in hamachi_tx(),
1832 so I think I'll comment it out here and see if better things
1833 happen.
6aa20a22 1834 */
1da177e4
LT
1835 /* hmp->stats.tx_packets = readl(ioaddr + 0x000); */
1836
1837 hmp->stats.rx_bytes = readl(ioaddr + 0x330); /* Total Uni+Brd+Multi */
1838 hmp->stats.tx_bytes = readl(ioaddr + 0x3B0); /* Total Uni+Brd+Multi */
1839 hmp->stats.multicast = readl(ioaddr + 0x320); /* Multicast Rx */
1840
1841 hmp->stats.rx_length_errors = readl(ioaddr + 0x368); /* Over+Undersized */
1842 hmp->stats.rx_over_errors = readl(ioaddr + 0x35C); /* Jabber */
1843 hmp->stats.rx_crc_errors = readl(ioaddr + 0x360); /* Jabber */
1844 hmp->stats.rx_frame_errors = readl(ioaddr + 0x364); /* Symbol Errs */
1845 hmp->stats.rx_missed_errors = readl(ioaddr + 0x36C); /* Dropped */
1846
1847 return &hmp->stats;
1848}
1849
1850static void set_rx_mode(struct net_device *dev)
1851{
1852 struct hamachi_private *hmp = netdev_priv(dev);
1853 void __iomem *ioaddr = hmp->base;
1854
1855 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4
LT
1856 writew(0x000F, ioaddr + AddrMode);
1857 } else if ((dev->mc_count > 63) || (dev->flags & IFF_ALLMULTI)) {
1858 /* Too many to match, or accept all multicasts. */
1859 writew(0x000B, ioaddr + AddrMode);
1860 } else if (dev->mc_count > 0) { /* Must use the CAM filter. */
1861 struct dev_mc_list *mclist;
1862 int i;
1863 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1864 i++, mclist = mclist->next) {
1865 writel(*(u32*)(mclist->dmi_addr), ioaddr + 0x100 + i*8);
1866 writel(0x20000 | (*(u16*)&mclist->dmi_addr[4]),
1867 ioaddr + 0x104 + i*8);
1868 }
1869 /* Clear remaining entries. */
1870 for (; i < 64; i++)
1871 writel(0, ioaddr + 0x104 + i*8);
1872 writew(0x0003, ioaddr + AddrMode);
1873 } else { /* Normal, unicast/broadcast-only mode. */
1874 writew(0x0001, ioaddr + AddrMode);
1875 }
1876}
1877
1878static int check_if_running(struct net_device *dev)
1879{
1880 if (!netif_running(dev))
1881 return -EINVAL;
1882 return 0;
1883}
1884
1885static void hamachi_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1886{
1887 struct hamachi_private *np = netdev_priv(dev);
1888 strcpy(info->driver, DRV_NAME);
1889 strcpy(info->version, DRV_VERSION);
1890 strcpy(info->bus_info, pci_name(np->pci_dev));
1891}
1892
1893static int hamachi_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1894{
1895 struct hamachi_private *np = netdev_priv(dev);
1896 spin_lock_irq(&np->lock);
1897 mii_ethtool_gset(&np->mii_if, ecmd);
1898 spin_unlock_irq(&np->lock);
1899 return 0;
1900}
1901
1902static int hamachi_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1903{
1904 struct hamachi_private *np = netdev_priv(dev);
1905 int res;
1906 spin_lock_irq(&np->lock);
1907 res = mii_ethtool_sset(&np->mii_if, ecmd);
1908 spin_unlock_irq(&np->lock);
1909 return res;
1910}
1911
1912static int hamachi_nway_reset(struct net_device *dev)
1913{
1914 struct hamachi_private *np = netdev_priv(dev);
1915 return mii_nway_restart(&np->mii_if);
1916}
1917
1918static u32 hamachi_get_link(struct net_device *dev)
1919{
1920 struct hamachi_private *np = netdev_priv(dev);
1921 return mii_link_ok(&np->mii_if);
1922}
1923
7282d491 1924static const struct ethtool_ops ethtool_ops = {
1da177e4
LT
1925 .begin = check_if_running,
1926 .get_drvinfo = hamachi_get_drvinfo,
1927 .get_settings = hamachi_get_settings,
1928 .set_settings = hamachi_set_settings,
1929 .nway_reset = hamachi_nway_reset,
1930 .get_link = hamachi_get_link,
1931};
1932
7282d491 1933static const struct ethtool_ops ethtool_ops_no_mii = {
1da177e4
LT
1934 .begin = check_if_running,
1935 .get_drvinfo = hamachi_get_drvinfo,
1936};
1937
1938static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1939{
1940 struct hamachi_private *np = netdev_priv(dev);
1941 struct mii_ioctl_data *data = if_mii(rq);
1942 int rc;
1943
1944 if (!netif_running(dev))
1945 return -EINVAL;
1946
1947 if (cmd == (SIOCDEVPRIVATE+3)) { /* set rx,tx intr params */
1948 u32 *d = (u32 *)&rq->ifr_ifru;
1949 /* Should add this check here or an ordinary user can do nasty
1950 * things. -KDU
1951 *
1952 * TODO: Shut down the Rx and Tx engines while doing this.
1953 */
1954 if (!capable(CAP_NET_ADMIN))
1955 return -EPERM;
1956 writel(d[0], np->base + TxIntrCtrl);
1957 writel(d[1], np->base + RxIntrCtrl);
1958 printk(KERN_NOTICE "%s: tx %08x, rx %08x intr\n", dev->name,
1959 (u32) readl(np->base + TxIntrCtrl),
1960 (u32) readl(np->base + RxIntrCtrl));
1961 rc = 0;
1962 }
1963
1964 else {
1965 spin_lock_irq(&np->lock);
1966 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1967 spin_unlock_irq(&np->lock);
1968 }
1969
1970 return rc;
1971}
1972
1973
1974static void __devexit hamachi_remove_one (struct pci_dev *pdev)
1975{
1976 struct net_device *dev = pci_get_drvdata(pdev);
1977
1978 if (dev) {
1979 struct hamachi_private *hmp = netdev_priv(dev);
1980
6aa20a22 1981 pci_free_consistent(pdev, RX_TOTAL_SIZE, hmp->rx_ring,
1da177e4 1982 hmp->rx_ring_dma);
6aa20a22 1983 pci_free_consistent(pdev, TX_TOTAL_SIZE, hmp->tx_ring,
1da177e4
LT
1984 hmp->tx_ring_dma);
1985 unregister_netdev(dev);
1986 iounmap(hmp->base);
1987 free_netdev(dev);
1988 pci_release_regions(pdev);
1989 pci_set_drvdata(pdev, NULL);
1990 }
1991}
1992
1993static struct pci_device_id hamachi_pci_tbl[] = {
1994 { 0x1318, 0x0911, PCI_ANY_ID, PCI_ANY_ID, },
1995 { 0, }
1996};
1997MODULE_DEVICE_TABLE(pci, hamachi_pci_tbl);
1998
1999static struct pci_driver hamachi_driver = {
2000 .name = DRV_NAME,
2001 .id_table = hamachi_pci_tbl,
2002 .probe = hamachi_init_one,
2003 .remove = __devexit_p(hamachi_remove_one),
2004};
2005
2006static int __init hamachi_init (void)
2007{
2008/* when a module, this is printed whether or not devices are found in probe */
2009#ifdef MODULE
2010 printk(version);
2011#endif
2012 return pci_register_driver(&hamachi_driver);
2013}
2014
2015static void __exit hamachi_exit (void)
2016{
2017 pci_unregister_driver(&hamachi_driver);
2018}
2019
2020
2021module_init(hamachi_init);
2022module_exit(hamachi_exit);