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ucc_geth: enable transmit time stamping.
[linux-2.6-block.git] / drivers / net / gianfar.c
CommitLineData
0bbaf069 1/*
1da177e4
LT		 2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
7f7f5316
AF		 5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
4c8d3d99 10 * Maintainer: Kumar Gala
a12f801d 11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 12 *
a12f801d
SG		 13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * Gianfar: AKA Lambda Draconis, "Dragon"
22 * RA 11 31 24.2
23 * Dec +69 19 52
24 * V 3.84
25 * B-V +1.62
26 *
27 * Theory of operation
0bbaf069 28 *
b31a1d8b
AF		 29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 31 *
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 36 * last descriptor of the ring.
37 *
38 * When a packet is received, the RXF bit in the
0bbaf069 39 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
bb40dcbb 43 * of frames or amount of time have passed). In NAPI, the
1da177e4 44 * interrupt handler will signal there is work to be done, and
0aa1538f 45 * exit. This method will start at the last known empty
0bbaf069 46 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
53 * skb.
54 *
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
63 */
64
59deab26
JP		 65#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
66#define DEBUG
67
1da177e4 68#include <linux/kernel.h>
1da177e4
LT		 69#include <linux/string.h>
70#include <linux/errno.h>
bb40dcbb 71#include <linux/unistd.h>
1da177e4
LT		 72#include <linux/slab.h>
73#include <linux/interrupt.h>
74#include <linux/init.h>
75#include <linux/delay.h>
76#include <linux/netdevice.h>
77#include <linux/etherdevice.h>
78#include <linux/skbuff.h>
0bbaf069 79#include <linux/if_vlan.h>
1da177e4
LT		 80#include <linux/spinlock.h>
81#include <linux/mm.h>
fe192a49 82#include <linux/of_mdio.h>
b31a1d8b 83#include <linux/of_platform.h>
0bbaf069
KG		 84#include <linux/ip.h>
85#include <linux/tcp.h>
86#include <linux/udp.h>
9c07b884 87#include <linux/in.h>
cc772ab7 88#include <linux/net_tstamp.h>
1da177e4
LT		 89
90#include <asm/io.h>
7d350977 91#include <asm/reg.h>
1da177e4
LT		 92#include <asm/irq.h>
93#include <asm/uaccess.h>
94#include <linux/module.h>
1da177e4
LT		 95#include <linux/dma-mapping.h>
96#include <linux/crc32.h>
bb40dcbb
AF		 97#include <linux/mii.h>
98#include <linux/phy.h>
b31a1d8b
AF		 99#include <linux/phy_fixed.h>
100#include <linux/of.h>
4b6ba8aa 101#include <linux/of_net.h>
1da177e4
LT		 102
103#include "gianfar.h"
1577ecef 104#include "fsl_pq_mdio.h"
1da177e4
LT		 105
106#define TX_TIMEOUT (1*HZ)
1da177e4
LT		 107#undef BRIEF_GFAR_ERRORS
108#undef VERBOSE_GFAR_ERRORS
109
1da177e4 110const char gfar_driver_name[] = "Gianfar Ethernet";
7f7f5316 111const char gfar_driver_version[] = "1.3";
1da177e4 112
1da177e4
LT		 113static int gfar_enet_open(struct net_device *dev);
114static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 115static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 116static void gfar_timeout(struct net_device *dev);
117static int gfar_close(struct net_device *dev);
815b97c6 118struct sk_buff *gfar_new_skb(struct net_device *dev);
a12f801d 119static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6 120 struct sk_buff *skb);
1da177e4
LT		 121static int gfar_set_mac_address(struct net_device *dev);
122static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 123static irqreturn_t gfar_error(int irq, void *dev_id);
124static irqreturn_t gfar_transmit(int irq, void *dev_id);
125static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4
LT		 126static void adjust_link(struct net_device *dev);
127static void init_registers(struct net_device *dev);
128static int init_phy(struct net_device *dev);
74888760 129static int gfar_probe(struct platform_device *ofdev);
2dc11581 130static int gfar_remove(struct platform_device *ofdev);
bb40dcbb 131static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 132static void gfar_set_multi(struct net_device *dev);
133static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 134static void gfar_configure_serdes(struct net_device *dev);
bea3348e 135static int gfar_poll(struct napi_struct *napi, int budget);
f2d71c2d
VW		 136#ifdef CONFIG_NET_POLL_CONTROLLER
137static void gfar_netpoll(struct net_device *dev);
138#endif
a12f801d
SG		 139int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
140static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
2c2db48a
DH		 141static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
142 int amount_pull);
0bbaf069
KG		 143static void gfar_vlan_rx_register(struct net_device *netdev,
144 struct vlan_group *grp);
7f7f5316 145void gfar_halt(struct net_device *dev);
d87eb127 146static void gfar_halt_nodisable(struct net_device *dev);
7f7f5316
AF		 147void gfar_start(struct net_device *dev);
148static void gfar_clear_exact_match(struct net_device *dev);
b6bc7650
JP		 149static void gfar_set_mac_for_addr(struct net_device *dev, int num,
150 const u8 *addr);
26ccfc37 151static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 152
1da177e4
LT		 153MODULE_AUTHOR("Freescale Semiconductor, Inc");
154MODULE_DESCRIPTION("Gianfar Ethernet Driver");
155MODULE_LICENSE("GPL");
156
a12f801d 157static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 158 dma_addr_t buf)
159{
8a102fe0
AV		 160 u32 lstatus;
161
162 bdp->bufPtr = buf;
163
164 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 165 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 166 lstatus |= BD_LFLAG(RXBD_WRAP);
167
168 eieio();
169
170 bdp->lstatus = lstatus;
171}
172
8728327e 173static int gfar_init_bds(struct net_device *ndev)
826aa4a0 174{
8728327e 175 struct gfar_private *priv = netdev_priv(ndev);
a12f801d
SG		 176 struct gfar_priv_tx_q *tx_queue = NULL;
177 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 178 struct txbd8 *txbdp;
179 struct rxbd8 *rxbdp;
fba4ed03 180 int i, j;
a12f801d 181
fba4ed03
SG		 182 for (i = 0; i < priv->num_tx_queues; i++) {
183 tx_queue = priv->tx_queue[i];
184 /* Initialize some variables in our dev structure */
185 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
186 tx_queue->dirty_tx = tx_queue->tx_bd_base;
187 tx_queue->cur_tx = tx_queue->tx_bd_base;
188 tx_queue->skb_curtx = 0;
189 tx_queue->skb_dirtytx = 0;
190
191 /* Initialize Transmit Descriptor Ring */
192 txbdp = tx_queue->tx_bd_base;
193 for (j = 0; j < tx_queue->tx_ring_size; j++) {
194 txbdp->lstatus = 0;
195 txbdp->bufPtr = 0;
196 txbdp++;
197 }
8728327e 198
fba4ed03
SG		 199 /* Set the last descriptor in the ring to indicate wrap */
200 txbdp--;
201 txbdp->status |= TXBD_WRAP;
8728327e
AV		 202 }
203
fba4ed03
SG		 204 for (i = 0; i < priv->num_rx_queues; i++) {
205 rx_queue = priv->rx_queue[i];
206 rx_queue->cur_rx = rx_queue->rx_bd_base;
207 rx_queue->skb_currx = 0;
208 rxbdp = rx_queue->rx_bd_base;
8728327e 209
fba4ed03
SG		 210 for (j = 0; j < rx_queue->rx_ring_size; j++) {
211 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 212
fba4ed03
SG		 213 if (skb) {
214 gfar_init_rxbdp(rx_queue, rxbdp,
215 rxbdp->bufPtr);
216 } else {
217 skb = gfar_new_skb(ndev);
218 if (!skb) {
59deab26 219 netdev_err(ndev, "Can't allocate RX buffers\n");
fba4ed03
SG		 220 goto err_rxalloc_fail;
221 }
222 rx_queue->rx_skbuff[j] = skb;
223
224 gfar_new_rxbdp(rx_queue, rxbdp, skb);
8728327e 225 }
8728327e 226
fba4ed03 227 rxbdp++;
8728327e
AV		 228 }
229
8728327e
AV		 230 }
231
232 return 0;
fba4ed03
SG		 233
234err_rxalloc_fail:
235 free_skb_resources(priv);
236 return -ENOMEM;
8728327e
AV		 237}
238
239static int gfar_alloc_skb_resources(struct net_device *ndev)
240{
826aa4a0 241 void *vaddr;
fba4ed03
SG		 242 dma_addr_t addr;
243 int i, j, k;
826aa4a0
AV		 244 struct gfar_private *priv = netdev_priv(ndev);
245 struct device *dev = &priv->ofdev->dev;
a12f801d
SG		 246 struct gfar_priv_tx_q *tx_queue = NULL;
247 struct gfar_priv_rx_q *rx_queue = NULL;
248
fba4ed03
SG		 249 priv->total_tx_ring_size = 0;
250 for (i = 0; i < priv->num_tx_queues; i++)
251 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
252
253 priv->total_rx_ring_size = 0;
254 for (i = 0; i < priv->num_rx_queues; i++)
255 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 256
257 /* Allocate memory for the buffer descriptors */
8728327e 258 vaddr = dma_alloc_coherent(dev,
fba4ed03
SG		 259 sizeof(struct txbd8) * priv->total_tx_ring_size +
260 sizeof(struct rxbd8) * priv->total_rx_ring_size,
261 &addr, GFP_KERNEL);
826aa4a0 262 if (!vaddr) {
59deab26
JP		 263 netif_err(priv, ifup, ndev,
264 "Could not allocate buffer descriptors!\n");
826aa4a0
AV		 265 return -ENOMEM;
266 }
267
fba4ed03
SG		 268 for (i = 0; i < priv->num_tx_queues; i++) {
269 tx_queue = priv->tx_queue[i];
270 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
271 tx_queue->tx_bd_dma_base = addr;
272 tx_queue->dev = ndev;
273 /* enet DMA only understands physical addresses */
274 addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
275 vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
276 }
826aa4a0 277
826aa4a0 278 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 279 for (i = 0; i < priv->num_rx_queues; i++) {
280 rx_queue = priv->rx_queue[i];
281 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
282 rx_queue->rx_bd_dma_base = addr;
283 rx_queue->dev = ndev;
284 addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
285 vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
286 }
826aa4a0
AV		 287
288 /* Setup the skbuff rings */
fba4ed03
SG		 289 for (i = 0; i < priv->num_tx_queues; i++) {
290 tx_queue = priv->tx_queue[i];
291 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
a12f801d 292 tx_queue->tx_ring_size, GFP_KERNEL);
fba4ed03 293 if (!tx_queue->tx_skbuff) {
59deab26
JP		 294 netif_err(priv, ifup, ndev,
295 "Could not allocate tx_skbuff\n");
fba4ed03
SG		 296 goto cleanup;
297 }
826aa4a0 298
fba4ed03
SG		 299 for (k = 0; k < tx_queue->tx_ring_size; k++)
300 tx_queue->tx_skbuff[k] = NULL;
301 }
826aa4a0 302
fba4ed03
SG		 303 for (i = 0; i < priv->num_rx_queues; i++) {
304 rx_queue = priv->rx_queue[i];
305 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
a12f801d 306 rx_queue->rx_ring_size, GFP_KERNEL);
826aa4a0 307
fba4ed03 308 if (!rx_queue->rx_skbuff) {
59deab26
JP		 309 netif_err(priv, ifup, ndev,
310 "Could not allocate rx_skbuff\n");
fba4ed03
SG		 311 goto cleanup;
312 }
313
314 for (j = 0; j < rx_queue->rx_ring_size; j++)
315 rx_queue->rx_skbuff[j] = NULL;
316 }
826aa4a0 317
8728327e
AV		 318 if (gfar_init_bds(ndev))
319 goto cleanup;
826aa4a0
AV		 320
321 return 0;
322
323cleanup:
324 free_skb_resources(priv);
325 return -ENOMEM;
326}
327
fba4ed03
SG		 328static void gfar_init_tx_rx_base(struct gfar_private *priv)
329{
46ceb60c 330 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 331 u32 __iomem *baddr;
fba4ed03
SG		 332 int i;
333
334 baddr = &regs->tbase0;
335 for(i = 0; i < priv->num_tx_queues; i++) {
336 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
337 baddr += 2;
338 }
339
340 baddr = &regs->rbase0;
341 for(i = 0; i < priv->num_rx_queues; i++) {
342 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
343 baddr += 2;
344 }
345}
346
826aa4a0
AV		 347static void gfar_init_mac(struct net_device *ndev)
348{
349 struct gfar_private *priv = netdev_priv(ndev);
46ceb60c 350 struct gfar __iomem *regs = priv->gfargrp[0].regs;
826aa4a0
AV		 351 u32 rctrl = 0;
352 u32 tctrl = 0;
353 u32 attrs = 0;
354
fba4ed03
SG		 355 /* write the tx/rx base registers */
356 gfar_init_tx_rx_base(priv);
32c513bc 357
826aa4a0 358 /* Configure the coalescing support */
46ceb60c 359 gfar_configure_coalescing(priv, 0xFF, 0xFF);
fba4ed03 360
1ccb8389 361 if (priv->rx_filer_enable) {
fba4ed03 362 rctrl |= RCTRL_FILREN;
1ccb8389
SG		 363 /* Program the RIR0 reg with the required distribution */
364 gfar_write(&regs->rir0, DEFAULT_RIR0);
365 }
826aa4a0 366
8b3afe95 367 if (ndev->features & NETIF_F_RXCSUM)
826aa4a0
AV		 368 rctrl |= RCTRL_CHECKSUMMING;
369
370 if (priv->extended_hash) {
371 rctrl |= RCTRL_EXTHASH;
372
373 gfar_clear_exact_match(ndev);
374 rctrl |= RCTRL_EMEN;
375 }
376
377 if (priv->padding) {
378 rctrl &= ~RCTRL_PAL_MASK;
379 rctrl |= RCTRL_PADDING(priv->padding);
380 }
381
cc772ab7
MR		 382 /* Insert receive time stamps into padding alignment bytes */
383 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
384 rctrl &= ~RCTRL_PAL_MASK;
97553f7f 385 rctrl |= RCTRL_PADDING(8);
cc772ab7
MR		 386 priv->padding = 8;
387 }
388
97553f7f
MR		 389 /* Enable HW time stamping if requested from user space */
390 if (priv->hwts_rx_en)
391 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
392
826aa4a0
AV		 393 /* keep vlan related bits if it's enabled */
394 if (priv->vlgrp) {
395 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
396 tctrl |= TCTRL_VLINS;
397 }
398
399 /* Init rctrl based on our settings */
400 gfar_write(&regs->rctrl, rctrl);
401
402 if (ndev->features & NETIF_F_IP_CSUM)
403 tctrl |= TCTRL_INIT_CSUM;
404
fba4ed03
SG		 405 tctrl |= TCTRL_TXSCHED_PRIO;
406
826aa4a0
AV		 407 gfar_write(&regs->tctrl, tctrl);
408
409 /* Set the extraction length and index */
410 attrs = ATTRELI_EL(priv->rx_stash_size) |
411 ATTRELI_EI(priv->rx_stash_index);
412
413 gfar_write(&regs->attreli, attrs);
414
415 /* Start with defaults, and add stashing or locking
416 * depending on the approprate variables */
417 attrs = ATTR_INIT_SETTINGS;
418
419 if (priv->bd_stash_en)
420 attrs |= ATTR_BDSTASH;
421
422 if (priv->rx_stash_size != 0)
423 attrs |= ATTR_BUFSTASH;
424
425 gfar_write(&regs->attr, attrs);
426
427 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
428 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
429 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
430}
431
a7f38041
SG		 432static struct net_device_stats *gfar_get_stats(struct net_device *dev)
433{
434 struct gfar_private *priv = netdev_priv(dev);
a7f38041
SG		 435 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
436 unsigned long tx_packets = 0, tx_bytes = 0;
437 int i = 0;
438
439 for (i = 0; i < priv->num_rx_queues; i++) {
440 rx_packets += priv->rx_queue[i]->stats.rx_packets;
441 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
442 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
443 }
444
445 dev->stats.rx_packets = rx_packets;
446 dev->stats.rx_bytes = rx_bytes;
447 dev->stats.rx_dropped = rx_dropped;
448
449 for (i = 0; i < priv->num_tx_queues; i++) {
1ac9ad13
ED		 450 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
451 tx_packets += priv->tx_queue[i]->stats.tx_packets;
a7f38041
SG		 452 }
453
454 dev->stats.tx_bytes = tx_bytes;
455 dev->stats.tx_packets = tx_packets;
456
457 return &dev->stats;
458}
459
26ccfc37
AF		 460static const struct net_device_ops gfar_netdev_ops = {
461 .ndo_open = gfar_enet_open,
462 .ndo_start_xmit = gfar_start_xmit,
463 .ndo_stop = gfar_close,
464 .ndo_change_mtu = gfar_change_mtu,
8b3afe95 465 .ndo_set_features = gfar_set_features,
26ccfc37
AF		 466 .ndo_set_multicast_list = gfar_set_multi,
467 .ndo_tx_timeout = gfar_timeout,
468 .ndo_do_ioctl = gfar_ioctl,
a7f38041 469 .ndo_get_stats = gfar_get_stats,
26ccfc37 470 .ndo_vlan_rx_register = gfar_vlan_rx_register,
240c102d
BH		 471 .ndo_set_mac_address = eth_mac_addr,
472 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 473#ifdef CONFIG_NET_POLL_CONTROLLER
474 .ndo_poll_controller = gfar_netpoll,
475#endif
476};
477
7a8b3372
SG		 478unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
479unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
480
fba4ed03
SG		 481void lock_rx_qs(struct gfar_private *priv)
482{
483 int i = 0x0;
484
485 for (i = 0; i < priv->num_rx_queues; i++)
486 spin_lock(&priv->rx_queue[i]->rxlock);
487}
488
489void lock_tx_qs(struct gfar_private *priv)
490{
491 int i = 0x0;
492
493 for (i = 0; i < priv->num_tx_queues; i++)
494 spin_lock(&priv->tx_queue[i]->txlock);
495}
496
497void unlock_rx_qs(struct gfar_private *priv)
498{
499 int i = 0x0;
500
501 for (i = 0; i < priv->num_rx_queues; i++)
502 spin_unlock(&priv->rx_queue[i]->rxlock);
503}
504
505void unlock_tx_qs(struct gfar_private *priv)
506{
507 int i = 0x0;
508
509 for (i = 0; i < priv->num_tx_queues; i++)
510 spin_unlock(&priv->tx_queue[i]->txlock);
511}
512
7f7f5316
AF		 513/* Returns 1 if incoming frames use an FCB */
514static inline int gfar_uses_fcb(struct gfar_private *priv)
0bbaf069 515{
8b3afe95 516 return priv->vlgrp || (priv->ndev->features & NETIF_F_RXCSUM) ||
cc772ab7 517 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
0bbaf069 518}
bb40dcbb 519
fba4ed03
SG		 520static void free_tx_pointers(struct gfar_private *priv)
521{
522 int i = 0;
523
524 for (i = 0; i < priv->num_tx_queues; i++)
525 kfree(priv->tx_queue[i]);
526}
527
528static void free_rx_pointers(struct gfar_private *priv)
529{
530 int i = 0;
531
532 for (i = 0; i < priv->num_rx_queues; i++)
533 kfree(priv->rx_queue[i]);
534}
535
46ceb60c
SG		 536static void unmap_group_regs(struct gfar_private *priv)
537{
538 int i = 0;
539
540 for (i = 0; i < MAXGROUPS; i++)
541 if (priv->gfargrp[i].regs)
542 iounmap(priv->gfargrp[i].regs);
543}
544
545static void disable_napi(struct gfar_private *priv)
546{
547 int i = 0;
548
549 for (i = 0; i < priv->num_grps; i++)
550 napi_disable(&priv->gfargrp[i].napi);
551}
552
553static void enable_napi(struct gfar_private *priv)
554{
555 int i = 0;
556
557 for (i = 0; i < priv->num_grps; i++)
558 napi_enable(&priv->gfargrp[i].napi);
559}
560
561static int gfar_parse_group(struct device_node *np,
562 struct gfar_private *priv, const char *model)
563{
564 u32 *queue_mask;
46ceb60c 565
7ce97d4f 566 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
46ceb60c
SG		 567 if (!priv->gfargrp[priv->num_grps].regs)
568 return -ENOMEM;
569
570 priv->gfargrp[priv->num_grps].interruptTransmit =
571 irq_of_parse_and_map(np, 0);
572
573 /* If we aren't the FEC we have multiple interrupts */
574 if (model && strcasecmp(model, "FEC")) {
575 priv->gfargrp[priv->num_grps].interruptReceive =
576 irq_of_parse_and_map(np, 1);
577 priv->gfargrp[priv->num_grps].interruptError =
578 irq_of_parse_and_map(np,2);
28cb6ccd
NK		 579 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
580 priv->gfargrp[priv->num_grps].interruptReceive == NO_IRQ ||
581 priv->gfargrp[priv->num_grps].interruptError == NO_IRQ)
46ceb60c 582 return -EINVAL;
46ceb60c
SG		 583 }
584
585 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
586 priv->gfargrp[priv->num_grps].priv = priv;
587 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
588 if(priv->mode == MQ_MG_MODE) {
589 queue_mask = (u32 *)of_get_property(np,
590 "fsl,rx-bit-map", NULL);
591 priv->gfargrp[priv->num_grps].rx_bit_map =
592 queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
593 queue_mask = (u32 *)of_get_property(np,
594 "fsl,tx-bit-map", NULL);
595 priv->gfargrp[priv->num_grps].tx_bit_map =
596 queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
597 } else {
598 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
599 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
600 }
601 priv->num_grps++;
602
603 return 0;
604}
605
2dc11581 606static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
b31a1d8b 607{
b31a1d8b
AF		 608 const char *model;
609 const char *ctype;
610 const void *mac_addr;
fba4ed03
SG		 611 int err = 0, i;
612 struct net_device *dev = NULL;
613 struct gfar_private *priv = NULL;
61c7a080 614 struct device_node *np = ofdev->dev.of_node;
46ceb60c 615 struct device_node *child = NULL;
4d7902f2
AF		 616 const u32 *stash;
617 const u32 *stash_len;
618 const u32 *stash_idx;
fba4ed03
SG		 619 unsigned int num_tx_qs, num_rx_qs;
620 u32 *tx_queues, *rx_queues;
b31a1d8b
AF		 621
622 if (!np || !of_device_is_available(np))
623 return -ENODEV;
624
fba4ed03
SG		 625 /* parse the num of tx and rx queues */
626 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
627 num_tx_qs = tx_queues ? *tx_queues : 1;
628
629 if (num_tx_qs > MAX_TX_QS) {
59deab26
JP		 630 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
631 num_tx_qs, MAX_TX_QS);
632 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 633 return -EINVAL;
634 }
635
636 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
637 num_rx_qs = rx_queues ? *rx_queues : 1;
638
639 if (num_rx_qs > MAX_RX_QS) {
59deab26
JP		 640 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
641 num_rx_qs, MAX_RX_QS);
642 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 643 return -EINVAL;
644 }
645
646 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
647 dev = *pdev;
648 if (NULL == dev)
649 return -ENOMEM;
650
651 priv = netdev_priv(dev);
61c7a080 652 priv->node = ofdev->dev.of_node;
fba4ed03
SG		 653 priv->ndev = dev;
654
fba4ed03 655 priv->num_tx_queues = num_tx_qs;
fe069123 656 netif_set_real_num_rx_queues(dev, num_rx_qs);
fba4ed03 657 priv->num_rx_queues = num_rx_qs;
46ceb60c 658 priv->num_grps = 0x0;
b31a1d8b
AF		 659
660 model = of_get_property(np, "model", NULL);
661
46ceb60c
SG		 662 for (i = 0; i < MAXGROUPS; i++)
663 priv->gfargrp[i].regs = NULL;
b31a1d8b 664
46ceb60c
SG		 665 /* Parse and initialize group specific information */
666 if (of_device_is_compatible(np, "fsl,etsec2")) {
667 priv->mode = MQ_MG_MODE;
668 for_each_child_of_node(np, child) {
669 err = gfar_parse_group(child, priv, model);
670 if (err)
671 goto err_grp_init;
b31a1d8b 672 }
46ceb60c
SG		 673 } else {
674 priv->mode = SQ_SG_MODE;
675 err = gfar_parse_group(np, priv, model);
676 if(err)
677 goto err_grp_init;
b31a1d8b
AF		 678 }
679
fba4ed03
SG		 680 for (i = 0; i < priv->num_tx_queues; i++)
681 priv->tx_queue[i] = NULL;
682 for (i = 0; i < priv->num_rx_queues; i++)
683 priv->rx_queue[i] = NULL;
684
685 for (i = 0; i < priv->num_tx_queues; i++) {
de47f072
JP		 686 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
687 GFP_KERNEL);
fba4ed03
SG		 688 if (!priv->tx_queue[i]) {
689 err = -ENOMEM;
690 goto tx_alloc_failed;
691 }
692 priv->tx_queue[i]->tx_skbuff = NULL;
693 priv->tx_queue[i]->qindex = i;
694 priv->tx_queue[i]->dev = dev;
695 spin_lock_init(&(priv->tx_queue[i]->txlock));
696 }
697
698 for (i = 0; i < priv->num_rx_queues; i++) {
de47f072
JP		 699 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
700 GFP_KERNEL);
fba4ed03
SG		 701 if (!priv->rx_queue[i]) {
702 err = -ENOMEM;
703 goto rx_alloc_failed;
704 }
705 priv->rx_queue[i]->rx_skbuff = NULL;
706 priv->rx_queue[i]->qindex = i;
707 priv->rx_queue[i]->dev = dev;
708 spin_lock_init(&(priv->rx_queue[i]->rxlock));
709 }
710
711
4d7902f2
AF		 712 stash = of_get_property(np, "bd-stash", NULL);
713
a12f801d 714 if (stash) {
4d7902f2
AF		 715 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
716 priv->bd_stash_en = 1;
717 }
718
719 stash_len = of_get_property(np, "rx-stash-len", NULL);
720
721 if (stash_len)
722 priv->rx_stash_size = *stash_len;
723
724 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
725
726 if (stash_idx)
727 priv->rx_stash_index = *stash_idx;
728
729 if (stash_len || stash_idx)
730 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
731
b31a1d8b
AF		 732 mac_addr = of_get_mac_address(np);
733 if (mac_addr)
734 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
735
736 if (model && !strcasecmp(model, "TSEC"))
737 priv->device_flags =
738 FSL_GIANFAR_DEV_HAS_GIGABIT |
739 FSL_GIANFAR_DEV_HAS_COALESCE |
740 FSL_GIANFAR_DEV_HAS_RMON |
741 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
742 if (model && !strcasecmp(model, "eTSEC"))
743 priv->device_flags =
744 FSL_GIANFAR_DEV_HAS_GIGABIT |
745 FSL_GIANFAR_DEV_HAS_COALESCE |
746 FSL_GIANFAR_DEV_HAS_RMON |
747 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
2c2db48a 748 FSL_GIANFAR_DEV_HAS_PADDING |
b31a1d8b
AF		 749 FSL_GIANFAR_DEV_HAS_CSUM |
750 FSL_GIANFAR_DEV_HAS_VLAN |
751 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
97553f7f
MR		 752 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
753 FSL_GIANFAR_DEV_HAS_TIMER;
b31a1d8b
AF		 754
755 ctype = of_get_property(np, "phy-connection-type", NULL);
756
757 /* We only care about rgmii-id. The rest are autodetected */
758 if (ctype && !strcmp(ctype, "rgmii-id"))
759 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
760 else
761 priv->interface = PHY_INTERFACE_MODE_MII;
762
763 if (of_get_property(np, "fsl,magic-packet", NULL))
764 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
765
fe192a49 766 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b
AF		 767
768 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 769 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 770
771 return 0;
772
fba4ed03
SG		 773rx_alloc_failed:
774 free_rx_pointers(priv);
775tx_alloc_failed:
776 free_tx_pointers(priv);
46ceb60c
SG		 777err_grp_init:
778 unmap_group_regs(priv);
fba4ed03 779 free_netdev(dev);
b31a1d8b
AF		 780 return err;
781}
782
cc772ab7
MR		 783static int gfar_hwtstamp_ioctl(struct net_device *netdev,
784 struct ifreq *ifr, int cmd)
785{
786 struct hwtstamp_config config;
787 struct gfar_private *priv = netdev_priv(netdev);
788
789 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
790 return -EFAULT;
791
792 /* reserved for future extensions */
793 if (config.flags)
794 return -EINVAL;
795
f0ee7acf
MR		 796 switch (config.tx_type) {
797 case HWTSTAMP_TX_OFF:
798 priv->hwts_tx_en = 0;
799 break;
800 case HWTSTAMP_TX_ON:
801 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
802 return -ERANGE;
803 priv->hwts_tx_en = 1;
804 break;
805 default:
cc772ab7 806 return -ERANGE;
f0ee7acf 807 }
cc772ab7
MR		 808
809 switch (config.rx_filter) {
810 case HWTSTAMP_FILTER_NONE:
97553f7f
MR		 811 if (priv->hwts_rx_en) {
812 stop_gfar(netdev);
813 priv->hwts_rx_en = 0;
814 startup_gfar(netdev);
815 }
cc772ab7
MR		 816 break;
817 default:
818 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
819 return -ERANGE;
97553f7f
MR		 820 if (!priv->hwts_rx_en) {
821 stop_gfar(netdev);
822 priv->hwts_rx_en = 1;
823 startup_gfar(netdev);
824 }
cc772ab7
MR		 825 config.rx_filter = HWTSTAMP_FILTER_ALL;
826 break;
827 }
828
829 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
830 -EFAULT : 0;
831}
832
0faac9f7
CW		 833/* Ioctl MII Interface */
834static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
835{
836 struct gfar_private *priv = netdev_priv(dev);
837
838 if (!netif_running(dev))
839 return -EINVAL;
840
cc772ab7
MR		 841 if (cmd == SIOCSHWTSTAMP)
842 return gfar_hwtstamp_ioctl(dev, rq, cmd);
843
0faac9f7
CW		 844 if (!priv->phydev)
845 return -ENODEV;
846
28b04113 847 return phy_mii_ioctl(priv->phydev, rq, cmd);
0faac9f7
CW		 848}
849
fba4ed03
SG		 850static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
851{
852 unsigned int new_bit_map = 0x0;
853 int mask = 0x1 << (max_qs - 1), i;
854 for (i = 0; i < max_qs; i++) {
855 if (bit_map & mask)
856 new_bit_map = new_bit_map + (1 << i);
857 mask = mask >> 0x1;
858 }
859 return new_bit_map;
860}
7a8b3372 861
18294ad1
AV		 862static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
863 u32 class)
7a8b3372
SG		 864{
865 u32 rqfpr = FPR_FILER_MASK;
866 u32 rqfcr = 0x0;
867
868 rqfar--;
869 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
870 ftp_rqfpr[rqfar] = rqfpr;
871 ftp_rqfcr[rqfar] = rqfcr;
872 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
873
874 rqfar--;
875 rqfcr = RQFCR_CMP_NOMATCH;
876 ftp_rqfpr[rqfar] = rqfpr;
877 ftp_rqfcr[rqfar] = rqfcr;
878 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
879
880 rqfar--;
881 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
882 rqfpr = class;
883 ftp_rqfcr[rqfar] = rqfcr;
884 ftp_rqfpr[rqfar] = rqfpr;
885 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
886
887 rqfar--;
888 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
889 rqfpr = class;
890 ftp_rqfcr[rqfar] = rqfcr;
891 ftp_rqfpr[rqfar] = rqfpr;
892 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
893
894 return rqfar;
895}
896
897static void gfar_init_filer_table(struct gfar_private *priv)
898{
899 int i = 0x0;
900 u32 rqfar = MAX_FILER_IDX;
901 u32 rqfcr = 0x0;
902 u32 rqfpr = FPR_FILER_MASK;
903
904 /* Default rule */
905 rqfcr = RQFCR_CMP_MATCH;
906 ftp_rqfcr[rqfar] = rqfcr;
907 ftp_rqfpr[rqfar] = rqfpr;
908 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
909
910 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
911 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
912 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
913 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
914 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
915 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
916
85dd08eb 917 /* cur_filer_idx indicated the first non-masked rule */
7a8b3372
SG		 918 priv->cur_filer_idx = rqfar;
919
920 /* Rest are masked rules */
921 rqfcr = RQFCR_CMP_NOMATCH;
922 for (i = 0; i < rqfar; i++) {
923 ftp_rqfcr[i] = rqfcr;
924 ftp_rqfpr[i] = rqfpr;
925 gfar_write_filer(priv, i, rqfcr, rqfpr);
926 }
927}
928
7d350977
AV		 929static void gfar_detect_errata(struct gfar_private *priv)
930{
931 struct device *dev = &priv->ofdev->dev;
932 unsigned int pvr = mfspr(SPRN_PVR);
933 unsigned int svr = mfspr(SPRN_SVR);
934 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
935 unsigned int rev = svr & 0xffff;
936
937 /* MPC8313 Rev 2.0 and higher; All MPC837x */
938 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
939 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
940 priv->errata |= GFAR_ERRATA_74;
941
deb90eac
AV		 942 /* MPC8313 and MPC837x all rev */
943 if ((pvr == 0x80850010 && mod == 0x80b0) ||
944 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
945 priv->errata |= GFAR_ERRATA_76;
946
511d934f
AV		 947 /* MPC8313 and MPC837x all rev */
948 if ((pvr == 0x80850010 && mod == 0x80b0) ||
949 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
950 priv->errata |= GFAR_ERRATA_A002;
951
4363c2fd
AD		 952 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
953 if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
954 (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
955 priv->errata |= GFAR_ERRATA_12;
956
7d350977
AV		 957 if (priv->errata)
958 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
959 priv->errata);
960}
961
bb40dcbb
AF		 962/* Set up the ethernet device structure, private data,
963 * and anything else we need before we start */
74888760 964static int gfar_probe(struct platform_device *ofdev)
1da177e4
LT		 965{
966 u32 tempval;
967 struct net_device *dev = NULL;
968 struct gfar_private *priv = NULL;
f4983704 969 struct gfar __iomem *regs = NULL;
46ceb60c 970 int err = 0, i, grp_idx = 0;
c50a5d9a 971 int len_devname;
fba4ed03 972 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
46ceb60c 973 u32 isrg = 0;
18294ad1 974 u32 __iomem *baddr;
1da177e4 975
fba4ed03 976 err = gfar_of_init(ofdev, &dev);
1da177e4 977
fba4ed03
SG		 978 if (err)
979 return err;
1da177e4
LT		 980
981 priv = netdev_priv(dev);
4826857f
KG		 982 priv->ndev = dev;
983 priv->ofdev = ofdev;
61c7a080 984 priv->node = ofdev->dev.of_node;
4826857f 985 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 986
d87eb127 987 spin_lock_init(&priv->bflock);
ab939905 988 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 989
b31a1d8b 990 dev_set_drvdata(&ofdev->dev, priv);
46ceb60c 991 regs = priv->gfargrp[0].regs;
1da177e4 992
7d350977
AV		 993 gfar_detect_errata(priv);
994
1da177e4
LT		 995 /* Stop the DMA engine now, in case it was running before */
996 /* (The firmware could have used it, and left it running). */
257d938a 997 gfar_halt(dev);
1da177e4
LT		 998
999 /* Reset MAC layer */
f4983704 1000 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1da177e4 1001
b98ac702
AF		 1002 /* We need to delay at least 3 TX clocks */
1003 udelay(2);
1004
1da177e4 1005 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
f4983704 1006 gfar_write(&regs->maccfg1, tempval);
1da177e4
LT		 1007
1008 /* Initialize MACCFG2. */
7d350977
AV		 1009 tempval = MACCFG2_INIT_SETTINGS;
1010 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1011 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1012 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 1013
1014 /* Initialize ECNTRL */
f4983704 1015 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1da177e4 1016
1da177e4 1017 /* Set the dev->base_addr to the gfar reg region */
f4983704 1018 dev->base_addr = (unsigned long) regs;
1da177e4 1019
b31a1d8b 1020 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4
LT		 1021
1022 /* Fill in the dev structure */
1da177e4 1023 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 1024 dev->mtu = 1500;
26ccfc37 1025 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 1026 dev->ethtool_ops = &gfar_ethtool_ops;
1027
fba4ed03 1028 /* Register for napi ...We are registering NAPI for each grp */
46ceb60c
SG		 1029 for (i = 0; i < priv->num_grps; i++)
1030 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
a12f801d 1031
b31a1d8b 1032 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
8b3afe95
MM		 1033 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1034 NETIF_F_RXCSUM;
1035 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1036 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1037 }
0bbaf069
KG		 1038
1039 priv->vlgrp = NULL;
1da177e4 1040
26ccfc37 1041 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
0bbaf069 1042 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
0bbaf069 1043
b31a1d8b 1044 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
0bbaf069
KG		 1045 priv->extended_hash = 1;
1046 priv->hash_width = 9;
1047
f4983704
SG		 1048 priv->hash_regs[0] = &regs->igaddr0;
1049 priv->hash_regs[1] = &regs->igaddr1;
1050 priv->hash_regs[2] = &regs->igaddr2;
1051 priv->hash_regs[3] = &regs->igaddr3;
1052 priv->hash_regs[4] = &regs->igaddr4;
1053 priv->hash_regs[5] = &regs->igaddr5;
1054 priv->hash_regs[6] = &regs->igaddr6;
1055 priv->hash_regs[7] = &regs->igaddr7;
1056 priv->hash_regs[8] = &regs->gaddr0;
1057 priv->hash_regs[9] = &regs->gaddr1;
1058 priv->hash_regs[10] = &regs->gaddr2;
1059 priv->hash_regs[11] = &regs->gaddr3;
1060 priv->hash_regs[12] = &regs->gaddr4;
1061 priv->hash_regs[13] = &regs->gaddr5;
1062 priv->hash_regs[14] = &regs->gaddr6;
1063 priv->hash_regs[15] = &regs->gaddr7;
0bbaf069
KG		 1064
1065 } else {
1066 priv->extended_hash = 0;
1067 priv->hash_width = 8;
1068
f4983704
SG		 1069 priv->hash_regs[0] = &regs->gaddr0;
1070 priv->hash_regs[1] = &regs->gaddr1;
1071 priv->hash_regs[2] = &regs->gaddr2;
1072 priv->hash_regs[3] = &regs->gaddr3;
1073 priv->hash_regs[4] = &regs->gaddr4;
1074 priv->hash_regs[5] = &regs->gaddr5;
1075 priv->hash_regs[6] = &regs->gaddr6;
1076 priv->hash_regs[7] = &regs->gaddr7;
0bbaf069
KG		 1077 }
1078
b31a1d8b 1079 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
0bbaf069
KG		 1080 priv->padding = DEFAULT_PADDING;
1081 else
1082 priv->padding = 0;
1083
cc772ab7
MR		 1084 if (dev->features & NETIF_F_IP_CSUM ||
1085 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
0bbaf069 1086 dev->hard_header_len += GMAC_FCB_LEN;
1da177e4 1087
46ceb60c
SG		 1088 /* Program the isrg regs only if number of grps > 1 */
1089 if (priv->num_grps > 1) {
1090 baddr = &regs->isrg0;
1091 for (i = 0; i < priv->num_grps; i++) {
1092 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1093 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1094 gfar_write(baddr, isrg);
1095 baddr++;
1096 isrg = 0x0;
1097 }
1098 }
1099
fba4ed03 1100 /* Need to reverse the bit maps as bit_map's MSB is q0
984b3f57 1101 * but, for_each_set_bit parses from right to left, which
fba4ed03 1102 * basically reverses the queue numbers */
46ceb60c
SG		 1103 for (i = 0; i< priv->num_grps; i++) {
1104 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1105 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1106 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1107 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1108 }
1109
1110 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1111 * also assign queues to groups */
1112 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1113 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
984b3f57 1114 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
46ceb60c
SG		 1115 priv->num_rx_queues) {
1116 priv->gfargrp[grp_idx].num_rx_queues++;
1117 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1118 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1119 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1120 }
1121 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
984b3f57 1122 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
46ceb60c
SG		 1123 priv->num_tx_queues) {
1124 priv->gfargrp[grp_idx].num_tx_queues++;
1125 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1126 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1127 tqueue = tqueue | (TQUEUE_EN0 >> i);
1128 }
1129 priv->gfargrp[grp_idx].rstat = rstat;
1130 priv->gfargrp[grp_idx].tstat = tstat;
1131 rstat = tstat =0;
fba4ed03 1132 }
fba4ed03
SG		 1133
1134 gfar_write(&regs->rqueue, rqueue);
1135 gfar_write(&regs->tqueue, tqueue);
1136
1da177e4 1137 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1138
a12f801d 1139 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1140 for (i = 0; i < priv->num_tx_queues; i++) {
1141 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1142 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1143 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1144 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1145 }
a12f801d 1146
fba4ed03
SG		 1147 for (i = 0; i < priv->num_rx_queues; i++) {
1148 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1149 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1150 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1151 }
1da177e4 1152
1ccb8389
SG		 1153 /* enable filer if using multiple RX queues*/
1154 if(priv->num_rx_queues > 1)
1155 priv->rx_filer_enable = 1;
0bbaf069
KG		 1156 /* Enable most messages by default */
1157 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1158
d3eab82b
TP		 1159 /* Carrier starts down, phylib will bring it up */
1160 netif_carrier_off(dev);
1161
1da177e4
LT		 1162 err = register_netdev(dev);
1163
1164 if (err) {
59deab26 1165 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1da177e4
LT		 1166 goto register_fail;
1167 }
1168
2884e5cc
AV		 1169 device_init_wakeup(&dev->dev,
1170 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1171
c50a5d9a
DH		 1172 /* fill out IRQ number and name fields */
1173 len_devname = strlen(dev->name);
46ceb60c
SG		 1174 for (i = 0; i < priv->num_grps; i++) {
1175 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1176 len_devname);
1177 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1178 strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1179 "_g", sizeof("_g"));
1180 priv->gfargrp[i].int_name_tx[
1181 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1182 strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1183 priv->gfargrp[i].int_name_tx)],
1184 "_tx", sizeof("_tx") + 1);
1185
1186 strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1187 len_devname);
1188 strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1189 "_g", sizeof("_g"));
1190 priv->gfargrp[i].int_name_rx[
1191 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1192 strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1193 priv->gfargrp[i].int_name_rx)],
1194 "_rx", sizeof("_rx") + 1);
1195
1196 strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1197 len_devname);
1198 strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1199 "_g", sizeof("_g"));
1200 priv->gfargrp[i].int_name_er[strlen(
1201 priv->gfargrp[i].int_name_er)] = i+48;
1202 strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1203 priv->gfargrp[i].int_name_er)],
1204 "_er", sizeof("_er") + 1);
1205 } else
1206 priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1207 }
c50a5d9a 1208
7a8b3372
SG		 1209 /* Initialize the filer table */
1210 gfar_init_filer_table(priv);
1211
7f7f5316
AF		 1212 /* Create all the sysfs files */
1213 gfar_init_sysfs(dev);
1214
1da177e4 1215 /* Print out the device info */
59deab26 1216 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1da177e4
LT		 1217
1218 /* Even more device info helps when determining which kernel */
7f7f5316 1219 /* provided which set of benchmarks. */
59deab26 1220 netdev_info(dev, "Running with NAPI enabled\n");
fba4ed03 1221 for (i = 0; i < priv->num_rx_queues; i++)
59deab26
JP		 1222 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1223 i, priv->rx_queue[i]->rx_ring_size);
fba4ed03 1224 for(i = 0; i < priv->num_tx_queues; i++)
59deab26
JP		 1225 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1226 i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1227
1228 return 0;
1229
1230register_fail:
46ceb60c 1231 unmap_group_regs(priv);
fba4ed03
SG		 1232 free_tx_pointers(priv);
1233 free_rx_pointers(priv);
fe192a49
GL		 1234 if (priv->phy_node)
1235 of_node_put(priv->phy_node);
1236 if (priv->tbi_node)
1237 of_node_put(priv->tbi_node);
1da177e4 1238 free_netdev(dev);
bb40dcbb 1239 return err;
1da177e4
LT		 1240}
1241
2dc11581 1242static int gfar_remove(struct platform_device *ofdev)
1da177e4 1243{
b31a1d8b 1244 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1da177e4 1245
fe192a49
GL		 1246 if (priv->phy_node)
1247 of_node_put(priv->phy_node);
1248 if (priv->tbi_node)
1249 of_node_put(priv->tbi_node);
1250
b31a1d8b 1251 dev_set_drvdata(&ofdev->dev, NULL);
1da177e4 1252
d9d8e041 1253 unregister_netdev(priv->ndev);
46ceb60c 1254 unmap_group_regs(priv);
4826857f 1255 free_netdev(priv->ndev);
1da177e4
LT		 1256
1257 return 0;
1258}
1259
d87eb127 1260#ifdef CONFIG_PM
be926fc4
AV		 1261
1262static int gfar_suspend(struct device *dev)
d87eb127 1263{
be926fc4
AV		 1264 struct gfar_private *priv = dev_get_drvdata(dev);
1265 struct net_device *ndev = priv->ndev;
46ceb60c 1266 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1267 unsigned long flags;
1268 u32 tempval;
1269
1270 int magic_packet = priv->wol_en &&
b31a1d8b 1271 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1272
be926fc4 1273 netif_device_detach(ndev);
d87eb127 1274
be926fc4 1275 if (netif_running(ndev)) {
fba4ed03
SG		 1276
1277 local_irq_save(flags);
1278 lock_tx_qs(priv);
1279 lock_rx_qs(priv);
d87eb127 1280
be926fc4 1281 gfar_halt_nodisable(ndev);
d87eb127
SW		 1282
1283 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1284 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1285
1286 tempval &= ~MACCFG1_TX_EN;
1287
1288 if (!magic_packet)
1289 tempval &= ~MACCFG1_RX_EN;
1290
f4983704 1291 gfar_write(&regs->maccfg1, tempval);
d87eb127 1292
fba4ed03
SG		 1293 unlock_rx_qs(priv);
1294 unlock_tx_qs(priv);
1295 local_irq_restore(flags);
d87eb127 1296
46ceb60c 1297 disable_napi(priv);
d87eb127
SW		 1298
1299 if (magic_packet) {
1300 /* Enable interrupt on Magic Packet */
f4983704 1301 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1302
1303 /* Enable Magic Packet mode */
f4983704 1304 tempval = gfar_read(&regs->maccfg2);
d87eb127 1305 tempval |= MACCFG2_MPEN;
f4983704 1306 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1307 } else {
1308 phy_stop(priv->phydev);
1309 }
1310 }
1311
1312 return 0;
1313}
1314
be926fc4 1315static int gfar_resume(struct device *dev)
d87eb127 1316{
be926fc4
AV		 1317 struct gfar_private *priv = dev_get_drvdata(dev);
1318 struct net_device *ndev = priv->ndev;
46ceb60c 1319 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1320 unsigned long flags;
1321 u32 tempval;
1322 int magic_packet = priv->wol_en &&
b31a1d8b 1323 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1324
be926fc4
AV		 1325 if (!netif_running(ndev)) {
1326 netif_device_attach(ndev);
d87eb127
SW		 1327 return 0;
1328 }
1329
1330 if (!magic_packet && priv->phydev)
1331 phy_start(priv->phydev);
1332
1333 /* Disable Magic Packet mode, in case something
1334 * else woke us up.
1335 */
fba4ed03
SG		 1336 local_irq_save(flags);
1337 lock_tx_qs(priv);
1338 lock_rx_qs(priv);
d87eb127 1339
f4983704 1340 tempval = gfar_read(&regs->maccfg2);
d87eb127 1341 tempval &= ~MACCFG2_MPEN;
f4983704 1342 gfar_write(&regs->maccfg2, tempval);
d87eb127 1343
be926fc4 1344 gfar_start(ndev);
d87eb127 1345
fba4ed03
SG		 1346 unlock_rx_qs(priv);
1347 unlock_tx_qs(priv);
1348 local_irq_restore(flags);
d87eb127 1349
be926fc4
AV		 1350 netif_device_attach(ndev);
1351
46ceb60c 1352 enable_napi(priv);
be926fc4
AV		 1353
1354 return 0;
1355}
1356
1357static int gfar_restore(struct device *dev)
1358{
1359 struct gfar_private *priv = dev_get_drvdata(dev);
1360 struct net_device *ndev = priv->ndev;
1361
1362 if (!netif_running(ndev))
1363 return 0;
1364
1365 gfar_init_bds(ndev);
1366 init_registers(ndev);
1367 gfar_set_mac_address(ndev);
1368 gfar_init_mac(ndev);
1369 gfar_start(ndev);
1370
1371 priv->oldlink = 0;
1372 priv->oldspeed = 0;
1373 priv->oldduplex = -1;
1374
1375 if (priv->phydev)
1376 phy_start(priv->phydev);
d87eb127 1377
be926fc4 1378 netif_device_attach(ndev);
5ea681d4 1379 enable_napi(priv);
d87eb127
SW		 1380
1381 return 0;
1382}
be926fc4
AV		 1383
1384static struct dev_pm_ops gfar_pm_ops = {
1385 .suspend = gfar_suspend,
1386 .resume = gfar_resume,
1387 .freeze = gfar_suspend,
1388 .thaw = gfar_resume,
1389 .restore = gfar_restore,
1390};
1391
1392#define GFAR_PM_OPS (&gfar_pm_ops)
1393
d87eb127 1394#else
be926fc4
AV		 1395
1396#define GFAR_PM_OPS NULL
be926fc4 1397
d87eb127 1398#endif
1da177e4 1399
e8a2b6a4
AF		 1400/* Reads the controller's registers to determine what interface
1401 * connects it to the PHY.
1402 */
1403static phy_interface_t gfar_get_interface(struct net_device *dev)
1404{
1405 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1406 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1407 u32 ecntrl;
1408
f4983704 1409 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1410
1411 if (ecntrl & ECNTRL_SGMII_MODE)
1412 return PHY_INTERFACE_MODE_SGMII;
1413
1414 if (ecntrl & ECNTRL_TBI_MODE) {
1415 if (ecntrl & ECNTRL_REDUCED_MODE)
1416 return PHY_INTERFACE_MODE_RTBI;
1417 else
1418 return PHY_INTERFACE_MODE_TBI;
1419 }
1420
1421 if (ecntrl & ECNTRL_REDUCED_MODE) {
1422 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1423 return PHY_INTERFACE_MODE_RMII;
7132ab7f 1424 else {
b31a1d8b 1425 phy_interface_t interface = priv->interface;
7132ab7f
AF		 1426
1427 /*
1428 * This isn't autodetected right now, so it must
1429 * be set by the device tree or platform code.
1430 */
1431 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1432 return PHY_INTERFACE_MODE_RGMII_ID;
1433
e8a2b6a4 1434 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1435 }
e8a2b6a4
AF		 1436 }
1437
b31a1d8b 1438 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1439 return PHY_INTERFACE_MODE_GMII;
1440
1441 return PHY_INTERFACE_MODE_MII;
1442}
1443
1444
bb40dcbb
AF		 1445/* Initializes driver's PHY state, and attaches to the PHY.
1446 * Returns 0 on success.
1da177e4
LT		 1447 */
1448static int init_phy(struct net_device *dev)
1449{
1450 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1451 uint gigabit_support =
b31a1d8b 1452 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
bb40dcbb 1453 SUPPORTED_1000baseT_Full : 0;
e8a2b6a4 1454 phy_interface_t interface;
1da177e4
LT		 1455
1456 priv->oldlink = 0;
1457 priv->oldspeed = 0;
1458 priv->oldduplex = -1;
1459
e8a2b6a4
AF		 1460 interface = gfar_get_interface(dev);
1461
1db780f8
AV		 1462 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1463 interface);
1464 if (!priv->phydev)
1465 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1466 interface);
1467 if (!priv->phydev) {
1468 dev_err(&dev->dev, "could not attach to PHY\n");
1469 return -ENODEV;
fe192a49 1470 }
1da177e4 1471
d3c12873
KJ		 1472 if (interface == PHY_INTERFACE_MODE_SGMII)
1473 gfar_configure_serdes(dev);
1474
bb40dcbb 1475 /* Remove any features not supported by the controller */
fe192a49
GL		 1476 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1477 priv->phydev->advertising = priv->phydev->supported;
1da177e4
LT		 1478
1479 return 0;
1da177e4
LT		 1480}
1481
d0313587
PG		 1482/*
1483 * Initialize TBI PHY interface for communicating with the
1484 * SERDES lynx PHY on the chip. We communicate with this PHY
1485 * through the MDIO bus on each controller, treating it as a
1486 * "normal" PHY at the address found in the TBIPA register. We assume
1487 * that the TBIPA register is valid. Either the MDIO bus code will set
1488 * it to a value that doesn't conflict with other PHYs on the bus, or the
1489 * value doesn't matter, as there are no other PHYs on the bus.
1490 */
d3c12873
KJ		 1491static void gfar_configure_serdes(struct net_device *dev)
1492{
1493 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1494 struct phy_device *tbiphy;
1495
1496 if (!priv->tbi_node) {
1497 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1498 "device tree specify a tbi-handle\n");
1499 return;
1500 }
c132419e 1501
fe192a49
GL		 1502 tbiphy = of_phy_find_device(priv->tbi_node);
1503 if (!tbiphy) {
1504 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1505 return;
1506 }
d3c12873 1507
b31a1d8b
AF		 1508 /*
1509 * If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1510 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1511 * everything for us? Resetting it takes the link down and requires
1512 * several seconds for it to come back.
1513 */
fe192a49 1514 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1515 return;
d3c12873 1516
d0313587 1517 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1518 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1519
fe192a49 1520 phy_write(tbiphy, MII_ADVERTISE,
d3c12873
KJ		 1521 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1522 ADVERTISE_1000XPSE_ASYM);
1523
fe192a49 1524 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
d3c12873
KJ		 1525 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1526}
1527
1da177e4
LT		 1528static void init_registers(struct net_device *dev)
1529{
1530 struct gfar_private *priv = netdev_priv(dev);
f4983704 1531 struct gfar __iomem *regs = NULL;
46ceb60c 1532 int i = 0;
1da177e4 1533
46ceb60c
SG		 1534 for (i = 0; i < priv->num_grps; i++) {
1535 regs = priv->gfargrp[i].regs;
1536 /* Clear IEVENT */
1537 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1da177e4 1538
46ceb60c
SG		 1539 /* Initialize IMASK */
1540 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1541 }
1da177e4 1542
46ceb60c 1543 regs = priv->gfargrp[0].regs;
1da177e4 1544 /* Init hash registers to zero */
f4983704
SG		 1545 gfar_write(&regs->igaddr0, 0);
1546 gfar_write(&regs->igaddr1, 0);
1547 gfar_write(&regs->igaddr2, 0);
1548 gfar_write(&regs->igaddr3, 0);
1549 gfar_write(&regs->igaddr4, 0);
1550 gfar_write(&regs->igaddr5, 0);
1551 gfar_write(&regs->igaddr6, 0);
1552 gfar_write(&regs->igaddr7, 0);
1553
1554 gfar_write(&regs->gaddr0, 0);
1555 gfar_write(&regs->gaddr1, 0);
1556 gfar_write(&regs->gaddr2, 0);
1557 gfar_write(&regs->gaddr3, 0);
1558 gfar_write(&regs->gaddr4, 0);
1559 gfar_write(&regs->gaddr5, 0);
1560 gfar_write(&regs->gaddr6, 0);
1561 gfar_write(&regs->gaddr7, 0);
1da177e4 1562
1da177e4 1563 /* Zero out the rmon mib registers if it has them */
b31a1d8b 1564 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
f4983704 1565 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1da177e4
LT		 1566
1567 /* Mask off the CAM interrupts */
f4983704
SG		 1568 gfar_write(&regs->rmon.cam1, 0xffffffff);
1569 gfar_write(&regs->rmon.cam2, 0xffffffff);
1da177e4
LT		 1570 }
1571
1572 /* Initialize the max receive buffer length */
f4983704 1573 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1da177e4 1574
1da177e4 1575 /* Initialize the Minimum Frame Length Register */
f4983704 1576 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1da177e4
LT		 1577}
1578
511d934f
AV		 1579static int __gfar_is_rx_idle(struct gfar_private *priv)
1580{
1581 u32 res;
1582
1583 /*
1584 * Normaly TSEC should not hang on GRS commands, so we should
1585 * actually wait for IEVENT_GRSC flag.
1586 */
1587 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1588 return 0;
1589
1590 /*
1591 * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1592 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1593 * and the Rx can be safely reset.
1594 */
1595 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1596 res &= 0x7f807f80;
1597 if ((res & 0xffff) == (res >> 16))
1598 return 1;
1599
1600 return 0;
1601}
0bbaf069
KG		 1602
1603/* Halt the receive and transmit queues */
d87eb127 1604static void gfar_halt_nodisable(struct net_device *dev)
1da177e4
LT		 1605{
1606 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1607 struct gfar __iomem *regs = NULL;
1da177e4 1608 u32 tempval;
46ceb60c 1609 int i = 0;
1da177e4 1610
46ceb60c
SG		 1611 for (i = 0; i < priv->num_grps; i++) {
1612 regs = priv->gfargrp[i].regs;
1613 /* Mask all interrupts */
1614 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1da177e4 1615
46ceb60c
SG		 1616 /* Clear all interrupts */
1617 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1618 }
1da177e4 1619
46ceb60c 1620 regs = priv->gfargrp[0].regs;
1da177e4 1621 /* Stop the DMA, and wait for it to stop */
f4983704 1622 tempval = gfar_read(&regs->dmactrl);
1da177e4
LT		 1623 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1624 != (DMACTRL_GRS | DMACTRL_GTS)) {
511d934f
AV		 1625 int ret;
1626
1da177e4 1627 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
f4983704 1628 gfar_write(&regs->dmactrl, tempval);
1da177e4 1629
511d934f
AV		 1630 do {
1631 ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1632 (IEVENT_GRSC | IEVENT_GTSC)) ==
1633 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1634 if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1635 ret = __gfar_is_rx_idle(priv);
1636 } while (!ret);
1da177e4 1637 }
d87eb127 1638}
d87eb127
SW		 1639
1640/* Halt the receive and transmit queues */
1641void gfar_halt(struct net_device *dev)
1642{
1643 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1644 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1645 u32 tempval;
1da177e4 1646
2a54adc3
SW		 1647 gfar_halt_nodisable(dev);
1648
1da177e4
LT		 1649 /* Disable Rx and Tx */
1650 tempval = gfar_read(&regs->maccfg1);
1651 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1652 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1653}
1654
46ceb60c
SG		 1655static void free_grp_irqs(struct gfar_priv_grp *grp)
1656{
1657 free_irq(grp->interruptError, grp);
1658 free_irq(grp->interruptTransmit, grp);
1659 free_irq(grp->interruptReceive, grp);
1660}
1661
0bbaf069
KG		 1662void stop_gfar(struct net_device *dev)
1663{
1664 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1665 unsigned long flags;
46ceb60c 1666 int i;
0bbaf069 1667
bb40dcbb
AF		 1668 phy_stop(priv->phydev);
1669
a12f801d 1670
0bbaf069 1671 /* Lock it down */
fba4ed03
SG		 1672 local_irq_save(flags);
1673 lock_tx_qs(priv);
1674 lock_rx_qs(priv);
0bbaf069 1675
0bbaf069 1676 gfar_halt(dev);
1da177e4 1677
fba4ed03
SG		 1678 unlock_rx_qs(priv);
1679 unlock_tx_qs(priv);
1680 local_irq_restore(flags);
1da177e4
LT		 1681
1682 /* Free the IRQs */
b31a1d8b 1683 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 1684 for (i = 0; i < priv->num_grps; i++)
1685 free_grp_irqs(&priv->gfargrp[i]);
1da177e4 1686 } else {
46ceb60c
SG		 1687 for (i = 0; i < priv->num_grps; i++)
1688 free_irq(priv->gfargrp[i].interruptTransmit,
1689 &priv->gfargrp[i]);
1da177e4
LT		 1690 }
1691
1692 free_skb_resources(priv);
1da177e4
LT		 1693}
1694
fba4ed03 1695static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1696{
1da177e4 1697 struct txbd8 *txbdp;
fba4ed03 1698 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1699 int i, j;
1da177e4 1700
a12f801d 1701 txbdp = tx_queue->tx_bd_base;
1da177e4 1702
a12f801d
SG		 1703 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1704 if (!tx_queue->tx_skbuff[i])
4669bc90 1705 continue;
1da177e4 1706
4826857f 1707 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90
DH		 1708 txbdp->length, DMA_TO_DEVICE);
1709 txbdp->lstatus = 0;
fba4ed03
SG		 1710 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1711 j++) {
4669bc90 1712 txbdp++;
4826857f 1713 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90 1714 txbdp->length, DMA_TO_DEVICE);
1da177e4 1715 }
ad5da7ab 1716 txbdp++;
a12f801d
SG		 1717 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1718 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1719 }
a12f801d 1720 kfree(tx_queue->tx_skbuff);
fba4ed03 1721}
1da177e4 1722
fba4ed03
SG		 1723static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1724{
1725 struct rxbd8 *rxbdp;
1726 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1727 int i;
1da177e4 1728
fba4ed03 1729 rxbdp = rx_queue->rx_bd_base;
1da177e4 1730
a12f801d
SG		 1731 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1732 if (rx_queue->rx_skbuff[i]) {
fba4ed03
SG		 1733 dma_unmap_single(&priv->ofdev->dev,
1734 rxbdp->bufPtr, priv->rx_buffer_size,
e69edd21 1735 DMA_FROM_DEVICE);
a12f801d
SG		 1736 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1737 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1738 }
e69edd21
AV		 1739 rxbdp->lstatus = 0;
1740 rxbdp->bufPtr = 0;
1741 rxbdp++;
1da177e4 1742 }
a12f801d 1743 kfree(rx_queue->rx_skbuff);
fba4ed03 1744}
e69edd21 1745
fba4ed03
SG		 1746/* If there are any tx skbs or rx skbs still around, free them.
1747 * Then free tx_skbuff and rx_skbuff */
1748static void free_skb_resources(struct gfar_private *priv)
1749{
1750 struct gfar_priv_tx_q *tx_queue = NULL;
1751 struct gfar_priv_rx_q *rx_queue = NULL;
1752 int i;
1753
1754 /* Go through all the buffer descriptors and free their data buffers */
1755 for (i = 0; i < priv->num_tx_queues; i++) {
1756 tx_queue = priv->tx_queue[i];
7c0d10d3 1757 if(tx_queue->tx_skbuff)
fba4ed03
SG		 1758 free_skb_tx_queue(tx_queue);
1759 }
1760
1761 for (i = 0; i < priv->num_rx_queues; i++) {
1762 rx_queue = priv->rx_queue[i];
7c0d10d3 1763 if(rx_queue->rx_skbuff)
fba4ed03
SG		 1764 free_skb_rx_queue(rx_queue);
1765 }
1766
1767 dma_free_coherent(&priv->ofdev->dev,
1768 sizeof(struct txbd8) * priv->total_tx_ring_size +
1769 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1770 priv->tx_queue[0]->tx_bd_base,
1771 priv->tx_queue[0]->tx_bd_dma_base);
7df9c43f 1772 skb_queue_purge(&priv->rx_recycle);
1da177e4
LT		 1773}
1774
0bbaf069
KG		 1775void gfar_start(struct net_device *dev)
1776{
1777 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1778 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1779 u32 tempval;
46ceb60c 1780 int i = 0;
0bbaf069
KG		 1781
1782 /* Enable Rx and Tx in MACCFG1 */
1783 tempval = gfar_read(&regs->maccfg1);
1784 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1785 gfar_write(&regs->maccfg1, tempval);
1786
1787 /* Initialize DMACTRL to have WWR and WOP */
f4983704 1788 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1789 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 1790 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1791
0bbaf069 1792 /* Make sure we aren't stopped */
f4983704 1793 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1794 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 1795 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1796
46ceb60c
SG		 1797 for (i = 0; i < priv->num_grps; i++) {
1798 regs = priv->gfargrp[i].regs;
1799 /* Clear THLT/RHLT, so that the DMA starts polling now */
1800 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1801 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1802 /* Unmask the interrupts we look for */
1803 gfar_write(&regs->imask, IMASK_DEFAULT);
1804 }
12dea57b 1805
1ae5dc34 1806 dev->trans_start = jiffies; /* prevent tx timeout */
0bbaf069
KG		 1807}
1808
46ceb60c 1809void gfar_configure_coalescing(struct gfar_private *priv,
18294ad1 1810 unsigned long tx_mask, unsigned long rx_mask)
1da177e4 1811{
46ceb60c 1812 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 1813 u32 __iomem *baddr;
46ceb60c 1814 int i = 0;
1da177e4 1815
46ceb60c
SG		 1816 /* Backward compatible case ---- even if we enable
1817 * multiple queues, there's only single reg to program
1818 */
1819 gfar_write(&regs->txic, 0);
1820 if(likely(priv->tx_queue[0]->txcoalescing))
1821 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1da177e4 1822
46ceb60c
SG		 1823 gfar_write(&regs->rxic, 0);
1824 if(unlikely(priv->rx_queue[0]->rxcoalescing))
1825 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
815b97c6 1826
46ceb60c
SG		 1827 if (priv->mode == MQ_MG_MODE) {
1828 baddr = &regs->txic0;
984b3f57 1829 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
46ceb60c
SG		 1830 if (likely(priv->tx_queue[i]->txcoalescing)) {
1831 gfar_write(baddr + i, 0);
1832 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1833 }
1834 }
1835
1836 baddr = &regs->rxic0;
984b3f57 1837 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
46ceb60c
SG		 1838 if (likely(priv->rx_queue[i]->rxcoalescing)) {
1839 gfar_write(baddr + i, 0);
1840 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1841 }
1842 }
1843 }
1844}
1845
1846static int register_grp_irqs(struct gfar_priv_grp *grp)
1847{
1848 struct gfar_private *priv = grp->priv;
1849 struct net_device *dev = priv->ndev;
1850 int err;
1da177e4 1851
1da177e4
LT		 1852 /* If the device has multiple interrupts, register for
1853 * them. Otherwise, only register for the one */
b31a1d8b 1854 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 1855 /* Install our interrupt handlers for Error,
1da177e4 1856 * Transmit, and Receive */
46ceb60c
SG		 1857 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1858 grp->int_name_er,grp)) < 0) {
59deab26
JP		 1859 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1860 grp->interruptError);
46ceb60c 1861
2145f1af 1862 goto err_irq_fail;
1da177e4
LT		 1863 }
1864
46ceb60c
SG		 1865 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1866 0, grp->int_name_tx, grp)) < 0) {
59deab26
JP		 1867 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1868 grp->interruptTransmit);
1da177e4
LT		 1869 goto tx_irq_fail;
1870 }
1871
46ceb60c
SG		 1872 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1873 grp->int_name_rx, grp)) < 0) {
59deab26
JP		 1874 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1875 grp->interruptReceive);
1da177e4
LT		 1876 goto rx_irq_fail;
1877 }
1878 } else {
46ceb60c
SG		 1879 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1880 grp->int_name_tx, grp)) < 0) {
59deab26
JP		 1881 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1882 grp->interruptTransmit);
1da177e4
LT		 1883 goto err_irq_fail;
1884 }
1885 }
1886
46ceb60c
SG		 1887 return 0;
1888
1889rx_irq_fail:
1890 free_irq(grp->interruptTransmit, grp);
1891tx_irq_fail:
1892 free_irq(grp->interruptError, grp);
1893err_irq_fail:
1894 return err;
1895
1896}
1897
1898/* Bring the controller up and running */
1899int startup_gfar(struct net_device *ndev)
1900{
1901 struct gfar_private *priv = netdev_priv(ndev);
1902 struct gfar __iomem *regs = NULL;
1903 int err, i, j;
1904
1905 for (i = 0; i < priv->num_grps; i++) {
1906 regs= priv->gfargrp[i].regs;
1907 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1908 }
1909
1910 regs= priv->gfargrp[0].regs;
1911 err = gfar_alloc_skb_resources(ndev);
1912 if (err)
1913 return err;
1914
1915 gfar_init_mac(ndev);
1916
1917 for (i = 0; i < priv->num_grps; i++) {
1918 err = register_grp_irqs(&priv->gfargrp[i]);
1919 if (err) {
1920 for (j = 0; j < i; j++)
1921 free_grp_irqs(&priv->gfargrp[j]);
ff76015f 1922 goto irq_fail;
46ceb60c
SG		 1923 }
1924 }
1925
7f7f5316 1926 /* Start the controller */
ccc05c6e 1927 gfar_start(ndev);
1da177e4 1928
826aa4a0
AV		 1929 phy_start(priv->phydev);
1930
46ceb60c
SG		 1931 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1932
1da177e4
LT		 1933 return 0;
1934
46ceb60c 1935irq_fail:
e69edd21 1936 free_skb_resources(priv);
1da177e4
LT		 1937 return err;
1938}
1939
1940/* Called when something needs to use the ethernet device */
1941/* Returns 0 for success. */
1942static int gfar_enet_open(struct net_device *dev)
1943{
94e8cc35 1944 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 1945 int err;
1946
46ceb60c 1947 enable_napi(priv);
bea3348e 1948
0fd56bb5
AF		 1949 skb_queue_head_init(&priv->rx_recycle);
1950
1da177e4
LT		 1951 /* Initialize a bunch of registers */
1952 init_registers(dev);
1953
1954 gfar_set_mac_address(dev);
1955
1956 err = init_phy(dev);
1957
a12f801d 1958 if (err) {
46ceb60c 1959 disable_napi(priv);
1da177e4 1960 return err;
bea3348e 1961 }
1da177e4
LT		 1962
1963 err = startup_gfar(dev);
db0e8e3f 1964 if (err) {
46ceb60c 1965 disable_napi(priv);
db0e8e3f
AV		 1966 return err;
1967 }
1da177e4 1968
fba4ed03 1969 netif_tx_start_all_queues(dev);
1da177e4 1970
2884e5cc
AV		 1971 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1972
1da177e4
LT		 1973 return err;
1974}
1975
54dc79fe 1976static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 1977{
54dc79fe 1978 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 1979
1980 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 1981
0bbaf069
KG		 1982 return fcb;
1983}
1984
1985static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1986{
7f7f5316 1987 u8 flags = 0;
0bbaf069
KG		 1988
1989 /* If we're here, it's a IP packet with a TCP or UDP
1990 * payload. We set it to checksum, using a pseudo-header
1991 * we provide
1992 */
7f7f5316 1993 flags = TXFCB_DEFAULT;
0bbaf069 1994
7f7f5316
AF		 1995 /* Tell the controller what the protocol is */
1996 /* And provide the already calculated phcs */
eddc9ec5 1997 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 1998 flags |= TXFCB_UDP;
4bedb452 1999 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 2000 } else
8da32de5 2001 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 2002
2003 /* l3os is the distance between the start of the
2004 * frame (skb->data) and the start of the IP hdr.
2005 * l4os is the distance between the start of the
2006 * l3 hdr and the l4 hdr */
bbe735e4 2007 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
cfe1fc77 2008 fcb->l4os = skb_network_header_len(skb);
0bbaf069 2009
7f7f5316 2010 fcb->flags = flags;
0bbaf069
KG		 2011}
2012
7f7f5316 2013void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 2014{
7f7f5316 2015 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 2016 fcb->vlctl = vlan_tx_tag_get(skb);
2017}
2018
4669bc90
DH		 2019static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2020 struct txbd8 *base, int ring_size)
2021{
2022 struct txbd8 *new_bd = bdp + stride;
2023
2024 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2025}
2026
2027static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2028 int ring_size)
2029{
2030 return skip_txbd(bdp, 1, base, ring_size);
2031}
2032
1da177e4
LT		 2033/* This is called by the kernel when a frame is ready for transmission. */
2034/* It is pointed to by the dev->hard_start_xmit function pointer */
2035static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2036{
2037 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2038 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 2039 struct netdev_queue *txq;
f4983704 2040 struct gfar __iomem *regs = NULL;
0bbaf069 2041 struct txfcb *fcb = NULL;
f0ee7acf 2042 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 2043 u32 lstatus;
f0ee7acf 2044 int i, rq = 0, do_tstamp = 0;
4669bc90 2045 u32 bufaddr;
fef6108d 2046 unsigned long flags;
f0ee7acf 2047 unsigned int nr_frags, nr_txbds, length;
fba4ed03 2048
deb90eac
AV		 2049 /*
2050 * TOE=1 frames larger than 2500 bytes may see excess delays
2051 * before start of transmission.
2052 */
2053 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2054 skb->ip_summed == CHECKSUM_PARTIAL &&
2055 skb->len > 2500)) {
2056 int ret;
2057
2058 ret = skb_checksum_help(skb);
2059 if (ret)
2060 return ret;
2061 }
2062
fba4ed03
SG		 2063 rq = skb->queue_mapping;
2064 tx_queue = priv->tx_queue[rq];
2065 txq = netdev_get_tx_queue(dev, rq);
a12f801d 2066 base = tx_queue->tx_bd_base;
46ceb60c 2067 regs = tx_queue->grp->regs;
f0ee7acf
MR		 2068
2069 /* check if time stamp should be generated */
2244d07b
OH		 2070 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2071 priv->hwts_tx_en))
f0ee7acf 2072 do_tstamp = 1;
4669bc90 2073
5b28beaf
LY		 2074 /* make space for additional header when fcb is needed */
2075 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
eab6d18d 2076 vlan_tx_tag_present(skb) ||
f0ee7acf 2077 unlikely(do_tstamp)) &&
5b28beaf 2078 (skb_headroom(skb) < GMAC_FCB_LEN)) {
54dc79fe
SH		 2079 struct sk_buff *skb_new;
2080
2081 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2082 if (!skb_new) {
2083 dev->stats.tx_errors++;
bd14ba84 2084 kfree_skb(skb);
54dc79fe
SH		 2085 return NETDEV_TX_OK;
2086 }
2087 kfree_skb(skb);
2088 skb = skb_new;
2089 }
2090
4669bc90
DH		 2091 /* total number of fragments in the SKB */
2092 nr_frags = skb_shinfo(skb)->nr_frags;
2093
f0ee7acf
MR		 2094 /* calculate the required number of TxBDs for this skb */
2095 if (unlikely(do_tstamp))
2096 nr_txbds = nr_frags + 2;
2097 else
2098 nr_txbds = nr_frags + 1;
2099
4669bc90 2100 /* check if there is space to queue this packet */
f0ee7acf 2101 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2102 /* no space, stop the queue */
fba4ed03 2103 netif_tx_stop_queue(txq);
4669bc90 2104 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2105 return NETDEV_TX_BUSY;
2106 }
1da177e4
LT		 2107
2108 /* Update transmit stats */
1ac9ad13
ED		 2109 tx_queue->stats.tx_bytes += skb->len;
2110 tx_queue->stats.tx_packets++;
1da177e4 2111
a12f801d 2112 txbdp = txbdp_start = tx_queue->cur_tx;
f0ee7acf
MR		 2113 lstatus = txbdp->lstatus;
2114
2115 /* Time stamp insertion requires one additional TxBD */
2116 if (unlikely(do_tstamp))
2117 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2118 tx_queue->tx_ring_size);
1da177e4 2119
4669bc90 2120 if (nr_frags == 0) {
f0ee7acf
MR		 2121 if (unlikely(do_tstamp))
2122 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2123 TXBD_INTERRUPT);
2124 else
2125 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
4669bc90
DH		 2126 } else {
2127 /* Place the fragment addresses and lengths into the TxBDs */
2128 for (i = 0; i < nr_frags; i++) {
2129 /* Point at the next BD, wrapping as needed */
a12f801d 2130 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2131
2132 length = skb_shinfo(skb)->frags[i].size;
2133
2134 lstatus = txbdp->lstatus | length |
2135 BD_LFLAG(TXBD_READY);
2136
2137 /* Handle the last BD specially */
2138 if (i == nr_frags - 1)
2139 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2140
4826857f 2141 bufaddr = dma_map_page(&priv->ofdev->dev,
4669bc90
DH		 2142 skb_shinfo(skb)->frags[i].page,
2143 skb_shinfo(skb)->frags[i].page_offset,
2144 length,
2145 DMA_TO_DEVICE);
2146
2147 /* set the TxBD length and buffer pointer */
2148 txbdp->bufPtr = bufaddr;
2149 txbdp->lstatus = lstatus;
2150 }
2151
2152 lstatus = txbdp_start->lstatus;
2153 }
1da177e4 2154
0bbaf069 2155 /* Set up checksumming */
12dea57b 2156 if (CHECKSUM_PARTIAL == skb->ip_summed) {
54dc79fe 2157 fcb = gfar_add_fcb(skb);
4363c2fd
AD		 2158 /* as specified by errata */
2159 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12)
2160 && ((unsigned long)fcb % 0x20) > 0x18)) {
2161 __skb_pull(skb, GMAC_FCB_LEN);
2162 skb_checksum_help(skb);
2163 } else {
2164 lstatus |= BD_LFLAG(TXBD_TOE);
2165 gfar_tx_checksum(skb, fcb);
2166 }
0bbaf069
KG		 2167 }
2168
eab6d18d 2169 if (vlan_tx_tag_present(skb)) {
54dc79fe
SH		 2170 if (unlikely(NULL == fcb)) {
2171 fcb = gfar_add_fcb(skb);
5a5efed4 2172 lstatus |= BD_LFLAG(TXBD_TOE);
7f7f5316 2173 }
54dc79fe
SH		 2174
2175 gfar_tx_vlan(skb, fcb);
0bbaf069
KG		 2176 }
2177
f0ee7acf
MR		 2178 /* Setup tx hardware time stamping if requested */
2179 if (unlikely(do_tstamp)) {
2244d07b 2180 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
f0ee7acf
MR		 2181 if (fcb == NULL)
2182 fcb = gfar_add_fcb(skb);
2183 fcb->ptp = 1;
2184 lstatus |= BD_LFLAG(TXBD_TOE);
2185 }
2186
4826857f 2187 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
4669bc90 2188 skb_headlen(skb), DMA_TO_DEVICE);
1da177e4 2189
f0ee7acf
MR		 2190 /*
2191 * If time stamping is requested one additional TxBD must be set up. The
2192 * first TxBD points to the FCB and must have a data length of
2193 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2194 * the full frame length.
2195 */
2196 if (unlikely(do_tstamp)) {
2197 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2198 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2199 (skb_headlen(skb) - GMAC_FCB_LEN);
2200 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2201 } else {
2202 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2203 }
1da177e4 2204
a3bc1f11
AV		 2205 /*
2206 * We can work in parallel with gfar_clean_tx_ring(), except
2207 * when modifying num_txbdfree. Note that we didn't grab the lock
2208 * when we were reading the num_txbdfree and checking for available
2209 * space, that's because outside of this function it can only grow,
2210 * and once we've got needed space, it cannot suddenly disappear.
2211 *
2212 * The lock also protects us from gfar_error(), which can modify
2213 * regs->tstat and thus retrigger the transfers, which is why we
2214 * also must grab the lock before setting ready bit for the first
2215 * to be transmitted BD.
2216 */
2217 spin_lock_irqsave(&tx_queue->txlock, flags);
2218
4669bc90
DH		 2219 /*
2220 * The powerpc-specific eieio() is used, as wmb() has too strong
3b6330ce
SW		 2221 * semantics (it requires synchronization between cacheable and
2222 * uncacheable mappings, which eieio doesn't provide and which we
2223 * don't need), thus requiring a more expensive sync instruction. At
2224 * some point, the set of architecture-independent barrier functions
2225 * should be expanded to include weaker barriers.
2226 */
3b6330ce 2227 eieio();
7f7f5316 2228
4669bc90
DH		 2229 txbdp_start->lstatus = lstatus;
2230
0eddba52
AV		 2231 eieio(); /* force lstatus write before tx_skbuff */
2232
2233 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2234
4669bc90
DH		 2235 /* Update the current skb pointer to the next entry we will use
2236 * (wrapping if necessary) */
a12f801d
SG		 2237 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2238 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2239
a12f801d 2240 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2241
2242 /* reduce TxBD free count */
f0ee7acf 2243 tx_queue->num_txbdfree -= (nr_txbds);
1da177e4
LT		 2244
2245 /* If the next BD still needs to be cleaned up, then the bds
2246 are full. We need to tell the kernel to stop sending us stuff. */
a12f801d 2247 if (!tx_queue->num_txbdfree) {
fba4ed03 2248 netif_tx_stop_queue(txq);
1da177e4 2249
09f75cd7 2250 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2251 }
2252
1da177e4 2253 /* Tell the DMA to go go go */
fba4ed03 2254 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4
LT		 2255
2256 /* Unlock priv */
a12f801d 2257 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 2258
54dc79fe 2259 return NETDEV_TX_OK;
1da177e4
LT		 2260}
2261
2262/* Stops the kernel queue, and halts the controller */
2263static int gfar_close(struct net_device *dev)
2264{
2265 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2266
46ceb60c 2267 disable_napi(priv);
bea3348e 2268
ab939905 2269 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2270 stop_gfar(dev);
2271
bb40dcbb
AF		 2272 /* Disconnect from the PHY */
2273 phy_disconnect(priv->phydev);
2274 priv->phydev = NULL;
1da177e4 2275
fba4ed03 2276 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2277
2278 return 0;
2279}
2280
1da177e4 2281/* Changes the mac address if the controller is not running. */
f162b9d5 2282static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2283{
7f7f5316 2284 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2285
2286 return 0;
2287}
2288
2289
0bbaf069
KG		 2290/* Enables and disables VLAN insertion/extraction */
2291static void gfar_vlan_rx_register(struct net_device *dev,
2292 struct vlan_group *grp)
2293{
2294 struct gfar_private *priv = netdev_priv(dev);
f4983704 2295 struct gfar __iomem *regs = NULL;
0bbaf069
KG		 2296 unsigned long flags;
2297 u32 tempval;
2298
46ceb60c 2299 regs = priv->gfargrp[0].regs;
fba4ed03
SG		 2300 local_irq_save(flags);
2301 lock_rx_qs(priv);
0bbaf069 2302
cd1f55a5 2303 priv->vlgrp = grp;
0bbaf069
KG		 2304
2305 if (grp) {
2306 /* Enable VLAN tag insertion */
f4983704 2307 tempval = gfar_read(&regs->tctrl);
0bbaf069
KG		 2308 tempval |= TCTRL_VLINS;
2309
f4983704 2310 gfar_write(&regs->tctrl, tempval);
6aa20a22 2311
0bbaf069 2312 /* Enable VLAN tag extraction */
f4983704 2313 tempval = gfar_read(&regs->rctrl);
77ecaf2d 2314 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
f4983704 2315 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2316 } else {
2317 /* Disable VLAN tag insertion */
f4983704 2318 tempval = gfar_read(&regs->tctrl);
0bbaf069 2319 tempval &= ~TCTRL_VLINS;
f4983704 2320 gfar_write(&regs->tctrl, tempval);
0bbaf069
KG		 2321
2322 /* Disable VLAN tag extraction */
f4983704 2323 tempval = gfar_read(&regs->rctrl);
0bbaf069 2324 tempval &= ~RCTRL_VLEX;
77ecaf2d
DH		 2325 /* If parse is no longer required, then disable parser */
2326 if (tempval & RCTRL_REQ_PARSER)
2327 tempval |= RCTRL_PRSDEP_INIT;
2328 else
2329 tempval &= ~RCTRL_PRSDEP_INIT;
f4983704 2330 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2331 }
2332
77ecaf2d
DH		 2333 gfar_change_mtu(dev, dev->mtu);
2334
fba4ed03
SG		 2335 unlock_rx_qs(priv);
2336 local_irq_restore(flags);
0bbaf069
KG		 2337}
2338
1da177e4
LT		 2339static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2340{
2341 int tempsize, tempval;
2342 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2343 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 2344 int oldsize = priv->rx_buffer_size;
0bbaf069
KG		 2345 int frame_size = new_mtu + ETH_HLEN;
2346
77ecaf2d 2347 if (priv->vlgrp)
faa89577 2348 frame_size += VLAN_HLEN;
0bbaf069 2349
1da177e4 2350 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
59deab26 2351 netif_err(priv, drv, dev, "Invalid MTU setting\n");
1da177e4
LT		 2352 return -EINVAL;
2353 }
2354
77ecaf2d
DH		 2355 if (gfar_uses_fcb(priv))
2356 frame_size += GMAC_FCB_LEN;
2357
2358 frame_size += priv->padding;
2359
1da177e4
LT		 2360 tempsize =
2361 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2362 INCREMENTAL_BUFFER_SIZE;
2363
2364 /* Only stop and start the controller if it isn't already
7f7f5316 2365 * stopped, and we changed something */
1da177e4
LT		 2366 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2367 stop_gfar(dev);
2368
2369 priv->rx_buffer_size = tempsize;
2370
2371 dev->mtu = new_mtu;
2372
f4983704
SG		 2373 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2374 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
1da177e4
LT		 2375
2376 /* If the mtu is larger than the max size for standard
2377 * ethernet frames (ie, a jumbo frame), then set maccfg2
2378 * to allow huge frames, and to check the length */
f4983704 2379 tempval = gfar_read(&regs->maccfg2);
1da177e4 2380
7d350977
AV		 2381 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2382 gfar_has_errata(priv, GFAR_ERRATA_74))
1da177e4
LT		 2383 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2384 else
2385 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2386
f4983704 2387 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 2388
2389 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2390 startup_gfar(dev);
2391
2392 return 0;
2393}
2394
ab939905 2395/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2396 * transmitted after a set amount of time.
2397 * For now, assume that clearing out all the structures, and
ab939905
SS		 2398 * starting over will fix the problem.
2399 */
2400static void gfar_reset_task(struct work_struct *work)
1da177e4 2401{
ab939905
SS		 2402 struct gfar_private *priv = container_of(work, struct gfar_private,
2403 reset_task);
4826857f 2404 struct net_device *dev = priv->ndev;
1da177e4
LT		 2405
2406 if (dev->flags & IFF_UP) {
fba4ed03 2407 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2408 stop_gfar(dev);
2409 startup_gfar(dev);
fba4ed03 2410 netif_tx_start_all_queues(dev);
1da177e4
LT		 2411 }
2412
263ba320 2413 netif_tx_schedule_all(dev);
1da177e4
LT		 2414}
2415
ab939905
SS		 2416static void gfar_timeout(struct net_device *dev)
2417{
2418 struct gfar_private *priv = netdev_priv(dev);
2419
2420 dev->stats.tx_errors++;
2421 schedule_work(&priv->reset_task);
2422}
2423
acbc0f03
EL		 2424static void gfar_align_skb(struct sk_buff *skb)
2425{
2426 /* We need the data buffer to be aligned properly. We will reserve
2427 * as many bytes as needed to align the data properly
2428 */
2429 skb_reserve(skb, RXBUF_ALIGNMENT -
2430 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2431}
2432
1da177e4 2433/* Interrupt Handler for Transmit complete */
a12f801d 2434static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2435{
a12f801d 2436 struct net_device *dev = tx_queue->dev;
d080cd63 2437 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2438 struct gfar_priv_rx_q *rx_queue = NULL;
f0ee7acf 2439 struct txbd8 *bdp, *next = NULL;
4669bc90 2440 struct txbd8 *lbdp = NULL;
a12f801d 2441 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2442 struct sk_buff *skb;
2443 int skb_dirtytx;
a12f801d 2444 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2445 int frags = 0, nr_txbds = 0;
4669bc90 2446 int i;
d080cd63 2447 int howmany = 0;
4669bc90 2448 u32 lstatus;
f0ee7acf 2449 size_t buflen;
1da177e4 2450
fba4ed03 2451 rx_queue = priv->rx_queue[tx_queue->qindex];
a12f801d
SG		 2452 bdp = tx_queue->dirty_tx;
2453 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2454
a12f801d 2455 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11
AV		 2456 unsigned long flags;
2457
4669bc90 2458 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf
MR		 2459
2460 /*
2461 * When time stamping, one additional TxBD must be freed.
2462 * Also, we need to dma_unmap_single() the TxPAL.
2463 */
2244d07b 2464 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
f0ee7acf
MR		 2465 nr_txbds = frags + 2;
2466 else
2467 nr_txbds = frags + 1;
2468
2469 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2470
4669bc90 2471 lstatus = lbdp->lstatus;
1da177e4 2472
4669bc90
DH		 2473 /* Only clean completed frames */
2474 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2475 (lstatus & BD_LENGTH_MASK))
2476 break;
2477
2244d07b 2478 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf
MR		 2479 next = next_txbd(bdp, base, tx_ring_size);
2480 buflen = next->length + GMAC_FCB_LEN;
2481 } else
2482 buflen = bdp->length;
2483
2484 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2485 buflen, DMA_TO_DEVICE);
2486
2244d07b 2487 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf
MR		 2488 struct skb_shared_hwtstamps shhwtstamps;
2489 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2490 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2491 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2492 skb_tstamp_tx(skb, &shhwtstamps);
2493 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2494 bdp = next;
2495 }
81183059 2496
4669bc90
DH		 2497 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2498 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2499
4669bc90 2500 for (i = 0; i < frags; i++) {
4826857f 2501 dma_unmap_page(&priv->ofdev->dev,
4669bc90
DH		 2502 bdp->bufPtr,
2503 bdp->length,
2504 DMA_TO_DEVICE);
2505 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2506 bdp = next_txbd(bdp, base, tx_ring_size);
2507 }
1da177e4 2508
0fd56bb5
AF		 2509 /*
2510 * If there's room in the queue (limit it to rx_buffer_size)
2511 * we add this skb back into the pool, if it's the right size
2512 */
a12f801d 2513 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
0fd56bb5 2514 skb_recycle_check(skb, priv->rx_buffer_size +
acbc0f03
EL		 2515 RXBUF_ALIGNMENT)) {
2516 gfar_align_skb(skb);
cd0ea241 2517 skb_queue_head(&priv->rx_recycle, skb);
acbc0f03 2518 } else
0fd56bb5
AF		 2519 dev_kfree_skb_any(skb);
2520
a12f801d 2521 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2522
4669bc90
DH		 2523 skb_dirtytx = (skb_dirtytx + 1) &
2524 TX_RING_MOD_MASK(tx_ring_size);
2525
2526 howmany++;
a3bc1f11 2527 spin_lock_irqsave(&tx_queue->txlock, flags);
f0ee7acf 2528 tx_queue->num_txbdfree += nr_txbds;
a3bc1f11 2529 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90 2530 }
1da177e4 2531
4669bc90 2532 /* If we freed a buffer, we can restart transmission, if necessary */
fba4ed03
SG		 2533 if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2534 netif_wake_subqueue(dev, tx_queue->qindex);
1da177e4 2535
4669bc90 2536 /* Update dirty indicators */
a12f801d
SG		 2537 tx_queue->skb_dirtytx = skb_dirtytx;
2538 tx_queue->dirty_tx = bdp;
1da177e4 2539
d080cd63
DH		 2540 return howmany;
2541}
2542
f4983704 2543static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
d080cd63 2544{
a6d0b91a
AV		 2545 unsigned long flags;
2546
fba4ed03
SG		 2547 spin_lock_irqsave(&gfargrp->grplock, flags);
2548 if (napi_schedule_prep(&gfargrp->napi)) {
f4983704 2549 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
fba4ed03 2550 __napi_schedule(&gfargrp->napi);
8707bdd4
JP		 2551 } else {
2552 /*
2553 * Clear IEVENT, so interrupts aren't called again
2554 * because of the packets that have already arrived.
2555 */
f4983704 2556 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2f448911 2557 }
fba4ed03 2558 spin_unlock_irqrestore(&gfargrp->grplock, flags);
a6d0b91a 2559
8c7396ae 2560}
1da177e4 2561
8c7396ae 2562/* Interrupt Handler for Transmit complete */
f4983704 2563static irqreturn_t gfar_transmit(int irq, void *grp_id)
8c7396ae 2564{
f4983704 2565 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2566 return IRQ_HANDLED;
2567}
2568
a12f801d 2569static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6
AF		 2570 struct sk_buff *skb)
2571{
a12f801d 2572 struct net_device *dev = rx_queue->dev;
815b97c6 2573 struct gfar_private *priv = netdev_priv(dev);
8a102fe0 2574 dma_addr_t buf;
815b97c6 2575
8a102fe0
AV		 2576 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2577 priv->rx_buffer_size, DMA_FROM_DEVICE);
a12f801d 2578 gfar_init_rxbdp(rx_queue, bdp, buf);
815b97c6
AF		 2579}
2580
acbc0f03 2581static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
1da177e4
LT		 2582{
2583 struct gfar_private *priv = netdev_priv(dev);
2584 struct sk_buff *skb = NULL;
1da177e4 2585
acbc0f03 2586 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
815b97c6 2587 if (!skb)
1da177e4
LT		 2588 return NULL;
2589
acbc0f03 2590 gfar_align_skb(skb);
7f7f5316 2591
acbc0f03
EL		 2592 return skb;
2593}
2594
2595struct sk_buff * gfar_new_skb(struct net_device *dev)
2596{
2597 struct gfar_private *priv = netdev_priv(dev);
2598 struct sk_buff *skb = NULL;
2599
cd0ea241 2600 skb = skb_dequeue(&priv->rx_recycle);
acbc0f03
EL		 2601 if (!skb)
2602 skb = gfar_alloc_skb(dev);
1da177e4 2603
1da177e4
LT		 2604 return skb;
2605}
2606
298e1a9e 2607static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2608{
298e1a9e 2609 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2610 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2611 struct gfar_extra_stats *estats = &priv->extra_stats;
2612
2613 /* If the packet was truncated, none of the other errors
2614 * matter */
2615 if (status & RXBD_TRUNCATED) {
2616 stats->rx_length_errors++;
2617
2618 estats->rx_trunc++;
2619
2620 return;
2621 }
2622 /* Count the errors, if there were any */
2623 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2624 stats->rx_length_errors++;
2625
2626 if (status & RXBD_LARGE)
2627 estats->rx_large++;
2628 else
2629 estats->rx_short++;
2630 }
2631 if (status & RXBD_NONOCTET) {
2632 stats->rx_frame_errors++;
2633 estats->rx_nonoctet++;
2634 }
2635 if (status & RXBD_CRCERR) {
2636 estats->rx_crcerr++;
2637 stats->rx_crc_errors++;
2638 }
2639 if (status & RXBD_OVERRUN) {
2640 estats->rx_overrun++;
2641 stats->rx_crc_errors++;
2642 }
2643}
2644
f4983704 2645irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2646{
f4983704 2647 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2648 return IRQ_HANDLED;
2649}
2650
0bbaf069
KG		 2651static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2652{
2653 /* If valid headers were found, and valid sums
2654 * were verified, then we tell the kernel that no
2655 * checksumming is necessary. Otherwise, it is */
7f7f5316 2656 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2657 skb->ip_summed = CHECKSUM_UNNECESSARY;
2658 else
bc8acf2c 2659 skb_checksum_none_assert(skb);
0bbaf069
KG		 2660}
2661
2662
1da177e4
LT		 2663/* gfar_process_frame() -- handle one incoming packet if skb
2664 * isn't NULL. */
2665static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2c2db48a 2666 int amount_pull)
1da177e4
LT		 2667{
2668 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2669 struct rxfcb *fcb = NULL;
1da177e4 2670
2c2db48a 2671 int ret;
1da177e4 2672
2c2db48a
DH		 2673 /* fcb is at the beginning if exists */
2674 fcb = (struct rxfcb *)skb->data;
0bbaf069 2675
2c2db48a
DH		 2676 /* Remove the FCB from the skb */
2677 /* Remove the padded bytes, if there are any */
f74dac08
SG		 2678 if (amount_pull) {
2679 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2680 skb_pull(skb, amount_pull);
f74dac08 2681 }
0bbaf069 2682
cc772ab7
MR		 2683 /* Get receive timestamp from the skb */
2684 if (priv->hwts_rx_en) {
2685 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2686 u64 *ns = (u64 *) skb->data;
2687 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2688 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2689 }
2690
2691 if (priv->padding)
2692 skb_pull(skb, priv->padding);
2693
8b3afe95 2694 if (dev->features & NETIF_F_RXCSUM)
2c2db48a 2695 gfar_rx_checksum(skb, fcb);
0bbaf069 2696
2c2db48a
DH		 2697 /* Tell the skb what kind of packet this is */
2698 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2699
2c2db48a
DH		 2700 /* Send the packet up the stack */
2701 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2702 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2703 else
2704 ret = netif_receive_skb(skb);
0bbaf069 2705
2c2db48a
DH		 2706 if (NET_RX_DROP == ret)
2707 priv->extra_stats.kernel_dropped++;
1da177e4
LT		 2708
2709 return 0;
2710}
2711
2712/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
0bbaf069 2713 * until the budget/quota has been reached. Returns the number
1da177e4
LT		 2714 * of frames handled
2715 */
a12f801d 2716int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2717{
a12f801d 2718 struct net_device *dev = rx_queue->dev;
31de198b 2719 struct rxbd8 *bdp, *base;
1da177e4 2720 struct sk_buff *skb;
2c2db48a
DH		 2721 int pkt_len;
2722 int amount_pull;
1da177e4
LT		 2723 int howmany = 0;
2724 struct gfar_private *priv = netdev_priv(dev);
2725
2726 /* Get the first full descriptor */
a12f801d
SG		 2727 bdp = rx_queue->cur_rx;
2728 base = rx_queue->rx_bd_base;
1da177e4 2729
cc772ab7 2730 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2c2db48a 2731
1da177e4 2732 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 2733 struct sk_buff *newskb;
3b6330ce 2734 rmb();
815b97c6
AF		 2735
2736 /* Add another skb for the future */
2737 newskb = gfar_new_skb(dev);
2738
a12f801d 2739 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2740
4826857f 2741 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
81183059
AF		 2742 priv->rx_buffer_size, DMA_FROM_DEVICE);
2743
63b88b90
AV		 2744 if (unlikely(!(bdp->status & RXBD_ERR) &&
2745 bdp->length > priv->rx_buffer_size))
2746 bdp->status = RXBD_LARGE;
2747
815b97c6
AF		 2748 /* We drop the frame if we failed to allocate a new buffer */
2749 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2750 bdp->status & RXBD_ERR)) {
2751 count_errors(bdp->status, dev);
2752
2753 if (unlikely(!newskb))
2754 newskb = skb;
acbc0f03 2755 else if (skb)
cd0ea241 2756 skb_queue_head(&priv->rx_recycle, skb);
815b97c6 2757 } else {
1da177e4 2758 /* Increment the number of packets */
a7f38041 2759 rx_queue->stats.rx_packets++;
1da177e4
LT		 2760 howmany++;
2761
2c2db48a
DH		 2762 if (likely(skb)) {
2763 pkt_len = bdp->length - ETH_FCS_LEN;
2764 /* Remove the FCS from the packet length */
2765 skb_put(skb, pkt_len);
a7f38041 2766 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2767 skb_record_rx_queue(skb, rx_queue->qindex);
2c2db48a
DH		 2768 gfar_process_frame(dev, skb, amount_pull);
2769
2770 } else {
59deab26 2771 netif_warn(priv, rx_err, dev, "Missing skb!\n");
a7f38041 2772 rx_queue->stats.rx_dropped++;
2c2db48a
DH		 2773 priv->extra_stats.rx_skbmissing++;
2774 }
1da177e4 2775
1da177e4
LT		 2776 }
2777
a12f801d 2778 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2779
815b97c6 2780 /* Setup the new bdp */
a12f801d 2781 gfar_new_rxbdp(rx_queue, bdp, newskb);
1da177e4
LT		 2782
2783 /* Update to the next pointer */
a12f801d 2784 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2785
2786 /* update to point at the next skb */
a12f801d
SG		 2787 rx_queue->skb_currx =
2788 (rx_queue->skb_currx + 1) &
2789 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2790 }
2791
2792 /* Update the current rxbd pointer to be the next one */
a12f801d 2793 rx_queue->cur_rx = bdp;
1da177e4 2794
1da177e4
LT		 2795 return howmany;
2796}
2797
bea3348e 2798static int gfar_poll(struct napi_struct *napi, int budget)
1da177e4 2799{
fba4ed03
SG		 2800 struct gfar_priv_grp *gfargrp = container_of(napi,
2801 struct gfar_priv_grp, napi);
2802 struct gfar_private *priv = gfargrp->priv;
46ceb60c 2803 struct gfar __iomem *regs = gfargrp->regs;
a12f801d 2804 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03
SG		 2805 struct gfar_priv_rx_q *rx_queue = NULL;
2806 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
18294ad1
AV		 2807 int tx_cleaned = 0, i, left_over_budget = budget;
2808 unsigned long serviced_queues = 0;
fba4ed03 2809 int num_queues = 0;
d080cd63 2810
fba4ed03
SG		 2811 num_queues = gfargrp->num_rx_queues;
2812 budget_per_queue = budget/num_queues;
2813
8c7396ae
DH		 2814 /* Clear IEVENT, so interrupts aren't called again
2815 * because of the packets that have already arrived */
f4983704 2816 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
8c7396ae 2817
fba4ed03 2818 while (num_queues && left_over_budget) {
1da177e4 2819
fba4ed03
SG		 2820 budget_per_queue = left_over_budget/num_queues;
2821 left_over_budget = 0;
2822
984b3f57 2823 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
fba4ed03
SG		 2824 if (test_bit(i, &serviced_queues))
2825 continue;
2826 rx_queue = priv->rx_queue[i];
2827 tx_queue = priv->tx_queue[rx_queue->qindex];
2828
a3bc1f11 2829 tx_cleaned += gfar_clean_tx_ring(tx_queue);
fba4ed03
SG		 2830 rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2831 budget_per_queue);
2832 rx_cleaned += rx_cleaned_per_queue;
2833 if(rx_cleaned_per_queue < budget_per_queue) {
2834 left_over_budget = left_over_budget +
2835 (budget_per_queue - rx_cleaned_per_queue);
2836 set_bit(i, &serviced_queues);
2837 num_queues--;
2838 }
2839 }
2840 }
1da177e4 2841
42199884
AF		 2842 if (tx_cleaned)
2843 return budget;
2844
2845 if (rx_cleaned < budget) {
288379f0 2846 napi_complete(napi);
1da177e4
LT		 2847
2848 /* Clear the halt bit in RSTAT */
fba4ed03 2849 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 2850
f4983704 2851 gfar_write(&regs->imask, IMASK_DEFAULT);
1da177e4
LT		 2852
2853 /* If we are coalescing interrupts, update the timer */
2854 /* Otherwise, clear it */
46ceb60c
SG		 2855 gfar_configure_coalescing(priv,
2856 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
1da177e4
LT		 2857 }
2858
42199884 2859 return rx_cleaned;
1da177e4 2860}
1da177e4 2861
f2d71c2d
VW		 2862#ifdef CONFIG_NET_POLL_CONTROLLER
2863/*
2864 * Polling 'interrupt' - used by things like netconsole to send skbs
2865 * without having to re-enable interrupts. It's not called while
2866 * the interrupt routine is executing.
2867 */
2868static void gfar_netpoll(struct net_device *dev)
2869{
2870 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2871 int i = 0;
f2d71c2d
VW		 2872
2873 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 2874 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 2875 for (i = 0; i < priv->num_grps; i++) {
2876 disable_irq(priv->gfargrp[i].interruptTransmit);
2877 disable_irq(priv->gfargrp[i].interruptReceive);
2878 disable_irq(priv->gfargrp[i].interruptError);
2879 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2880 &priv->gfargrp[i]);
2881 enable_irq(priv->gfargrp[i].interruptError);
2882 enable_irq(priv->gfargrp[i].interruptReceive);
2883 enable_irq(priv->gfargrp[i].interruptTransmit);
2884 }
f2d71c2d 2885 } else {
46ceb60c
SG		 2886 for (i = 0; i < priv->num_grps; i++) {
2887 disable_irq(priv->gfargrp[i].interruptTransmit);
2888 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2889 &priv->gfargrp[i]);
2890 enable_irq(priv->gfargrp[i].interruptTransmit);
43de004b 2891 }
f2d71c2d
VW		 2892 }
2893}
2894#endif
2895
1da177e4 2896/* The interrupt handler for devices with one interrupt */
f4983704 2897static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 2898{
f4983704 2899 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 2900
2901 /* Save ievent for future reference */
f4983704 2902 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 2903
1da177e4 2904 /* Check for reception */
538cc7ee 2905 if (events & IEVENT_RX_MASK)
f4983704 2906 gfar_receive(irq, grp_id);
1da177e4
LT		 2907
2908 /* Check for transmit completion */
538cc7ee 2909 if (events & IEVENT_TX_MASK)
f4983704 2910 gfar_transmit(irq, grp_id);
1da177e4 2911
538cc7ee
SS		 2912 /* Check for errors */
2913 if (events & IEVENT_ERR_MASK)
f4983704 2914 gfar_error(irq, grp_id);
1da177e4
LT		 2915
2916 return IRQ_HANDLED;
2917}
2918
1da177e4
LT		 2919/* Called every time the controller might need to be made
2920 * aware of new link state. The PHY code conveys this
bb40dcbb 2921 * information through variables in the phydev structure, and this
1da177e4
LT		 2922 * function converts those variables into the appropriate
2923 * register values, and can bring down the device if needed.
2924 */
2925static void adjust_link(struct net_device *dev)
2926{
2927 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2928 struct gfar __iomem *regs = priv->gfargrp[0].regs;
bb40dcbb
AF		 2929 unsigned long flags;
2930 struct phy_device *phydev = priv->phydev;
2931 int new_state = 0;
2932
fba4ed03
SG		 2933 local_irq_save(flags);
2934 lock_tx_qs(priv);
2935
bb40dcbb
AF		 2936 if (phydev->link) {
2937 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 2938 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 2939
1da177e4
LT		 2940 /* Now we make sure that we can be in full duplex mode.
2941 * If not, we operate in half-duplex mode. */
bb40dcbb
AF		 2942 if (phydev->duplex != priv->oldduplex) {
2943 new_state = 1;
2944 if (!(phydev->duplex))
1da177e4 2945 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 2946 else
1da177e4 2947 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 2948
bb40dcbb 2949 priv->oldduplex = phydev->duplex;
1da177e4
LT		 2950 }
2951
bb40dcbb
AF		 2952 if (phydev->speed != priv->oldspeed) {
2953 new_state = 1;
2954 switch (phydev->speed) {
1da177e4 2955 case 1000:
1da177e4
LT		 2956 tempval =
2957 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
f430e49e
LY		 2958
2959 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2960 break;
2961 case 100:
2962 case 10:
1da177e4
LT		 2963 tempval =
2964 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 2965
2966 /* Reduced mode distinguishes
2967 * between 10 and 100 */
2968 if (phydev->speed == SPEED_100)
2969 ecntrl |= ECNTRL_R100;
2970 else
2971 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2972 break;
2973 default:
59deab26
JP		 2974 netif_warn(priv, link, dev,
2975 "Ack! Speed (%d) is not 10/100/1000!\n",
2976 phydev->speed);
1da177e4
LT		 2977 break;
2978 }
2979
bb40dcbb 2980 priv->oldspeed = phydev->speed;
1da177e4
LT		 2981 }
2982
bb40dcbb 2983 gfar_write(&regs->maccfg2, tempval);
7f7f5316 2984 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 2985
1da177e4 2986 if (!priv->oldlink) {
bb40dcbb 2987 new_state = 1;
1da177e4 2988 priv->oldlink = 1;
1da177e4 2989 }
bb40dcbb
AF		 2990 } else if (priv->oldlink) {
2991 new_state = 1;
2992 priv->oldlink = 0;
2993 priv->oldspeed = 0;
2994 priv->oldduplex = -1;
1da177e4 2995 }
1da177e4 2996
bb40dcbb
AF		 2997 if (new_state && netif_msg_link(priv))
2998 phy_print_status(phydev);
fba4ed03
SG		 2999 unlock_tx_qs(priv);
3000 local_irq_restore(flags);
bb40dcbb 3001}
1da177e4
LT		 3002
3003/* Update the hash table based on the current list of multicast
3004 * addresses we subscribe to. Also, change the promiscuity of
3005 * the device based on the flags (this function is called
3006 * whenever dev->flags is changed */
3007static void gfar_set_multi(struct net_device *dev)
3008{
22bedad3 3009 struct netdev_hw_addr *ha;
1da177e4 3010 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3011 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 3012 u32 tempval;
3013
a12f801d 3014 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 3015 /* Set RCTRL to PROM */
3016 tempval = gfar_read(&regs->rctrl);
3017 tempval |= RCTRL_PROM;
3018 gfar_write(&regs->rctrl, tempval);
3019 } else {
3020 /* Set RCTRL to not PROM */
3021 tempval = gfar_read(&regs->rctrl);
3022 tempval &= ~(RCTRL_PROM);
3023 gfar_write(&regs->rctrl, tempval);
3024 }
6aa20a22 3025
a12f801d 3026 if (dev->flags & IFF_ALLMULTI) {
1da177e4 3027 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 3028 gfar_write(&regs->igaddr0, 0xffffffff);
3029 gfar_write(&regs->igaddr1, 0xffffffff);
3030 gfar_write(&regs->igaddr2, 0xffffffff);
3031 gfar_write(&regs->igaddr3, 0xffffffff);
3032 gfar_write(&regs->igaddr4, 0xffffffff);
3033 gfar_write(&regs->igaddr5, 0xffffffff);
3034 gfar_write(&regs->igaddr6, 0xffffffff);
3035 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 3036 gfar_write(&regs->gaddr0, 0xffffffff);
3037 gfar_write(&regs->gaddr1, 0xffffffff);
3038 gfar_write(&regs->gaddr2, 0xffffffff);
3039 gfar_write(&regs->gaddr3, 0xffffffff);
3040 gfar_write(&regs->gaddr4, 0xffffffff);
3041 gfar_write(&regs->gaddr5, 0xffffffff);
3042 gfar_write(&regs->gaddr6, 0xffffffff);
3043 gfar_write(&regs->gaddr7, 0xffffffff);
3044 } else {
7f7f5316
AF		 3045 int em_num;
3046 int idx;
3047
1da177e4 3048 /* zero out the hash */
0bbaf069
KG		 3049 gfar_write(&regs->igaddr0, 0x0);
3050 gfar_write(&regs->igaddr1, 0x0);
3051 gfar_write(&regs->igaddr2, 0x0);
3052 gfar_write(&regs->igaddr3, 0x0);
3053 gfar_write(&regs->igaddr4, 0x0);
3054 gfar_write(&regs->igaddr5, 0x0);
3055 gfar_write(&regs->igaddr6, 0x0);
3056 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 3057 gfar_write(&regs->gaddr0, 0x0);
3058 gfar_write(&regs->gaddr1, 0x0);
3059 gfar_write(&regs->gaddr2, 0x0);
3060 gfar_write(&regs->gaddr3, 0x0);
3061 gfar_write(&regs->gaddr4, 0x0);
3062 gfar_write(&regs->gaddr5, 0x0);
3063 gfar_write(&regs->gaddr6, 0x0);
3064 gfar_write(&regs->gaddr7, 0x0);
3065
7f7f5316
AF		 3066 /* If we have extended hash tables, we need to
3067 * clear the exact match registers to prepare for
3068 * setting them */
3069 if (priv->extended_hash) {
3070 em_num = GFAR_EM_NUM + 1;
3071 gfar_clear_exact_match(dev);
3072 idx = 1;
3073 } else {
3074 idx = 0;
3075 em_num = 0;
3076 }
3077
4cd24eaf 3078 if (netdev_mc_empty(dev))
1da177e4
LT		 3079 return;
3080
3081 /* Parse the list, and set the appropriate bits */
22bedad3 3082 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 3083 if (idx < em_num) {
22bedad3 3084 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 3085 idx++;
3086 } else
22bedad3 3087 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 3088 }
3089 }
1da177e4
LT		 3090}
3091
7f7f5316
AF		 3092
3093/* Clears each of the exact match registers to zero, so they
3094 * don't interfere with normal reception */
3095static void gfar_clear_exact_match(struct net_device *dev)
3096{
3097 int idx;
b6bc7650 3098 static const u8 zero_arr[MAC_ADDR_LEN] = {0, 0, 0, 0, 0, 0};
7f7f5316
AF		 3099
3100 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
b6bc7650 3101 gfar_set_mac_for_addr(dev, idx, zero_arr);
7f7f5316
AF		 3102}
3103
1da177e4
LT		 3104/* Set the appropriate hash bit for the given addr */
3105/* The algorithm works like so:
3106 * 1) Take the Destination Address (ie the multicast address), and
3107 * do a CRC on it (little endian), and reverse the bits of the
3108 * result.
3109 * 2) Use the 8 most significant bits as a hash into a 256-entry
3110 * table. The table is controlled through 8 32-bit registers:
3111 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3112 * gaddr7. This means that the 3 most significant bits in the
3113 * hash index which gaddr register to use, and the 5 other bits
3114 * indicate which bit (assuming an IBM numbering scheme, which
3115 * for PowerPC (tm) is usually the case) in the register holds
3116 * the entry. */
3117static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3118{
3119 u32 tempval;
3120 struct gfar_private *priv = netdev_priv(dev);
1da177e4 3121 u32 result = ether_crc(MAC_ADDR_LEN, addr);
0bbaf069
KG		 3122 int width = priv->hash_width;
3123 u8 whichbit = (result >> (32 - width)) & 0x1f;
3124 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3125 u32 value = (1 << (31-whichbit));
3126
0bbaf069 3127 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3128 tempval |= value;
0bbaf069 3129 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3130}
3131
7f7f5316
AF		 3132
3133/* There are multiple MAC Address register pairs on some controllers
3134 * This function sets the numth pair to a given address
3135 */
b6bc7650
JP		 3136static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3137 const u8 *addr)
7f7f5316
AF		 3138{
3139 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3140 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316
AF		 3141 int idx;
3142 char tmpbuf[MAC_ADDR_LEN];
3143 u32 tempval;
f4983704 3144 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3145
3146 macptr += num*2;
3147
3148 /* Now copy it into the mac registers backwards, cuz */
3149 /* little endian is silly */
3150 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3151 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3152
3153 gfar_write(macptr, *((u32 *) (tmpbuf)));
3154
3155 tempval = *((u32 *) (tmpbuf + 4));
3156
3157 gfar_write(macptr+1, tempval);
3158}
3159
1da177e4 3160/* GFAR error interrupt handler */
f4983704 3161static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3162{
f4983704
SG		 3163 struct gfar_priv_grp *gfargrp = grp_id;
3164 struct gfar __iomem *regs = gfargrp->regs;
3165 struct gfar_private *priv= gfargrp->priv;
3166 struct net_device *dev = priv->ndev;
1da177e4
LT		 3167
3168 /* Save ievent for future reference */
f4983704 3169 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3170
3171 /* Clear IEVENT */
f4983704 3172 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3173
3174 /* Magic Packet is not an error. */
b31a1d8b 3175 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3176 (events & IEVENT_MAG))
3177 events &= ~IEVENT_MAG;
1da177e4
LT		 3178
3179 /* Hmm... */
0bbaf069 3180 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
59deab26
JP		 3181 netdev_dbg(dev, "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3182 events, gfar_read(&regs->imask));
1da177e4
LT		 3183
3184 /* Update the error counters */
3185 if (events & IEVENT_TXE) {
09f75cd7 3186 dev->stats.tx_errors++;
1da177e4
LT		 3187
3188 if (events & IEVENT_LC)
09f75cd7 3189 dev->stats.tx_window_errors++;
1da177e4 3190 if (events & IEVENT_CRL)
09f75cd7 3191 dev->stats.tx_aborted_errors++;
1da177e4 3192 if (events & IEVENT_XFUN) {
836cf7fa
AV		 3193 unsigned long flags;
3194
59deab26
JP		 3195 netif_dbg(priv, tx_err, dev,
3196 "TX FIFO underrun, packet dropped\n");
09f75cd7 3197 dev->stats.tx_dropped++;
1da177e4
LT		 3198 priv->extra_stats.tx_underrun++;
3199
836cf7fa
AV		 3200 local_irq_save(flags);
3201 lock_tx_qs(priv);
3202
1da177e4 3203 /* Reactivate the Tx Queues */
fba4ed03 3204 gfar_write(&regs->tstat, gfargrp->tstat);
836cf7fa
AV		 3205
3206 unlock_tx_qs(priv);
3207 local_irq_restore(flags);
1da177e4 3208 }
59deab26 3209 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
1da177e4
LT		 3210 }
3211 if (events & IEVENT_BSY) {
09f75cd7 3212 dev->stats.rx_errors++;
1da177e4
LT		 3213 priv->extra_stats.rx_bsy++;
3214
f4983704 3215 gfar_receive(irq, grp_id);
1da177e4 3216
59deab26
JP		 3217 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3218 gfar_read(&regs->rstat));
1da177e4
LT		 3219 }
3220 if (events & IEVENT_BABR) {
09f75cd7 3221 dev->stats.rx_errors++;
1da177e4
LT		 3222 priv->extra_stats.rx_babr++;
3223
59deab26 3224 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
1da177e4
LT		 3225 }
3226 if (events & IEVENT_EBERR) {
3227 priv->extra_stats.eberr++;
59deab26 3228 netif_dbg(priv, rx_err, dev, "bus error\n");
1da177e4 3229 }
59deab26
JP		 3230 if (events & IEVENT_RXC)
3231 netif_dbg(priv, rx_status, dev, "control frame\n");
1da177e4
LT		 3232
3233 if (events & IEVENT_BABT) {
3234 priv->extra_stats.tx_babt++;
59deab26 3235 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
1da177e4
LT		 3236 }
3237 return IRQ_HANDLED;
3238}
3239
b31a1d8b
AF		 3240static struct of_device_id gfar_match[] =
3241{
3242 {
3243 .type = "network",
3244 .compatible = "gianfar",
3245 },
46ceb60c
SG		 3246 {
3247 .compatible = "fsl,etsec2",
3248 },
b31a1d8b
AF		 3249 {},
3250};
e72701ac 3251MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3252
1da177e4 3253/* Structure for a device driver */
74888760 3254static struct platform_driver gfar_driver = {
4018294b
GL		 3255 .driver = {
3256 .name = "fsl-gianfar",
3257 .owner = THIS_MODULE,
3258 .pm = GFAR_PM_OPS,
3259 .of_match_table = gfar_match,
3260 },
1da177e4
LT		 3261 .probe = gfar_probe,
3262 .remove = gfar_remove,
3263};
3264
3265static int __init gfar_init(void)
3266{
74888760 3267 return platform_driver_register(&gfar_driver);
1da177e4
LT		 3268}
3269
3270static void __exit gfar_exit(void)
3271{
74888760 3272 platform_driver_unregister(&gfar_driver);
1da177e4
LT		 3273}
3274
3275module_init(gfar_init);
3276module_exit(gfar_exit);
3277
Linux 6.x block layer and io_uring tree(s)