Commit | Line | Data |
---|---|---|
0bbaf069 | 1 | /* |
1da177e4 LT |
2 | * drivers/net/gianfar.c |
3 | * | |
4 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
5 | * This driver is designed for the non-CPM ethernet controllers |
6 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
7 | * Based on 8260_io/fcc_enet.c |
8 | * | |
9 | * Author: Andy Fleming | |
4c8d3d99 | 10 | * Maintainer: Kumar Gala |
a12f801d | 11 | * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> |
1da177e4 | 12 | * |
6c43e046 | 13 | * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc. |
a12f801d | 14 | * Copyright 2007 MontaVista Software, Inc. |
1da177e4 LT |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify it | |
17 | * under the terms of the GNU General Public License as published by the | |
18 | * Free Software Foundation; either version 2 of the License, or (at your | |
19 | * option) any later version. | |
20 | * | |
21 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
22 | * RA 11 31 24.2 | |
23 | * Dec +69 19 52 | |
24 | * V 3.84 | |
25 | * B-V +1.62 | |
26 | * | |
27 | * Theory of operation | |
0bbaf069 | 28 | * |
b31a1d8b AF |
29 | * The driver is initialized through of_device. Configuration information |
30 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
31 | * |
32 | * The Gianfar Ethernet Controller uses a ring of buffer | |
33 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
34 | * pointing to the physical address of the start of the ring. |
35 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
36 | * last descriptor of the ring. |
37 | * | |
38 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 39 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
40 | * corresponding bit in the IMASK register is also set (if |
41 | * interrupt coalescing is active, then the interrupt may not | |
42 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 43 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 44 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 45 | * exit. This method will start at the last known empty |
0bbaf069 | 46 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
47 | * are none left with data (NAPI will stop after a set number of |
48 | * packets to give time to other tasks, but will eventually | |
49 | * process all the packets). The data arrives inside a | |
50 | * pre-allocated skb, and so after the skb is passed up to the | |
51 | * stack, a new skb must be allocated, and the address field in | |
52 | * the buffer descriptor must be updated to indicate this new | |
53 | * skb. | |
54 | * | |
55 | * When the kernel requests that a packet be transmitted, the | |
56 | * driver starts where it left off last time, and points the | |
57 | * descriptor at the buffer which was passed in. The driver | |
58 | * then informs the DMA engine that there are packets ready to | |
59 | * be transmitted. Once the controller is finished transmitting | |
60 | * the packet, an interrupt may be triggered (under the same | |
61 | * conditions as for reception, but depending on the TXF bit). | |
62 | * The driver then cleans up the buffer. | |
63 | */ | |
64 | ||
1da177e4 | 65 | #include <linux/kernel.h> |
1da177e4 LT |
66 | #include <linux/string.h> |
67 | #include <linux/errno.h> | |
bb40dcbb | 68 | #include <linux/unistd.h> |
1da177e4 LT |
69 | #include <linux/slab.h> |
70 | #include <linux/interrupt.h> | |
71 | #include <linux/init.h> | |
72 | #include <linux/delay.h> | |
73 | #include <linux/netdevice.h> | |
74 | #include <linux/etherdevice.h> | |
75 | #include <linux/skbuff.h> | |
0bbaf069 | 76 | #include <linux/if_vlan.h> |
1da177e4 LT |
77 | #include <linux/spinlock.h> |
78 | #include <linux/mm.h> | |
fe192a49 | 79 | #include <linux/of_mdio.h> |
b31a1d8b | 80 | #include <linux/of_platform.h> |
0bbaf069 KG |
81 | #include <linux/ip.h> |
82 | #include <linux/tcp.h> | |
83 | #include <linux/udp.h> | |
9c07b884 | 84 | #include <linux/in.h> |
cc772ab7 | 85 | #include <linux/net_tstamp.h> |
1da177e4 LT |
86 | |
87 | #include <asm/io.h> | |
7d350977 | 88 | #include <asm/reg.h> |
1da177e4 LT |
89 | #include <asm/irq.h> |
90 | #include <asm/uaccess.h> | |
91 | #include <linux/module.h> | |
1da177e4 LT |
92 | #include <linux/dma-mapping.h> |
93 | #include <linux/crc32.h> | |
bb40dcbb AF |
94 | #include <linux/mii.h> |
95 | #include <linux/phy.h> | |
b31a1d8b AF |
96 | #include <linux/phy_fixed.h> |
97 | #include <linux/of.h> | |
4b6ba8aa | 98 | #include <linux/of_net.h> |
1da177e4 LT |
99 | |
100 | #include "gianfar.h" | |
1577ecef | 101 | #include "fsl_pq_mdio.h" |
1da177e4 LT |
102 | |
103 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 LT |
104 | #undef BRIEF_GFAR_ERRORS |
105 | #undef VERBOSE_GFAR_ERRORS | |
106 | ||
1da177e4 | 107 | const char gfar_driver_name[] = "Gianfar Ethernet"; |
7f7f5316 | 108 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 109 | |
1da177e4 LT |
110 | static int gfar_enet_open(struct net_device *dev); |
111 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 112 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
113 | static void gfar_timeout(struct net_device *dev); |
114 | static int gfar_close(struct net_device *dev); | |
815b97c6 | 115 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
a12f801d | 116 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
815b97c6 | 117 | struct sk_buff *skb); |
1da177e4 LT |
118 | static int gfar_set_mac_address(struct net_device *dev); |
119 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
120 | static irqreturn_t gfar_error(int irq, void *dev_id); |
121 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
122 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
123 | static void adjust_link(struct net_device *dev); |
124 | static void init_registers(struct net_device *dev); | |
125 | static int init_phy(struct net_device *dev); | |
74888760 | 126 | static int gfar_probe(struct platform_device *ofdev); |
2dc11581 | 127 | static int gfar_remove(struct platform_device *ofdev); |
bb40dcbb | 128 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
129 | static void gfar_set_multi(struct net_device *dev); |
130 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 131 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 132 | static int gfar_poll(struct napi_struct *napi, int budget); |
f2d71c2d VW |
133 | #ifdef CONFIG_NET_POLL_CONTROLLER |
134 | static void gfar_netpoll(struct net_device *dev); | |
135 | #endif | |
a12f801d SG |
136 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); |
137 | static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); | |
2c2db48a DH |
138 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
139 | int amount_pull); | |
0bbaf069 KG |
140 | static void gfar_vlan_rx_register(struct net_device *netdev, |
141 | struct vlan_group *grp); | |
7f7f5316 | 142 | void gfar_halt(struct net_device *dev); |
d87eb127 | 143 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
144 | void gfar_start(struct net_device *dev); |
145 | static void gfar_clear_exact_match(struct net_device *dev); | |
b6bc7650 JP |
146 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
147 | const u8 *addr); | |
26ccfc37 | 148 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 149 | |
1da177e4 LT |
150 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
151 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
152 | MODULE_LICENSE("GPL"); | |
153 | ||
a12f801d | 154 | static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
8a102fe0 AV |
155 | dma_addr_t buf) |
156 | { | |
8a102fe0 AV |
157 | u32 lstatus; |
158 | ||
159 | bdp->bufPtr = buf; | |
160 | ||
161 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); | |
a12f801d | 162 | if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) |
8a102fe0 AV |
163 | lstatus |= BD_LFLAG(RXBD_WRAP); |
164 | ||
165 | eieio(); | |
166 | ||
167 | bdp->lstatus = lstatus; | |
168 | } | |
169 | ||
8728327e | 170 | static int gfar_init_bds(struct net_device *ndev) |
826aa4a0 | 171 | { |
8728327e | 172 | struct gfar_private *priv = netdev_priv(ndev); |
a12f801d SG |
173 | struct gfar_priv_tx_q *tx_queue = NULL; |
174 | struct gfar_priv_rx_q *rx_queue = NULL; | |
826aa4a0 AV |
175 | struct txbd8 *txbdp; |
176 | struct rxbd8 *rxbdp; | |
fba4ed03 | 177 | int i, j; |
a12f801d | 178 | |
fba4ed03 SG |
179 | for (i = 0; i < priv->num_tx_queues; i++) { |
180 | tx_queue = priv->tx_queue[i]; | |
181 | /* Initialize some variables in our dev structure */ | |
182 | tx_queue->num_txbdfree = tx_queue->tx_ring_size; | |
183 | tx_queue->dirty_tx = tx_queue->tx_bd_base; | |
184 | tx_queue->cur_tx = tx_queue->tx_bd_base; | |
185 | tx_queue->skb_curtx = 0; | |
186 | tx_queue->skb_dirtytx = 0; | |
187 | ||
188 | /* Initialize Transmit Descriptor Ring */ | |
189 | txbdp = tx_queue->tx_bd_base; | |
190 | for (j = 0; j < tx_queue->tx_ring_size; j++) { | |
191 | txbdp->lstatus = 0; | |
192 | txbdp->bufPtr = 0; | |
193 | txbdp++; | |
194 | } | |
8728327e | 195 | |
fba4ed03 SG |
196 | /* Set the last descriptor in the ring to indicate wrap */ |
197 | txbdp--; | |
198 | txbdp->status |= TXBD_WRAP; | |
8728327e AV |
199 | } |
200 | ||
fba4ed03 SG |
201 | for (i = 0; i < priv->num_rx_queues; i++) { |
202 | rx_queue = priv->rx_queue[i]; | |
203 | rx_queue->cur_rx = rx_queue->rx_bd_base; | |
204 | rx_queue->skb_currx = 0; | |
205 | rxbdp = rx_queue->rx_bd_base; | |
8728327e | 206 | |
fba4ed03 SG |
207 | for (j = 0; j < rx_queue->rx_ring_size; j++) { |
208 | struct sk_buff *skb = rx_queue->rx_skbuff[j]; | |
8728327e | 209 | |
fba4ed03 SG |
210 | if (skb) { |
211 | gfar_init_rxbdp(rx_queue, rxbdp, | |
212 | rxbdp->bufPtr); | |
213 | } else { | |
214 | skb = gfar_new_skb(ndev); | |
215 | if (!skb) { | |
216 | pr_err("%s: Can't allocate RX buffers\n", | |
217 | ndev->name); | |
218 | goto err_rxalloc_fail; | |
219 | } | |
220 | rx_queue->rx_skbuff[j] = skb; | |
221 | ||
222 | gfar_new_rxbdp(rx_queue, rxbdp, skb); | |
8728327e | 223 | } |
8728327e | 224 | |
fba4ed03 | 225 | rxbdp++; |
8728327e AV |
226 | } |
227 | ||
8728327e AV |
228 | } |
229 | ||
230 | return 0; | |
fba4ed03 SG |
231 | |
232 | err_rxalloc_fail: | |
233 | free_skb_resources(priv); | |
234 | return -ENOMEM; | |
8728327e AV |
235 | } |
236 | ||
237 | static int gfar_alloc_skb_resources(struct net_device *ndev) | |
238 | { | |
826aa4a0 | 239 | void *vaddr; |
fba4ed03 SG |
240 | dma_addr_t addr; |
241 | int i, j, k; | |
826aa4a0 AV |
242 | struct gfar_private *priv = netdev_priv(ndev); |
243 | struct device *dev = &priv->ofdev->dev; | |
a12f801d SG |
244 | struct gfar_priv_tx_q *tx_queue = NULL; |
245 | struct gfar_priv_rx_q *rx_queue = NULL; | |
246 | ||
fba4ed03 SG |
247 | priv->total_tx_ring_size = 0; |
248 | for (i = 0; i < priv->num_tx_queues; i++) | |
249 | priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; | |
250 | ||
251 | priv->total_rx_ring_size = 0; | |
252 | for (i = 0; i < priv->num_rx_queues; i++) | |
253 | priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; | |
826aa4a0 AV |
254 | |
255 | /* Allocate memory for the buffer descriptors */ | |
8728327e | 256 | vaddr = dma_alloc_coherent(dev, |
fba4ed03 SG |
257 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
258 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
259 | &addr, GFP_KERNEL); | |
826aa4a0 AV |
260 | if (!vaddr) { |
261 | if (netif_msg_ifup(priv)) | |
262 | pr_err("%s: Could not allocate buffer descriptors!\n", | |
263 | ndev->name); | |
264 | return -ENOMEM; | |
265 | } | |
266 | ||
fba4ed03 SG |
267 | for (i = 0; i < priv->num_tx_queues; i++) { |
268 | tx_queue = priv->tx_queue[i]; | |
269 | tx_queue->tx_bd_base = (struct txbd8 *) vaddr; | |
270 | tx_queue->tx_bd_dma_base = addr; | |
271 | tx_queue->dev = ndev; | |
272 | /* enet DMA only understands physical addresses */ | |
273 | addr += sizeof(struct txbd8) *tx_queue->tx_ring_size; | |
274 | vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size; | |
275 | } | |
826aa4a0 | 276 | |
826aa4a0 | 277 | /* Start the rx descriptor ring where the tx ring leaves off */ |
fba4ed03 SG |
278 | for (i = 0; i < priv->num_rx_queues; i++) { |
279 | rx_queue = priv->rx_queue[i]; | |
280 | rx_queue->rx_bd_base = (struct rxbd8 *) vaddr; | |
281 | rx_queue->rx_bd_dma_base = addr; | |
282 | rx_queue->dev = ndev; | |
283 | addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size; | |
284 | vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size; | |
285 | } | |
826aa4a0 AV |
286 | |
287 | /* Setup the skbuff rings */ | |
fba4ed03 SG |
288 | for (i = 0; i < priv->num_tx_queues; i++) { |
289 | tx_queue = priv->tx_queue[i]; | |
290 | tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) * | |
a12f801d | 291 | tx_queue->tx_ring_size, GFP_KERNEL); |
fba4ed03 SG |
292 | if (!tx_queue->tx_skbuff) { |
293 | if (netif_msg_ifup(priv)) | |
294 | pr_err("%s: Could not allocate tx_skbuff\n", | |
295 | ndev->name); | |
296 | goto cleanup; | |
297 | } | |
826aa4a0 | 298 | |
fba4ed03 SG |
299 | for (k = 0; k < tx_queue->tx_ring_size; k++) |
300 | tx_queue->tx_skbuff[k] = NULL; | |
301 | } | |
826aa4a0 | 302 | |
fba4ed03 SG |
303 | for (i = 0; i < priv->num_rx_queues; i++) { |
304 | rx_queue = priv->rx_queue[i]; | |
305 | rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) * | |
a12f801d | 306 | rx_queue->rx_ring_size, GFP_KERNEL); |
826aa4a0 | 307 | |
fba4ed03 SG |
308 | if (!rx_queue->rx_skbuff) { |
309 | if (netif_msg_ifup(priv)) | |
310 | pr_err("%s: Could not allocate rx_skbuff\n", | |
311 | ndev->name); | |
312 | goto cleanup; | |
313 | } | |
314 | ||
315 | for (j = 0; j < rx_queue->rx_ring_size; j++) | |
316 | rx_queue->rx_skbuff[j] = NULL; | |
317 | } | |
826aa4a0 | 318 | |
8728327e AV |
319 | if (gfar_init_bds(ndev)) |
320 | goto cleanup; | |
826aa4a0 AV |
321 | |
322 | return 0; | |
323 | ||
324 | cleanup: | |
325 | free_skb_resources(priv); | |
326 | return -ENOMEM; | |
327 | } | |
328 | ||
fba4ed03 SG |
329 | static void gfar_init_tx_rx_base(struct gfar_private *priv) |
330 | { | |
46ceb60c | 331 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 332 | u32 __iomem *baddr; |
fba4ed03 SG |
333 | int i; |
334 | ||
335 | baddr = ®s->tbase0; | |
336 | for(i = 0; i < priv->num_tx_queues; i++) { | |
337 | gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); | |
338 | baddr += 2; | |
339 | } | |
340 | ||
341 | baddr = ®s->rbase0; | |
342 | for(i = 0; i < priv->num_rx_queues; i++) { | |
343 | gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); | |
344 | baddr += 2; | |
345 | } | |
346 | } | |
347 | ||
826aa4a0 AV |
348 | static void gfar_init_mac(struct net_device *ndev) |
349 | { | |
350 | struct gfar_private *priv = netdev_priv(ndev); | |
46ceb60c | 351 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
826aa4a0 AV |
352 | u32 rctrl = 0; |
353 | u32 tctrl = 0; | |
354 | u32 attrs = 0; | |
355 | ||
fba4ed03 SG |
356 | /* write the tx/rx base registers */ |
357 | gfar_init_tx_rx_base(priv); | |
32c513bc | 358 | |
826aa4a0 | 359 | /* Configure the coalescing support */ |
46ceb60c | 360 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
fba4ed03 | 361 | |
1ccb8389 | 362 | if (priv->rx_filer_enable) { |
fba4ed03 | 363 | rctrl |= RCTRL_FILREN; |
1ccb8389 SG |
364 | /* Program the RIR0 reg with the required distribution */ |
365 | gfar_write(®s->rir0, DEFAULT_RIR0); | |
366 | } | |
826aa4a0 | 367 | |
8b3afe95 | 368 | if (ndev->features & NETIF_F_RXCSUM) |
826aa4a0 AV |
369 | rctrl |= RCTRL_CHECKSUMMING; |
370 | ||
371 | if (priv->extended_hash) { | |
372 | rctrl |= RCTRL_EXTHASH; | |
373 | ||
374 | gfar_clear_exact_match(ndev); | |
375 | rctrl |= RCTRL_EMEN; | |
376 | } | |
377 | ||
378 | if (priv->padding) { | |
379 | rctrl &= ~RCTRL_PAL_MASK; | |
380 | rctrl |= RCTRL_PADDING(priv->padding); | |
381 | } | |
382 | ||
cc772ab7 MR |
383 | /* Insert receive time stamps into padding alignment bytes */ |
384 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) { | |
385 | rctrl &= ~RCTRL_PAL_MASK; | |
97553f7f | 386 | rctrl |= RCTRL_PADDING(8); |
cc772ab7 MR |
387 | priv->padding = 8; |
388 | } | |
389 | ||
97553f7f MR |
390 | /* Enable HW time stamping if requested from user space */ |
391 | if (priv->hwts_rx_en) | |
392 | rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; | |
393 | ||
826aa4a0 AV |
394 | /* keep vlan related bits if it's enabled */ |
395 | if (priv->vlgrp) { | |
396 | rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; | |
397 | tctrl |= TCTRL_VLINS; | |
398 | } | |
399 | ||
400 | /* Init rctrl based on our settings */ | |
401 | gfar_write(®s->rctrl, rctrl); | |
402 | ||
403 | if (ndev->features & NETIF_F_IP_CSUM) | |
404 | tctrl |= TCTRL_INIT_CSUM; | |
405 | ||
fba4ed03 SG |
406 | tctrl |= TCTRL_TXSCHED_PRIO; |
407 | ||
826aa4a0 AV |
408 | gfar_write(®s->tctrl, tctrl); |
409 | ||
410 | /* Set the extraction length and index */ | |
411 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
412 | ATTRELI_EI(priv->rx_stash_index); | |
413 | ||
414 | gfar_write(®s->attreli, attrs); | |
415 | ||
416 | /* Start with defaults, and add stashing or locking | |
417 | * depending on the approprate variables */ | |
418 | attrs = ATTR_INIT_SETTINGS; | |
419 | ||
420 | if (priv->bd_stash_en) | |
421 | attrs |= ATTR_BDSTASH; | |
422 | ||
423 | if (priv->rx_stash_size != 0) | |
424 | attrs |= ATTR_BUFSTASH; | |
425 | ||
426 | gfar_write(®s->attr, attrs); | |
427 | ||
428 | gfar_write(®s->fifo_tx_thr, priv->fifo_threshold); | |
429 | gfar_write(®s->fifo_tx_starve, priv->fifo_starve); | |
430 | gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
431 | } | |
432 | ||
a7f38041 SG |
433 | static struct net_device_stats *gfar_get_stats(struct net_device *dev) |
434 | { | |
435 | struct gfar_private *priv = netdev_priv(dev); | |
a7f38041 SG |
436 | unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; |
437 | unsigned long tx_packets = 0, tx_bytes = 0; | |
438 | int i = 0; | |
439 | ||
440 | for (i = 0; i < priv->num_rx_queues; i++) { | |
441 | rx_packets += priv->rx_queue[i]->stats.rx_packets; | |
442 | rx_bytes += priv->rx_queue[i]->stats.rx_bytes; | |
443 | rx_dropped += priv->rx_queue[i]->stats.rx_dropped; | |
444 | } | |
445 | ||
446 | dev->stats.rx_packets = rx_packets; | |
447 | dev->stats.rx_bytes = rx_bytes; | |
448 | dev->stats.rx_dropped = rx_dropped; | |
449 | ||
450 | for (i = 0; i < priv->num_tx_queues; i++) { | |
1ac9ad13 ED |
451 | tx_bytes += priv->tx_queue[i]->stats.tx_bytes; |
452 | tx_packets += priv->tx_queue[i]->stats.tx_packets; | |
a7f38041 SG |
453 | } |
454 | ||
455 | dev->stats.tx_bytes = tx_bytes; | |
456 | dev->stats.tx_packets = tx_packets; | |
457 | ||
458 | return &dev->stats; | |
459 | } | |
460 | ||
26ccfc37 AF |
461 | static const struct net_device_ops gfar_netdev_ops = { |
462 | .ndo_open = gfar_enet_open, | |
463 | .ndo_start_xmit = gfar_start_xmit, | |
464 | .ndo_stop = gfar_close, | |
465 | .ndo_change_mtu = gfar_change_mtu, | |
8b3afe95 | 466 | .ndo_set_features = gfar_set_features, |
26ccfc37 AF |
467 | .ndo_set_multicast_list = gfar_set_multi, |
468 | .ndo_tx_timeout = gfar_timeout, | |
469 | .ndo_do_ioctl = gfar_ioctl, | |
a7f38041 | 470 | .ndo_get_stats = gfar_get_stats, |
26ccfc37 | 471 | .ndo_vlan_rx_register = gfar_vlan_rx_register, |
240c102d BH |
472 | .ndo_set_mac_address = eth_mac_addr, |
473 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
474 | #ifdef CONFIG_NET_POLL_CONTROLLER |
475 | .ndo_poll_controller = gfar_netpoll, | |
476 | #endif | |
477 | }; | |
478 | ||
fba4ed03 SG |
479 | void lock_rx_qs(struct gfar_private *priv) |
480 | { | |
481 | int i = 0x0; | |
482 | ||
483 | for (i = 0; i < priv->num_rx_queues; i++) | |
484 | spin_lock(&priv->rx_queue[i]->rxlock); | |
485 | } | |
486 | ||
487 | void lock_tx_qs(struct gfar_private *priv) | |
488 | { | |
489 | int i = 0x0; | |
490 | ||
491 | for (i = 0; i < priv->num_tx_queues; i++) | |
492 | spin_lock(&priv->tx_queue[i]->txlock); | |
493 | } | |
494 | ||
495 | void unlock_rx_qs(struct gfar_private *priv) | |
496 | { | |
497 | int i = 0x0; | |
498 | ||
499 | for (i = 0; i < priv->num_rx_queues; i++) | |
500 | spin_unlock(&priv->rx_queue[i]->rxlock); | |
501 | } | |
502 | ||
503 | void unlock_tx_qs(struct gfar_private *priv) | |
504 | { | |
505 | int i = 0x0; | |
506 | ||
507 | for (i = 0; i < priv->num_tx_queues; i++) | |
508 | spin_unlock(&priv->tx_queue[i]->txlock); | |
509 | } | |
510 | ||
7f7f5316 AF |
511 | /* Returns 1 if incoming frames use an FCB */ |
512 | static inline int gfar_uses_fcb(struct gfar_private *priv) | |
0bbaf069 | 513 | { |
8b3afe95 | 514 | return priv->vlgrp || (priv->ndev->features & NETIF_F_RXCSUM) || |
cc772ab7 | 515 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER); |
0bbaf069 | 516 | } |
bb40dcbb | 517 | |
fba4ed03 SG |
518 | static void free_tx_pointers(struct gfar_private *priv) |
519 | { | |
520 | int i = 0; | |
521 | ||
522 | for (i = 0; i < priv->num_tx_queues; i++) | |
523 | kfree(priv->tx_queue[i]); | |
524 | } | |
525 | ||
526 | static void free_rx_pointers(struct gfar_private *priv) | |
527 | { | |
528 | int i = 0; | |
529 | ||
530 | for (i = 0; i < priv->num_rx_queues; i++) | |
531 | kfree(priv->rx_queue[i]); | |
532 | } | |
533 | ||
46ceb60c SG |
534 | static void unmap_group_regs(struct gfar_private *priv) |
535 | { | |
536 | int i = 0; | |
537 | ||
538 | for (i = 0; i < MAXGROUPS; i++) | |
539 | if (priv->gfargrp[i].regs) | |
540 | iounmap(priv->gfargrp[i].regs); | |
541 | } | |
542 | ||
543 | static void disable_napi(struct gfar_private *priv) | |
544 | { | |
545 | int i = 0; | |
546 | ||
547 | for (i = 0; i < priv->num_grps; i++) | |
548 | napi_disable(&priv->gfargrp[i].napi); | |
549 | } | |
550 | ||
551 | static void enable_napi(struct gfar_private *priv) | |
552 | { | |
553 | int i = 0; | |
554 | ||
555 | for (i = 0; i < priv->num_grps; i++) | |
556 | napi_enable(&priv->gfargrp[i].napi); | |
557 | } | |
558 | ||
559 | static int gfar_parse_group(struct device_node *np, | |
560 | struct gfar_private *priv, const char *model) | |
561 | { | |
562 | u32 *queue_mask; | |
46ceb60c | 563 | |
7ce97d4f | 564 | priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0); |
46ceb60c SG |
565 | if (!priv->gfargrp[priv->num_grps].regs) |
566 | return -ENOMEM; | |
567 | ||
568 | priv->gfargrp[priv->num_grps].interruptTransmit = | |
569 | irq_of_parse_and_map(np, 0); | |
570 | ||
571 | /* If we aren't the FEC we have multiple interrupts */ | |
572 | if (model && strcasecmp(model, "FEC")) { | |
573 | priv->gfargrp[priv->num_grps].interruptReceive = | |
574 | irq_of_parse_and_map(np, 1); | |
575 | priv->gfargrp[priv->num_grps].interruptError = | |
576 | irq_of_parse_and_map(np,2); | |
28cb6ccd NK |
577 | if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ || |
578 | priv->gfargrp[priv->num_grps].interruptReceive == NO_IRQ || | |
579 | priv->gfargrp[priv->num_grps].interruptError == NO_IRQ) | |
46ceb60c | 580 | return -EINVAL; |
46ceb60c SG |
581 | } |
582 | ||
583 | priv->gfargrp[priv->num_grps].grp_id = priv->num_grps; | |
584 | priv->gfargrp[priv->num_grps].priv = priv; | |
585 | spin_lock_init(&priv->gfargrp[priv->num_grps].grplock); | |
586 | if(priv->mode == MQ_MG_MODE) { | |
587 | queue_mask = (u32 *)of_get_property(np, | |
588 | "fsl,rx-bit-map", NULL); | |
589 | priv->gfargrp[priv->num_grps].rx_bit_map = | |
590 | queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps); | |
591 | queue_mask = (u32 *)of_get_property(np, | |
592 | "fsl,tx-bit-map", NULL); | |
593 | priv->gfargrp[priv->num_grps].tx_bit_map = | |
594 | queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); | |
595 | } else { | |
596 | priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF; | |
597 | priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF; | |
598 | } | |
599 | priv->num_grps++; | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
2dc11581 | 604 | static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) |
b31a1d8b | 605 | { |
b31a1d8b AF |
606 | const char *model; |
607 | const char *ctype; | |
608 | const void *mac_addr; | |
fba4ed03 SG |
609 | int err = 0, i; |
610 | struct net_device *dev = NULL; | |
611 | struct gfar_private *priv = NULL; | |
61c7a080 | 612 | struct device_node *np = ofdev->dev.of_node; |
46ceb60c | 613 | struct device_node *child = NULL; |
4d7902f2 AF |
614 | const u32 *stash; |
615 | const u32 *stash_len; | |
616 | const u32 *stash_idx; | |
fba4ed03 SG |
617 | unsigned int num_tx_qs, num_rx_qs; |
618 | u32 *tx_queues, *rx_queues; | |
b31a1d8b AF |
619 | |
620 | if (!np || !of_device_is_available(np)) | |
621 | return -ENODEV; | |
622 | ||
fba4ed03 SG |
623 | /* parse the num of tx and rx queues */ |
624 | tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); | |
625 | num_tx_qs = tx_queues ? *tx_queues : 1; | |
626 | ||
627 | if (num_tx_qs > MAX_TX_QS) { | |
628 | printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", | |
629 | num_tx_qs, MAX_TX_QS); | |
630 | printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n"); | |
631 | return -EINVAL; | |
632 | } | |
633 | ||
634 | rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); | |
635 | num_rx_qs = rx_queues ? *rx_queues : 1; | |
636 | ||
637 | if (num_rx_qs > MAX_RX_QS) { | |
638 | printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", | |
639 | num_tx_qs, MAX_TX_QS); | |
640 | printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n"); | |
641 | return -EINVAL; | |
642 | } | |
643 | ||
644 | *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); | |
645 | dev = *pdev; | |
646 | if (NULL == dev) | |
647 | return -ENOMEM; | |
648 | ||
649 | priv = netdev_priv(dev); | |
61c7a080 | 650 | priv->node = ofdev->dev.of_node; |
fba4ed03 SG |
651 | priv->ndev = dev; |
652 | ||
fba4ed03 | 653 | priv->num_tx_queues = num_tx_qs; |
fe069123 | 654 | netif_set_real_num_rx_queues(dev, num_rx_qs); |
fba4ed03 | 655 | priv->num_rx_queues = num_rx_qs; |
46ceb60c | 656 | priv->num_grps = 0x0; |
b31a1d8b AF |
657 | |
658 | model = of_get_property(np, "model", NULL); | |
659 | ||
46ceb60c SG |
660 | for (i = 0; i < MAXGROUPS; i++) |
661 | priv->gfargrp[i].regs = NULL; | |
b31a1d8b | 662 | |
46ceb60c SG |
663 | /* Parse and initialize group specific information */ |
664 | if (of_device_is_compatible(np, "fsl,etsec2")) { | |
665 | priv->mode = MQ_MG_MODE; | |
666 | for_each_child_of_node(np, child) { | |
667 | err = gfar_parse_group(child, priv, model); | |
668 | if (err) | |
669 | goto err_grp_init; | |
b31a1d8b | 670 | } |
46ceb60c SG |
671 | } else { |
672 | priv->mode = SQ_SG_MODE; | |
673 | err = gfar_parse_group(np, priv, model); | |
674 | if(err) | |
675 | goto err_grp_init; | |
b31a1d8b AF |
676 | } |
677 | ||
fba4ed03 SG |
678 | for (i = 0; i < priv->num_tx_queues; i++) |
679 | priv->tx_queue[i] = NULL; | |
680 | for (i = 0; i < priv->num_rx_queues; i++) | |
681 | priv->rx_queue[i] = NULL; | |
682 | ||
683 | for (i = 0; i < priv->num_tx_queues; i++) { | |
de47f072 JP |
684 | priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), |
685 | GFP_KERNEL); | |
fba4ed03 SG |
686 | if (!priv->tx_queue[i]) { |
687 | err = -ENOMEM; | |
688 | goto tx_alloc_failed; | |
689 | } | |
690 | priv->tx_queue[i]->tx_skbuff = NULL; | |
691 | priv->tx_queue[i]->qindex = i; | |
692 | priv->tx_queue[i]->dev = dev; | |
693 | spin_lock_init(&(priv->tx_queue[i]->txlock)); | |
694 | } | |
695 | ||
696 | for (i = 0; i < priv->num_rx_queues; i++) { | |
de47f072 JP |
697 | priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), |
698 | GFP_KERNEL); | |
fba4ed03 SG |
699 | if (!priv->rx_queue[i]) { |
700 | err = -ENOMEM; | |
701 | goto rx_alloc_failed; | |
702 | } | |
703 | priv->rx_queue[i]->rx_skbuff = NULL; | |
704 | priv->rx_queue[i]->qindex = i; | |
705 | priv->rx_queue[i]->dev = dev; | |
706 | spin_lock_init(&(priv->rx_queue[i]->rxlock)); | |
707 | } | |
708 | ||
709 | ||
4d7902f2 AF |
710 | stash = of_get_property(np, "bd-stash", NULL); |
711 | ||
a12f801d | 712 | if (stash) { |
4d7902f2 AF |
713 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; |
714 | priv->bd_stash_en = 1; | |
715 | } | |
716 | ||
717 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
718 | ||
719 | if (stash_len) | |
720 | priv->rx_stash_size = *stash_len; | |
721 | ||
722 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
723 | ||
724 | if (stash_idx) | |
725 | priv->rx_stash_index = *stash_idx; | |
726 | ||
727 | if (stash_len || stash_idx) | |
728 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
729 | ||
b31a1d8b AF |
730 | mac_addr = of_get_mac_address(np); |
731 | if (mac_addr) | |
732 | memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN); | |
733 | ||
734 | if (model && !strcasecmp(model, "TSEC")) | |
735 | priv->device_flags = | |
736 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
737 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
738 | FSL_GIANFAR_DEV_HAS_RMON | | |
739 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
740 | if (model && !strcasecmp(model, "eTSEC")) | |
741 | priv->device_flags = | |
742 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
743 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
744 | FSL_GIANFAR_DEV_HAS_RMON | | |
745 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
2c2db48a | 746 | FSL_GIANFAR_DEV_HAS_PADDING | |
b31a1d8b AF |
747 | FSL_GIANFAR_DEV_HAS_CSUM | |
748 | FSL_GIANFAR_DEV_HAS_VLAN | | |
749 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
97553f7f MR |
750 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | |
751 | FSL_GIANFAR_DEV_HAS_TIMER; | |
b31a1d8b AF |
752 | |
753 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
754 | ||
755 | /* We only care about rgmii-id. The rest are autodetected */ | |
756 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
757 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
758 | else | |
759 | priv->interface = PHY_INTERFACE_MODE_MII; | |
760 | ||
761 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
762 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
763 | ||
fe192a49 | 764 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
b31a1d8b AF |
765 | |
766 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 767 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
768 | |
769 | return 0; | |
770 | ||
fba4ed03 SG |
771 | rx_alloc_failed: |
772 | free_rx_pointers(priv); | |
773 | tx_alloc_failed: | |
774 | free_tx_pointers(priv); | |
46ceb60c SG |
775 | err_grp_init: |
776 | unmap_group_regs(priv); | |
fba4ed03 | 777 | free_netdev(dev); |
b31a1d8b AF |
778 | return err; |
779 | } | |
780 | ||
cc772ab7 MR |
781 | static int gfar_hwtstamp_ioctl(struct net_device *netdev, |
782 | struct ifreq *ifr, int cmd) | |
783 | { | |
784 | struct hwtstamp_config config; | |
785 | struct gfar_private *priv = netdev_priv(netdev); | |
786 | ||
787 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
788 | return -EFAULT; | |
789 | ||
790 | /* reserved for future extensions */ | |
791 | if (config.flags) | |
792 | return -EINVAL; | |
793 | ||
f0ee7acf MR |
794 | switch (config.tx_type) { |
795 | case HWTSTAMP_TX_OFF: | |
796 | priv->hwts_tx_en = 0; | |
797 | break; | |
798 | case HWTSTAMP_TX_ON: | |
799 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
800 | return -ERANGE; | |
801 | priv->hwts_tx_en = 1; | |
802 | break; | |
803 | default: | |
cc772ab7 | 804 | return -ERANGE; |
f0ee7acf | 805 | } |
cc772ab7 MR |
806 | |
807 | switch (config.rx_filter) { | |
808 | case HWTSTAMP_FILTER_NONE: | |
97553f7f MR |
809 | if (priv->hwts_rx_en) { |
810 | stop_gfar(netdev); | |
811 | priv->hwts_rx_en = 0; | |
812 | startup_gfar(netdev); | |
813 | } | |
cc772ab7 MR |
814 | break; |
815 | default: | |
816 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
817 | return -ERANGE; | |
97553f7f MR |
818 | if (!priv->hwts_rx_en) { |
819 | stop_gfar(netdev); | |
820 | priv->hwts_rx_en = 1; | |
821 | startup_gfar(netdev); | |
822 | } | |
cc772ab7 MR |
823 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
824 | break; | |
825 | } | |
826 | ||
827 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
828 | -EFAULT : 0; | |
829 | } | |
830 | ||
0faac9f7 CW |
831 | /* Ioctl MII Interface */ |
832 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
833 | { | |
834 | struct gfar_private *priv = netdev_priv(dev); | |
835 | ||
836 | if (!netif_running(dev)) | |
837 | return -EINVAL; | |
838 | ||
cc772ab7 MR |
839 | if (cmd == SIOCSHWTSTAMP) |
840 | return gfar_hwtstamp_ioctl(dev, rq, cmd); | |
841 | ||
0faac9f7 CW |
842 | if (!priv->phydev) |
843 | return -ENODEV; | |
844 | ||
28b04113 | 845 | return phy_mii_ioctl(priv->phydev, rq, cmd); |
0faac9f7 CW |
846 | } |
847 | ||
fba4ed03 SG |
848 | static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs) |
849 | { | |
850 | unsigned int new_bit_map = 0x0; | |
851 | int mask = 0x1 << (max_qs - 1), i; | |
852 | for (i = 0; i < max_qs; i++) { | |
853 | if (bit_map & mask) | |
854 | new_bit_map = new_bit_map + (1 << i); | |
855 | mask = mask >> 0x1; | |
856 | } | |
857 | return new_bit_map; | |
858 | } | |
7a8b3372 | 859 | |
18294ad1 AV |
860 | static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, |
861 | u32 class) | |
7a8b3372 SG |
862 | { |
863 | u32 rqfpr = FPR_FILER_MASK; | |
864 | u32 rqfcr = 0x0; | |
865 | ||
866 | rqfar--; | |
867 | rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; | |
6c43e046 WJB |
868 | priv->ftp_rqfpr[rqfar] = rqfpr; |
869 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
870 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
871 | ||
872 | rqfar--; | |
873 | rqfcr = RQFCR_CMP_NOMATCH; | |
6c43e046 WJB |
874 | priv->ftp_rqfpr[rqfar] = rqfpr; |
875 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
876 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
877 | ||
878 | rqfar--; | |
879 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; | |
880 | rqfpr = class; | |
6c43e046 WJB |
881 | priv->ftp_rqfcr[rqfar] = rqfcr; |
882 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
883 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
884 | ||
885 | rqfar--; | |
886 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; | |
887 | rqfpr = class; | |
6c43e046 WJB |
888 | priv->ftp_rqfcr[rqfar] = rqfcr; |
889 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
890 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
891 | ||
892 | return rqfar; | |
893 | } | |
894 | ||
895 | static void gfar_init_filer_table(struct gfar_private *priv) | |
896 | { | |
897 | int i = 0x0; | |
898 | u32 rqfar = MAX_FILER_IDX; | |
899 | u32 rqfcr = 0x0; | |
900 | u32 rqfpr = FPR_FILER_MASK; | |
901 | ||
902 | /* Default rule */ | |
903 | rqfcr = RQFCR_CMP_MATCH; | |
6c43e046 WJB |
904 | priv->ftp_rqfcr[rqfar] = rqfcr; |
905 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
906 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
907 | ||
908 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); | |
909 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); | |
910 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); | |
911 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); | |
912 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); | |
913 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); | |
914 | ||
85dd08eb | 915 | /* cur_filer_idx indicated the first non-masked rule */ |
7a8b3372 SG |
916 | priv->cur_filer_idx = rqfar; |
917 | ||
918 | /* Rest are masked rules */ | |
919 | rqfcr = RQFCR_CMP_NOMATCH; | |
920 | for (i = 0; i < rqfar; i++) { | |
6c43e046 WJB |
921 | priv->ftp_rqfcr[i] = rqfcr; |
922 | priv->ftp_rqfpr[i] = rqfpr; | |
7a8b3372 SG |
923 | gfar_write_filer(priv, i, rqfcr, rqfpr); |
924 | } | |
925 | } | |
926 | ||
7d350977 AV |
927 | static void gfar_detect_errata(struct gfar_private *priv) |
928 | { | |
929 | struct device *dev = &priv->ofdev->dev; | |
930 | unsigned int pvr = mfspr(SPRN_PVR); | |
931 | unsigned int svr = mfspr(SPRN_SVR); | |
932 | unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ | |
933 | unsigned int rev = svr & 0xffff; | |
934 | ||
935 | /* MPC8313 Rev 2.0 and higher; All MPC837x */ | |
936 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || | |
937 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) | |
938 | priv->errata |= GFAR_ERRATA_74; | |
939 | ||
deb90eac AV |
940 | /* MPC8313 and MPC837x all rev */ |
941 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
942 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) | |
943 | priv->errata |= GFAR_ERRATA_76; | |
944 | ||
511d934f AV |
945 | /* MPC8313 and MPC837x all rev */ |
946 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
947 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) | |
948 | priv->errata |= GFAR_ERRATA_A002; | |
949 | ||
4363c2fd AD |
950 | /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */ |
951 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) || | |
952 | (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020)) | |
953 | priv->errata |= GFAR_ERRATA_12; | |
954 | ||
7d350977 AV |
955 | if (priv->errata) |
956 | dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", | |
957 | priv->errata); | |
958 | } | |
959 | ||
bb40dcbb AF |
960 | /* Set up the ethernet device structure, private data, |
961 | * and anything else we need before we start */ | |
74888760 | 962 | static int gfar_probe(struct platform_device *ofdev) |
1da177e4 LT |
963 | { |
964 | u32 tempval; | |
965 | struct net_device *dev = NULL; | |
966 | struct gfar_private *priv = NULL; | |
f4983704 | 967 | struct gfar __iomem *regs = NULL; |
46ceb60c | 968 | int err = 0, i, grp_idx = 0; |
c50a5d9a | 969 | int len_devname; |
fba4ed03 | 970 | u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0; |
46ceb60c | 971 | u32 isrg = 0; |
18294ad1 | 972 | u32 __iomem *baddr; |
1da177e4 | 973 | |
fba4ed03 | 974 | err = gfar_of_init(ofdev, &dev); |
1da177e4 | 975 | |
fba4ed03 SG |
976 | if (err) |
977 | return err; | |
1da177e4 LT |
978 | |
979 | priv = netdev_priv(dev); | |
4826857f KG |
980 | priv->ndev = dev; |
981 | priv->ofdev = ofdev; | |
61c7a080 | 982 | priv->node = ofdev->dev.of_node; |
4826857f | 983 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 984 | |
d87eb127 | 985 | spin_lock_init(&priv->bflock); |
ab939905 | 986 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 987 | |
b31a1d8b | 988 | dev_set_drvdata(&ofdev->dev, priv); |
46ceb60c | 989 | regs = priv->gfargrp[0].regs; |
1da177e4 | 990 | |
7d350977 AV |
991 | gfar_detect_errata(priv); |
992 | ||
1da177e4 LT |
993 | /* Stop the DMA engine now, in case it was running before */ |
994 | /* (The firmware could have used it, and left it running). */ | |
257d938a | 995 | gfar_halt(dev); |
1da177e4 LT |
996 | |
997 | /* Reset MAC layer */ | |
f4983704 | 998 | gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); |
1da177e4 | 999 | |
b98ac702 AF |
1000 | /* We need to delay at least 3 TX clocks */ |
1001 | udelay(2); | |
1002 | ||
1da177e4 | 1003 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
f4983704 | 1004 | gfar_write(®s->maccfg1, tempval); |
1da177e4 LT |
1005 | |
1006 | /* Initialize MACCFG2. */ | |
7d350977 AV |
1007 | tempval = MACCFG2_INIT_SETTINGS; |
1008 | if (gfar_has_errata(priv, GFAR_ERRATA_74)) | |
1009 | tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; | |
1010 | gfar_write(®s->maccfg2, tempval); | |
1da177e4 LT |
1011 | |
1012 | /* Initialize ECNTRL */ | |
f4983704 | 1013 | gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); |
1da177e4 | 1014 | |
1da177e4 | 1015 | /* Set the dev->base_addr to the gfar reg region */ |
f4983704 | 1016 | dev->base_addr = (unsigned long) regs; |
1da177e4 | 1017 | |
b31a1d8b | 1018 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 LT |
1019 | |
1020 | /* Fill in the dev structure */ | |
1da177e4 | 1021 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 | 1022 | dev->mtu = 1500; |
26ccfc37 | 1023 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
1024 | dev->ethtool_ops = &gfar_ethtool_ops; |
1025 | ||
fba4ed03 | 1026 | /* Register for napi ...We are registering NAPI for each grp */ |
46ceb60c SG |
1027 | for (i = 0; i < priv->num_grps; i++) |
1028 | netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT); | |
a12f801d | 1029 | |
b31a1d8b | 1030 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
8b3afe95 MM |
1031 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
1032 | NETIF_F_RXCSUM; | |
1033 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | | |
1034 | NETIF_F_RXCSUM | NETIF_F_HIGHDMA; | |
1035 | } | |
0bbaf069 KG |
1036 | |
1037 | priv->vlgrp = NULL; | |
1da177e4 | 1038 | |
26ccfc37 | 1039 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) |
0bbaf069 | 1040 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
0bbaf069 | 1041 | |
b31a1d8b | 1042 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
1043 | priv->extended_hash = 1; |
1044 | priv->hash_width = 9; | |
1045 | ||
f4983704 SG |
1046 | priv->hash_regs[0] = ®s->igaddr0; |
1047 | priv->hash_regs[1] = ®s->igaddr1; | |
1048 | priv->hash_regs[2] = ®s->igaddr2; | |
1049 | priv->hash_regs[3] = ®s->igaddr3; | |
1050 | priv->hash_regs[4] = ®s->igaddr4; | |
1051 | priv->hash_regs[5] = ®s->igaddr5; | |
1052 | priv->hash_regs[6] = ®s->igaddr6; | |
1053 | priv->hash_regs[7] = ®s->igaddr7; | |
1054 | priv->hash_regs[8] = ®s->gaddr0; | |
1055 | priv->hash_regs[9] = ®s->gaddr1; | |
1056 | priv->hash_regs[10] = ®s->gaddr2; | |
1057 | priv->hash_regs[11] = ®s->gaddr3; | |
1058 | priv->hash_regs[12] = ®s->gaddr4; | |
1059 | priv->hash_regs[13] = ®s->gaddr5; | |
1060 | priv->hash_regs[14] = ®s->gaddr6; | |
1061 | priv->hash_regs[15] = ®s->gaddr7; | |
0bbaf069 KG |
1062 | |
1063 | } else { | |
1064 | priv->extended_hash = 0; | |
1065 | priv->hash_width = 8; | |
1066 | ||
f4983704 SG |
1067 | priv->hash_regs[0] = ®s->gaddr0; |
1068 | priv->hash_regs[1] = ®s->gaddr1; | |
1069 | priv->hash_regs[2] = ®s->gaddr2; | |
1070 | priv->hash_regs[3] = ®s->gaddr3; | |
1071 | priv->hash_regs[4] = ®s->gaddr4; | |
1072 | priv->hash_regs[5] = ®s->gaddr5; | |
1073 | priv->hash_regs[6] = ®s->gaddr6; | |
1074 | priv->hash_regs[7] = ®s->gaddr7; | |
0bbaf069 KG |
1075 | } |
1076 | ||
b31a1d8b | 1077 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
1078 | priv->padding = DEFAULT_PADDING; |
1079 | else | |
1080 | priv->padding = 0; | |
1081 | ||
cc772ab7 MR |
1082 | if (dev->features & NETIF_F_IP_CSUM || |
1083 | priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) | |
0bbaf069 | 1084 | dev->hard_header_len += GMAC_FCB_LEN; |
1da177e4 | 1085 | |
46ceb60c SG |
1086 | /* Program the isrg regs only if number of grps > 1 */ |
1087 | if (priv->num_grps > 1) { | |
1088 | baddr = ®s->isrg0; | |
1089 | for (i = 0; i < priv->num_grps; i++) { | |
1090 | isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX); | |
1091 | isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX); | |
1092 | gfar_write(baddr, isrg); | |
1093 | baddr++; | |
1094 | isrg = 0x0; | |
1095 | } | |
1096 | } | |
1097 | ||
fba4ed03 | 1098 | /* Need to reverse the bit maps as bit_map's MSB is q0 |
984b3f57 | 1099 | * but, for_each_set_bit parses from right to left, which |
fba4ed03 | 1100 | * basically reverses the queue numbers */ |
46ceb60c SG |
1101 | for (i = 0; i< priv->num_grps; i++) { |
1102 | priv->gfargrp[i].tx_bit_map = reverse_bitmap( | |
1103 | priv->gfargrp[i].tx_bit_map, MAX_TX_QS); | |
1104 | priv->gfargrp[i].rx_bit_map = reverse_bitmap( | |
1105 | priv->gfargrp[i].rx_bit_map, MAX_RX_QS); | |
1106 | } | |
1107 | ||
1108 | /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, | |
1109 | * also assign queues to groups */ | |
1110 | for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { | |
1111 | priv->gfargrp[grp_idx].num_rx_queues = 0x0; | |
984b3f57 | 1112 | for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, |
46ceb60c SG |
1113 | priv->num_rx_queues) { |
1114 | priv->gfargrp[grp_idx].num_rx_queues++; | |
1115 | priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1116 | rstat = rstat | (RSTAT_CLEAR_RHALT >> i); | |
1117 | rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i); | |
1118 | } | |
1119 | priv->gfargrp[grp_idx].num_tx_queues = 0x0; | |
984b3f57 | 1120 | for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map, |
46ceb60c SG |
1121 | priv->num_tx_queues) { |
1122 | priv->gfargrp[grp_idx].num_tx_queues++; | |
1123 | priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1124 | tstat = tstat | (TSTAT_CLEAR_THALT >> i); | |
1125 | tqueue = tqueue | (TQUEUE_EN0 >> i); | |
1126 | } | |
1127 | priv->gfargrp[grp_idx].rstat = rstat; | |
1128 | priv->gfargrp[grp_idx].tstat = tstat; | |
1129 | rstat = tstat =0; | |
fba4ed03 | 1130 | } |
fba4ed03 SG |
1131 | |
1132 | gfar_write(®s->rqueue, rqueue); | |
1133 | gfar_write(®s->tqueue, tqueue); | |
1134 | ||
1da177e4 | 1135 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; |
1da177e4 | 1136 | |
a12f801d | 1137 | /* Initializing some of the rx/tx queue level parameters */ |
fba4ed03 SG |
1138 | for (i = 0; i < priv->num_tx_queues; i++) { |
1139 | priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; | |
1140 | priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; | |
1141 | priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; | |
1142 | priv->tx_queue[i]->txic = DEFAULT_TXIC; | |
1143 | } | |
a12f801d | 1144 | |
fba4ed03 SG |
1145 | for (i = 0; i < priv->num_rx_queues; i++) { |
1146 | priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
1147 | priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; | |
1148 | priv->rx_queue[i]->rxic = DEFAULT_RXIC; | |
1149 | } | |
1da177e4 | 1150 | |
1ccb8389 SG |
1151 | /* enable filer if using multiple RX queues*/ |
1152 | if(priv->num_rx_queues > 1) | |
1153 | priv->rx_filer_enable = 1; | |
0bbaf069 KG |
1154 | /* Enable most messages by default */ |
1155 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
1156 | ||
d3eab82b TP |
1157 | /* Carrier starts down, phylib will bring it up */ |
1158 | netif_carrier_off(dev); | |
1159 | ||
1da177e4 LT |
1160 | err = register_netdev(dev); |
1161 | ||
1162 | if (err) { | |
1163 | printk(KERN_ERR "%s: Cannot register net device, aborting.\n", | |
1164 | dev->name); | |
1165 | goto register_fail; | |
1166 | } | |
1167 | ||
2884e5cc AV |
1168 | device_init_wakeup(&dev->dev, |
1169 | priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
1170 | ||
c50a5d9a DH |
1171 | /* fill out IRQ number and name fields */ |
1172 | len_devname = strlen(dev->name); | |
46ceb60c SG |
1173 | for (i = 0; i < priv->num_grps; i++) { |
1174 | strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name, | |
1175 | len_devname); | |
1176 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { | |
1177 | strncpy(&priv->gfargrp[i].int_name_tx[len_devname], | |
1178 | "_g", sizeof("_g")); | |
1179 | priv->gfargrp[i].int_name_tx[ | |
1180 | strlen(priv->gfargrp[i].int_name_tx)] = i+48; | |
1181 | strncpy(&priv->gfargrp[i].int_name_tx[strlen( | |
1182 | priv->gfargrp[i].int_name_tx)], | |
1183 | "_tx", sizeof("_tx") + 1); | |
1184 | ||
1185 | strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name, | |
1186 | len_devname); | |
1187 | strncpy(&priv->gfargrp[i].int_name_rx[len_devname], | |
1188 | "_g", sizeof("_g")); | |
1189 | priv->gfargrp[i].int_name_rx[ | |
1190 | strlen(priv->gfargrp[i].int_name_rx)] = i+48; | |
1191 | strncpy(&priv->gfargrp[i].int_name_rx[strlen( | |
1192 | priv->gfargrp[i].int_name_rx)], | |
1193 | "_rx", sizeof("_rx") + 1); | |
1194 | ||
1195 | strncpy(&priv->gfargrp[i].int_name_er[0], dev->name, | |
1196 | len_devname); | |
1197 | strncpy(&priv->gfargrp[i].int_name_er[len_devname], | |
1198 | "_g", sizeof("_g")); | |
1199 | priv->gfargrp[i].int_name_er[strlen( | |
1200 | priv->gfargrp[i].int_name_er)] = i+48; | |
1201 | strncpy(&priv->gfargrp[i].int_name_er[strlen(\ | |
1202 | priv->gfargrp[i].int_name_er)], | |
1203 | "_er", sizeof("_er") + 1); | |
1204 | } else | |
1205 | priv->gfargrp[i].int_name_tx[len_devname] = '\0'; | |
1206 | } | |
c50a5d9a | 1207 | |
7a8b3372 SG |
1208 | /* Initialize the filer table */ |
1209 | gfar_init_filer_table(priv); | |
1210 | ||
7f7f5316 AF |
1211 | /* Create all the sysfs files */ |
1212 | gfar_init_sysfs(dev); | |
1213 | ||
1da177e4 | 1214 | /* Print out the device info */ |
e174961c | 1215 | printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr); |
1da177e4 LT |
1216 | |
1217 | /* Even more device info helps when determining which kernel */ | |
7f7f5316 | 1218 | /* provided which set of benchmarks. */ |
1da177e4 | 1219 | printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name); |
fba4ed03 | 1220 | for (i = 0; i < priv->num_rx_queues; i++) |
ddc01b3b | 1221 | printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n", |
fba4ed03 SG |
1222 | dev->name, i, priv->rx_queue[i]->rx_ring_size); |
1223 | for(i = 0; i < priv->num_tx_queues; i++) | |
ddc01b3b | 1224 | printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n", |
fba4ed03 | 1225 | dev->name, i, priv->tx_queue[i]->tx_ring_size); |
1da177e4 LT |
1226 | |
1227 | return 0; | |
1228 | ||
1229 | register_fail: | |
46ceb60c | 1230 | unmap_group_regs(priv); |
fba4ed03 SG |
1231 | free_tx_pointers(priv); |
1232 | free_rx_pointers(priv); | |
fe192a49 GL |
1233 | if (priv->phy_node) |
1234 | of_node_put(priv->phy_node); | |
1235 | if (priv->tbi_node) | |
1236 | of_node_put(priv->tbi_node); | |
1da177e4 | 1237 | free_netdev(dev); |
bb40dcbb | 1238 | return err; |
1da177e4 LT |
1239 | } |
1240 | ||
2dc11581 | 1241 | static int gfar_remove(struct platform_device *ofdev) |
1da177e4 | 1242 | { |
b31a1d8b | 1243 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
1da177e4 | 1244 | |
fe192a49 GL |
1245 | if (priv->phy_node) |
1246 | of_node_put(priv->phy_node); | |
1247 | if (priv->tbi_node) | |
1248 | of_node_put(priv->tbi_node); | |
1249 | ||
b31a1d8b | 1250 | dev_set_drvdata(&ofdev->dev, NULL); |
1da177e4 | 1251 | |
d9d8e041 | 1252 | unregister_netdev(priv->ndev); |
46ceb60c | 1253 | unmap_group_regs(priv); |
4826857f | 1254 | free_netdev(priv->ndev); |
1da177e4 LT |
1255 | |
1256 | return 0; | |
1257 | } | |
1258 | ||
d87eb127 | 1259 | #ifdef CONFIG_PM |
be926fc4 AV |
1260 | |
1261 | static int gfar_suspend(struct device *dev) | |
d87eb127 | 1262 | { |
be926fc4 AV |
1263 | struct gfar_private *priv = dev_get_drvdata(dev); |
1264 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1265 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1266 | unsigned long flags; |
1267 | u32 tempval; | |
1268 | ||
1269 | int magic_packet = priv->wol_en && | |
b31a1d8b | 1270 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 | 1271 | |
be926fc4 | 1272 | netif_device_detach(ndev); |
d87eb127 | 1273 | |
be926fc4 | 1274 | if (netif_running(ndev)) { |
fba4ed03 SG |
1275 | |
1276 | local_irq_save(flags); | |
1277 | lock_tx_qs(priv); | |
1278 | lock_rx_qs(priv); | |
d87eb127 | 1279 | |
be926fc4 | 1280 | gfar_halt_nodisable(ndev); |
d87eb127 SW |
1281 | |
1282 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
f4983704 | 1283 | tempval = gfar_read(®s->maccfg1); |
d87eb127 SW |
1284 | |
1285 | tempval &= ~MACCFG1_TX_EN; | |
1286 | ||
1287 | if (!magic_packet) | |
1288 | tempval &= ~MACCFG1_RX_EN; | |
1289 | ||
f4983704 | 1290 | gfar_write(®s->maccfg1, tempval); |
d87eb127 | 1291 | |
fba4ed03 SG |
1292 | unlock_rx_qs(priv); |
1293 | unlock_tx_qs(priv); | |
1294 | local_irq_restore(flags); | |
d87eb127 | 1295 | |
46ceb60c | 1296 | disable_napi(priv); |
d87eb127 SW |
1297 | |
1298 | if (magic_packet) { | |
1299 | /* Enable interrupt on Magic Packet */ | |
f4983704 | 1300 | gfar_write(®s->imask, IMASK_MAG); |
d87eb127 SW |
1301 | |
1302 | /* Enable Magic Packet mode */ | |
f4983704 | 1303 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1304 | tempval |= MACCFG2_MPEN; |
f4983704 | 1305 | gfar_write(®s->maccfg2, tempval); |
d87eb127 SW |
1306 | } else { |
1307 | phy_stop(priv->phydev); | |
1308 | } | |
1309 | } | |
1310 | ||
1311 | return 0; | |
1312 | } | |
1313 | ||
be926fc4 | 1314 | static int gfar_resume(struct device *dev) |
d87eb127 | 1315 | { |
be926fc4 AV |
1316 | struct gfar_private *priv = dev_get_drvdata(dev); |
1317 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1318 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1319 | unsigned long flags; |
1320 | u32 tempval; | |
1321 | int magic_packet = priv->wol_en && | |
b31a1d8b | 1322 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 | 1323 | |
be926fc4 AV |
1324 | if (!netif_running(ndev)) { |
1325 | netif_device_attach(ndev); | |
d87eb127 SW |
1326 | return 0; |
1327 | } | |
1328 | ||
1329 | if (!magic_packet && priv->phydev) | |
1330 | phy_start(priv->phydev); | |
1331 | ||
1332 | /* Disable Magic Packet mode, in case something | |
1333 | * else woke us up. | |
1334 | */ | |
fba4ed03 SG |
1335 | local_irq_save(flags); |
1336 | lock_tx_qs(priv); | |
1337 | lock_rx_qs(priv); | |
d87eb127 | 1338 | |
f4983704 | 1339 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1340 | tempval &= ~MACCFG2_MPEN; |
f4983704 | 1341 | gfar_write(®s->maccfg2, tempval); |
d87eb127 | 1342 | |
be926fc4 | 1343 | gfar_start(ndev); |
d87eb127 | 1344 | |
fba4ed03 SG |
1345 | unlock_rx_qs(priv); |
1346 | unlock_tx_qs(priv); | |
1347 | local_irq_restore(flags); | |
d87eb127 | 1348 | |
be926fc4 AV |
1349 | netif_device_attach(ndev); |
1350 | ||
46ceb60c | 1351 | enable_napi(priv); |
be926fc4 AV |
1352 | |
1353 | return 0; | |
1354 | } | |
1355 | ||
1356 | static int gfar_restore(struct device *dev) | |
1357 | { | |
1358 | struct gfar_private *priv = dev_get_drvdata(dev); | |
1359 | struct net_device *ndev = priv->ndev; | |
1360 | ||
1361 | if (!netif_running(ndev)) | |
1362 | return 0; | |
1363 | ||
1364 | gfar_init_bds(ndev); | |
1365 | init_registers(ndev); | |
1366 | gfar_set_mac_address(ndev); | |
1367 | gfar_init_mac(ndev); | |
1368 | gfar_start(ndev); | |
1369 | ||
1370 | priv->oldlink = 0; | |
1371 | priv->oldspeed = 0; | |
1372 | priv->oldduplex = -1; | |
1373 | ||
1374 | if (priv->phydev) | |
1375 | phy_start(priv->phydev); | |
d87eb127 | 1376 | |
be926fc4 | 1377 | netif_device_attach(ndev); |
5ea681d4 | 1378 | enable_napi(priv); |
d87eb127 SW |
1379 | |
1380 | return 0; | |
1381 | } | |
be926fc4 AV |
1382 | |
1383 | static struct dev_pm_ops gfar_pm_ops = { | |
1384 | .suspend = gfar_suspend, | |
1385 | .resume = gfar_resume, | |
1386 | .freeze = gfar_suspend, | |
1387 | .thaw = gfar_resume, | |
1388 | .restore = gfar_restore, | |
1389 | }; | |
1390 | ||
1391 | #define GFAR_PM_OPS (&gfar_pm_ops) | |
1392 | ||
d87eb127 | 1393 | #else |
be926fc4 AV |
1394 | |
1395 | #define GFAR_PM_OPS NULL | |
be926fc4 | 1396 | |
d87eb127 | 1397 | #endif |
1da177e4 | 1398 | |
e8a2b6a4 AF |
1399 | /* Reads the controller's registers to determine what interface |
1400 | * connects it to the PHY. | |
1401 | */ | |
1402 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
1403 | { | |
1404 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1405 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
f4983704 SG |
1406 | u32 ecntrl; |
1407 | ||
f4983704 | 1408 | ecntrl = gfar_read(®s->ecntrl); |
e8a2b6a4 AF |
1409 | |
1410 | if (ecntrl & ECNTRL_SGMII_MODE) | |
1411 | return PHY_INTERFACE_MODE_SGMII; | |
1412 | ||
1413 | if (ecntrl & ECNTRL_TBI_MODE) { | |
1414 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
1415 | return PHY_INTERFACE_MODE_RTBI; | |
1416 | else | |
1417 | return PHY_INTERFACE_MODE_TBI; | |
1418 | } | |
1419 | ||
1420 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
1421 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) | |
1422 | return PHY_INTERFACE_MODE_RMII; | |
7132ab7f | 1423 | else { |
b31a1d8b | 1424 | phy_interface_t interface = priv->interface; |
7132ab7f AF |
1425 | |
1426 | /* | |
1427 | * This isn't autodetected right now, so it must | |
1428 | * be set by the device tree or platform code. | |
1429 | */ | |
1430 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
1431 | return PHY_INTERFACE_MODE_RGMII_ID; | |
1432 | ||
e8a2b6a4 | 1433 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 1434 | } |
e8a2b6a4 AF |
1435 | } |
1436 | ||
b31a1d8b | 1437 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
1438 | return PHY_INTERFACE_MODE_GMII; |
1439 | ||
1440 | return PHY_INTERFACE_MODE_MII; | |
1441 | } | |
1442 | ||
1443 | ||
bb40dcbb AF |
1444 | /* Initializes driver's PHY state, and attaches to the PHY. |
1445 | * Returns 0 on success. | |
1da177e4 LT |
1446 | */ |
1447 | static int init_phy(struct net_device *dev) | |
1448 | { | |
1449 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 1450 | uint gigabit_support = |
b31a1d8b | 1451 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb | 1452 | SUPPORTED_1000baseT_Full : 0; |
e8a2b6a4 | 1453 | phy_interface_t interface; |
1da177e4 LT |
1454 | |
1455 | priv->oldlink = 0; | |
1456 | priv->oldspeed = 0; | |
1457 | priv->oldduplex = -1; | |
1458 | ||
e8a2b6a4 AF |
1459 | interface = gfar_get_interface(dev); |
1460 | ||
1db780f8 AV |
1461 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, |
1462 | interface); | |
1463 | if (!priv->phydev) | |
1464 | priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, | |
1465 | interface); | |
1466 | if (!priv->phydev) { | |
1467 | dev_err(&dev->dev, "could not attach to PHY\n"); | |
1468 | return -ENODEV; | |
fe192a49 | 1469 | } |
1da177e4 | 1470 | |
d3c12873 KJ |
1471 | if (interface == PHY_INTERFACE_MODE_SGMII) |
1472 | gfar_configure_serdes(dev); | |
1473 | ||
bb40dcbb | 1474 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
1475 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
1476 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
1477 | |
1478 | return 0; | |
1da177e4 LT |
1479 | } |
1480 | ||
d0313587 PG |
1481 | /* |
1482 | * Initialize TBI PHY interface for communicating with the | |
1483 | * SERDES lynx PHY on the chip. We communicate with this PHY | |
1484 | * through the MDIO bus on each controller, treating it as a | |
1485 | * "normal" PHY at the address found in the TBIPA register. We assume | |
1486 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
1487 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
1488 | * value doesn't matter, as there are no other PHYs on the bus. | |
1489 | */ | |
d3c12873 KJ |
1490 | static void gfar_configure_serdes(struct net_device *dev) |
1491 | { | |
1492 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
1493 | struct phy_device *tbiphy; |
1494 | ||
1495 | if (!priv->tbi_node) { | |
1496 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
1497 | "device tree specify a tbi-handle\n"); | |
1498 | return; | |
1499 | } | |
c132419e | 1500 | |
fe192a49 GL |
1501 | tbiphy = of_phy_find_device(priv->tbi_node); |
1502 | if (!tbiphy) { | |
1503 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
1504 | return; |
1505 | } | |
d3c12873 | 1506 | |
b31a1d8b AF |
1507 | /* |
1508 | * If the link is already up, we must already be ok, and don't need to | |
bdb59f94 TP |
1509 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
1510 | * everything for us? Resetting it takes the link down and requires | |
1511 | * several seconds for it to come back. | |
1512 | */ | |
fe192a49 | 1513 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 1514 | return; |
d3c12873 | 1515 | |
d0313587 | 1516 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 1517 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 1518 | |
fe192a49 | 1519 | phy_write(tbiphy, MII_ADVERTISE, |
d3c12873 KJ |
1520 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
1521 | ADVERTISE_1000XPSE_ASYM); | |
1522 | ||
fe192a49 | 1523 | phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE | |
d3c12873 KJ |
1524 | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000); |
1525 | } | |
1526 | ||
1da177e4 LT |
1527 | static void init_registers(struct net_device *dev) |
1528 | { | |
1529 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 1530 | struct gfar __iomem *regs = NULL; |
46ceb60c | 1531 | int i = 0; |
1da177e4 | 1532 | |
46ceb60c SG |
1533 | for (i = 0; i < priv->num_grps; i++) { |
1534 | regs = priv->gfargrp[i].regs; | |
1535 | /* Clear IEVENT */ | |
1536 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1da177e4 | 1537 | |
46ceb60c SG |
1538 | /* Initialize IMASK */ |
1539 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1540 | } | |
1da177e4 | 1541 | |
46ceb60c | 1542 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1543 | /* Init hash registers to zero */ |
f4983704 SG |
1544 | gfar_write(®s->igaddr0, 0); |
1545 | gfar_write(®s->igaddr1, 0); | |
1546 | gfar_write(®s->igaddr2, 0); | |
1547 | gfar_write(®s->igaddr3, 0); | |
1548 | gfar_write(®s->igaddr4, 0); | |
1549 | gfar_write(®s->igaddr5, 0); | |
1550 | gfar_write(®s->igaddr6, 0); | |
1551 | gfar_write(®s->igaddr7, 0); | |
1552 | ||
1553 | gfar_write(®s->gaddr0, 0); | |
1554 | gfar_write(®s->gaddr1, 0); | |
1555 | gfar_write(®s->gaddr2, 0); | |
1556 | gfar_write(®s->gaddr3, 0); | |
1557 | gfar_write(®s->gaddr4, 0); | |
1558 | gfar_write(®s->gaddr5, 0); | |
1559 | gfar_write(®s->gaddr6, 0); | |
1560 | gfar_write(®s->gaddr7, 0); | |
1da177e4 | 1561 | |
1da177e4 | 1562 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 1563 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
f4983704 | 1564 | memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
1565 | |
1566 | /* Mask off the CAM interrupts */ | |
f4983704 SG |
1567 | gfar_write(®s->rmon.cam1, 0xffffffff); |
1568 | gfar_write(®s->rmon.cam2, 0xffffffff); | |
1da177e4 LT |
1569 | } |
1570 | ||
1571 | /* Initialize the max receive buffer length */ | |
f4983704 | 1572 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
1da177e4 | 1573 | |
1da177e4 | 1574 | /* Initialize the Minimum Frame Length Register */ |
f4983704 | 1575 | gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); |
1da177e4 LT |
1576 | } |
1577 | ||
511d934f AV |
1578 | static int __gfar_is_rx_idle(struct gfar_private *priv) |
1579 | { | |
1580 | u32 res; | |
1581 | ||
1582 | /* | |
1583 | * Normaly TSEC should not hang on GRS commands, so we should | |
1584 | * actually wait for IEVENT_GRSC flag. | |
1585 | */ | |
1586 | if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002))) | |
1587 | return 0; | |
1588 | ||
1589 | /* | |
1590 | * Read the eTSEC register at offset 0xD1C. If bits 7-14 are | |
1591 | * the same as bits 23-30, the eTSEC Rx is assumed to be idle | |
1592 | * and the Rx can be safely reset. | |
1593 | */ | |
1594 | res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); | |
1595 | res &= 0x7f807f80; | |
1596 | if ((res & 0xffff) == (res >> 16)) | |
1597 | return 1; | |
1598 | ||
1599 | return 0; | |
1600 | } | |
0bbaf069 KG |
1601 | |
1602 | /* Halt the receive and transmit queues */ | |
d87eb127 | 1603 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
1604 | { |
1605 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1606 | struct gfar __iomem *regs = NULL; |
1da177e4 | 1607 | u32 tempval; |
46ceb60c | 1608 | int i = 0; |
1da177e4 | 1609 | |
46ceb60c SG |
1610 | for (i = 0; i < priv->num_grps; i++) { |
1611 | regs = priv->gfargrp[i].regs; | |
1612 | /* Mask all interrupts */ | |
1613 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1da177e4 | 1614 | |
46ceb60c SG |
1615 | /* Clear all interrupts */ |
1616 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1617 | } | |
1da177e4 | 1618 | |
46ceb60c | 1619 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1620 | /* Stop the DMA, and wait for it to stop */ |
f4983704 | 1621 | tempval = gfar_read(®s->dmactrl); |
1da177e4 LT |
1622 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) |
1623 | != (DMACTRL_GRS | DMACTRL_GTS)) { | |
511d934f AV |
1624 | int ret; |
1625 | ||
1da177e4 | 1626 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1627 | gfar_write(®s->dmactrl, tempval); |
1da177e4 | 1628 | |
511d934f AV |
1629 | do { |
1630 | ret = spin_event_timeout(((gfar_read(®s->ievent) & | |
1631 | (IEVENT_GRSC | IEVENT_GTSC)) == | |
1632 | (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0); | |
1633 | if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC)) | |
1634 | ret = __gfar_is_rx_idle(priv); | |
1635 | } while (!ret); | |
1da177e4 | 1636 | } |
d87eb127 | 1637 | } |
d87eb127 SW |
1638 | |
1639 | /* Halt the receive and transmit queues */ | |
1640 | void gfar_halt(struct net_device *dev) | |
1641 | { | |
1642 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1643 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 | 1644 | u32 tempval; |
1da177e4 | 1645 | |
2a54adc3 SW |
1646 | gfar_halt_nodisable(dev); |
1647 | ||
1da177e4 LT |
1648 | /* Disable Rx and Tx */ |
1649 | tempval = gfar_read(®s->maccfg1); | |
1650 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1651 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
1652 | } |
1653 | ||
46ceb60c SG |
1654 | static void free_grp_irqs(struct gfar_priv_grp *grp) |
1655 | { | |
1656 | free_irq(grp->interruptError, grp); | |
1657 | free_irq(grp->interruptTransmit, grp); | |
1658 | free_irq(grp->interruptReceive, grp); | |
1659 | } | |
1660 | ||
0bbaf069 KG |
1661 | void stop_gfar(struct net_device *dev) |
1662 | { | |
1663 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1664 | unsigned long flags; |
46ceb60c | 1665 | int i; |
0bbaf069 | 1666 | |
bb40dcbb AF |
1667 | phy_stop(priv->phydev); |
1668 | ||
a12f801d | 1669 | |
0bbaf069 | 1670 | /* Lock it down */ |
fba4ed03 SG |
1671 | local_irq_save(flags); |
1672 | lock_tx_qs(priv); | |
1673 | lock_rx_qs(priv); | |
0bbaf069 | 1674 | |
0bbaf069 | 1675 | gfar_halt(dev); |
1da177e4 | 1676 | |
fba4ed03 SG |
1677 | unlock_rx_qs(priv); |
1678 | unlock_tx_qs(priv); | |
1679 | local_irq_restore(flags); | |
1da177e4 LT |
1680 | |
1681 | /* Free the IRQs */ | |
b31a1d8b | 1682 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
1683 | for (i = 0; i < priv->num_grps; i++) |
1684 | free_grp_irqs(&priv->gfargrp[i]); | |
1da177e4 | 1685 | } else { |
46ceb60c SG |
1686 | for (i = 0; i < priv->num_grps; i++) |
1687 | free_irq(priv->gfargrp[i].interruptTransmit, | |
1688 | &priv->gfargrp[i]); | |
1da177e4 LT |
1689 | } |
1690 | ||
1691 | free_skb_resources(priv); | |
1da177e4 LT |
1692 | } |
1693 | ||
fba4ed03 | 1694 | static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 1695 | { |
1da177e4 | 1696 | struct txbd8 *txbdp; |
fba4ed03 | 1697 | struct gfar_private *priv = netdev_priv(tx_queue->dev); |
4669bc90 | 1698 | int i, j; |
1da177e4 | 1699 | |
a12f801d | 1700 | txbdp = tx_queue->tx_bd_base; |
1da177e4 | 1701 | |
a12f801d SG |
1702 | for (i = 0; i < tx_queue->tx_ring_size; i++) { |
1703 | if (!tx_queue->tx_skbuff[i]) | |
4669bc90 | 1704 | continue; |
1da177e4 | 1705 | |
4826857f | 1706 | dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr, |
4669bc90 DH |
1707 | txbdp->length, DMA_TO_DEVICE); |
1708 | txbdp->lstatus = 0; | |
fba4ed03 SG |
1709 | for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; |
1710 | j++) { | |
4669bc90 | 1711 | txbdp++; |
4826857f | 1712 | dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr, |
4669bc90 | 1713 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 1714 | } |
ad5da7ab | 1715 | txbdp++; |
a12f801d SG |
1716 | dev_kfree_skb_any(tx_queue->tx_skbuff[i]); |
1717 | tx_queue->tx_skbuff[i] = NULL; | |
1da177e4 | 1718 | } |
a12f801d | 1719 | kfree(tx_queue->tx_skbuff); |
fba4ed03 | 1720 | } |
1da177e4 | 1721 | |
fba4ed03 SG |
1722 | static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) |
1723 | { | |
1724 | struct rxbd8 *rxbdp; | |
1725 | struct gfar_private *priv = netdev_priv(rx_queue->dev); | |
1726 | int i; | |
1da177e4 | 1727 | |
fba4ed03 | 1728 | rxbdp = rx_queue->rx_bd_base; |
1da177e4 | 1729 | |
a12f801d SG |
1730 | for (i = 0; i < rx_queue->rx_ring_size; i++) { |
1731 | if (rx_queue->rx_skbuff[i]) { | |
fba4ed03 SG |
1732 | dma_unmap_single(&priv->ofdev->dev, |
1733 | rxbdp->bufPtr, priv->rx_buffer_size, | |
e69edd21 | 1734 | DMA_FROM_DEVICE); |
a12f801d SG |
1735 | dev_kfree_skb_any(rx_queue->rx_skbuff[i]); |
1736 | rx_queue->rx_skbuff[i] = NULL; | |
1da177e4 | 1737 | } |
e69edd21 AV |
1738 | rxbdp->lstatus = 0; |
1739 | rxbdp->bufPtr = 0; | |
1740 | rxbdp++; | |
1da177e4 | 1741 | } |
a12f801d | 1742 | kfree(rx_queue->rx_skbuff); |
fba4ed03 | 1743 | } |
e69edd21 | 1744 | |
fba4ed03 SG |
1745 | /* If there are any tx skbs or rx skbs still around, free them. |
1746 | * Then free tx_skbuff and rx_skbuff */ | |
1747 | static void free_skb_resources(struct gfar_private *priv) | |
1748 | { | |
1749 | struct gfar_priv_tx_q *tx_queue = NULL; | |
1750 | struct gfar_priv_rx_q *rx_queue = NULL; | |
1751 | int i; | |
1752 | ||
1753 | /* Go through all the buffer descriptors and free their data buffers */ | |
1754 | for (i = 0; i < priv->num_tx_queues; i++) { | |
1755 | tx_queue = priv->tx_queue[i]; | |
7c0d10d3 | 1756 | if(tx_queue->tx_skbuff) |
fba4ed03 SG |
1757 | free_skb_tx_queue(tx_queue); |
1758 | } | |
1759 | ||
1760 | for (i = 0; i < priv->num_rx_queues; i++) { | |
1761 | rx_queue = priv->rx_queue[i]; | |
7c0d10d3 | 1762 | if(rx_queue->rx_skbuff) |
fba4ed03 SG |
1763 | free_skb_rx_queue(rx_queue); |
1764 | } | |
1765 | ||
1766 | dma_free_coherent(&priv->ofdev->dev, | |
1767 | sizeof(struct txbd8) * priv->total_tx_ring_size + | |
1768 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
1769 | priv->tx_queue[0]->tx_bd_base, | |
1770 | priv->tx_queue[0]->tx_bd_dma_base); | |
7df9c43f | 1771 | skb_queue_purge(&priv->rx_recycle); |
1da177e4 LT |
1772 | } |
1773 | ||
0bbaf069 KG |
1774 | void gfar_start(struct net_device *dev) |
1775 | { | |
1776 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1777 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
0bbaf069 | 1778 | u32 tempval; |
46ceb60c | 1779 | int i = 0; |
0bbaf069 KG |
1780 | |
1781 | /* Enable Rx and Tx in MACCFG1 */ | |
1782 | tempval = gfar_read(®s->maccfg1); | |
1783 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1784 | gfar_write(®s->maccfg1, tempval); | |
1785 | ||
1786 | /* Initialize DMACTRL to have WWR and WOP */ | |
f4983704 | 1787 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1788 | tempval |= DMACTRL_INIT_SETTINGS; |
f4983704 | 1789 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1790 | |
0bbaf069 | 1791 | /* Make sure we aren't stopped */ |
f4983704 | 1792 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1793 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1794 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1795 | |
46ceb60c SG |
1796 | for (i = 0; i < priv->num_grps; i++) { |
1797 | regs = priv->gfargrp[i].regs; | |
1798 | /* Clear THLT/RHLT, so that the DMA starts polling now */ | |
1799 | gfar_write(®s->tstat, priv->gfargrp[i].tstat); | |
1800 | gfar_write(®s->rstat, priv->gfargrp[i].rstat); | |
1801 | /* Unmask the interrupts we look for */ | |
1802 | gfar_write(®s->imask, IMASK_DEFAULT); | |
1803 | } | |
12dea57b | 1804 | |
1ae5dc34 | 1805 | dev->trans_start = jiffies; /* prevent tx timeout */ |
0bbaf069 KG |
1806 | } |
1807 | ||
46ceb60c | 1808 | void gfar_configure_coalescing(struct gfar_private *priv, |
18294ad1 | 1809 | unsigned long tx_mask, unsigned long rx_mask) |
1da177e4 | 1810 | { |
46ceb60c | 1811 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 1812 | u32 __iomem *baddr; |
46ceb60c | 1813 | int i = 0; |
1da177e4 | 1814 | |
46ceb60c SG |
1815 | /* Backward compatible case ---- even if we enable |
1816 | * multiple queues, there's only single reg to program | |
1817 | */ | |
1818 | gfar_write(®s->txic, 0); | |
1819 | if(likely(priv->tx_queue[0]->txcoalescing)) | |
1820 | gfar_write(®s->txic, priv->tx_queue[0]->txic); | |
1da177e4 | 1821 | |
46ceb60c SG |
1822 | gfar_write(®s->rxic, 0); |
1823 | if(unlikely(priv->rx_queue[0]->rxcoalescing)) | |
1824 | gfar_write(®s->rxic, priv->rx_queue[0]->rxic); | |
815b97c6 | 1825 | |
46ceb60c SG |
1826 | if (priv->mode == MQ_MG_MODE) { |
1827 | baddr = ®s->txic0; | |
984b3f57 | 1828 | for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { |
46ceb60c SG |
1829 | if (likely(priv->tx_queue[i]->txcoalescing)) { |
1830 | gfar_write(baddr + i, 0); | |
1831 | gfar_write(baddr + i, priv->tx_queue[i]->txic); | |
1832 | } | |
1833 | } | |
1834 | ||
1835 | baddr = ®s->rxic0; | |
984b3f57 | 1836 | for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { |
46ceb60c SG |
1837 | if (likely(priv->rx_queue[i]->rxcoalescing)) { |
1838 | gfar_write(baddr + i, 0); | |
1839 | gfar_write(baddr + i, priv->rx_queue[i]->rxic); | |
1840 | } | |
1841 | } | |
1842 | } | |
1843 | } | |
1844 | ||
1845 | static int register_grp_irqs(struct gfar_priv_grp *grp) | |
1846 | { | |
1847 | struct gfar_private *priv = grp->priv; | |
1848 | struct net_device *dev = priv->ndev; | |
1849 | int err; | |
1da177e4 | 1850 | |
1da177e4 LT |
1851 | /* If the device has multiple interrupts, register for |
1852 | * them. Otherwise, only register for the one */ | |
b31a1d8b | 1853 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1854 | /* Install our interrupt handlers for Error, |
1da177e4 | 1855 | * Transmit, and Receive */ |
46ceb60c SG |
1856 | if ((err = request_irq(grp->interruptError, gfar_error, 0, |
1857 | grp->int_name_er,grp)) < 0) { | |
0bbaf069 | 1858 | if (netif_msg_intr(priv)) |
46ceb60c SG |
1859 | printk(KERN_ERR "%s: Can't get IRQ %d\n", |
1860 | dev->name, grp->interruptError); | |
1861 | ||
2145f1af | 1862 | goto err_irq_fail; |
1da177e4 LT |
1863 | } |
1864 | ||
46ceb60c SG |
1865 | if ((err = request_irq(grp->interruptTransmit, gfar_transmit, |
1866 | 0, grp->int_name_tx, grp)) < 0) { | |
0bbaf069 | 1867 | if (netif_msg_intr(priv)) |
46ceb60c SG |
1868 | printk(KERN_ERR "%s: Can't get IRQ %d\n", |
1869 | dev->name, grp->interruptTransmit); | |
1da177e4 LT |
1870 | goto tx_irq_fail; |
1871 | } | |
1872 | ||
46ceb60c SG |
1873 | if ((err = request_irq(grp->interruptReceive, gfar_receive, 0, |
1874 | grp->int_name_rx, grp)) < 0) { | |
0bbaf069 | 1875 | if (netif_msg_intr(priv)) |
46ceb60c SG |
1876 | printk(KERN_ERR "%s: Can't get IRQ %d\n", |
1877 | dev->name, grp->interruptReceive); | |
1da177e4 LT |
1878 | goto rx_irq_fail; |
1879 | } | |
1880 | } else { | |
46ceb60c SG |
1881 | if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0, |
1882 | grp->int_name_tx, grp)) < 0) { | |
0bbaf069 | 1883 | if (netif_msg_intr(priv)) |
46ceb60c SG |
1884 | printk(KERN_ERR "%s: Can't get IRQ %d\n", |
1885 | dev->name, grp->interruptTransmit); | |
1da177e4 LT |
1886 | goto err_irq_fail; |
1887 | } | |
1888 | } | |
1889 | ||
46ceb60c SG |
1890 | return 0; |
1891 | ||
1892 | rx_irq_fail: | |
1893 | free_irq(grp->interruptTransmit, grp); | |
1894 | tx_irq_fail: | |
1895 | free_irq(grp->interruptError, grp); | |
1896 | err_irq_fail: | |
1897 | return err; | |
1898 | ||
1899 | } | |
1900 | ||
1901 | /* Bring the controller up and running */ | |
1902 | int startup_gfar(struct net_device *ndev) | |
1903 | { | |
1904 | struct gfar_private *priv = netdev_priv(ndev); | |
1905 | struct gfar __iomem *regs = NULL; | |
1906 | int err, i, j; | |
1907 | ||
1908 | for (i = 0; i < priv->num_grps; i++) { | |
1909 | regs= priv->gfargrp[i].regs; | |
1910 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1911 | } | |
1912 | ||
1913 | regs= priv->gfargrp[0].regs; | |
1914 | err = gfar_alloc_skb_resources(ndev); | |
1915 | if (err) | |
1916 | return err; | |
1917 | ||
1918 | gfar_init_mac(ndev); | |
1919 | ||
1920 | for (i = 0; i < priv->num_grps; i++) { | |
1921 | err = register_grp_irqs(&priv->gfargrp[i]); | |
1922 | if (err) { | |
1923 | for (j = 0; j < i; j++) | |
1924 | free_grp_irqs(&priv->gfargrp[j]); | |
ff76015f | 1925 | goto irq_fail; |
46ceb60c SG |
1926 | } |
1927 | } | |
1928 | ||
7f7f5316 | 1929 | /* Start the controller */ |
ccc05c6e | 1930 | gfar_start(ndev); |
1da177e4 | 1931 | |
826aa4a0 AV |
1932 | phy_start(priv->phydev); |
1933 | ||
46ceb60c SG |
1934 | gfar_configure_coalescing(priv, 0xFF, 0xFF); |
1935 | ||
1da177e4 LT |
1936 | return 0; |
1937 | ||
46ceb60c | 1938 | irq_fail: |
e69edd21 | 1939 | free_skb_resources(priv); |
1da177e4 LT |
1940 | return err; |
1941 | } | |
1942 | ||
1943 | /* Called when something needs to use the ethernet device */ | |
1944 | /* Returns 0 for success. */ | |
1945 | static int gfar_enet_open(struct net_device *dev) | |
1946 | { | |
94e8cc35 | 1947 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1948 | int err; |
1949 | ||
46ceb60c | 1950 | enable_napi(priv); |
bea3348e | 1951 | |
0fd56bb5 AF |
1952 | skb_queue_head_init(&priv->rx_recycle); |
1953 | ||
1da177e4 LT |
1954 | /* Initialize a bunch of registers */ |
1955 | init_registers(dev); | |
1956 | ||
1957 | gfar_set_mac_address(dev); | |
1958 | ||
1959 | err = init_phy(dev); | |
1960 | ||
a12f801d | 1961 | if (err) { |
46ceb60c | 1962 | disable_napi(priv); |
1da177e4 | 1963 | return err; |
bea3348e | 1964 | } |
1da177e4 LT |
1965 | |
1966 | err = startup_gfar(dev); | |
db0e8e3f | 1967 | if (err) { |
46ceb60c | 1968 | disable_napi(priv); |
db0e8e3f AV |
1969 | return err; |
1970 | } | |
1da177e4 | 1971 | |
fba4ed03 | 1972 | netif_tx_start_all_queues(dev); |
1da177e4 | 1973 | |
2884e5cc AV |
1974 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
1975 | ||
1da177e4 LT |
1976 | return err; |
1977 | } | |
1978 | ||
54dc79fe | 1979 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 1980 | { |
54dc79fe | 1981 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
1982 | |
1983 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 1984 | |
0bbaf069 KG |
1985 | return fcb; |
1986 | } | |
1987 | ||
1988 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb) | |
1989 | { | |
7f7f5316 | 1990 | u8 flags = 0; |
0bbaf069 KG |
1991 | |
1992 | /* If we're here, it's a IP packet with a TCP or UDP | |
1993 | * payload. We set it to checksum, using a pseudo-header | |
1994 | * we provide | |
1995 | */ | |
7f7f5316 | 1996 | flags = TXFCB_DEFAULT; |
0bbaf069 | 1997 | |
7f7f5316 AF |
1998 | /* Tell the controller what the protocol is */ |
1999 | /* And provide the already calculated phcs */ | |
eddc9ec5 | 2000 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 2001 | flags |= TXFCB_UDP; |
4bedb452 | 2002 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 2003 | } else |
8da32de5 | 2004 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
2005 | |
2006 | /* l3os is the distance between the start of the | |
2007 | * frame (skb->data) and the start of the IP hdr. | |
2008 | * l4os is the distance between the start of the | |
2009 | * l3 hdr and the l4 hdr */ | |
bbe735e4 | 2010 | fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN); |
cfe1fc77 | 2011 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 2012 | |
7f7f5316 | 2013 | fcb->flags = flags; |
0bbaf069 KG |
2014 | } |
2015 | ||
7f7f5316 | 2016 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 2017 | { |
7f7f5316 | 2018 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
2019 | fcb->vlctl = vlan_tx_tag_get(skb); |
2020 | } | |
2021 | ||
4669bc90 DH |
2022 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
2023 | struct txbd8 *base, int ring_size) | |
2024 | { | |
2025 | struct txbd8 *new_bd = bdp + stride; | |
2026 | ||
2027 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
2028 | } | |
2029 | ||
2030 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
2031 | int ring_size) | |
2032 | { | |
2033 | return skip_txbd(bdp, 1, base, ring_size); | |
2034 | } | |
2035 | ||
1da177e4 LT |
2036 | /* This is called by the kernel when a frame is ready for transmission. */ |
2037 | /* It is pointed to by the dev->hard_start_xmit function pointer */ | |
2038 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
2039 | { | |
2040 | struct gfar_private *priv = netdev_priv(dev); | |
a12f801d | 2041 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2042 | struct netdev_queue *txq; |
f4983704 | 2043 | struct gfar __iomem *regs = NULL; |
0bbaf069 | 2044 | struct txfcb *fcb = NULL; |
f0ee7acf | 2045 | struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; |
5a5efed4 | 2046 | u32 lstatus; |
f0ee7acf | 2047 | int i, rq = 0, do_tstamp = 0; |
4669bc90 | 2048 | u32 bufaddr; |
fef6108d | 2049 | unsigned long flags; |
f0ee7acf | 2050 | unsigned int nr_frags, nr_txbds, length; |
fba4ed03 | 2051 | |
deb90eac AV |
2052 | /* |
2053 | * TOE=1 frames larger than 2500 bytes may see excess delays | |
2054 | * before start of transmission. | |
2055 | */ | |
2056 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) && | |
2057 | skb->ip_summed == CHECKSUM_PARTIAL && | |
2058 | skb->len > 2500)) { | |
2059 | int ret; | |
2060 | ||
2061 | ret = skb_checksum_help(skb); | |
2062 | if (ret) | |
2063 | return ret; | |
2064 | } | |
2065 | ||
fba4ed03 SG |
2066 | rq = skb->queue_mapping; |
2067 | tx_queue = priv->tx_queue[rq]; | |
2068 | txq = netdev_get_tx_queue(dev, rq); | |
a12f801d | 2069 | base = tx_queue->tx_bd_base; |
46ceb60c | 2070 | regs = tx_queue->grp->regs; |
f0ee7acf MR |
2071 | |
2072 | /* check if time stamp should be generated */ | |
2244d07b OH |
2073 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && |
2074 | priv->hwts_tx_en)) | |
f0ee7acf | 2075 | do_tstamp = 1; |
4669bc90 | 2076 | |
5b28beaf LY |
2077 | /* make space for additional header when fcb is needed */ |
2078 | if (((skb->ip_summed == CHECKSUM_PARTIAL) || | |
eab6d18d | 2079 | vlan_tx_tag_present(skb) || |
f0ee7acf | 2080 | unlikely(do_tstamp)) && |
5b28beaf | 2081 | (skb_headroom(skb) < GMAC_FCB_LEN)) { |
54dc79fe SH |
2082 | struct sk_buff *skb_new; |
2083 | ||
2084 | skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN); | |
2085 | if (!skb_new) { | |
2086 | dev->stats.tx_errors++; | |
bd14ba84 | 2087 | kfree_skb(skb); |
54dc79fe SH |
2088 | return NETDEV_TX_OK; |
2089 | } | |
2090 | kfree_skb(skb); | |
2091 | skb = skb_new; | |
2092 | } | |
2093 | ||
4669bc90 DH |
2094 | /* total number of fragments in the SKB */ |
2095 | nr_frags = skb_shinfo(skb)->nr_frags; | |
2096 | ||
f0ee7acf MR |
2097 | /* calculate the required number of TxBDs for this skb */ |
2098 | if (unlikely(do_tstamp)) | |
2099 | nr_txbds = nr_frags + 2; | |
2100 | else | |
2101 | nr_txbds = nr_frags + 1; | |
2102 | ||
4669bc90 | 2103 | /* check if there is space to queue this packet */ |
f0ee7acf | 2104 | if (nr_txbds > tx_queue->num_txbdfree) { |
4669bc90 | 2105 | /* no space, stop the queue */ |
fba4ed03 | 2106 | netif_tx_stop_queue(txq); |
4669bc90 | 2107 | dev->stats.tx_fifo_errors++; |
4669bc90 DH |
2108 | return NETDEV_TX_BUSY; |
2109 | } | |
1da177e4 LT |
2110 | |
2111 | /* Update transmit stats */ | |
1ac9ad13 ED |
2112 | tx_queue->stats.tx_bytes += skb->len; |
2113 | tx_queue->stats.tx_packets++; | |
1da177e4 | 2114 | |
a12f801d | 2115 | txbdp = txbdp_start = tx_queue->cur_tx; |
f0ee7acf MR |
2116 | lstatus = txbdp->lstatus; |
2117 | ||
2118 | /* Time stamp insertion requires one additional TxBD */ | |
2119 | if (unlikely(do_tstamp)) | |
2120 | txbdp_tstamp = txbdp = next_txbd(txbdp, base, | |
2121 | tx_queue->tx_ring_size); | |
1da177e4 | 2122 | |
4669bc90 | 2123 | if (nr_frags == 0) { |
f0ee7acf MR |
2124 | if (unlikely(do_tstamp)) |
2125 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | | |
2126 | TXBD_INTERRUPT); | |
2127 | else | |
2128 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
4669bc90 DH |
2129 | } else { |
2130 | /* Place the fragment addresses and lengths into the TxBDs */ | |
2131 | for (i = 0; i < nr_frags; i++) { | |
2132 | /* Point at the next BD, wrapping as needed */ | |
a12f801d | 2133 | txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2134 | |
2135 | length = skb_shinfo(skb)->frags[i].size; | |
2136 | ||
2137 | lstatus = txbdp->lstatus | length | | |
2138 | BD_LFLAG(TXBD_READY); | |
2139 | ||
2140 | /* Handle the last BD specially */ | |
2141 | if (i == nr_frags - 1) | |
2142 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 2143 | |
4826857f | 2144 | bufaddr = dma_map_page(&priv->ofdev->dev, |
4669bc90 DH |
2145 | skb_shinfo(skb)->frags[i].page, |
2146 | skb_shinfo(skb)->frags[i].page_offset, | |
2147 | length, | |
2148 | DMA_TO_DEVICE); | |
2149 | ||
2150 | /* set the TxBD length and buffer pointer */ | |
2151 | txbdp->bufPtr = bufaddr; | |
2152 | txbdp->lstatus = lstatus; | |
2153 | } | |
2154 | ||
2155 | lstatus = txbdp_start->lstatus; | |
2156 | } | |
1da177e4 | 2157 | |
0bbaf069 | 2158 | /* Set up checksumming */ |
12dea57b | 2159 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
54dc79fe | 2160 | fcb = gfar_add_fcb(skb); |
4363c2fd AD |
2161 | /* as specified by errata */ |
2162 | if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) | |
2163 | && ((unsigned long)fcb % 0x20) > 0x18)) { | |
2164 | __skb_pull(skb, GMAC_FCB_LEN); | |
2165 | skb_checksum_help(skb); | |
2166 | } else { | |
2167 | lstatus |= BD_LFLAG(TXBD_TOE); | |
2168 | gfar_tx_checksum(skb, fcb); | |
2169 | } | |
0bbaf069 KG |
2170 | } |
2171 | ||
eab6d18d | 2172 | if (vlan_tx_tag_present(skb)) { |
54dc79fe SH |
2173 | if (unlikely(NULL == fcb)) { |
2174 | fcb = gfar_add_fcb(skb); | |
5a5efed4 | 2175 | lstatus |= BD_LFLAG(TXBD_TOE); |
7f7f5316 | 2176 | } |
54dc79fe SH |
2177 | |
2178 | gfar_tx_vlan(skb, fcb); | |
0bbaf069 KG |
2179 | } |
2180 | ||
f0ee7acf MR |
2181 | /* Setup tx hardware time stamping if requested */ |
2182 | if (unlikely(do_tstamp)) { | |
2244d07b | 2183 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
f0ee7acf MR |
2184 | if (fcb == NULL) |
2185 | fcb = gfar_add_fcb(skb); | |
2186 | fcb->ptp = 1; | |
2187 | lstatus |= BD_LFLAG(TXBD_TOE); | |
2188 | } | |
2189 | ||
4826857f | 2190 | txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, |
4669bc90 | 2191 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 2192 | |
f0ee7acf MR |
2193 | /* |
2194 | * If time stamping is requested one additional TxBD must be set up. The | |
2195 | * first TxBD points to the FCB and must have a data length of | |
2196 | * GMAC_FCB_LEN. The second TxBD points to the actual frame data with | |
2197 | * the full frame length. | |
2198 | */ | |
2199 | if (unlikely(do_tstamp)) { | |
2200 | txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN; | |
2201 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | | |
2202 | (skb_headlen(skb) - GMAC_FCB_LEN); | |
2203 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; | |
2204 | } else { | |
2205 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); | |
2206 | } | |
1da177e4 | 2207 | |
a3bc1f11 AV |
2208 | /* |
2209 | * We can work in parallel with gfar_clean_tx_ring(), except | |
2210 | * when modifying num_txbdfree. Note that we didn't grab the lock | |
2211 | * when we were reading the num_txbdfree and checking for available | |
2212 | * space, that's because outside of this function it can only grow, | |
2213 | * and once we've got needed space, it cannot suddenly disappear. | |
2214 | * | |
2215 | * The lock also protects us from gfar_error(), which can modify | |
2216 | * regs->tstat and thus retrigger the transfers, which is why we | |
2217 | * also must grab the lock before setting ready bit for the first | |
2218 | * to be transmitted BD. | |
2219 | */ | |
2220 | spin_lock_irqsave(&tx_queue->txlock, flags); | |
2221 | ||
4669bc90 DH |
2222 | /* |
2223 | * The powerpc-specific eieio() is used, as wmb() has too strong | |
3b6330ce SW |
2224 | * semantics (it requires synchronization between cacheable and |
2225 | * uncacheable mappings, which eieio doesn't provide and which we | |
2226 | * don't need), thus requiring a more expensive sync instruction. At | |
2227 | * some point, the set of architecture-independent barrier functions | |
2228 | * should be expanded to include weaker barriers. | |
2229 | */ | |
3b6330ce | 2230 | eieio(); |
7f7f5316 | 2231 | |
4669bc90 DH |
2232 | txbdp_start->lstatus = lstatus; |
2233 | ||
0eddba52 AV |
2234 | eieio(); /* force lstatus write before tx_skbuff */ |
2235 | ||
2236 | tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; | |
2237 | ||
4669bc90 DH |
2238 | /* Update the current skb pointer to the next entry we will use |
2239 | * (wrapping if necessary) */ | |
a12f801d SG |
2240 | tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & |
2241 | TX_RING_MOD_MASK(tx_queue->tx_ring_size); | |
4669bc90 | 2242 | |
a12f801d | 2243 | tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2244 | |
2245 | /* reduce TxBD free count */ | |
f0ee7acf | 2246 | tx_queue->num_txbdfree -= (nr_txbds); |
1da177e4 LT |
2247 | |
2248 | /* If the next BD still needs to be cleaned up, then the bds | |
2249 | are full. We need to tell the kernel to stop sending us stuff. */ | |
a12f801d | 2250 | if (!tx_queue->num_txbdfree) { |
fba4ed03 | 2251 | netif_tx_stop_queue(txq); |
1da177e4 | 2252 | |
09f75cd7 | 2253 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
2254 | } |
2255 | ||
1da177e4 | 2256 | /* Tell the DMA to go go go */ |
fba4ed03 | 2257 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); |
1da177e4 LT |
2258 | |
2259 | /* Unlock priv */ | |
a12f801d | 2260 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
1da177e4 | 2261 | |
54dc79fe | 2262 | return NETDEV_TX_OK; |
1da177e4 LT |
2263 | } |
2264 | ||
2265 | /* Stops the kernel queue, and halts the controller */ | |
2266 | static int gfar_close(struct net_device *dev) | |
2267 | { | |
2268 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e | 2269 | |
46ceb60c | 2270 | disable_napi(priv); |
bea3348e | 2271 | |
ab939905 | 2272 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
2273 | stop_gfar(dev); |
2274 | ||
bb40dcbb AF |
2275 | /* Disconnect from the PHY */ |
2276 | phy_disconnect(priv->phydev); | |
2277 | priv->phydev = NULL; | |
1da177e4 | 2278 | |
fba4ed03 | 2279 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2280 | |
2281 | return 0; | |
2282 | } | |
2283 | ||
1da177e4 | 2284 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 2285 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 2286 | { |
7f7f5316 | 2287 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
2288 | |
2289 | return 0; | |
2290 | } | |
2291 | ||
f3dc1586 SP |
2292 | /* Check if rx parser should be activated */ |
2293 | void gfar_check_rx_parser_mode(struct gfar_private *priv) | |
2294 | { | |
2295 | struct gfar __iomem *regs; | |
2296 | u32 tempval; | |
2297 | ||
2298 | regs = priv->gfargrp[0].regs; | |
2299 | ||
2300 | tempval = gfar_read(®s->rctrl); | |
2301 | /* If parse is no longer required, then disable parser */ | |
2302 | if (tempval & RCTRL_REQ_PARSER) | |
2303 | tempval |= RCTRL_PRSDEP_INIT; | |
2304 | else | |
2305 | tempval &= ~RCTRL_PRSDEP_INIT; | |
2306 | gfar_write(®s->rctrl, tempval); | |
2307 | } | |
2308 | ||
1da177e4 | 2309 | |
0bbaf069 KG |
2310 | /* Enables and disables VLAN insertion/extraction */ |
2311 | static void gfar_vlan_rx_register(struct net_device *dev, | |
2312 | struct vlan_group *grp) | |
2313 | { | |
2314 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 2315 | struct gfar __iomem *regs = NULL; |
0bbaf069 KG |
2316 | unsigned long flags; |
2317 | u32 tempval; | |
2318 | ||
46ceb60c | 2319 | regs = priv->gfargrp[0].regs; |
fba4ed03 SG |
2320 | local_irq_save(flags); |
2321 | lock_rx_qs(priv); | |
0bbaf069 | 2322 | |
cd1f55a5 | 2323 | priv->vlgrp = grp; |
0bbaf069 KG |
2324 | |
2325 | if (grp) { | |
2326 | /* Enable VLAN tag insertion */ | |
f4983704 | 2327 | tempval = gfar_read(®s->tctrl); |
0bbaf069 KG |
2328 | tempval |= TCTRL_VLINS; |
2329 | ||
f4983704 | 2330 | gfar_write(®s->tctrl, tempval); |
6aa20a22 | 2331 | |
0bbaf069 | 2332 | /* Enable VLAN tag extraction */ |
f4983704 | 2333 | tempval = gfar_read(®s->rctrl); |
77ecaf2d | 2334 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); |
f4983704 | 2335 | gfar_write(®s->rctrl, tempval); |
0bbaf069 KG |
2336 | } else { |
2337 | /* Disable VLAN tag insertion */ | |
f4983704 | 2338 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2339 | tempval &= ~TCTRL_VLINS; |
f4983704 | 2340 | gfar_write(®s->tctrl, tempval); |
0bbaf069 KG |
2341 | |
2342 | /* Disable VLAN tag extraction */ | |
f4983704 | 2343 | tempval = gfar_read(®s->rctrl); |
0bbaf069 | 2344 | tempval &= ~RCTRL_VLEX; |
f4983704 | 2345 | gfar_write(®s->rctrl, tempval); |
f3dc1586 SP |
2346 | |
2347 | gfar_check_rx_parser_mode(priv); | |
0bbaf069 KG |
2348 | } |
2349 | ||
77ecaf2d DH |
2350 | gfar_change_mtu(dev, dev->mtu); |
2351 | ||
fba4ed03 SG |
2352 | unlock_rx_qs(priv); |
2353 | local_irq_restore(flags); | |
0bbaf069 KG |
2354 | } |
2355 | ||
1da177e4 LT |
2356 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
2357 | { | |
2358 | int tempsize, tempval; | |
2359 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2360 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 | 2361 | int oldsize = priv->rx_buffer_size; |
0bbaf069 KG |
2362 | int frame_size = new_mtu + ETH_HLEN; |
2363 | ||
77ecaf2d | 2364 | if (priv->vlgrp) |
faa89577 | 2365 | frame_size += VLAN_HLEN; |
0bbaf069 | 2366 | |
1da177e4 | 2367 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
0bbaf069 KG |
2368 | if (netif_msg_drv(priv)) |
2369 | printk(KERN_ERR "%s: Invalid MTU setting\n", | |
2370 | dev->name); | |
1da177e4 LT |
2371 | return -EINVAL; |
2372 | } | |
2373 | ||
77ecaf2d DH |
2374 | if (gfar_uses_fcb(priv)) |
2375 | frame_size += GMAC_FCB_LEN; | |
2376 | ||
2377 | frame_size += priv->padding; | |
2378 | ||
1da177e4 LT |
2379 | tempsize = |
2380 | (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + | |
2381 | INCREMENTAL_BUFFER_SIZE; | |
2382 | ||
2383 | /* Only stop and start the controller if it isn't already | |
7f7f5316 | 2384 | * stopped, and we changed something */ |
1da177e4 LT |
2385 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
2386 | stop_gfar(dev); | |
2387 | ||
2388 | priv->rx_buffer_size = tempsize; | |
2389 | ||
2390 | dev->mtu = new_mtu; | |
2391 | ||
f4983704 SG |
2392 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
2393 | gfar_write(®s->maxfrm, priv->rx_buffer_size); | |
1da177e4 LT |
2394 | |
2395 | /* If the mtu is larger than the max size for standard | |
2396 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
2397 | * to allow huge frames, and to check the length */ | |
f4983704 | 2398 | tempval = gfar_read(®s->maccfg2); |
1da177e4 | 2399 | |
7d350977 AV |
2400 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || |
2401 | gfar_has_errata(priv, GFAR_ERRATA_74)) | |
1da177e4 LT |
2402 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); |
2403 | else | |
2404 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
2405 | ||
f4983704 | 2406 | gfar_write(®s->maccfg2, tempval); |
1da177e4 LT |
2407 | |
2408 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
2409 | startup_gfar(dev); | |
2410 | ||
2411 | return 0; | |
2412 | } | |
2413 | ||
ab939905 | 2414 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
2415 | * transmitted after a set amount of time. |
2416 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
2417 | * starting over will fix the problem. |
2418 | */ | |
2419 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 2420 | { |
ab939905 SS |
2421 | struct gfar_private *priv = container_of(work, struct gfar_private, |
2422 | reset_task); | |
4826857f | 2423 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
2424 | |
2425 | if (dev->flags & IFF_UP) { | |
fba4ed03 | 2426 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2427 | stop_gfar(dev); |
2428 | startup_gfar(dev); | |
fba4ed03 | 2429 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
2430 | } |
2431 | ||
263ba320 | 2432 | netif_tx_schedule_all(dev); |
1da177e4 LT |
2433 | } |
2434 | ||
ab939905 SS |
2435 | static void gfar_timeout(struct net_device *dev) |
2436 | { | |
2437 | struct gfar_private *priv = netdev_priv(dev); | |
2438 | ||
2439 | dev->stats.tx_errors++; | |
2440 | schedule_work(&priv->reset_task); | |
2441 | } | |
2442 | ||
acbc0f03 EL |
2443 | static void gfar_align_skb(struct sk_buff *skb) |
2444 | { | |
2445 | /* We need the data buffer to be aligned properly. We will reserve | |
2446 | * as many bytes as needed to align the data properly | |
2447 | */ | |
2448 | skb_reserve(skb, RXBUF_ALIGNMENT - | |
2449 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); | |
2450 | } | |
2451 | ||
1da177e4 | 2452 | /* Interrupt Handler for Transmit complete */ |
a12f801d | 2453 | static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 2454 | { |
a12f801d | 2455 | struct net_device *dev = tx_queue->dev; |
d080cd63 | 2456 | struct gfar_private *priv = netdev_priv(dev); |
a12f801d | 2457 | struct gfar_priv_rx_q *rx_queue = NULL; |
f0ee7acf | 2458 | struct txbd8 *bdp, *next = NULL; |
4669bc90 | 2459 | struct txbd8 *lbdp = NULL; |
a12f801d | 2460 | struct txbd8 *base = tx_queue->tx_bd_base; |
4669bc90 DH |
2461 | struct sk_buff *skb; |
2462 | int skb_dirtytx; | |
a12f801d | 2463 | int tx_ring_size = tx_queue->tx_ring_size; |
f0ee7acf | 2464 | int frags = 0, nr_txbds = 0; |
4669bc90 | 2465 | int i; |
d080cd63 | 2466 | int howmany = 0; |
4669bc90 | 2467 | u32 lstatus; |
f0ee7acf | 2468 | size_t buflen; |
1da177e4 | 2469 | |
fba4ed03 | 2470 | rx_queue = priv->rx_queue[tx_queue->qindex]; |
a12f801d SG |
2471 | bdp = tx_queue->dirty_tx; |
2472 | skb_dirtytx = tx_queue->skb_dirtytx; | |
1da177e4 | 2473 | |
a12f801d | 2474 | while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { |
a3bc1f11 AV |
2475 | unsigned long flags; |
2476 | ||
4669bc90 | 2477 | frags = skb_shinfo(skb)->nr_frags; |
f0ee7acf MR |
2478 | |
2479 | /* | |
2480 | * When time stamping, one additional TxBD must be freed. | |
2481 | * Also, we need to dma_unmap_single() the TxPAL. | |
2482 | */ | |
2244d07b | 2483 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) |
f0ee7acf MR |
2484 | nr_txbds = frags + 2; |
2485 | else | |
2486 | nr_txbds = frags + 1; | |
2487 | ||
2488 | lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); | |
1da177e4 | 2489 | |
4669bc90 | 2490 | lstatus = lbdp->lstatus; |
1da177e4 | 2491 | |
4669bc90 DH |
2492 | /* Only clean completed frames */ |
2493 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
2494 | (lstatus & BD_LENGTH_MASK)) | |
2495 | break; | |
2496 | ||
2244d07b | 2497 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf MR |
2498 | next = next_txbd(bdp, base, tx_ring_size); |
2499 | buflen = next->length + GMAC_FCB_LEN; | |
2500 | } else | |
2501 | buflen = bdp->length; | |
2502 | ||
2503 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, | |
2504 | buflen, DMA_TO_DEVICE); | |
2505 | ||
2244d07b | 2506 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf MR |
2507 | struct skb_shared_hwtstamps shhwtstamps; |
2508 | u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); | |
2509 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
2510 | shhwtstamps.hwtstamp = ns_to_ktime(*ns); | |
2511 | skb_tstamp_tx(skb, &shhwtstamps); | |
2512 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
2513 | bdp = next; | |
2514 | } | |
81183059 | 2515 | |
4669bc90 DH |
2516 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2517 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 2518 | |
4669bc90 | 2519 | for (i = 0; i < frags; i++) { |
4826857f | 2520 | dma_unmap_page(&priv->ofdev->dev, |
4669bc90 DH |
2521 | bdp->bufPtr, |
2522 | bdp->length, | |
2523 | DMA_TO_DEVICE); | |
2524 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
2525 | bdp = next_txbd(bdp, base, tx_ring_size); | |
2526 | } | |
1da177e4 | 2527 | |
0fd56bb5 AF |
2528 | /* |
2529 | * If there's room in the queue (limit it to rx_buffer_size) | |
2530 | * we add this skb back into the pool, if it's the right size | |
2531 | */ | |
a12f801d | 2532 | if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size && |
0fd56bb5 | 2533 | skb_recycle_check(skb, priv->rx_buffer_size + |
acbc0f03 EL |
2534 | RXBUF_ALIGNMENT)) { |
2535 | gfar_align_skb(skb); | |
cd0ea241 | 2536 | skb_queue_head(&priv->rx_recycle, skb); |
acbc0f03 | 2537 | } else |
0fd56bb5 AF |
2538 | dev_kfree_skb_any(skb); |
2539 | ||
a12f801d | 2540 | tx_queue->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 2541 | |
4669bc90 DH |
2542 | skb_dirtytx = (skb_dirtytx + 1) & |
2543 | TX_RING_MOD_MASK(tx_ring_size); | |
2544 | ||
2545 | howmany++; | |
a3bc1f11 | 2546 | spin_lock_irqsave(&tx_queue->txlock, flags); |
f0ee7acf | 2547 | tx_queue->num_txbdfree += nr_txbds; |
a3bc1f11 | 2548 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
4669bc90 | 2549 | } |
1da177e4 | 2550 | |
4669bc90 | 2551 | /* If we freed a buffer, we can restart transmission, if necessary */ |
fba4ed03 SG |
2552 | if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree) |
2553 | netif_wake_subqueue(dev, tx_queue->qindex); | |
1da177e4 | 2554 | |
4669bc90 | 2555 | /* Update dirty indicators */ |
a12f801d SG |
2556 | tx_queue->skb_dirtytx = skb_dirtytx; |
2557 | tx_queue->dirty_tx = bdp; | |
1da177e4 | 2558 | |
d080cd63 DH |
2559 | return howmany; |
2560 | } | |
2561 | ||
f4983704 | 2562 | static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp) |
d080cd63 | 2563 | { |
a6d0b91a AV |
2564 | unsigned long flags; |
2565 | ||
fba4ed03 SG |
2566 | spin_lock_irqsave(&gfargrp->grplock, flags); |
2567 | if (napi_schedule_prep(&gfargrp->napi)) { | |
f4983704 | 2568 | gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); |
fba4ed03 | 2569 | __napi_schedule(&gfargrp->napi); |
8707bdd4 JP |
2570 | } else { |
2571 | /* | |
2572 | * Clear IEVENT, so interrupts aren't called again | |
2573 | * because of the packets that have already arrived. | |
2574 | */ | |
f4983704 | 2575 | gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); |
2f448911 | 2576 | } |
fba4ed03 | 2577 | spin_unlock_irqrestore(&gfargrp->grplock, flags); |
a6d0b91a | 2578 | |
8c7396ae | 2579 | } |
1da177e4 | 2580 | |
8c7396ae | 2581 | /* Interrupt Handler for Transmit complete */ |
f4983704 | 2582 | static irqreturn_t gfar_transmit(int irq, void *grp_id) |
8c7396ae | 2583 | { |
f4983704 | 2584 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2585 | return IRQ_HANDLED; |
2586 | } | |
2587 | ||
a12f801d | 2588 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
815b97c6 AF |
2589 | struct sk_buff *skb) |
2590 | { | |
a12f801d | 2591 | struct net_device *dev = rx_queue->dev; |
815b97c6 | 2592 | struct gfar_private *priv = netdev_priv(dev); |
8a102fe0 | 2593 | dma_addr_t buf; |
815b97c6 | 2594 | |
8a102fe0 AV |
2595 | buf = dma_map_single(&priv->ofdev->dev, skb->data, |
2596 | priv->rx_buffer_size, DMA_FROM_DEVICE); | |
a12f801d | 2597 | gfar_init_rxbdp(rx_queue, bdp, buf); |
815b97c6 AF |
2598 | } |
2599 | ||
acbc0f03 | 2600 | static struct sk_buff * gfar_alloc_skb(struct net_device *dev) |
1da177e4 LT |
2601 | { |
2602 | struct gfar_private *priv = netdev_priv(dev); | |
2603 | struct sk_buff *skb = NULL; | |
1da177e4 | 2604 | |
acbc0f03 | 2605 | skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); |
815b97c6 | 2606 | if (!skb) |
1da177e4 LT |
2607 | return NULL; |
2608 | ||
acbc0f03 | 2609 | gfar_align_skb(skb); |
7f7f5316 | 2610 | |
acbc0f03 EL |
2611 | return skb; |
2612 | } | |
2613 | ||
2614 | struct sk_buff * gfar_new_skb(struct net_device *dev) | |
2615 | { | |
2616 | struct gfar_private *priv = netdev_priv(dev); | |
2617 | struct sk_buff *skb = NULL; | |
2618 | ||
cd0ea241 | 2619 | skb = skb_dequeue(&priv->rx_recycle); |
acbc0f03 EL |
2620 | if (!skb) |
2621 | skb = gfar_alloc_skb(dev); | |
1da177e4 | 2622 | |
1da177e4 LT |
2623 | return skb; |
2624 | } | |
2625 | ||
298e1a9e | 2626 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 2627 | { |
298e1a9e | 2628 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 2629 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
2630 | struct gfar_extra_stats *estats = &priv->extra_stats; |
2631 | ||
2632 | /* If the packet was truncated, none of the other errors | |
2633 | * matter */ | |
2634 | if (status & RXBD_TRUNCATED) { | |
2635 | stats->rx_length_errors++; | |
2636 | ||
2637 | estats->rx_trunc++; | |
2638 | ||
2639 | return; | |
2640 | } | |
2641 | /* Count the errors, if there were any */ | |
2642 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
2643 | stats->rx_length_errors++; | |
2644 | ||
2645 | if (status & RXBD_LARGE) | |
2646 | estats->rx_large++; | |
2647 | else | |
2648 | estats->rx_short++; | |
2649 | } | |
2650 | if (status & RXBD_NONOCTET) { | |
2651 | stats->rx_frame_errors++; | |
2652 | estats->rx_nonoctet++; | |
2653 | } | |
2654 | if (status & RXBD_CRCERR) { | |
2655 | estats->rx_crcerr++; | |
2656 | stats->rx_crc_errors++; | |
2657 | } | |
2658 | if (status & RXBD_OVERRUN) { | |
2659 | estats->rx_overrun++; | |
2660 | stats->rx_crc_errors++; | |
2661 | } | |
2662 | } | |
2663 | ||
f4983704 | 2664 | irqreturn_t gfar_receive(int irq, void *grp_id) |
1da177e4 | 2665 | { |
f4983704 | 2666 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2667 | return IRQ_HANDLED; |
2668 | } | |
2669 | ||
0bbaf069 KG |
2670 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
2671 | { | |
2672 | /* If valid headers were found, and valid sums | |
2673 | * were verified, then we tell the kernel that no | |
2674 | * checksumming is necessary. Otherwise, it is */ | |
7f7f5316 | 2675 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
2676 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2677 | else | |
bc8acf2c | 2678 | skb_checksum_none_assert(skb); |
0bbaf069 KG |
2679 | } |
2680 | ||
2681 | ||
1da177e4 LT |
2682 | /* gfar_process_frame() -- handle one incoming packet if skb |
2683 | * isn't NULL. */ | |
2684 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, | |
2c2db48a | 2685 | int amount_pull) |
1da177e4 LT |
2686 | { |
2687 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 2688 | struct rxfcb *fcb = NULL; |
1da177e4 | 2689 | |
2c2db48a | 2690 | int ret; |
1da177e4 | 2691 | |
2c2db48a DH |
2692 | /* fcb is at the beginning if exists */ |
2693 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 2694 | |
2c2db48a DH |
2695 | /* Remove the FCB from the skb */ |
2696 | /* Remove the padded bytes, if there are any */ | |
f74dac08 SG |
2697 | if (amount_pull) { |
2698 | skb_record_rx_queue(skb, fcb->rq); | |
2c2db48a | 2699 | skb_pull(skb, amount_pull); |
f74dac08 | 2700 | } |
0bbaf069 | 2701 | |
cc772ab7 MR |
2702 | /* Get receive timestamp from the skb */ |
2703 | if (priv->hwts_rx_en) { | |
2704 | struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); | |
2705 | u64 *ns = (u64 *) skb->data; | |
2706 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
2707 | shhwtstamps->hwtstamp = ns_to_ktime(*ns); | |
2708 | } | |
2709 | ||
2710 | if (priv->padding) | |
2711 | skb_pull(skb, priv->padding); | |
2712 | ||
8b3afe95 | 2713 | if (dev->features & NETIF_F_RXCSUM) |
2c2db48a | 2714 | gfar_rx_checksum(skb, fcb); |
0bbaf069 | 2715 | |
2c2db48a DH |
2716 | /* Tell the skb what kind of packet this is */ |
2717 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 2718 | |
2c2db48a DH |
2719 | /* Send the packet up the stack */ |
2720 | if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) | |
2721 | ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl); | |
2722 | else | |
2723 | ret = netif_receive_skb(skb); | |
0bbaf069 | 2724 | |
2c2db48a DH |
2725 | if (NET_RX_DROP == ret) |
2726 | priv->extra_stats.kernel_dropped++; | |
1da177e4 LT |
2727 | |
2728 | return 0; | |
2729 | } | |
2730 | ||
2731 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
0bbaf069 | 2732 | * until the budget/quota has been reached. Returns the number |
1da177e4 LT |
2733 | * of frames handled |
2734 | */ | |
a12f801d | 2735 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) |
1da177e4 | 2736 | { |
a12f801d | 2737 | struct net_device *dev = rx_queue->dev; |
31de198b | 2738 | struct rxbd8 *bdp, *base; |
1da177e4 | 2739 | struct sk_buff *skb; |
2c2db48a DH |
2740 | int pkt_len; |
2741 | int amount_pull; | |
1da177e4 LT |
2742 | int howmany = 0; |
2743 | struct gfar_private *priv = netdev_priv(dev); | |
2744 | ||
2745 | /* Get the first full descriptor */ | |
a12f801d SG |
2746 | bdp = rx_queue->cur_rx; |
2747 | base = rx_queue->rx_bd_base; | |
1da177e4 | 2748 | |
cc772ab7 | 2749 | amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0); |
2c2db48a | 2750 | |
1da177e4 | 2751 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 2752 | struct sk_buff *newskb; |
3b6330ce | 2753 | rmb(); |
815b97c6 AF |
2754 | |
2755 | /* Add another skb for the future */ | |
2756 | newskb = gfar_new_skb(dev); | |
2757 | ||
a12f801d | 2758 | skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; |
1da177e4 | 2759 | |
4826857f | 2760 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, |
81183059 AF |
2761 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
2762 | ||
63b88b90 AV |
2763 | if (unlikely(!(bdp->status & RXBD_ERR) && |
2764 | bdp->length > priv->rx_buffer_size)) | |
2765 | bdp->status = RXBD_LARGE; | |
2766 | ||
815b97c6 AF |
2767 | /* We drop the frame if we failed to allocate a new buffer */ |
2768 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
2769 | bdp->status & RXBD_ERR)) { | |
2770 | count_errors(bdp->status, dev); | |
2771 | ||
2772 | if (unlikely(!newskb)) | |
2773 | newskb = skb; | |
acbc0f03 | 2774 | else if (skb) |
cd0ea241 | 2775 | skb_queue_head(&priv->rx_recycle, skb); |
815b97c6 | 2776 | } else { |
1da177e4 | 2777 | /* Increment the number of packets */ |
a7f38041 | 2778 | rx_queue->stats.rx_packets++; |
1da177e4 LT |
2779 | howmany++; |
2780 | ||
2c2db48a DH |
2781 | if (likely(skb)) { |
2782 | pkt_len = bdp->length - ETH_FCS_LEN; | |
2783 | /* Remove the FCS from the packet length */ | |
2784 | skb_put(skb, pkt_len); | |
a7f38041 | 2785 | rx_queue->stats.rx_bytes += pkt_len; |
f74dac08 | 2786 | skb_record_rx_queue(skb, rx_queue->qindex); |
2c2db48a DH |
2787 | gfar_process_frame(dev, skb, amount_pull); |
2788 | ||
2789 | } else { | |
2790 | if (netif_msg_rx_err(priv)) | |
2791 | printk(KERN_WARNING | |
2792 | "%s: Missing skb!\n", dev->name); | |
a7f38041 | 2793 | rx_queue->stats.rx_dropped++; |
2c2db48a DH |
2794 | priv->extra_stats.rx_skbmissing++; |
2795 | } | |
1da177e4 | 2796 | |
1da177e4 LT |
2797 | } |
2798 | ||
a12f801d | 2799 | rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; |
1da177e4 | 2800 | |
815b97c6 | 2801 | /* Setup the new bdp */ |
a12f801d | 2802 | gfar_new_rxbdp(rx_queue, bdp, newskb); |
1da177e4 LT |
2803 | |
2804 | /* Update to the next pointer */ | |
a12f801d | 2805 | bdp = next_bd(bdp, base, rx_queue->rx_ring_size); |
1da177e4 LT |
2806 | |
2807 | /* update to point at the next skb */ | |
a12f801d SG |
2808 | rx_queue->skb_currx = |
2809 | (rx_queue->skb_currx + 1) & | |
2810 | RX_RING_MOD_MASK(rx_queue->rx_ring_size); | |
1da177e4 LT |
2811 | } |
2812 | ||
2813 | /* Update the current rxbd pointer to be the next one */ | |
a12f801d | 2814 | rx_queue->cur_rx = bdp; |
1da177e4 | 2815 | |
1da177e4 LT |
2816 | return howmany; |
2817 | } | |
2818 | ||
bea3348e | 2819 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 2820 | { |
fba4ed03 SG |
2821 | struct gfar_priv_grp *gfargrp = container_of(napi, |
2822 | struct gfar_priv_grp, napi); | |
2823 | struct gfar_private *priv = gfargrp->priv; | |
46ceb60c | 2824 | struct gfar __iomem *regs = gfargrp->regs; |
a12f801d | 2825 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 SG |
2826 | struct gfar_priv_rx_q *rx_queue = NULL; |
2827 | int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0; | |
18294ad1 AV |
2828 | int tx_cleaned = 0, i, left_over_budget = budget; |
2829 | unsigned long serviced_queues = 0; | |
fba4ed03 | 2830 | int num_queues = 0; |
d080cd63 | 2831 | |
fba4ed03 SG |
2832 | num_queues = gfargrp->num_rx_queues; |
2833 | budget_per_queue = budget/num_queues; | |
2834 | ||
8c7396ae DH |
2835 | /* Clear IEVENT, so interrupts aren't called again |
2836 | * because of the packets that have already arrived */ | |
f4983704 | 2837 | gfar_write(®s->ievent, IEVENT_RTX_MASK); |
8c7396ae | 2838 | |
fba4ed03 | 2839 | while (num_queues && left_over_budget) { |
1da177e4 | 2840 | |
fba4ed03 SG |
2841 | budget_per_queue = left_over_budget/num_queues; |
2842 | left_over_budget = 0; | |
2843 | ||
984b3f57 | 2844 | for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { |
fba4ed03 SG |
2845 | if (test_bit(i, &serviced_queues)) |
2846 | continue; | |
2847 | rx_queue = priv->rx_queue[i]; | |
2848 | tx_queue = priv->tx_queue[rx_queue->qindex]; | |
2849 | ||
a3bc1f11 | 2850 | tx_cleaned += gfar_clean_tx_ring(tx_queue); |
fba4ed03 SG |
2851 | rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue, |
2852 | budget_per_queue); | |
2853 | rx_cleaned += rx_cleaned_per_queue; | |
2854 | if(rx_cleaned_per_queue < budget_per_queue) { | |
2855 | left_over_budget = left_over_budget + | |
2856 | (budget_per_queue - rx_cleaned_per_queue); | |
2857 | set_bit(i, &serviced_queues); | |
2858 | num_queues--; | |
2859 | } | |
2860 | } | |
2861 | } | |
1da177e4 | 2862 | |
42199884 AF |
2863 | if (tx_cleaned) |
2864 | return budget; | |
2865 | ||
2866 | if (rx_cleaned < budget) { | |
288379f0 | 2867 | napi_complete(napi); |
1da177e4 LT |
2868 | |
2869 | /* Clear the halt bit in RSTAT */ | |
fba4ed03 | 2870 | gfar_write(®s->rstat, gfargrp->rstat); |
1da177e4 | 2871 | |
f4983704 | 2872 | gfar_write(®s->imask, IMASK_DEFAULT); |
1da177e4 LT |
2873 | |
2874 | /* If we are coalescing interrupts, update the timer */ | |
2875 | /* Otherwise, clear it */ | |
46ceb60c SG |
2876 | gfar_configure_coalescing(priv, |
2877 | gfargrp->rx_bit_map, gfargrp->tx_bit_map); | |
1da177e4 LT |
2878 | } |
2879 | ||
42199884 | 2880 | return rx_cleaned; |
1da177e4 | 2881 | } |
1da177e4 | 2882 | |
f2d71c2d VW |
2883 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2884 | /* | |
2885 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
2886 | * without having to re-enable interrupts. It's not called while | |
2887 | * the interrupt routine is executing. | |
2888 | */ | |
2889 | static void gfar_netpoll(struct net_device *dev) | |
2890 | { | |
2891 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2892 | int i = 0; |
f2d71c2d VW |
2893 | |
2894 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 2895 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
2896 | for (i = 0; i < priv->num_grps; i++) { |
2897 | disable_irq(priv->gfargrp[i].interruptTransmit); | |
2898 | disable_irq(priv->gfargrp[i].interruptReceive); | |
2899 | disable_irq(priv->gfargrp[i].interruptError); | |
2900 | gfar_interrupt(priv->gfargrp[i].interruptTransmit, | |
2901 | &priv->gfargrp[i]); | |
2902 | enable_irq(priv->gfargrp[i].interruptError); | |
2903 | enable_irq(priv->gfargrp[i].interruptReceive); | |
2904 | enable_irq(priv->gfargrp[i].interruptTransmit); | |
2905 | } | |
f2d71c2d | 2906 | } else { |
46ceb60c SG |
2907 | for (i = 0; i < priv->num_grps; i++) { |
2908 | disable_irq(priv->gfargrp[i].interruptTransmit); | |
2909 | gfar_interrupt(priv->gfargrp[i].interruptTransmit, | |
2910 | &priv->gfargrp[i]); | |
2911 | enable_irq(priv->gfargrp[i].interruptTransmit); | |
43de004b | 2912 | } |
f2d71c2d VW |
2913 | } |
2914 | } | |
2915 | #endif | |
2916 | ||
1da177e4 | 2917 | /* The interrupt handler for devices with one interrupt */ |
f4983704 | 2918 | static irqreturn_t gfar_interrupt(int irq, void *grp_id) |
1da177e4 | 2919 | { |
f4983704 | 2920 | struct gfar_priv_grp *gfargrp = grp_id; |
1da177e4 LT |
2921 | |
2922 | /* Save ievent for future reference */ | |
f4983704 | 2923 | u32 events = gfar_read(&gfargrp->regs->ievent); |
1da177e4 | 2924 | |
1da177e4 | 2925 | /* Check for reception */ |
538cc7ee | 2926 | if (events & IEVENT_RX_MASK) |
f4983704 | 2927 | gfar_receive(irq, grp_id); |
1da177e4 LT |
2928 | |
2929 | /* Check for transmit completion */ | |
538cc7ee | 2930 | if (events & IEVENT_TX_MASK) |
f4983704 | 2931 | gfar_transmit(irq, grp_id); |
1da177e4 | 2932 | |
538cc7ee SS |
2933 | /* Check for errors */ |
2934 | if (events & IEVENT_ERR_MASK) | |
f4983704 | 2935 | gfar_error(irq, grp_id); |
1da177e4 LT |
2936 | |
2937 | return IRQ_HANDLED; | |
2938 | } | |
2939 | ||
1da177e4 LT |
2940 | /* Called every time the controller might need to be made |
2941 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 2942 | * information through variables in the phydev structure, and this |
1da177e4 LT |
2943 | * function converts those variables into the appropriate |
2944 | * register values, and can bring down the device if needed. | |
2945 | */ | |
2946 | static void adjust_link(struct net_device *dev) | |
2947 | { | |
2948 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2949 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
bb40dcbb AF |
2950 | unsigned long flags; |
2951 | struct phy_device *phydev = priv->phydev; | |
2952 | int new_state = 0; | |
2953 | ||
fba4ed03 SG |
2954 | local_irq_save(flags); |
2955 | lock_tx_qs(priv); | |
2956 | ||
bb40dcbb AF |
2957 | if (phydev->link) { |
2958 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 2959 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 2960 | |
1da177e4 LT |
2961 | /* Now we make sure that we can be in full duplex mode. |
2962 | * If not, we operate in half-duplex mode. */ | |
bb40dcbb AF |
2963 | if (phydev->duplex != priv->oldduplex) { |
2964 | new_state = 1; | |
2965 | if (!(phydev->duplex)) | |
1da177e4 | 2966 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 2967 | else |
1da177e4 | 2968 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 2969 | |
bb40dcbb | 2970 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
2971 | } |
2972 | ||
bb40dcbb AF |
2973 | if (phydev->speed != priv->oldspeed) { |
2974 | new_state = 1; | |
2975 | switch (phydev->speed) { | |
1da177e4 | 2976 | case 1000: |
1da177e4 LT |
2977 | tempval = |
2978 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
2979 | |
2980 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2981 | break; |
2982 | case 100: | |
2983 | case 10: | |
1da177e4 LT |
2984 | tempval = |
2985 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
2986 | |
2987 | /* Reduced mode distinguishes | |
2988 | * between 10 and 100 */ | |
2989 | if (phydev->speed == SPEED_100) | |
2990 | ecntrl |= ECNTRL_R100; | |
2991 | else | |
2992 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2993 | break; |
2994 | default: | |
0bbaf069 KG |
2995 | if (netif_msg_link(priv)) |
2996 | printk(KERN_WARNING | |
bb40dcbb AF |
2997 | "%s: Ack! Speed (%d) is not 10/100/1000!\n", |
2998 | dev->name, phydev->speed); | |
1da177e4 LT |
2999 | break; |
3000 | } | |
3001 | ||
bb40dcbb | 3002 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
3003 | } |
3004 | ||
bb40dcbb | 3005 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 3006 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 3007 | |
1da177e4 | 3008 | if (!priv->oldlink) { |
bb40dcbb | 3009 | new_state = 1; |
1da177e4 | 3010 | priv->oldlink = 1; |
1da177e4 | 3011 | } |
bb40dcbb AF |
3012 | } else if (priv->oldlink) { |
3013 | new_state = 1; | |
3014 | priv->oldlink = 0; | |
3015 | priv->oldspeed = 0; | |
3016 | priv->oldduplex = -1; | |
1da177e4 | 3017 | } |
1da177e4 | 3018 | |
bb40dcbb AF |
3019 | if (new_state && netif_msg_link(priv)) |
3020 | phy_print_status(phydev); | |
fba4ed03 SG |
3021 | unlock_tx_qs(priv); |
3022 | local_irq_restore(flags); | |
bb40dcbb | 3023 | } |
1da177e4 LT |
3024 | |
3025 | /* Update the hash table based on the current list of multicast | |
3026 | * addresses we subscribe to. Also, change the promiscuity of | |
3027 | * the device based on the flags (this function is called | |
3028 | * whenever dev->flags is changed */ | |
3029 | static void gfar_set_multi(struct net_device *dev) | |
3030 | { | |
22bedad3 | 3031 | struct netdev_hw_addr *ha; |
1da177e4 | 3032 | struct gfar_private *priv = netdev_priv(dev); |
46ceb60c | 3033 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 LT |
3034 | u32 tempval; |
3035 | ||
a12f801d | 3036 | if (dev->flags & IFF_PROMISC) { |
1da177e4 LT |
3037 | /* Set RCTRL to PROM */ |
3038 | tempval = gfar_read(®s->rctrl); | |
3039 | tempval |= RCTRL_PROM; | |
3040 | gfar_write(®s->rctrl, tempval); | |
3041 | } else { | |
3042 | /* Set RCTRL to not PROM */ | |
3043 | tempval = gfar_read(®s->rctrl); | |
3044 | tempval &= ~(RCTRL_PROM); | |
3045 | gfar_write(®s->rctrl, tempval); | |
3046 | } | |
6aa20a22 | 3047 | |
a12f801d | 3048 | if (dev->flags & IFF_ALLMULTI) { |
1da177e4 | 3049 | /* Set the hash to rx all multicast frames */ |
0bbaf069 KG |
3050 | gfar_write(®s->igaddr0, 0xffffffff); |
3051 | gfar_write(®s->igaddr1, 0xffffffff); | |
3052 | gfar_write(®s->igaddr2, 0xffffffff); | |
3053 | gfar_write(®s->igaddr3, 0xffffffff); | |
3054 | gfar_write(®s->igaddr4, 0xffffffff); | |
3055 | gfar_write(®s->igaddr5, 0xffffffff); | |
3056 | gfar_write(®s->igaddr6, 0xffffffff); | |
3057 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
3058 | gfar_write(®s->gaddr0, 0xffffffff); |
3059 | gfar_write(®s->gaddr1, 0xffffffff); | |
3060 | gfar_write(®s->gaddr2, 0xffffffff); | |
3061 | gfar_write(®s->gaddr3, 0xffffffff); | |
3062 | gfar_write(®s->gaddr4, 0xffffffff); | |
3063 | gfar_write(®s->gaddr5, 0xffffffff); | |
3064 | gfar_write(®s->gaddr6, 0xffffffff); | |
3065 | gfar_write(®s->gaddr7, 0xffffffff); | |
3066 | } else { | |
7f7f5316 AF |
3067 | int em_num; |
3068 | int idx; | |
3069 | ||
1da177e4 | 3070 | /* zero out the hash */ |
0bbaf069 KG |
3071 | gfar_write(®s->igaddr0, 0x0); |
3072 | gfar_write(®s->igaddr1, 0x0); | |
3073 | gfar_write(®s->igaddr2, 0x0); | |
3074 | gfar_write(®s->igaddr3, 0x0); | |
3075 | gfar_write(®s->igaddr4, 0x0); | |
3076 | gfar_write(®s->igaddr5, 0x0); | |
3077 | gfar_write(®s->igaddr6, 0x0); | |
3078 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
3079 | gfar_write(®s->gaddr0, 0x0); |
3080 | gfar_write(®s->gaddr1, 0x0); | |
3081 | gfar_write(®s->gaddr2, 0x0); | |
3082 | gfar_write(®s->gaddr3, 0x0); | |
3083 | gfar_write(®s->gaddr4, 0x0); | |
3084 | gfar_write(®s->gaddr5, 0x0); | |
3085 | gfar_write(®s->gaddr6, 0x0); | |
3086 | gfar_write(®s->gaddr7, 0x0); | |
3087 | ||
7f7f5316 AF |
3088 | /* If we have extended hash tables, we need to |
3089 | * clear the exact match registers to prepare for | |
3090 | * setting them */ | |
3091 | if (priv->extended_hash) { | |
3092 | em_num = GFAR_EM_NUM + 1; | |
3093 | gfar_clear_exact_match(dev); | |
3094 | idx = 1; | |
3095 | } else { | |
3096 | idx = 0; | |
3097 | em_num = 0; | |
3098 | } | |
3099 | ||
4cd24eaf | 3100 | if (netdev_mc_empty(dev)) |
1da177e4 LT |
3101 | return; |
3102 | ||
3103 | /* Parse the list, and set the appropriate bits */ | |
22bedad3 | 3104 | netdev_for_each_mc_addr(ha, dev) { |
7f7f5316 | 3105 | if (idx < em_num) { |
22bedad3 | 3106 | gfar_set_mac_for_addr(dev, idx, ha->addr); |
7f7f5316 AF |
3107 | idx++; |
3108 | } else | |
22bedad3 | 3109 | gfar_set_hash_for_addr(dev, ha->addr); |
1da177e4 LT |
3110 | } |
3111 | } | |
1da177e4 LT |
3112 | } |
3113 | ||
7f7f5316 AF |
3114 | |
3115 | /* Clears each of the exact match registers to zero, so they | |
3116 | * don't interfere with normal reception */ | |
3117 | static void gfar_clear_exact_match(struct net_device *dev) | |
3118 | { | |
3119 | int idx; | |
b6bc7650 | 3120 | static const u8 zero_arr[MAC_ADDR_LEN] = {0, 0, 0, 0, 0, 0}; |
7f7f5316 AF |
3121 | |
3122 | for(idx = 1;idx < GFAR_EM_NUM + 1;idx++) | |
b6bc7650 | 3123 | gfar_set_mac_for_addr(dev, idx, zero_arr); |
7f7f5316 AF |
3124 | } |
3125 | ||
1da177e4 LT |
3126 | /* Set the appropriate hash bit for the given addr */ |
3127 | /* The algorithm works like so: | |
3128 | * 1) Take the Destination Address (ie the multicast address), and | |
3129 | * do a CRC on it (little endian), and reverse the bits of the | |
3130 | * result. | |
3131 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
3132 | * table. The table is controlled through 8 32-bit registers: | |
3133 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
3134 | * gaddr7. This means that the 3 most significant bits in the | |
3135 | * hash index which gaddr register to use, and the 5 other bits | |
3136 | * indicate which bit (assuming an IBM numbering scheme, which | |
3137 | * for PowerPC (tm) is usually the case) in the register holds | |
3138 | * the entry. */ | |
3139 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) | |
3140 | { | |
3141 | u32 tempval; | |
3142 | struct gfar_private *priv = netdev_priv(dev); | |
1da177e4 | 3143 | u32 result = ether_crc(MAC_ADDR_LEN, addr); |
0bbaf069 KG |
3144 | int width = priv->hash_width; |
3145 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
3146 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
3147 | u32 value = (1 << (31-whichbit)); |
3148 | ||
0bbaf069 | 3149 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 3150 | tempval |= value; |
0bbaf069 | 3151 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
3152 | } |
3153 | ||
7f7f5316 AF |
3154 | |
3155 | /* There are multiple MAC Address register pairs on some controllers | |
3156 | * This function sets the numth pair to a given address | |
3157 | */ | |
b6bc7650 JP |
3158 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
3159 | const u8 *addr) | |
7f7f5316 AF |
3160 | { |
3161 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3162 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
7f7f5316 AF |
3163 | int idx; |
3164 | char tmpbuf[MAC_ADDR_LEN]; | |
3165 | u32 tempval; | |
f4983704 | 3166 | u32 __iomem *macptr = ®s->macstnaddr1; |
7f7f5316 AF |
3167 | |
3168 | macptr += num*2; | |
3169 | ||
3170 | /* Now copy it into the mac registers backwards, cuz */ | |
3171 | /* little endian is silly */ | |
3172 | for (idx = 0; idx < MAC_ADDR_LEN; idx++) | |
3173 | tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx]; | |
3174 | ||
3175 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
3176 | ||
3177 | tempval = *((u32 *) (tmpbuf + 4)); | |
3178 | ||
3179 | gfar_write(macptr+1, tempval); | |
3180 | } | |
3181 | ||
1da177e4 | 3182 | /* GFAR error interrupt handler */ |
f4983704 | 3183 | static irqreturn_t gfar_error(int irq, void *grp_id) |
1da177e4 | 3184 | { |
f4983704 SG |
3185 | struct gfar_priv_grp *gfargrp = grp_id; |
3186 | struct gfar __iomem *regs = gfargrp->regs; | |
3187 | struct gfar_private *priv= gfargrp->priv; | |
3188 | struct net_device *dev = priv->ndev; | |
1da177e4 LT |
3189 | |
3190 | /* Save ievent for future reference */ | |
f4983704 | 3191 | u32 events = gfar_read(®s->ievent); |
1da177e4 LT |
3192 | |
3193 | /* Clear IEVENT */ | |
f4983704 | 3194 | gfar_write(®s->ievent, events & IEVENT_ERR_MASK); |
d87eb127 SW |
3195 | |
3196 | /* Magic Packet is not an error. */ | |
b31a1d8b | 3197 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
3198 | (events & IEVENT_MAG)) |
3199 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
3200 | |
3201 | /* Hmm... */ | |
0bbaf069 KG |
3202 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
3203 | printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
f4983704 | 3204 | dev->name, events, gfar_read(®s->imask)); |
1da177e4 LT |
3205 | |
3206 | /* Update the error counters */ | |
3207 | if (events & IEVENT_TXE) { | |
09f75cd7 | 3208 | dev->stats.tx_errors++; |
1da177e4 LT |
3209 | |
3210 | if (events & IEVENT_LC) | |
09f75cd7 | 3211 | dev->stats.tx_window_errors++; |
1da177e4 | 3212 | if (events & IEVENT_CRL) |
09f75cd7 | 3213 | dev->stats.tx_aborted_errors++; |
1da177e4 | 3214 | if (events & IEVENT_XFUN) { |
836cf7fa AV |
3215 | unsigned long flags; |
3216 | ||
0bbaf069 | 3217 | if (netif_msg_tx_err(priv)) |
538cc7ee SS |
3218 | printk(KERN_DEBUG "%s: TX FIFO underrun, " |
3219 | "packet dropped.\n", dev->name); | |
09f75cd7 | 3220 | dev->stats.tx_dropped++; |
1da177e4 LT |
3221 | priv->extra_stats.tx_underrun++; |
3222 | ||
836cf7fa AV |
3223 | local_irq_save(flags); |
3224 | lock_tx_qs(priv); | |
3225 | ||
1da177e4 | 3226 | /* Reactivate the Tx Queues */ |
fba4ed03 | 3227 | gfar_write(®s->tstat, gfargrp->tstat); |
836cf7fa AV |
3228 | |
3229 | unlock_tx_qs(priv); | |
3230 | local_irq_restore(flags); | |
1da177e4 | 3231 | } |
0bbaf069 KG |
3232 | if (netif_msg_tx_err(priv)) |
3233 | printk(KERN_DEBUG "%s: Transmit Error\n", dev->name); | |
1da177e4 LT |
3234 | } |
3235 | if (events & IEVENT_BSY) { | |
09f75cd7 | 3236 | dev->stats.rx_errors++; |
1da177e4 LT |
3237 | priv->extra_stats.rx_bsy++; |
3238 | ||
f4983704 | 3239 | gfar_receive(irq, grp_id); |
1da177e4 | 3240 | |
0bbaf069 | 3241 | if (netif_msg_rx_err(priv)) |
538cc7ee | 3242 | printk(KERN_DEBUG "%s: busy error (rstat: %x)\n", |
f4983704 | 3243 | dev->name, gfar_read(®s->rstat)); |
1da177e4 LT |
3244 | } |
3245 | if (events & IEVENT_BABR) { | |
09f75cd7 | 3246 | dev->stats.rx_errors++; |
1da177e4 LT |
3247 | priv->extra_stats.rx_babr++; |
3248 | ||
0bbaf069 | 3249 | if (netif_msg_rx_err(priv)) |
538cc7ee | 3250 | printk(KERN_DEBUG "%s: babbling RX error\n", dev->name); |
1da177e4 LT |
3251 | } |
3252 | if (events & IEVENT_EBERR) { | |
3253 | priv->extra_stats.eberr++; | |
0bbaf069 | 3254 | if (netif_msg_rx_err(priv)) |
538cc7ee | 3255 | printk(KERN_DEBUG "%s: bus error\n", dev->name); |
1da177e4 | 3256 | } |
0bbaf069 | 3257 | if ((events & IEVENT_RXC) && netif_msg_rx_status(priv)) |
538cc7ee | 3258 | printk(KERN_DEBUG "%s: control frame\n", dev->name); |
1da177e4 LT |
3259 | |
3260 | if (events & IEVENT_BABT) { | |
3261 | priv->extra_stats.tx_babt++; | |
0bbaf069 | 3262 | if (netif_msg_tx_err(priv)) |
538cc7ee | 3263 | printk(KERN_DEBUG "%s: babbling TX error\n", dev->name); |
1da177e4 LT |
3264 | } |
3265 | return IRQ_HANDLED; | |
3266 | } | |
3267 | ||
b31a1d8b AF |
3268 | static struct of_device_id gfar_match[] = |
3269 | { | |
3270 | { | |
3271 | .type = "network", | |
3272 | .compatible = "gianfar", | |
3273 | }, | |
46ceb60c SG |
3274 | { |
3275 | .compatible = "fsl,etsec2", | |
3276 | }, | |
b31a1d8b AF |
3277 | {}, |
3278 | }; | |
e72701ac | 3279 | MODULE_DEVICE_TABLE(of, gfar_match); |
b31a1d8b | 3280 | |
1da177e4 | 3281 | /* Structure for a device driver */ |
74888760 | 3282 | static struct platform_driver gfar_driver = { |
4018294b GL |
3283 | .driver = { |
3284 | .name = "fsl-gianfar", | |
3285 | .owner = THIS_MODULE, | |
3286 | .pm = GFAR_PM_OPS, | |
3287 | .of_match_table = gfar_match, | |
3288 | }, | |
1da177e4 LT |
3289 | .probe = gfar_probe, |
3290 | .remove = gfar_remove, | |
3291 | }; | |
3292 | ||
3293 | static int __init gfar_init(void) | |
3294 | { | |
74888760 | 3295 | return platform_driver_register(&gfar_driver); |
1da177e4 LT |
3296 | } |
3297 | ||
3298 | static void __exit gfar_exit(void) | |
3299 | { | |
74888760 | 3300 | platform_driver_unregister(&gfar_driver); |
1da177e4 LT |
3301 | } |
3302 | ||
3303 | module_init(gfar_init); | |
3304 | module_exit(gfar_exit); | |
3305 |