Commit | Line | Data |
---|---|---|
0bbaf069 | 1 | /* |
1da177e4 LT |
2 | * drivers/net/gianfar.c |
3 | * | |
4 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
5 | * This driver is designed for the non-CPM ethernet controllers |
6 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
7 | * Based on 8260_io/fcc_enet.c |
8 | * | |
9 | * Author: Andy Fleming | |
4c8d3d99 | 10 | * Maintainer: Kumar Gala |
1da177e4 | 11 | * |
e8a2b6a4 | 12 | * Copyright (c) 2002-2006 Freescale Semiconductor, Inc. |
538cc7ee | 13 | * Copyright (c) 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
1da177e4 | 64 | #include <linux/kernel.h> |
1da177e4 LT |
65 | #include <linux/string.h> |
66 | #include <linux/errno.h> | |
bb40dcbb | 67 | #include <linux/unistd.h> |
1da177e4 LT |
68 | #include <linux/slab.h> |
69 | #include <linux/interrupt.h> | |
70 | #include <linux/init.h> | |
71 | #include <linux/delay.h> | |
72 | #include <linux/netdevice.h> | |
73 | #include <linux/etherdevice.h> | |
74 | #include <linux/skbuff.h> | |
0bbaf069 | 75 | #include <linux/if_vlan.h> |
1da177e4 LT |
76 | #include <linux/spinlock.h> |
77 | #include <linux/mm.h> | |
b31a1d8b | 78 | #include <linux/of_platform.h> |
0bbaf069 KG |
79 | #include <linux/ip.h> |
80 | #include <linux/tcp.h> | |
81 | #include <linux/udp.h> | |
9c07b884 | 82 | #include <linux/in.h> |
1da177e4 LT |
83 | |
84 | #include <asm/io.h> | |
85 | #include <asm/irq.h> | |
86 | #include <asm/uaccess.h> | |
87 | #include <linux/module.h> | |
1da177e4 LT |
88 | #include <linux/dma-mapping.h> |
89 | #include <linux/crc32.h> | |
bb40dcbb AF |
90 | #include <linux/mii.h> |
91 | #include <linux/phy.h> | |
b31a1d8b AF |
92 | #include <linux/phy_fixed.h> |
93 | #include <linux/of.h> | |
1da177e4 LT |
94 | |
95 | #include "gianfar.h" | |
1577ecef | 96 | #include "fsl_pq_mdio.h" |
1da177e4 LT |
97 | |
98 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 LT |
99 | #undef BRIEF_GFAR_ERRORS |
100 | #undef VERBOSE_GFAR_ERRORS | |
101 | ||
1da177e4 | 102 | const char gfar_driver_name[] = "Gianfar Ethernet"; |
7f7f5316 | 103 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 104 | |
1da177e4 LT |
105 | static int gfar_enet_open(struct net_device *dev); |
106 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 107 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
108 | static void gfar_timeout(struct net_device *dev); |
109 | static int gfar_close(struct net_device *dev); | |
815b97c6 AF |
110 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
111 | static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp, | |
112 | struct sk_buff *skb); | |
1da177e4 LT |
113 | static int gfar_set_mac_address(struct net_device *dev); |
114 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
115 | static irqreturn_t gfar_error(int irq, void *dev_id); |
116 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
117 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
118 | static void adjust_link(struct net_device *dev); |
119 | static void init_registers(struct net_device *dev); | |
120 | static int init_phy(struct net_device *dev); | |
b31a1d8b AF |
121 | static int gfar_probe(struct of_device *ofdev, |
122 | const struct of_device_id *match); | |
123 | static int gfar_remove(struct of_device *ofdev); | |
bb40dcbb | 124 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
125 | static void gfar_set_multi(struct net_device *dev); |
126 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 127 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 128 | static int gfar_poll(struct napi_struct *napi, int budget); |
f2d71c2d VW |
129 | #ifdef CONFIG_NET_POLL_CONTROLLER |
130 | static void gfar_netpoll(struct net_device *dev); | |
131 | #endif | |
0bbaf069 | 132 | int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit); |
f162b9d5 | 133 | static int gfar_clean_tx_ring(struct net_device *dev); |
2c2db48a DH |
134 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
135 | int amount_pull); | |
0bbaf069 KG |
136 | static void gfar_vlan_rx_register(struct net_device *netdev, |
137 | struct vlan_group *grp); | |
7f7f5316 | 138 | void gfar_halt(struct net_device *dev); |
d87eb127 | 139 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
140 | void gfar_start(struct net_device *dev); |
141 | static void gfar_clear_exact_match(struct net_device *dev); | |
142 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr); | |
26ccfc37 | 143 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 144 | |
1da177e4 LT |
145 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
146 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
147 | MODULE_LICENSE("GPL"); | |
148 | ||
26ccfc37 AF |
149 | static const struct net_device_ops gfar_netdev_ops = { |
150 | .ndo_open = gfar_enet_open, | |
151 | .ndo_start_xmit = gfar_start_xmit, | |
152 | .ndo_stop = gfar_close, | |
153 | .ndo_change_mtu = gfar_change_mtu, | |
154 | .ndo_set_multicast_list = gfar_set_multi, | |
155 | .ndo_tx_timeout = gfar_timeout, | |
156 | .ndo_do_ioctl = gfar_ioctl, | |
157 | .ndo_vlan_rx_register = gfar_vlan_rx_register, | |
158 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
159 | .ndo_poll_controller = gfar_netpoll, | |
160 | #endif | |
161 | }; | |
162 | ||
7f7f5316 AF |
163 | /* Returns 1 if incoming frames use an FCB */ |
164 | static inline int gfar_uses_fcb(struct gfar_private *priv) | |
0bbaf069 | 165 | { |
77ecaf2d | 166 | return priv->vlgrp || priv->rx_csum_enable; |
0bbaf069 | 167 | } |
bb40dcbb | 168 | |
b31a1d8b AF |
169 | static int gfar_of_init(struct net_device *dev) |
170 | { | |
171 | struct device_node *phy, *mdio; | |
172 | const unsigned int *id; | |
173 | const char *model; | |
174 | const char *ctype; | |
175 | const void *mac_addr; | |
176 | const phandle *ph; | |
177 | u64 addr, size; | |
178 | int err = 0; | |
179 | struct gfar_private *priv = netdev_priv(dev); | |
180 | struct device_node *np = priv->node; | |
181 | char bus_name[MII_BUS_ID_SIZE]; | |
4d7902f2 AF |
182 | const u32 *stash; |
183 | const u32 *stash_len; | |
184 | const u32 *stash_idx; | |
b31a1d8b AF |
185 | |
186 | if (!np || !of_device_is_available(np)) | |
187 | return -ENODEV; | |
188 | ||
189 | /* get a pointer to the register memory */ | |
190 | addr = of_translate_address(np, of_get_address(np, 0, &size, NULL)); | |
191 | priv->regs = ioremap(addr, size); | |
192 | ||
193 | if (priv->regs == NULL) | |
194 | return -ENOMEM; | |
195 | ||
196 | priv->interruptTransmit = irq_of_parse_and_map(np, 0); | |
197 | ||
198 | model = of_get_property(np, "model", NULL); | |
199 | ||
200 | /* If we aren't the FEC we have multiple interrupts */ | |
201 | if (model && strcasecmp(model, "FEC")) { | |
202 | priv->interruptReceive = irq_of_parse_and_map(np, 1); | |
203 | ||
204 | priv->interruptError = irq_of_parse_and_map(np, 2); | |
205 | ||
206 | if (priv->interruptTransmit < 0 || | |
207 | priv->interruptReceive < 0 || | |
208 | priv->interruptError < 0) { | |
209 | err = -EINVAL; | |
210 | goto err_out; | |
211 | } | |
212 | } | |
213 | ||
4d7902f2 AF |
214 | stash = of_get_property(np, "bd-stash", NULL); |
215 | ||
216 | if(stash) { | |
217 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; | |
218 | priv->bd_stash_en = 1; | |
219 | } | |
220 | ||
221 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
222 | ||
223 | if (stash_len) | |
224 | priv->rx_stash_size = *stash_len; | |
225 | ||
226 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
227 | ||
228 | if (stash_idx) | |
229 | priv->rx_stash_index = *stash_idx; | |
230 | ||
231 | if (stash_len || stash_idx) | |
232 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
233 | ||
b31a1d8b AF |
234 | mac_addr = of_get_mac_address(np); |
235 | if (mac_addr) | |
236 | memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN); | |
237 | ||
238 | if (model && !strcasecmp(model, "TSEC")) | |
239 | priv->device_flags = | |
240 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
241 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
242 | FSL_GIANFAR_DEV_HAS_RMON | | |
243 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
244 | if (model && !strcasecmp(model, "eTSEC")) | |
245 | priv->device_flags = | |
246 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
247 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
248 | FSL_GIANFAR_DEV_HAS_RMON | | |
249 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
2c2db48a | 250 | FSL_GIANFAR_DEV_HAS_PADDING | |
b31a1d8b AF |
251 | FSL_GIANFAR_DEV_HAS_CSUM | |
252 | FSL_GIANFAR_DEV_HAS_VLAN | | |
253 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
254 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH; | |
255 | ||
256 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
257 | ||
258 | /* We only care about rgmii-id. The rest are autodetected */ | |
259 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
260 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
261 | else | |
262 | priv->interface = PHY_INTERFACE_MODE_MII; | |
263 | ||
264 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
265 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
266 | ||
267 | ph = of_get_property(np, "phy-handle", NULL); | |
268 | if (ph == NULL) { | |
269 | u32 *fixed_link; | |
270 | ||
271 | fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL); | |
272 | if (!fixed_link) { | |
273 | err = -ENODEV; | |
274 | goto err_out; | |
275 | } | |
276 | ||
a1d8f601 KG |
277 | snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), |
278 | PHY_ID_FMT, "0", fixed_link[0]); | |
b31a1d8b AF |
279 | } else { |
280 | phy = of_find_node_by_phandle(*ph); | |
281 | ||
282 | if (phy == NULL) { | |
283 | err = -ENODEV; | |
284 | goto err_out; | |
285 | } | |
286 | ||
287 | mdio = of_get_parent(phy); | |
288 | ||
289 | id = of_get_property(phy, "reg", NULL); | |
290 | ||
291 | of_node_put(phy); | |
b31a1d8b | 292 | |
1577ecef | 293 | fsl_pq_mdio_bus_name(bus_name, mdio); |
ee76db5e | 294 | of_node_put(mdio); |
a1d8f601 | 295 | snprintf(priv->phy_bus_id, sizeof(priv->phy_bus_id), "%s:%02x", |
b31a1d8b AF |
296 | bus_name, *id); |
297 | } | |
298 | ||
299 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
300 | ph = of_get_property(np, "tbi-handle", NULL); | |
301 | if (ph) { | |
302 | struct device_node *tbi = of_find_node_by_phandle(*ph); | |
303 | struct of_device *ofdev; | |
304 | struct mii_bus *bus; | |
305 | ||
306 | if (!tbi) | |
307 | return 0; | |
308 | ||
309 | mdio = of_get_parent(tbi); | |
310 | if (!mdio) | |
311 | return 0; | |
312 | ||
313 | ofdev = of_find_device_by_node(mdio); | |
314 | ||
315 | of_node_put(mdio); | |
316 | ||
317 | id = of_get_property(tbi, "reg", NULL); | |
318 | if (!id) | |
319 | return 0; | |
320 | ||
321 | of_node_put(tbi); | |
322 | ||
323 | bus = dev_get_drvdata(&ofdev->dev); | |
324 | ||
325 | priv->tbiphy = bus->phy_map[*id]; | |
326 | } | |
327 | ||
328 | return 0; | |
329 | ||
330 | err_out: | |
331 | iounmap(priv->regs); | |
332 | return err; | |
333 | } | |
334 | ||
0faac9f7 CW |
335 | /* Ioctl MII Interface */ |
336 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
337 | { | |
338 | struct gfar_private *priv = netdev_priv(dev); | |
339 | ||
340 | if (!netif_running(dev)) | |
341 | return -EINVAL; | |
342 | ||
343 | if (!priv->phydev) | |
344 | return -ENODEV; | |
345 | ||
346 | return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); | |
347 | } | |
348 | ||
bb40dcbb AF |
349 | /* Set up the ethernet device structure, private data, |
350 | * and anything else we need before we start */ | |
b31a1d8b AF |
351 | static int gfar_probe(struct of_device *ofdev, |
352 | const struct of_device_id *match) | |
1da177e4 LT |
353 | { |
354 | u32 tempval; | |
355 | struct net_device *dev = NULL; | |
356 | struct gfar_private *priv = NULL; | |
b31a1d8b | 357 | DECLARE_MAC_BUF(mac); |
c50a5d9a DH |
358 | int err = 0; |
359 | int len_devname; | |
1da177e4 LT |
360 | |
361 | /* Create an ethernet device instance */ | |
362 | dev = alloc_etherdev(sizeof (*priv)); | |
363 | ||
bb40dcbb | 364 | if (NULL == dev) |
1da177e4 LT |
365 | return -ENOMEM; |
366 | ||
367 | priv = netdev_priv(dev); | |
4826857f KG |
368 | priv->ndev = dev; |
369 | priv->ofdev = ofdev; | |
b31a1d8b | 370 | priv->node = ofdev->node; |
4826857f | 371 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 372 | |
b31a1d8b | 373 | err = gfar_of_init(dev); |
1da177e4 | 374 | |
b31a1d8b | 375 | if (err) |
1da177e4 | 376 | goto regs_fail; |
1da177e4 | 377 | |
fef6108d AF |
378 | spin_lock_init(&priv->txlock); |
379 | spin_lock_init(&priv->rxlock); | |
d87eb127 | 380 | spin_lock_init(&priv->bflock); |
ab939905 | 381 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 382 | |
b31a1d8b | 383 | dev_set_drvdata(&ofdev->dev, priv); |
1da177e4 LT |
384 | |
385 | /* Stop the DMA engine now, in case it was running before */ | |
386 | /* (The firmware could have used it, and left it running). */ | |
257d938a | 387 | gfar_halt(dev); |
1da177e4 LT |
388 | |
389 | /* Reset MAC layer */ | |
390 | gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); | |
391 | ||
b98ac702 AF |
392 | /* We need to delay at least 3 TX clocks */ |
393 | udelay(2); | |
394 | ||
1da177e4 LT |
395 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
396 | gfar_write(&priv->regs->maccfg1, tempval); | |
397 | ||
398 | /* Initialize MACCFG2. */ | |
399 | gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS); | |
400 | ||
401 | /* Initialize ECNTRL */ | |
402 | gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS); | |
403 | ||
1da177e4 LT |
404 | /* Set the dev->base_addr to the gfar reg region */ |
405 | dev->base_addr = (unsigned long) (priv->regs); | |
406 | ||
b31a1d8b | 407 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 LT |
408 | |
409 | /* Fill in the dev structure */ | |
1da177e4 | 410 | dev->watchdog_timeo = TX_TIMEOUT; |
bea3348e | 411 | netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT); |
1da177e4 | 412 | dev->mtu = 1500; |
1da177e4 | 413 | |
26ccfc37 | 414 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
415 | dev->ethtool_ops = &gfar_ethtool_ops; |
416 | ||
b31a1d8b | 417 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
0bbaf069 | 418 | priv->rx_csum_enable = 1; |
4669bc90 | 419 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA; |
0bbaf069 KG |
420 | } else |
421 | priv->rx_csum_enable = 0; | |
422 | ||
423 | priv->vlgrp = NULL; | |
1da177e4 | 424 | |
26ccfc37 | 425 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) |
0bbaf069 | 426 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
0bbaf069 | 427 | |
b31a1d8b | 428 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
429 | priv->extended_hash = 1; |
430 | priv->hash_width = 9; | |
431 | ||
432 | priv->hash_regs[0] = &priv->regs->igaddr0; | |
433 | priv->hash_regs[1] = &priv->regs->igaddr1; | |
434 | priv->hash_regs[2] = &priv->regs->igaddr2; | |
435 | priv->hash_regs[3] = &priv->regs->igaddr3; | |
436 | priv->hash_regs[4] = &priv->regs->igaddr4; | |
437 | priv->hash_regs[5] = &priv->regs->igaddr5; | |
438 | priv->hash_regs[6] = &priv->regs->igaddr6; | |
439 | priv->hash_regs[7] = &priv->regs->igaddr7; | |
440 | priv->hash_regs[8] = &priv->regs->gaddr0; | |
441 | priv->hash_regs[9] = &priv->regs->gaddr1; | |
442 | priv->hash_regs[10] = &priv->regs->gaddr2; | |
443 | priv->hash_regs[11] = &priv->regs->gaddr3; | |
444 | priv->hash_regs[12] = &priv->regs->gaddr4; | |
445 | priv->hash_regs[13] = &priv->regs->gaddr5; | |
446 | priv->hash_regs[14] = &priv->regs->gaddr6; | |
447 | priv->hash_regs[15] = &priv->regs->gaddr7; | |
448 | ||
449 | } else { | |
450 | priv->extended_hash = 0; | |
451 | priv->hash_width = 8; | |
452 | ||
453 | priv->hash_regs[0] = &priv->regs->gaddr0; | |
1577ecef | 454 | priv->hash_regs[1] = &priv->regs->gaddr1; |
0bbaf069 KG |
455 | priv->hash_regs[2] = &priv->regs->gaddr2; |
456 | priv->hash_regs[3] = &priv->regs->gaddr3; | |
457 | priv->hash_regs[4] = &priv->regs->gaddr4; | |
458 | priv->hash_regs[5] = &priv->regs->gaddr5; | |
459 | priv->hash_regs[6] = &priv->regs->gaddr6; | |
460 | priv->hash_regs[7] = &priv->regs->gaddr7; | |
461 | } | |
462 | ||
b31a1d8b | 463 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
464 | priv->padding = DEFAULT_PADDING; |
465 | else | |
466 | priv->padding = 0; | |
467 | ||
0bbaf069 KG |
468 | if (dev->features & NETIF_F_IP_CSUM) |
469 | dev->hard_header_len += GMAC_FCB_LEN; | |
1da177e4 LT |
470 | |
471 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; | |
1da177e4 LT |
472 | priv->tx_ring_size = DEFAULT_TX_RING_SIZE; |
473 | priv->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
4669bc90 | 474 | priv->num_txbdfree = DEFAULT_TX_RING_SIZE; |
1da177e4 LT |
475 | |
476 | priv->txcoalescing = DEFAULT_TX_COALESCE; | |
b46a8454 | 477 | priv->txic = DEFAULT_TXIC; |
1da177e4 | 478 | priv->rxcoalescing = DEFAULT_RX_COALESCE; |
b46a8454 | 479 | priv->rxic = DEFAULT_RXIC; |
1da177e4 | 480 | |
0bbaf069 KG |
481 | /* Enable most messages by default */ |
482 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
483 | ||
d3eab82b TP |
484 | /* Carrier starts down, phylib will bring it up */ |
485 | netif_carrier_off(dev); | |
486 | ||
1da177e4 LT |
487 | err = register_netdev(dev); |
488 | ||
489 | if (err) { | |
490 | printk(KERN_ERR "%s: Cannot register net device, aborting.\n", | |
491 | dev->name); | |
492 | goto register_fail; | |
493 | } | |
494 | ||
2884e5cc AV |
495 | device_init_wakeup(&dev->dev, |
496 | priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
497 | ||
c50a5d9a DH |
498 | /* fill out IRQ number and name fields */ |
499 | len_devname = strlen(dev->name); | |
500 | strncpy(&priv->int_name_tx[0], dev->name, len_devname); | |
501 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { | |
502 | strncpy(&priv->int_name_tx[len_devname], | |
503 | "_tx", sizeof("_tx") + 1); | |
504 | ||
505 | strncpy(&priv->int_name_rx[0], dev->name, len_devname); | |
506 | strncpy(&priv->int_name_rx[len_devname], | |
507 | "_rx", sizeof("_rx") + 1); | |
508 | ||
509 | strncpy(&priv->int_name_er[0], dev->name, len_devname); | |
510 | strncpy(&priv->int_name_er[len_devname], | |
511 | "_er", sizeof("_er") + 1); | |
512 | } else | |
513 | priv->int_name_tx[len_devname] = '\0'; | |
514 | ||
7f7f5316 AF |
515 | /* Create all the sysfs files */ |
516 | gfar_init_sysfs(dev); | |
517 | ||
1da177e4 | 518 | /* Print out the device info */ |
e174961c | 519 | printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr); |
1da177e4 LT |
520 | |
521 | /* Even more device info helps when determining which kernel */ | |
7f7f5316 | 522 | /* provided which set of benchmarks. */ |
1da177e4 | 523 | printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name); |
1da177e4 LT |
524 | printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n", |
525 | dev->name, priv->rx_ring_size, priv->tx_ring_size); | |
526 | ||
527 | return 0; | |
528 | ||
529 | register_fail: | |
cc8c6e37 | 530 | iounmap(priv->regs); |
1da177e4 LT |
531 | regs_fail: |
532 | free_netdev(dev); | |
bb40dcbb | 533 | return err; |
1da177e4 LT |
534 | } |
535 | ||
b31a1d8b | 536 | static int gfar_remove(struct of_device *ofdev) |
1da177e4 | 537 | { |
b31a1d8b | 538 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
1da177e4 | 539 | |
b31a1d8b | 540 | dev_set_drvdata(&ofdev->dev, NULL); |
1da177e4 | 541 | |
cc8c6e37 | 542 | iounmap(priv->regs); |
4826857f | 543 | free_netdev(priv->ndev); |
1da177e4 LT |
544 | |
545 | return 0; | |
546 | } | |
547 | ||
d87eb127 | 548 | #ifdef CONFIG_PM |
b31a1d8b | 549 | static int gfar_suspend(struct of_device *ofdev, pm_message_t state) |
d87eb127 | 550 | { |
b31a1d8b | 551 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
29ded5f7 | 552 | struct net_device *dev = priv->ndev; |
d87eb127 SW |
553 | unsigned long flags; |
554 | u32 tempval; | |
555 | ||
556 | int magic_packet = priv->wol_en && | |
b31a1d8b | 557 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 SW |
558 | |
559 | netif_device_detach(dev); | |
560 | ||
561 | if (netif_running(dev)) { | |
562 | spin_lock_irqsave(&priv->txlock, flags); | |
563 | spin_lock(&priv->rxlock); | |
564 | ||
565 | gfar_halt_nodisable(dev); | |
566 | ||
567 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
568 | tempval = gfar_read(&priv->regs->maccfg1); | |
569 | ||
570 | tempval &= ~MACCFG1_TX_EN; | |
571 | ||
572 | if (!magic_packet) | |
573 | tempval &= ~MACCFG1_RX_EN; | |
574 | ||
575 | gfar_write(&priv->regs->maccfg1, tempval); | |
576 | ||
577 | spin_unlock(&priv->rxlock); | |
578 | spin_unlock_irqrestore(&priv->txlock, flags); | |
579 | ||
d87eb127 | 580 | napi_disable(&priv->napi); |
d87eb127 SW |
581 | |
582 | if (magic_packet) { | |
583 | /* Enable interrupt on Magic Packet */ | |
584 | gfar_write(&priv->regs->imask, IMASK_MAG); | |
585 | ||
586 | /* Enable Magic Packet mode */ | |
587 | tempval = gfar_read(&priv->regs->maccfg2); | |
588 | tempval |= MACCFG2_MPEN; | |
589 | gfar_write(&priv->regs->maccfg2, tempval); | |
590 | } else { | |
591 | phy_stop(priv->phydev); | |
592 | } | |
593 | } | |
594 | ||
595 | return 0; | |
596 | } | |
597 | ||
b31a1d8b | 598 | static int gfar_resume(struct of_device *ofdev) |
d87eb127 | 599 | { |
b31a1d8b | 600 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
29ded5f7 | 601 | struct net_device *dev = priv->ndev; |
d87eb127 SW |
602 | unsigned long flags; |
603 | u32 tempval; | |
604 | int magic_packet = priv->wol_en && | |
b31a1d8b | 605 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 SW |
606 | |
607 | if (!netif_running(dev)) { | |
608 | netif_device_attach(dev); | |
609 | return 0; | |
610 | } | |
611 | ||
612 | if (!magic_packet && priv->phydev) | |
613 | phy_start(priv->phydev); | |
614 | ||
615 | /* Disable Magic Packet mode, in case something | |
616 | * else woke us up. | |
617 | */ | |
618 | ||
619 | spin_lock_irqsave(&priv->txlock, flags); | |
620 | spin_lock(&priv->rxlock); | |
621 | ||
622 | tempval = gfar_read(&priv->regs->maccfg2); | |
623 | tempval &= ~MACCFG2_MPEN; | |
624 | gfar_write(&priv->regs->maccfg2, tempval); | |
625 | ||
626 | gfar_start(dev); | |
627 | ||
628 | spin_unlock(&priv->rxlock); | |
629 | spin_unlock_irqrestore(&priv->txlock, flags); | |
630 | ||
631 | netif_device_attach(dev); | |
632 | ||
d87eb127 | 633 | napi_enable(&priv->napi); |
d87eb127 SW |
634 | |
635 | return 0; | |
636 | } | |
637 | #else | |
638 | #define gfar_suspend NULL | |
639 | #define gfar_resume NULL | |
640 | #endif | |
1da177e4 | 641 | |
e8a2b6a4 AF |
642 | /* Reads the controller's registers to determine what interface |
643 | * connects it to the PHY. | |
644 | */ | |
645 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
646 | { | |
647 | struct gfar_private *priv = netdev_priv(dev); | |
648 | u32 ecntrl = gfar_read(&priv->regs->ecntrl); | |
649 | ||
650 | if (ecntrl & ECNTRL_SGMII_MODE) | |
651 | return PHY_INTERFACE_MODE_SGMII; | |
652 | ||
653 | if (ecntrl & ECNTRL_TBI_MODE) { | |
654 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
655 | return PHY_INTERFACE_MODE_RTBI; | |
656 | else | |
657 | return PHY_INTERFACE_MODE_TBI; | |
658 | } | |
659 | ||
660 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
661 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) | |
662 | return PHY_INTERFACE_MODE_RMII; | |
7132ab7f | 663 | else { |
b31a1d8b | 664 | phy_interface_t interface = priv->interface; |
7132ab7f AF |
665 | |
666 | /* | |
667 | * This isn't autodetected right now, so it must | |
668 | * be set by the device tree or platform code. | |
669 | */ | |
670 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
671 | return PHY_INTERFACE_MODE_RGMII_ID; | |
672 | ||
e8a2b6a4 | 673 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 674 | } |
e8a2b6a4 AF |
675 | } |
676 | ||
b31a1d8b | 677 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
678 | return PHY_INTERFACE_MODE_GMII; |
679 | ||
680 | return PHY_INTERFACE_MODE_MII; | |
681 | } | |
682 | ||
683 | ||
bb40dcbb AF |
684 | /* Initializes driver's PHY state, and attaches to the PHY. |
685 | * Returns 0 on success. | |
1da177e4 LT |
686 | */ |
687 | static int init_phy(struct net_device *dev) | |
688 | { | |
689 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 690 | uint gigabit_support = |
b31a1d8b | 691 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb AF |
692 | SUPPORTED_1000baseT_Full : 0; |
693 | struct phy_device *phydev; | |
e8a2b6a4 | 694 | phy_interface_t interface; |
1da177e4 LT |
695 | |
696 | priv->oldlink = 0; | |
697 | priv->oldspeed = 0; | |
698 | priv->oldduplex = -1; | |
699 | ||
e8a2b6a4 AF |
700 | interface = gfar_get_interface(dev); |
701 | ||
b31a1d8b | 702 | phydev = phy_connect(dev, priv->phy_bus_id, &adjust_link, 0, interface); |
1da177e4 | 703 | |
d3c12873 KJ |
704 | if (interface == PHY_INTERFACE_MODE_SGMII) |
705 | gfar_configure_serdes(dev); | |
706 | ||
bb40dcbb AF |
707 | if (IS_ERR(phydev)) { |
708 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
709 | return PTR_ERR(phydev); | |
1da177e4 LT |
710 | } |
711 | ||
bb40dcbb AF |
712 | /* Remove any features not supported by the controller */ |
713 | phydev->supported &= (GFAR_SUPPORTED | gigabit_support); | |
714 | phydev->advertising = phydev->supported; | |
1da177e4 | 715 | |
bb40dcbb | 716 | priv->phydev = phydev; |
1da177e4 LT |
717 | |
718 | return 0; | |
1da177e4 LT |
719 | } |
720 | ||
d0313587 PG |
721 | /* |
722 | * Initialize TBI PHY interface for communicating with the | |
723 | * SERDES lynx PHY on the chip. We communicate with this PHY | |
724 | * through the MDIO bus on each controller, treating it as a | |
725 | * "normal" PHY at the address found in the TBIPA register. We assume | |
726 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
727 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
728 | * value doesn't matter, as there are no other PHYs on the bus. | |
729 | */ | |
d3c12873 KJ |
730 | static void gfar_configure_serdes(struct net_device *dev) |
731 | { | |
732 | struct gfar_private *priv = netdev_priv(dev); | |
c132419e | 733 | |
b31a1d8b AF |
734 | if (!priv->tbiphy) { |
735 | printk(KERN_WARNING "SGMII mode requires that the device " | |
736 | "tree specify a tbi-handle\n"); | |
737 | return; | |
738 | } | |
d3c12873 | 739 | |
b31a1d8b AF |
740 | /* |
741 | * If the link is already up, we must already be ok, and don't need to | |
bdb59f94 TP |
742 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
743 | * everything for us? Resetting it takes the link down and requires | |
744 | * several seconds for it to come back. | |
745 | */ | |
b31a1d8b AF |
746 | if (phy_read(priv->tbiphy, MII_BMSR) & BMSR_LSTATUS) |
747 | return; | |
d3c12873 | 748 | |
d0313587 | 749 | /* Single clk mode, mii mode off(for serdes communication) */ |
b31a1d8b | 750 | phy_write(priv->tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 751 | |
b31a1d8b | 752 | phy_write(priv->tbiphy, MII_ADVERTISE, |
d3c12873 KJ |
753 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
754 | ADVERTISE_1000XPSE_ASYM); | |
755 | ||
b31a1d8b | 756 | phy_write(priv->tbiphy, MII_BMCR, BMCR_ANENABLE | |
d3c12873 KJ |
757 | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000); |
758 | } | |
759 | ||
1da177e4 LT |
760 | static void init_registers(struct net_device *dev) |
761 | { | |
762 | struct gfar_private *priv = netdev_priv(dev); | |
763 | ||
764 | /* Clear IEVENT */ | |
765 | gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR); | |
766 | ||
767 | /* Initialize IMASK */ | |
768 | gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR); | |
769 | ||
770 | /* Init hash registers to zero */ | |
0bbaf069 KG |
771 | gfar_write(&priv->regs->igaddr0, 0); |
772 | gfar_write(&priv->regs->igaddr1, 0); | |
773 | gfar_write(&priv->regs->igaddr2, 0); | |
774 | gfar_write(&priv->regs->igaddr3, 0); | |
775 | gfar_write(&priv->regs->igaddr4, 0); | |
776 | gfar_write(&priv->regs->igaddr5, 0); | |
777 | gfar_write(&priv->regs->igaddr6, 0); | |
778 | gfar_write(&priv->regs->igaddr7, 0); | |
1da177e4 LT |
779 | |
780 | gfar_write(&priv->regs->gaddr0, 0); | |
781 | gfar_write(&priv->regs->gaddr1, 0); | |
782 | gfar_write(&priv->regs->gaddr2, 0); | |
783 | gfar_write(&priv->regs->gaddr3, 0); | |
784 | gfar_write(&priv->regs->gaddr4, 0); | |
785 | gfar_write(&priv->regs->gaddr5, 0); | |
786 | gfar_write(&priv->regs->gaddr6, 0); | |
787 | gfar_write(&priv->regs->gaddr7, 0); | |
788 | ||
1da177e4 | 789 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 790 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
cc8c6e37 | 791 | memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
792 | |
793 | /* Mask off the CAM interrupts */ | |
794 | gfar_write(&priv->regs->rmon.cam1, 0xffffffff); | |
795 | gfar_write(&priv->regs->rmon.cam2, 0xffffffff); | |
796 | } | |
797 | ||
798 | /* Initialize the max receive buffer length */ | |
799 | gfar_write(&priv->regs->mrblr, priv->rx_buffer_size); | |
800 | ||
1da177e4 LT |
801 | /* Initialize the Minimum Frame Length Register */ |
802 | gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS); | |
1da177e4 LT |
803 | } |
804 | ||
0bbaf069 KG |
805 | |
806 | /* Halt the receive and transmit queues */ | |
d87eb127 | 807 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
808 | { |
809 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 810 | struct gfar __iomem *regs = priv->regs; |
1da177e4 LT |
811 | u32 tempval; |
812 | ||
1da177e4 LT |
813 | /* Mask all interrupts */ |
814 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
815 | ||
816 | /* Clear all interrupts */ | |
817 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
818 | ||
819 | /* Stop the DMA, and wait for it to stop */ | |
820 | tempval = gfar_read(&priv->regs->dmactrl); | |
821 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) | |
822 | != (DMACTRL_GRS | DMACTRL_GTS)) { | |
823 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); | |
824 | gfar_write(&priv->regs->dmactrl, tempval); | |
825 | ||
826 | while (!(gfar_read(&priv->regs->ievent) & | |
827 | (IEVENT_GRSC | IEVENT_GTSC))) | |
828 | cpu_relax(); | |
829 | } | |
d87eb127 | 830 | } |
d87eb127 SW |
831 | |
832 | /* Halt the receive and transmit queues */ | |
833 | void gfar_halt(struct net_device *dev) | |
834 | { | |
835 | struct gfar_private *priv = netdev_priv(dev); | |
836 | struct gfar __iomem *regs = priv->regs; | |
837 | u32 tempval; | |
1da177e4 | 838 | |
2a54adc3 SW |
839 | gfar_halt_nodisable(dev); |
840 | ||
1da177e4 LT |
841 | /* Disable Rx and Tx */ |
842 | tempval = gfar_read(®s->maccfg1); | |
843 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
844 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
845 | } |
846 | ||
847 | void stop_gfar(struct net_device *dev) | |
848 | { | |
849 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 850 | struct gfar __iomem *regs = priv->regs; |
0bbaf069 KG |
851 | unsigned long flags; |
852 | ||
bb40dcbb AF |
853 | phy_stop(priv->phydev); |
854 | ||
0bbaf069 | 855 | /* Lock it down */ |
fef6108d AF |
856 | spin_lock_irqsave(&priv->txlock, flags); |
857 | spin_lock(&priv->rxlock); | |
0bbaf069 | 858 | |
0bbaf069 | 859 | gfar_halt(dev); |
1da177e4 | 860 | |
fef6108d AF |
861 | spin_unlock(&priv->rxlock); |
862 | spin_unlock_irqrestore(&priv->txlock, flags); | |
1da177e4 LT |
863 | |
864 | /* Free the IRQs */ | |
b31a1d8b | 865 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
1da177e4 LT |
866 | free_irq(priv->interruptError, dev); |
867 | free_irq(priv->interruptTransmit, dev); | |
868 | free_irq(priv->interruptReceive, dev); | |
869 | } else { | |
1577ecef | 870 | free_irq(priv->interruptTransmit, dev); |
1da177e4 LT |
871 | } |
872 | ||
873 | free_skb_resources(priv); | |
874 | ||
4826857f | 875 | dma_free_coherent(&priv->ofdev->dev, |
1da177e4 LT |
876 | sizeof(struct txbd8)*priv->tx_ring_size |
877 | + sizeof(struct rxbd8)*priv->rx_ring_size, | |
878 | priv->tx_bd_base, | |
0bbaf069 | 879 | gfar_read(®s->tbase0)); |
1da177e4 LT |
880 | } |
881 | ||
882 | /* If there are any tx skbs or rx skbs still around, free them. | |
883 | * Then free tx_skbuff and rx_skbuff */ | |
bb40dcbb | 884 | static void free_skb_resources(struct gfar_private *priv) |
1da177e4 LT |
885 | { |
886 | struct rxbd8 *rxbdp; | |
887 | struct txbd8 *txbdp; | |
4669bc90 | 888 | int i, j; |
1da177e4 LT |
889 | |
890 | /* Go through all the buffer descriptors and free their data buffers */ | |
891 | txbdp = priv->tx_bd_base; | |
892 | ||
893 | for (i = 0; i < priv->tx_ring_size; i++) { | |
4669bc90 DH |
894 | if (!priv->tx_skbuff[i]) |
895 | continue; | |
1da177e4 | 896 | |
4826857f | 897 | dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr, |
4669bc90 DH |
898 | txbdp->length, DMA_TO_DEVICE); |
899 | txbdp->lstatus = 0; | |
900 | for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) { | |
901 | txbdp++; | |
4826857f | 902 | dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr, |
4669bc90 | 903 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 904 | } |
ad5da7ab | 905 | txbdp++; |
4669bc90 DH |
906 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
907 | priv->tx_skbuff[i] = NULL; | |
1da177e4 LT |
908 | } |
909 | ||
910 | kfree(priv->tx_skbuff); | |
911 | ||
912 | rxbdp = priv->rx_bd_base; | |
913 | ||
914 | /* rx_skbuff is not guaranteed to be allocated, so only | |
915 | * free it and its contents if it is allocated */ | |
916 | if(priv->rx_skbuff != NULL) { | |
917 | for (i = 0; i < priv->rx_ring_size; i++) { | |
918 | if (priv->rx_skbuff[i]) { | |
4826857f | 919 | dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr, |
7f7f5316 | 920 | priv->rx_buffer_size, |
1da177e4 LT |
921 | DMA_FROM_DEVICE); |
922 | ||
923 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
924 | priv->rx_skbuff[i] = NULL; | |
925 | } | |
926 | ||
5a5efed4 | 927 | rxbdp->lstatus = 0; |
1da177e4 LT |
928 | rxbdp->bufPtr = 0; |
929 | ||
930 | rxbdp++; | |
931 | } | |
932 | ||
933 | kfree(priv->rx_skbuff); | |
934 | } | |
935 | } | |
936 | ||
0bbaf069 KG |
937 | void gfar_start(struct net_device *dev) |
938 | { | |
939 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 940 | struct gfar __iomem *regs = priv->regs; |
0bbaf069 KG |
941 | u32 tempval; |
942 | ||
943 | /* Enable Rx and Tx in MACCFG1 */ | |
944 | tempval = gfar_read(®s->maccfg1); | |
945 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
946 | gfar_write(®s->maccfg1, tempval); | |
947 | ||
948 | /* Initialize DMACTRL to have WWR and WOP */ | |
949 | tempval = gfar_read(&priv->regs->dmactrl); | |
950 | tempval |= DMACTRL_INIT_SETTINGS; | |
951 | gfar_write(&priv->regs->dmactrl, tempval); | |
952 | ||
0bbaf069 KG |
953 | /* Make sure we aren't stopped */ |
954 | tempval = gfar_read(&priv->regs->dmactrl); | |
955 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); | |
956 | gfar_write(&priv->regs->dmactrl, tempval); | |
957 | ||
fef6108d AF |
958 | /* Clear THLT/RHLT, so that the DMA starts polling now */ |
959 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT); | |
960 | gfar_write(®s->rstat, RSTAT_CLEAR_RHALT); | |
961 | ||
0bbaf069 KG |
962 | /* Unmask the interrupts we look for */ |
963 | gfar_write(®s->imask, IMASK_DEFAULT); | |
12dea57b DH |
964 | |
965 | dev->trans_start = jiffies; | |
0bbaf069 KG |
966 | } |
967 | ||
1da177e4 LT |
968 | /* Bring the controller up and running */ |
969 | int startup_gfar(struct net_device *dev) | |
970 | { | |
971 | struct txbd8 *txbdp; | |
972 | struct rxbd8 *rxbdp; | |
f9663aea | 973 | dma_addr_t addr = 0; |
1da177e4 LT |
974 | unsigned long vaddr; |
975 | int i; | |
976 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 977 | struct gfar __iomem *regs = priv->regs; |
1da177e4 | 978 | int err = 0; |
0bbaf069 | 979 | u32 rctrl = 0; |
7f7f5316 | 980 | u32 attrs = 0; |
1da177e4 LT |
981 | |
982 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
983 | ||
984 | /* Allocate memory for the buffer descriptors */ | |
4826857f | 985 | vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev, |
1da177e4 LT |
986 | sizeof (struct txbd8) * priv->tx_ring_size + |
987 | sizeof (struct rxbd8) * priv->rx_ring_size, | |
988 | &addr, GFP_KERNEL); | |
989 | ||
990 | if (vaddr == 0) { | |
0bbaf069 KG |
991 | if (netif_msg_ifup(priv)) |
992 | printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n", | |
993 | dev->name); | |
1da177e4 LT |
994 | return -ENOMEM; |
995 | } | |
996 | ||
997 | priv->tx_bd_base = (struct txbd8 *) vaddr; | |
998 | ||
999 | /* enet DMA only understands physical addresses */ | |
0bbaf069 | 1000 | gfar_write(®s->tbase0, addr); |
1da177e4 LT |
1001 | |
1002 | /* Start the rx descriptor ring where the tx ring leaves off */ | |
1003 | addr = addr + sizeof (struct txbd8) * priv->tx_ring_size; | |
1004 | vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size; | |
1005 | priv->rx_bd_base = (struct rxbd8 *) vaddr; | |
0bbaf069 | 1006 | gfar_write(®s->rbase0, addr); |
1da177e4 LT |
1007 | |
1008 | /* Setup the skbuff rings */ | |
1009 | priv->tx_skbuff = | |
1010 | (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) * | |
1011 | priv->tx_ring_size, GFP_KERNEL); | |
1012 | ||
bb40dcbb | 1013 | if (NULL == priv->tx_skbuff) { |
0bbaf069 KG |
1014 | if (netif_msg_ifup(priv)) |
1015 | printk(KERN_ERR "%s: Could not allocate tx_skbuff\n", | |
1016 | dev->name); | |
1da177e4 LT |
1017 | err = -ENOMEM; |
1018 | goto tx_skb_fail; | |
1019 | } | |
1020 | ||
1021 | for (i = 0; i < priv->tx_ring_size; i++) | |
1022 | priv->tx_skbuff[i] = NULL; | |
1023 | ||
1024 | priv->rx_skbuff = | |
1025 | (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) * | |
1026 | priv->rx_ring_size, GFP_KERNEL); | |
1027 | ||
bb40dcbb | 1028 | if (NULL == priv->rx_skbuff) { |
0bbaf069 KG |
1029 | if (netif_msg_ifup(priv)) |
1030 | printk(KERN_ERR "%s: Could not allocate rx_skbuff\n", | |
1031 | dev->name); | |
1da177e4 LT |
1032 | err = -ENOMEM; |
1033 | goto rx_skb_fail; | |
1034 | } | |
1035 | ||
1036 | for (i = 0; i < priv->rx_ring_size; i++) | |
1037 | priv->rx_skbuff[i] = NULL; | |
1038 | ||
1039 | /* Initialize some variables in our dev structure */ | |
4669bc90 | 1040 | priv->num_txbdfree = priv->tx_ring_size; |
1da177e4 LT |
1041 | priv->dirty_tx = priv->cur_tx = priv->tx_bd_base; |
1042 | priv->cur_rx = priv->rx_bd_base; | |
1043 | priv->skb_curtx = priv->skb_dirtytx = 0; | |
1044 | priv->skb_currx = 0; | |
1045 | ||
1046 | /* Initialize Transmit Descriptor Ring */ | |
1047 | txbdp = priv->tx_bd_base; | |
1048 | for (i = 0; i < priv->tx_ring_size; i++) { | |
5a5efed4 | 1049 | txbdp->lstatus = 0; |
1da177e4 LT |
1050 | txbdp->bufPtr = 0; |
1051 | txbdp++; | |
1052 | } | |
1053 | ||
1054 | /* Set the last descriptor in the ring to indicate wrap */ | |
1055 | txbdp--; | |
1056 | txbdp->status |= TXBD_WRAP; | |
1057 | ||
1058 | rxbdp = priv->rx_bd_base; | |
1059 | for (i = 0; i < priv->rx_ring_size; i++) { | |
815b97c6 | 1060 | struct sk_buff *skb; |
1da177e4 | 1061 | |
815b97c6 | 1062 | skb = gfar_new_skb(dev); |
1da177e4 | 1063 | |
815b97c6 AF |
1064 | if (!skb) { |
1065 | printk(KERN_ERR "%s: Can't allocate RX buffers\n", | |
1066 | dev->name); | |
1067 | ||
1068 | goto err_rxalloc_fail; | |
1069 | } | |
1da177e4 LT |
1070 | |
1071 | priv->rx_skbuff[i] = skb; | |
1072 | ||
815b97c6 AF |
1073 | gfar_new_rxbdp(dev, rxbdp, skb); |
1074 | ||
1da177e4 LT |
1075 | rxbdp++; |
1076 | } | |
1077 | ||
1078 | /* Set the last descriptor in the ring to wrap */ | |
1079 | rxbdp--; | |
1080 | rxbdp->status |= RXBD_WRAP; | |
1081 | ||
1082 | /* If the device has multiple interrupts, register for | |
1083 | * them. Otherwise, only register for the one */ | |
b31a1d8b | 1084 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1085 | /* Install our interrupt handlers for Error, |
1da177e4 LT |
1086 | * Transmit, and Receive */ |
1087 | if (request_irq(priv->interruptError, gfar_error, | |
c50a5d9a | 1088 | 0, priv->int_name_er, dev) < 0) { |
0bbaf069 KG |
1089 | if (netif_msg_intr(priv)) |
1090 | printk(KERN_ERR "%s: Can't get IRQ %d\n", | |
1091 | dev->name, priv->interruptError); | |
1da177e4 LT |
1092 | |
1093 | err = -1; | |
1094 | goto err_irq_fail; | |
1095 | } | |
1096 | ||
1097 | if (request_irq(priv->interruptTransmit, gfar_transmit, | |
c50a5d9a | 1098 | 0, priv->int_name_tx, dev) < 0) { |
0bbaf069 KG |
1099 | if (netif_msg_intr(priv)) |
1100 | printk(KERN_ERR "%s: Can't get IRQ %d\n", | |
1101 | dev->name, priv->interruptTransmit); | |
1da177e4 LT |
1102 | |
1103 | err = -1; | |
1104 | ||
1105 | goto tx_irq_fail; | |
1106 | } | |
1107 | ||
1108 | if (request_irq(priv->interruptReceive, gfar_receive, | |
c50a5d9a | 1109 | 0, priv->int_name_rx, dev) < 0) { |
0bbaf069 KG |
1110 | if (netif_msg_intr(priv)) |
1111 | printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n", | |
1112 | dev->name, priv->interruptReceive); | |
1da177e4 LT |
1113 | |
1114 | err = -1; | |
1115 | goto rx_irq_fail; | |
1116 | } | |
1117 | } else { | |
1118 | if (request_irq(priv->interruptTransmit, gfar_interrupt, | |
c50a5d9a | 1119 | 0, priv->int_name_tx, dev) < 0) { |
0bbaf069 KG |
1120 | if (netif_msg_intr(priv)) |
1121 | printk(KERN_ERR "%s: Can't get IRQ %d\n", | |
c50a5d9a | 1122 | dev->name, priv->interruptTransmit); |
1da177e4 LT |
1123 | |
1124 | err = -1; | |
1125 | goto err_irq_fail; | |
1126 | } | |
1127 | } | |
1128 | ||
bb40dcbb | 1129 | phy_start(priv->phydev); |
1da177e4 LT |
1130 | |
1131 | /* Configure the coalescing support */ | |
b46a8454 | 1132 | gfar_write(®s->txic, 0); |
1da177e4 | 1133 | if (priv->txcoalescing) |
b46a8454 | 1134 | gfar_write(®s->txic, priv->txic); |
1da177e4 | 1135 | |
b46a8454 | 1136 | gfar_write(®s->rxic, 0); |
1da177e4 | 1137 | if (priv->rxcoalescing) |
b46a8454 | 1138 | gfar_write(®s->rxic, priv->rxic); |
1da177e4 | 1139 | |
0bbaf069 KG |
1140 | if (priv->rx_csum_enable) |
1141 | rctrl |= RCTRL_CHECKSUMMING; | |
1da177e4 | 1142 | |
7f7f5316 | 1143 | if (priv->extended_hash) { |
0bbaf069 | 1144 | rctrl |= RCTRL_EXTHASH; |
1da177e4 | 1145 | |
7f7f5316 AF |
1146 | gfar_clear_exact_match(dev); |
1147 | rctrl |= RCTRL_EMEN; | |
1148 | } | |
1149 | ||
7f7f5316 AF |
1150 | if (priv->padding) { |
1151 | rctrl &= ~RCTRL_PAL_MASK; | |
1152 | rctrl |= RCTRL_PADDING(priv->padding); | |
1153 | } | |
1154 | ||
0bbaf069 KG |
1155 | /* Init rctrl based on our settings */ |
1156 | gfar_write(&priv->regs->rctrl, rctrl); | |
1da177e4 | 1157 | |
0bbaf069 KG |
1158 | if (dev->features & NETIF_F_IP_CSUM) |
1159 | gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM); | |
1da177e4 | 1160 | |
7f7f5316 AF |
1161 | /* Set the extraction length and index */ |
1162 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
1163 | ATTRELI_EI(priv->rx_stash_index); | |
1164 | ||
1165 | gfar_write(&priv->regs->attreli, attrs); | |
1166 | ||
1167 | /* Start with defaults, and add stashing or locking | |
1168 | * depending on the approprate variables */ | |
1169 | attrs = ATTR_INIT_SETTINGS; | |
1170 | ||
1171 | if (priv->bd_stash_en) | |
1172 | attrs |= ATTR_BDSTASH; | |
1173 | ||
1174 | if (priv->rx_stash_size != 0) | |
1175 | attrs |= ATTR_BUFSTASH; | |
1176 | ||
1177 | gfar_write(&priv->regs->attr, attrs); | |
1178 | ||
1179 | gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold); | |
1180 | gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve); | |
1181 | gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
1182 | ||
1183 | /* Start the controller */ | |
0bbaf069 | 1184 | gfar_start(dev); |
1da177e4 LT |
1185 | |
1186 | return 0; | |
1187 | ||
1188 | rx_irq_fail: | |
1189 | free_irq(priv->interruptTransmit, dev); | |
1190 | tx_irq_fail: | |
1191 | free_irq(priv->interruptError, dev); | |
1192 | err_irq_fail: | |
7d2e3cb7 | 1193 | err_rxalloc_fail: |
1da177e4 LT |
1194 | rx_skb_fail: |
1195 | free_skb_resources(priv); | |
1196 | tx_skb_fail: | |
4826857f | 1197 | dma_free_coherent(&priv->ofdev->dev, |
1da177e4 LT |
1198 | sizeof(struct txbd8)*priv->tx_ring_size |
1199 | + sizeof(struct rxbd8)*priv->rx_ring_size, | |
1200 | priv->tx_bd_base, | |
0bbaf069 | 1201 | gfar_read(®s->tbase0)); |
1da177e4 | 1202 | |
1da177e4 LT |
1203 | return err; |
1204 | } | |
1205 | ||
1206 | /* Called when something needs to use the ethernet device */ | |
1207 | /* Returns 0 for success. */ | |
1208 | static int gfar_enet_open(struct net_device *dev) | |
1209 | { | |
94e8cc35 | 1210 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1211 | int err; |
1212 | ||
bea3348e SH |
1213 | napi_enable(&priv->napi); |
1214 | ||
0fd56bb5 AF |
1215 | skb_queue_head_init(&priv->rx_recycle); |
1216 | ||
1da177e4 LT |
1217 | /* Initialize a bunch of registers */ |
1218 | init_registers(dev); | |
1219 | ||
1220 | gfar_set_mac_address(dev); | |
1221 | ||
1222 | err = init_phy(dev); | |
1223 | ||
bea3348e SH |
1224 | if(err) { |
1225 | napi_disable(&priv->napi); | |
1da177e4 | 1226 | return err; |
bea3348e | 1227 | } |
1da177e4 LT |
1228 | |
1229 | err = startup_gfar(dev); | |
db0e8e3f | 1230 | if (err) { |
bea3348e | 1231 | napi_disable(&priv->napi); |
db0e8e3f AV |
1232 | return err; |
1233 | } | |
1da177e4 LT |
1234 | |
1235 | netif_start_queue(dev); | |
1236 | ||
2884e5cc AV |
1237 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
1238 | ||
1da177e4 LT |
1239 | return err; |
1240 | } | |
1241 | ||
54dc79fe | 1242 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 1243 | { |
54dc79fe | 1244 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
a22823e7 | 1245 | cacheable_memzero(fcb, GMAC_FCB_LEN); |
0bbaf069 | 1246 | |
0bbaf069 KG |
1247 | return fcb; |
1248 | } | |
1249 | ||
1250 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb) | |
1251 | { | |
7f7f5316 | 1252 | u8 flags = 0; |
0bbaf069 KG |
1253 | |
1254 | /* If we're here, it's a IP packet with a TCP or UDP | |
1255 | * payload. We set it to checksum, using a pseudo-header | |
1256 | * we provide | |
1257 | */ | |
7f7f5316 | 1258 | flags = TXFCB_DEFAULT; |
0bbaf069 | 1259 | |
7f7f5316 AF |
1260 | /* Tell the controller what the protocol is */ |
1261 | /* And provide the already calculated phcs */ | |
eddc9ec5 | 1262 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 1263 | flags |= TXFCB_UDP; |
4bedb452 | 1264 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 1265 | } else |
8da32de5 | 1266 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
1267 | |
1268 | /* l3os is the distance between the start of the | |
1269 | * frame (skb->data) and the start of the IP hdr. | |
1270 | * l4os is the distance between the start of the | |
1271 | * l3 hdr and the l4 hdr */ | |
bbe735e4 | 1272 | fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN); |
cfe1fc77 | 1273 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 1274 | |
7f7f5316 | 1275 | fcb->flags = flags; |
0bbaf069 KG |
1276 | } |
1277 | ||
7f7f5316 | 1278 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 1279 | { |
7f7f5316 | 1280 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
1281 | fcb->vlctl = vlan_tx_tag_get(skb); |
1282 | } | |
1283 | ||
4669bc90 DH |
1284 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
1285 | struct txbd8 *base, int ring_size) | |
1286 | { | |
1287 | struct txbd8 *new_bd = bdp + stride; | |
1288 | ||
1289 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
1290 | } | |
1291 | ||
1292 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
1293 | int ring_size) | |
1294 | { | |
1295 | return skip_txbd(bdp, 1, base, ring_size); | |
1296 | } | |
1297 | ||
1da177e4 LT |
1298 | /* This is called by the kernel when a frame is ready for transmission. */ |
1299 | /* It is pointed to by the dev->hard_start_xmit function pointer */ | |
1300 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1301 | { | |
1302 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1303 | struct txfcb *fcb = NULL; |
4669bc90 | 1304 | struct txbd8 *txbdp, *txbdp_start, *base; |
5a5efed4 | 1305 | u32 lstatus; |
4669bc90 DH |
1306 | int i; |
1307 | u32 bufaddr; | |
fef6108d | 1308 | unsigned long flags; |
4669bc90 DH |
1309 | unsigned int nr_frags, length; |
1310 | ||
1311 | base = priv->tx_bd_base; | |
1312 | ||
5b28beaf LY |
1313 | /* make space for additional header when fcb is needed */ |
1314 | if (((skb->ip_summed == CHECKSUM_PARTIAL) || | |
1315 | (priv->vlgrp && vlan_tx_tag_present(skb))) && | |
1316 | (skb_headroom(skb) < GMAC_FCB_LEN)) { | |
54dc79fe SH |
1317 | struct sk_buff *skb_new; |
1318 | ||
1319 | skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN); | |
1320 | if (!skb_new) { | |
1321 | dev->stats.tx_errors++; | |
bd14ba84 | 1322 | kfree_skb(skb); |
54dc79fe SH |
1323 | return NETDEV_TX_OK; |
1324 | } | |
1325 | kfree_skb(skb); | |
1326 | skb = skb_new; | |
1327 | } | |
1328 | ||
4669bc90 DH |
1329 | /* total number of fragments in the SKB */ |
1330 | nr_frags = skb_shinfo(skb)->nr_frags; | |
1331 | ||
1332 | spin_lock_irqsave(&priv->txlock, flags); | |
1333 | ||
1334 | /* check if there is space to queue this packet */ | |
7958a453 | 1335 | if ((nr_frags+1) > priv->num_txbdfree) { |
4669bc90 DH |
1336 | /* no space, stop the queue */ |
1337 | netif_stop_queue(dev); | |
1338 | dev->stats.tx_fifo_errors++; | |
1339 | spin_unlock_irqrestore(&priv->txlock, flags); | |
1340 | return NETDEV_TX_BUSY; | |
1341 | } | |
1da177e4 LT |
1342 | |
1343 | /* Update transmit stats */ | |
09f75cd7 | 1344 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 1345 | |
4669bc90 | 1346 | txbdp = txbdp_start = priv->cur_tx; |
1da177e4 | 1347 | |
4669bc90 DH |
1348 | if (nr_frags == 0) { |
1349 | lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1350 | } else { | |
1351 | /* Place the fragment addresses and lengths into the TxBDs */ | |
1352 | for (i = 0; i < nr_frags; i++) { | |
1353 | /* Point at the next BD, wrapping as needed */ | |
1354 | txbdp = next_txbd(txbdp, base, priv->tx_ring_size); | |
1355 | ||
1356 | length = skb_shinfo(skb)->frags[i].size; | |
1357 | ||
1358 | lstatus = txbdp->lstatus | length | | |
1359 | BD_LFLAG(TXBD_READY); | |
1360 | ||
1361 | /* Handle the last BD specially */ | |
1362 | if (i == nr_frags - 1) | |
1363 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 1364 | |
4826857f | 1365 | bufaddr = dma_map_page(&priv->ofdev->dev, |
4669bc90 DH |
1366 | skb_shinfo(skb)->frags[i].page, |
1367 | skb_shinfo(skb)->frags[i].page_offset, | |
1368 | length, | |
1369 | DMA_TO_DEVICE); | |
1370 | ||
1371 | /* set the TxBD length and buffer pointer */ | |
1372 | txbdp->bufPtr = bufaddr; | |
1373 | txbdp->lstatus = lstatus; | |
1374 | } | |
1375 | ||
1376 | lstatus = txbdp_start->lstatus; | |
1377 | } | |
1da177e4 | 1378 | |
0bbaf069 | 1379 | /* Set up checksumming */ |
12dea57b | 1380 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
54dc79fe SH |
1381 | fcb = gfar_add_fcb(skb); |
1382 | lstatus |= BD_LFLAG(TXBD_TOE); | |
1383 | gfar_tx_checksum(skb, fcb); | |
0bbaf069 KG |
1384 | } |
1385 | ||
77ecaf2d | 1386 | if (priv->vlgrp && vlan_tx_tag_present(skb)) { |
54dc79fe SH |
1387 | if (unlikely(NULL == fcb)) { |
1388 | fcb = gfar_add_fcb(skb); | |
5a5efed4 | 1389 | lstatus |= BD_LFLAG(TXBD_TOE); |
7f7f5316 | 1390 | } |
54dc79fe SH |
1391 | |
1392 | gfar_tx_vlan(skb, fcb); | |
0bbaf069 KG |
1393 | } |
1394 | ||
4669bc90 | 1395 | /* setup the TxBD length and buffer pointer for the first BD */ |
1da177e4 | 1396 | priv->tx_skbuff[priv->skb_curtx] = skb; |
4826857f | 1397 | txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, |
4669bc90 | 1398 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 1399 | |
4669bc90 | 1400 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); |
1da177e4 | 1401 | |
4669bc90 DH |
1402 | /* |
1403 | * The powerpc-specific eieio() is used, as wmb() has too strong | |
3b6330ce SW |
1404 | * semantics (it requires synchronization between cacheable and |
1405 | * uncacheable mappings, which eieio doesn't provide and which we | |
1406 | * don't need), thus requiring a more expensive sync instruction. At | |
1407 | * some point, the set of architecture-independent barrier functions | |
1408 | * should be expanded to include weaker barriers. | |
1409 | */ | |
3b6330ce | 1410 | eieio(); |
7f7f5316 | 1411 | |
4669bc90 DH |
1412 | txbdp_start->lstatus = lstatus; |
1413 | ||
1414 | /* Update the current skb pointer to the next entry we will use | |
1415 | * (wrapping if necessary) */ | |
1416 | priv->skb_curtx = (priv->skb_curtx + 1) & | |
1417 | TX_RING_MOD_MASK(priv->tx_ring_size); | |
1418 | ||
1419 | priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size); | |
1420 | ||
1421 | /* reduce TxBD free count */ | |
1422 | priv->num_txbdfree -= (nr_frags + 1); | |
1423 | ||
1424 | dev->trans_start = jiffies; | |
1da177e4 LT |
1425 | |
1426 | /* If the next BD still needs to be cleaned up, then the bds | |
1427 | are full. We need to tell the kernel to stop sending us stuff. */ | |
4669bc90 | 1428 | if (!priv->num_txbdfree) { |
1da177e4 LT |
1429 | netif_stop_queue(dev); |
1430 | ||
09f75cd7 | 1431 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
1432 | } |
1433 | ||
1da177e4 LT |
1434 | /* Tell the DMA to go go go */ |
1435 | gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT); | |
1436 | ||
1437 | /* Unlock priv */ | |
fef6108d | 1438 | spin_unlock_irqrestore(&priv->txlock, flags); |
1da177e4 | 1439 | |
54dc79fe | 1440 | return NETDEV_TX_OK; |
1da177e4 LT |
1441 | } |
1442 | ||
1443 | /* Stops the kernel queue, and halts the controller */ | |
1444 | static int gfar_close(struct net_device *dev) | |
1445 | { | |
1446 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e SH |
1447 | |
1448 | napi_disable(&priv->napi); | |
1449 | ||
0fd56bb5 | 1450 | skb_queue_purge(&priv->rx_recycle); |
ab939905 | 1451 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
1452 | stop_gfar(dev); |
1453 | ||
bb40dcbb AF |
1454 | /* Disconnect from the PHY */ |
1455 | phy_disconnect(priv->phydev); | |
1456 | priv->phydev = NULL; | |
1da177e4 LT |
1457 | |
1458 | netif_stop_queue(dev); | |
1459 | ||
1460 | return 0; | |
1461 | } | |
1462 | ||
1da177e4 | 1463 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 1464 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 1465 | { |
7f7f5316 | 1466 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
1467 | |
1468 | return 0; | |
1469 | } | |
1470 | ||
1471 | ||
0bbaf069 KG |
1472 | /* Enables and disables VLAN insertion/extraction */ |
1473 | static void gfar_vlan_rx_register(struct net_device *dev, | |
1474 | struct vlan_group *grp) | |
1475 | { | |
1476 | struct gfar_private *priv = netdev_priv(dev); | |
1477 | unsigned long flags; | |
1478 | u32 tempval; | |
1479 | ||
fef6108d | 1480 | spin_lock_irqsave(&priv->rxlock, flags); |
0bbaf069 | 1481 | |
cd1f55a5 | 1482 | priv->vlgrp = grp; |
0bbaf069 KG |
1483 | |
1484 | if (grp) { | |
1485 | /* Enable VLAN tag insertion */ | |
1486 | tempval = gfar_read(&priv->regs->tctrl); | |
1487 | tempval |= TCTRL_VLINS; | |
1488 | ||
1489 | gfar_write(&priv->regs->tctrl, tempval); | |
6aa20a22 | 1490 | |
0bbaf069 KG |
1491 | /* Enable VLAN tag extraction */ |
1492 | tempval = gfar_read(&priv->regs->rctrl); | |
1493 | tempval |= RCTRL_VLEX; | |
77ecaf2d | 1494 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); |
0bbaf069 KG |
1495 | gfar_write(&priv->regs->rctrl, tempval); |
1496 | } else { | |
1497 | /* Disable VLAN tag insertion */ | |
1498 | tempval = gfar_read(&priv->regs->tctrl); | |
1499 | tempval &= ~TCTRL_VLINS; | |
1500 | gfar_write(&priv->regs->tctrl, tempval); | |
1501 | ||
1502 | /* Disable VLAN tag extraction */ | |
1503 | tempval = gfar_read(&priv->regs->rctrl); | |
1504 | tempval &= ~RCTRL_VLEX; | |
77ecaf2d DH |
1505 | /* If parse is no longer required, then disable parser */ |
1506 | if (tempval & RCTRL_REQ_PARSER) | |
1507 | tempval |= RCTRL_PRSDEP_INIT; | |
1508 | else | |
1509 | tempval &= ~RCTRL_PRSDEP_INIT; | |
0bbaf069 KG |
1510 | gfar_write(&priv->regs->rctrl, tempval); |
1511 | } | |
1512 | ||
77ecaf2d DH |
1513 | gfar_change_mtu(dev, dev->mtu); |
1514 | ||
fef6108d | 1515 | spin_unlock_irqrestore(&priv->rxlock, flags); |
0bbaf069 KG |
1516 | } |
1517 | ||
1da177e4 LT |
1518 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
1519 | { | |
1520 | int tempsize, tempval; | |
1521 | struct gfar_private *priv = netdev_priv(dev); | |
1522 | int oldsize = priv->rx_buffer_size; | |
0bbaf069 KG |
1523 | int frame_size = new_mtu + ETH_HLEN; |
1524 | ||
77ecaf2d | 1525 | if (priv->vlgrp) |
faa89577 | 1526 | frame_size += VLAN_HLEN; |
0bbaf069 | 1527 | |
1da177e4 | 1528 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
0bbaf069 KG |
1529 | if (netif_msg_drv(priv)) |
1530 | printk(KERN_ERR "%s: Invalid MTU setting\n", | |
1531 | dev->name); | |
1da177e4 LT |
1532 | return -EINVAL; |
1533 | } | |
1534 | ||
77ecaf2d DH |
1535 | if (gfar_uses_fcb(priv)) |
1536 | frame_size += GMAC_FCB_LEN; | |
1537 | ||
1538 | frame_size += priv->padding; | |
1539 | ||
1da177e4 LT |
1540 | tempsize = |
1541 | (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + | |
1542 | INCREMENTAL_BUFFER_SIZE; | |
1543 | ||
1544 | /* Only stop and start the controller if it isn't already | |
7f7f5316 | 1545 | * stopped, and we changed something */ |
1da177e4 LT |
1546 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
1547 | stop_gfar(dev); | |
1548 | ||
1549 | priv->rx_buffer_size = tempsize; | |
1550 | ||
1551 | dev->mtu = new_mtu; | |
1552 | ||
1553 | gfar_write(&priv->regs->mrblr, priv->rx_buffer_size); | |
1554 | gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size); | |
1555 | ||
1556 | /* If the mtu is larger than the max size for standard | |
1557 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
1558 | * to allow huge frames, and to check the length */ | |
1559 | tempval = gfar_read(&priv->regs->maccfg2); | |
1560 | ||
1561 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE) | |
1562 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
1563 | else | |
1564 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
1565 | ||
1566 | gfar_write(&priv->regs->maccfg2, tempval); | |
1567 | ||
1568 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
1569 | startup_gfar(dev); | |
1570 | ||
1571 | return 0; | |
1572 | } | |
1573 | ||
ab939905 | 1574 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
1575 | * transmitted after a set amount of time. |
1576 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
1577 | * starting over will fix the problem. |
1578 | */ | |
1579 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 1580 | { |
ab939905 SS |
1581 | struct gfar_private *priv = container_of(work, struct gfar_private, |
1582 | reset_task); | |
4826857f | 1583 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
1584 | |
1585 | if (dev->flags & IFF_UP) { | |
1586 | stop_gfar(dev); | |
1587 | startup_gfar(dev); | |
1588 | } | |
1589 | ||
263ba320 | 1590 | netif_tx_schedule_all(dev); |
1da177e4 LT |
1591 | } |
1592 | ||
ab939905 SS |
1593 | static void gfar_timeout(struct net_device *dev) |
1594 | { | |
1595 | struct gfar_private *priv = netdev_priv(dev); | |
1596 | ||
1597 | dev->stats.tx_errors++; | |
1598 | schedule_work(&priv->reset_task); | |
1599 | } | |
1600 | ||
1da177e4 | 1601 | /* Interrupt Handler for Transmit complete */ |
f162b9d5 | 1602 | static int gfar_clean_tx_ring(struct net_device *dev) |
1da177e4 | 1603 | { |
d080cd63 | 1604 | struct gfar_private *priv = netdev_priv(dev); |
4669bc90 DH |
1605 | struct txbd8 *bdp; |
1606 | struct txbd8 *lbdp = NULL; | |
1607 | struct txbd8 *base = priv->tx_bd_base; | |
1608 | struct sk_buff *skb; | |
1609 | int skb_dirtytx; | |
1610 | int tx_ring_size = priv->tx_ring_size; | |
1611 | int frags = 0; | |
1612 | int i; | |
d080cd63 | 1613 | int howmany = 0; |
4669bc90 | 1614 | u32 lstatus; |
1da177e4 | 1615 | |
1da177e4 | 1616 | bdp = priv->dirty_tx; |
4669bc90 | 1617 | skb_dirtytx = priv->skb_dirtytx; |
1da177e4 | 1618 | |
4669bc90 DH |
1619 | while ((skb = priv->tx_skbuff[skb_dirtytx])) { |
1620 | frags = skb_shinfo(skb)->nr_frags; | |
1621 | lbdp = skip_txbd(bdp, frags, base, tx_ring_size); | |
1da177e4 | 1622 | |
4669bc90 | 1623 | lstatus = lbdp->lstatus; |
1da177e4 | 1624 | |
4669bc90 DH |
1625 | /* Only clean completed frames */ |
1626 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
1627 | (lstatus & BD_LENGTH_MASK)) | |
1628 | break; | |
1629 | ||
4826857f | 1630 | dma_unmap_single(&priv->ofdev->dev, |
4669bc90 DH |
1631 | bdp->bufPtr, |
1632 | bdp->length, | |
1633 | DMA_TO_DEVICE); | |
81183059 | 1634 | |
4669bc90 DH |
1635 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
1636 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 1637 | |
4669bc90 | 1638 | for (i = 0; i < frags; i++) { |
4826857f | 1639 | dma_unmap_page(&priv->ofdev->dev, |
4669bc90 DH |
1640 | bdp->bufPtr, |
1641 | bdp->length, | |
1642 | DMA_TO_DEVICE); | |
1643 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
1644 | bdp = next_txbd(bdp, base, tx_ring_size); | |
1645 | } | |
1da177e4 | 1646 | |
0fd56bb5 AF |
1647 | /* |
1648 | * If there's room in the queue (limit it to rx_buffer_size) | |
1649 | * we add this skb back into the pool, if it's the right size | |
1650 | */ | |
1651 | if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size && | |
1652 | skb_recycle_check(skb, priv->rx_buffer_size + | |
1653 | RXBUF_ALIGNMENT)) | |
1654 | __skb_queue_head(&priv->rx_recycle, skb); | |
1655 | else | |
1656 | dev_kfree_skb_any(skb); | |
1657 | ||
4669bc90 | 1658 | priv->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 1659 | |
4669bc90 DH |
1660 | skb_dirtytx = (skb_dirtytx + 1) & |
1661 | TX_RING_MOD_MASK(tx_ring_size); | |
1662 | ||
1663 | howmany++; | |
1664 | priv->num_txbdfree += frags + 1; | |
1665 | } | |
1da177e4 | 1666 | |
4669bc90 DH |
1667 | /* If we freed a buffer, we can restart transmission, if necessary */ |
1668 | if (netif_queue_stopped(dev) && priv->num_txbdfree) | |
1669 | netif_wake_queue(dev); | |
1da177e4 | 1670 | |
4669bc90 DH |
1671 | /* Update dirty indicators */ |
1672 | priv->skb_dirtytx = skb_dirtytx; | |
1673 | priv->dirty_tx = bdp; | |
1da177e4 | 1674 | |
d080cd63 DH |
1675 | dev->stats.tx_packets += howmany; |
1676 | ||
1677 | return howmany; | |
1678 | } | |
1679 | ||
8c7396ae | 1680 | static void gfar_schedule_cleanup(struct net_device *dev) |
d080cd63 | 1681 | { |
d080cd63 | 1682 | struct gfar_private *priv = netdev_priv(dev); |
a6d0b91a AV |
1683 | unsigned long flags; |
1684 | ||
1685 | spin_lock_irqsave(&priv->txlock, flags); | |
1686 | spin_lock(&priv->rxlock); | |
1687 | ||
288379f0 | 1688 | if (napi_schedule_prep(&priv->napi)) { |
8c7396ae | 1689 | gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED); |
288379f0 | 1690 | __napi_schedule(&priv->napi); |
8707bdd4 JP |
1691 | } else { |
1692 | /* | |
1693 | * Clear IEVENT, so interrupts aren't called again | |
1694 | * because of the packets that have already arrived. | |
1695 | */ | |
1696 | gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK); | |
2f448911 | 1697 | } |
a6d0b91a AV |
1698 | |
1699 | spin_unlock(&priv->rxlock); | |
1700 | spin_unlock_irqrestore(&priv->txlock, flags); | |
8c7396ae | 1701 | } |
1da177e4 | 1702 | |
8c7396ae DH |
1703 | /* Interrupt Handler for Transmit complete */ |
1704 | static irqreturn_t gfar_transmit(int irq, void *dev_id) | |
1705 | { | |
1706 | gfar_schedule_cleanup((struct net_device *)dev_id); | |
1da177e4 LT |
1707 | return IRQ_HANDLED; |
1708 | } | |
1709 | ||
815b97c6 AF |
1710 | static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp, |
1711 | struct sk_buff *skb) | |
1712 | { | |
1713 | struct gfar_private *priv = netdev_priv(dev); | |
5a5efed4 | 1714 | u32 lstatus; |
815b97c6 | 1715 | |
4826857f | 1716 | bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, |
815b97c6 AF |
1717 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
1718 | ||
5a5efed4 | 1719 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); |
815b97c6 AF |
1720 | |
1721 | if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1) | |
5a5efed4 | 1722 | lstatus |= BD_LFLAG(RXBD_WRAP); |
815b97c6 AF |
1723 | |
1724 | eieio(); | |
1725 | ||
5a5efed4 | 1726 | bdp->lstatus = lstatus; |
815b97c6 AF |
1727 | } |
1728 | ||
1729 | ||
1730 | struct sk_buff * gfar_new_skb(struct net_device *dev) | |
1da177e4 | 1731 | { |
7f7f5316 | 1732 | unsigned int alignamount; |
1da177e4 LT |
1733 | struct gfar_private *priv = netdev_priv(dev); |
1734 | struct sk_buff *skb = NULL; | |
1da177e4 | 1735 | |
0fd56bb5 AF |
1736 | skb = __skb_dequeue(&priv->rx_recycle); |
1737 | if (!skb) | |
1738 | skb = netdev_alloc_skb(dev, | |
1739 | priv->rx_buffer_size + RXBUF_ALIGNMENT); | |
1da177e4 | 1740 | |
815b97c6 | 1741 | if (!skb) |
1da177e4 LT |
1742 | return NULL; |
1743 | ||
7f7f5316 | 1744 | alignamount = RXBUF_ALIGNMENT - |
bea3348e | 1745 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)); |
7f7f5316 | 1746 | |
1da177e4 LT |
1747 | /* We need the data buffer to be aligned properly. We will reserve |
1748 | * as many bytes as needed to align the data properly | |
1749 | */ | |
7f7f5316 | 1750 | skb_reserve(skb, alignamount); |
1da177e4 | 1751 | |
1da177e4 LT |
1752 | return skb; |
1753 | } | |
1754 | ||
298e1a9e | 1755 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 1756 | { |
298e1a9e | 1757 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 1758 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
1759 | struct gfar_extra_stats *estats = &priv->extra_stats; |
1760 | ||
1761 | /* If the packet was truncated, none of the other errors | |
1762 | * matter */ | |
1763 | if (status & RXBD_TRUNCATED) { | |
1764 | stats->rx_length_errors++; | |
1765 | ||
1766 | estats->rx_trunc++; | |
1767 | ||
1768 | return; | |
1769 | } | |
1770 | /* Count the errors, if there were any */ | |
1771 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
1772 | stats->rx_length_errors++; | |
1773 | ||
1774 | if (status & RXBD_LARGE) | |
1775 | estats->rx_large++; | |
1776 | else | |
1777 | estats->rx_short++; | |
1778 | } | |
1779 | if (status & RXBD_NONOCTET) { | |
1780 | stats->rx_frame_errors++; | |
1781 | estats->rx_nonoctet++; | |
1782 | } | |
1783 | if (status & RXBD_CRCERR) { | |
1784 | estats->rx_crcerr++; | |
1785 | stats->rx_crc_errors++; | |
1786 | } | |
1787 | if (status & RXBD_OVERRUN) { | |
1788 | estats->rx_overrun++; | |
1789 | stats->rx_crc_errors++; | |
1790 | } | |
1791 | } | |
1792 | ||
7d12e780 | 1793 | irqreturn_t gfar_receive(int irq, void *dev_id) |
1da177e4 | 1794 | { |
8c7396ae | 1795 | gfar_schedule_cleanup((struct net_device *)dev_id); |
1da177e4 LT |
1796 | return IRQ_HANDLED; |
1797 | } | |
1798 | ||
0bbaf069 KG |
1799 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
1800 | { | |
1801 | /* If valid headers were found, and valid sums | |
1802 | * were verified, then we tell the kernel that no | |
1803 | * checksumming is necessary. Otherwise, it is */ | |
7f7f5316 | 1804 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
1805 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
1806 | else | |
1807 | skb->ip_summed = CHECKSUM_NONE; | |
1808 | } | |
1809 | ||
1810 | ||
1da177e4 LT |
1811 | /* gfar_process_frame() -- handle one incoming packet if skb |
1812 | * isn't NULL. */ | |
1813 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, | |
2c2db48a | 1814 | int amount_pull) |
1da177e4 LT |
1815 | { |
1816 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1817 | struct rxfcb *fcb = NULL; |
1da177e4 | 1818 | |
2c2db48a | 1819 | int ret; |
1da177e4 | 1820 | |
2c2db48a DH |
1821 | /* fcb is at the beginning if exists */ |
1822 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 1823 | |
2c2db48a DH |
1824 | /* Remove the FCB from the skb */ |
1825 | /* Remove the padded bytes, if there are any */ | |
1826 | if (amount_pull) | |
1827 | skb_pull(skb, amount_pull); | |
0bbaf069 | 1828 | |
2c2db48a DH |
1829 | if (priv->rx_csum_enable) |
1830 | gfar_rx_checksum(skb, fcb); | |
0bbaf069 | 1831 | |
2c2db48a DH |
1832 | /* Tell the skb what kind of packet this is */ |
1833 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 1834 | |
2c2db48a DH |
1835 | /* Send the packet up the stack */ |
1836 | if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) | |
1837 | ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl); | |
1838 | else | |
1839 | ret = netif_receive_skb(skb); | |
0bbaf069 | 1840 | |
2c2db48a DH |
1841 | if (NET_RX_DROP == ret) |
1842 | priv->extra_stats.kernel_dropped++; | |
1da177e4 LT |
1843 | |
1844 | return 0; | |
1845 | } | |
1846 | ||
1847 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
0bbaf069 | 1848 | * until the budget/quota has been reached. Returns the number |
1da177e4 LT |
1849 | * of frames handled |
1850 | */ | |
0bbaf069 | 1851 | int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit) |
1da177e4 | 1852 | { |
31de198b | 1853 | struct rxbd8 *bdp, *base; |
1da177e4 | 1854 | struct sk_buff *skb; |
2c2db48a DH |
1855 | int pkt_len; |
1856 | int amount_pull; | |
1da177e4 LT |
1857 | int howmany = 0; |
1858 | struct gfar_private *priv = netdev_priv(dev); | |
1859 | ||
1860 | /* Get the first full descriptor */ | |
1861 | bdp = priv->cur_rx; | |
31de198b | 1862 | base = priv->rx_bd_base; |
1da177e4 | 1863 | |
2c2db48a DH |
1864 | amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) + |
1865 | priv->padding; | |
1866 | ||
1da177e4 | 1867 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 1868 | struct sk_buff *newskb; |
3b6330ce | 1869 | rmb(); |
815b97c6 AF |
1870 | |
1871 | /* Add another skb for the future */ | |
1872 | newskb = gfar_new_skb(dev); | |
1873 | ||
1da177e4 LT |
1874 | skb = priv->rx_skbuff[priv->skb_currx]; |
1875 | ||
4826857f | 1876 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, |
81183059 AF |
1877 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
1878 | ||
815b97c6 AF |
1879 | /* We drop the frame if we failed to allocate a new buffer */ |
1880 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
1881 | bdp->status & RXBD_ERR)) { | |
1882 | count_errors(bdp->status, dev); | |
1883 | ||
1884 | if (unlikely(!newskb)) | |
1885 | newskb = skb; | |
8882d9a6 | 1886 | else if (skb) |
0fd56bb5 | 1887 | __skb_queue_head(&priv->rx_recycle, skb); |
815b97c6 | 1888 | } else { |
1da177e4 | 1889 | /* Increment the number of packets */ |
09f75cd7 | 1890 | dev->stats.rx_packets++; |
1da177e4 LT |
1891 | howmany++; |
1892 | ||
2c2db48a DH |
1893 | if (likely(skb)) { |
1894 | pkt_len = bdp->length - ETH_FCS_LEN; | |
1895 | /* Remove the FCS from the packet length */ | |
1896 | skb_put(skb, pkt_len); | |
1897 | dev->stats.rx_bytes += pkt_len; | |
1da177e4 | 1898 | |
1577ecef AF |
1899 | if (in_irq() || irqs_disabled()) |
1900 | printk("Interrupt problem!\n"); | |
2c2db48a DH |
1901 | gfar_process_frame(dev, skb, amount_pull); |
1902 | ||
1903 | } else { | |
1904 | if (netif_msg_rx_err(priv)) | |
1905 | printk(KERN_WARNING | |
1906 | "%s: Missing skb!\n", dev->name); | |
1907 | dev->stats.rx_dropped++; | |
1908 | priv->extra_stats.rx_skbmissing++; | |
1909 | } | |
1da177e4 | 1910 | |
1da177e4 LT |
1911 | } |
1912 | ||
815b97c6 | 1913 | priv->rx_skbuff[priv->skb_currx] = newskb; |
1da177e4 | 1914 | |
815b97c6 AF |
1915 | /* Setup the new bdp */ |
1916 | gfar_new_rxbdp(dev, bdp, newskb); | |
1da177e4 LT |
1917 | |
1918 | /* Update to the next pointer */ | |
31de198b | 1919 | bdp = next_bd(bdp, base, priv->rx_ring_size); |
1da177e4 LT |
1920 | |
1921 | /* update to point at the next skb */ | |
1922 | priv->skb_currx = | |
815b97c6 AF |
1923 | (priv->skb_currx + 1) & |
1924 | RX_RING_MOD_MASK(priv->rx_ring_size); | |
1da177e4 LT |
1925 | } |
1926 | ||
1927 | /* Update the current rxbd pointer to be the next one */ | |
1928 | priv->cur_rx = bdp; | |
1929 | ||
1da177e4 LT |
1930 | return howmany; |
1931 | } | |
1932 | ||
bea3348e | 1933 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 1934 | { |
bea3348e | 1935 | struct gfar_private *priv = container_of(napi, struct gfar_private, napi); |
4826857f | 1936 | struct net_device *dev = priv->ndev; |
42199884 AF |
1937 | int tx_cleaned = 0; |
1938 | int rx_cleaned = 0; | |
d080cd63 DH |
1939 | unsigned long flags; |
1940 | ||
8c7396ae DH |
1941 | /* Clear IEVENT, so interrupts aren't called again |
1942 | * because of the packets that have already arrived */ | |
1943 | gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK); | |
1944 | ||
d080cd63 DH |
1945 | /* If we fail to get the lock, don't bother with the TX BDs */ |
1946 | if (spin_trylock_irqsave(&priv->txlock, flags)) { | |
42199884 | 1947 | tx_cleaned = gfar_clean_tx_ring(dev); |
d080cd63 DH |
1948 | spin_unlock_irqrestore(&priv->txlock, flags); |
1949 | } | |
1da177e4 | 1950 | |
42199884 | 1951 | rx_cleaned = gfar_clean_rx_ring(dev, budget); |
1da177e4 | 1952 | |
42199884 AF |
1953 | if (tx_cleaned) |
1954 | return budget; | |
1955 | ||
1956 | if (rx_cleaned < budget) { | |
288379f0 | 1957 | napi_complete(napi); |
1da177e4 LT |
1958 | |
1959 | /* Clear the halt bit in RSTAT */ | |
1960 | gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT); | |
1961 | ||
1962 | gfar_write(&priv->regs->imask, IMASK_DEFAULT); | |
1963 | ||
1964 | /* If we are coalescing interrupts, update the timer */ | |
1965 | /* Otherwise, clear it */ | |
2f448911 AF |
1966 | if (likely(priv->rxcoalescing)) { |
1967 | gfar_write(&priv->regs->rxic, 0); | |
b46a8454 | 1968 | gfar_write(&priv->regs->rxic, priv->rxic); |
2f448911 | 1969 | } |
8c7396ae DH |
1970 | if (likely(priv->txcoalescing)) { |
1971 | gfar_write(&priv->regs->txic, 0); | |
1972 | gfar_write(&priv->regs->txic, priv->txic); | |
1973 | } | |
1da177e4 LT |
1974 | } |
1975 | ||
42199884 | 1976 | return rx_cleaned; |
1da177e4 | 1977 | } |
1da177e4 | 1978 | |
f2d71c2d VW |
1979 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1980 | /* | |
1981 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
1982 | * without having to re-enable interrupts. It's not called while | |
1983 | * the interrupt routine is executing. | |
1984 | */ | |
1985 | static void gfar_netpoll(struct net_device *dev) | |
1986 | { | |
1987 | struct gfar_private *priv = netdev_priv(dev); | |
1988 | ||
1989 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 1990 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
f2d71c2d VW |
1991 | disable_irq(priv->interruptTransmit); |
1992 | disable_irq(priv->interruptReceive); | |
1993 | disable_irq(priv->interruptError); | |
1994 | gfar_interrupt(priv->interruptTransmit, dev); | |
1995 | enable_irq(priv->interruptError); | |
1996 | enable_irq(priv->interruptReceive); | |
1997 | enable_irq(priv->interruptTransmit); | |
1998 | } else { | |
1999 | disable_irq(priv->interruptTransmit); | |
2000 | gfar_interrupt(priv->interruptTransmit, dev); | |
2001 | enable_irq(priv->interruptTransmit); | |
2002 | } | |
2003 | } | |
2004 | #endif | |
2005 | ||
1da177e4 | 2006 | /* The interrupt handler for devices with one interrupt */ |
7d12e780 | 2007 | static irqreturn_t gfar_interrupt(int irq, void *dev_id) |
1da177e4 LT |
2008 | { |
2009 | struct net_device *dev = dev_id; | |
2010 | struct gfar_private *priv = netdev_priv(dev); | |
2011 | ||
2012 | /* Save ievent for future reference */ | |
2013 | u32 events = gfar_read(&priv->regs->ievent); | |
2014 | ||
1da177e4 | 2015 | /* Check for reception */ |
538cc7ee | 2016 | if (events & IEVENT_RX_MASK) |
7d12e780 | 2017 | gfar_receive(irq, dev_id); |
1da177e4 LT |
2018 | |
2019 | /* Check for transmit completion */ | |
538cc7ee | 2020 | if (events & IEVENT_TX_MASK) |
7d12e780 | 2021 | gfar_transmit(irq, dev_id); |
1da177e4 | 2022 | |
538cc7ee SS |
2023 | /* Check for errors */ |
2024 | if (events & IEVENT_ERR_MASK) | |
2025 | gfar_error(irq, dev_id); | |
1da177e4 LT |
2026 | |
2027 | return IRQ_HANDLED; | |
2028 | } | |
2029 | ||
1da177e4 LT |
2030 | /* Called every time the controller might need to be made |
2031 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 2032 | * information through variables in the phydev structure, and this |
1da177e4 LT |
2033 | * function converts those variables into the appropriate |
2034 | * register values, and can bring down the device if needed. | |
2035 | */ | |
2036 | static void adjust_link(struct net_device *dev) | |
2037 | { | |
2038 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 2039 | struct gfar __iomem *regs = priv->regs; |
bb40dcbb AF |
2040 | unsigned long flags; |
2041 | struct phy_device *phydev = priv->phydev; | |
2042 | int new_state = 0; | |
2043 | ||
fef6108d | 2044 | spin_lock_irqsave(&priv->txlock, flags); |
bb40dcbb AF |
2045 | if (phydev->link) { |
2046 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 2047 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 2048 | |
1da177e4 LT |
2049 | /* Now we make sure that we can be in full duplex mode. |
2050 | * If not, we operate in half-duplex mode. */ | |
bb40dcbb AF |
2051 | if (phydev->duplex != priv->oldduplex) { |
2052 | new_state = 1; | |
2053 | if (!(phydev->duplex)) | |
1da177e4 | 2054 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 2055 | else |
1da177e4 | 2056 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 2057 | |
bb40dcbb | 2058 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
2059 | } |
2060 | ||
bb40dcbb AF |
2061 | if (phydev->speed != priv->oldspeed) { |
2062 | new_state = 1; | |
2063 | switch (phydev->speed) { | |
1da177e4 | 2064 | case 1000: |
1da177e4 LT |
2065 | tempval = |
2066 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
2067 | |
2068 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2069 | break; |
2070 | case 100: | |
2071 | case 10: | |
1da177e4 LT |
2072 | tempval = |
2073 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
2074 | |
2075 | /* Reduced mode distinguishes | |
2076 | * between 10 and 100 */ | |
2077 | if (phydev->speed == SPEED_100) | |
2078 | ecntrl |= ECNTRL_R100; | |
2079 | else | |
2080 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2081 | break; |
2082 | default: | |
0bbaf069 KG |
2083 | if (netif_msg_link(priv)) |
2084 | printk(KERN_WARNING | |
bb40dcbb AF |
2085 | "%s: Ack! Speed (%d) is not 10/100/1000!\n", |
2086 | dev->name, phydev->speed); | |
1da177e4 LT |
2087 | break; |
2088 | } | |
2089 | ||
bb40dcbb | 2090 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
2091 | } |
2092 | ||
bb40dcbb | 2093 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 2094 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 2095 | |
1da177e4 | 2096 | if (!priv->oldlink) { |
bb40dcbb | 2097 | new_state = 1; |
1da177e4 | 2098 | priv->oldlink = 1; |
1da177e4 | 2099 | } |
bb40dcbb AF |
2100 | } else if (priv->oldlink) { |
2101 | new_state = 1; | |
2102 | priv->oldlink = 0; | |
2103 | priv->oldspeed = 0; | |
2104 | priv->oldduplex = -1; | |
1da177e4 | 2105 | } |
1da177e4 | 2106 | |
bb40dcbb AF |
2107 | if (new_state && netif_msg_link(priv)) |
2108 | phy_print_status(phydev); | |
2109 | ||
fef6108d | 2110 | spin_unlock_irqrestore(&priv->txlock, flags); |
bb40dcbb | 2111 | } |
1da177e4 LT |
2112 | |
2113 | /* Update the hash table based on the current list of multicast | |
2114 | * addresses we subscribe to. Also, change the promiscuity of | |
2115 | * the device based on the flags (this function is called | |
2116 | * whenever dev->flags is changed */ | |
2117 | static void gfar_set_multi(struct net_device *dev) | |
2118 | { | |
2119 | struct dev_mc_list *mc_ptr; | |
2120 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 2121 | struct gfar __iomem *regs = priv->regs; |
1da177e4 LT |
2122 | u32 tempval; |
2123 | ||
2124 | if(dev->flags & IFF_PROMISC) { | |
1da177e4 LT |
2125 | /* Set RCTRL to PROM */ |
2126 | tempval = gfar_read(®s->rctrl); | |
2127 | tempval |= RCTRL_PROM; | |
2128 | gfar_write(®s->rctrl, tempval); | |
2129 | } else { | |
2130 | /* Set RCTRL to not PROM */ | |
2131 | tempval = gfar_read(®s->rctrl); | |
2132 | tempval &= ~(RCTRL_PROM); | |
2133 | gfar_write(®s->rctrl, tempval); | |
2134 | } | |
6aa20a22 | 2135 | |
1da177e4 LT |
2136 | if(dev->flags & IFF_ALLMULTI) { |
2137 | /* Set the hash to rx all multicast frames */ | |
0bbaf069 KG |
2138 | gfar_write(®s->igaddr0, 0xffffffff); |
2139 | gfar_write(®s->igaddr1, 0xffffffff); | |
2140 | gfar_write(®s->igaddr2, 0xffffffff); | |
2141 | gfar_write(®s->igaddr3, 0xffffffff); | |
2142 | gfar_write(®s->igaddr4, 0xffffffff); | |
2143 | gfar_write(®s->igaddr5, 0xffffffff); | |
2144 | gfar_write(®s->igaddr6, 0xffffffff); | |
2145 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
2146 | gfar_write(®s->gaddr0, 0xffffffff); |
2147 | gfar_write(®s->gaddr1, 0xffffffff); | |
2148 | gfar_write(®s->gaddr2, 0xffffffff); | |
2149 | gfar_write(®s->gaddr3, 0xffffffff); | |
2150 | gfar_write(®s->gaddr4, 0xffffffff); | |
2151 | gfar_write(®s->gaddr5, 0xffffffff); | |
2152 | gfar_write(®s->gaddr6, 0xffffffff); | |
2153 | gfar_write(®s->gaddr7, 0xffffffff); | |
2154 | } else { | |
7f7f5316 AF |
2155 | int em_num; |
2156 | int idx; | |
2157 | ||
1da177e4 | 2158 | /* zero out the hash */ |
0bbaf069 KG |
2159 | gfar_write(®s->igaddr0, 0x0); |
2160 | gfar_write(®s->igaddr1, 0x0); | |
2161 | gfar_write(®s->igaddr2, 0x0); | |
2162 | gfar_write(®s->igaddr3, 0x0); | |
2163 | gfar_write(®s->igaddr4, 0x0); | |
2164 | gfar_write(®s->igaddr5, 0x0); | |
2165 | gfar_write(®s->igaddr6, 0x0); | |
2166 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
2167 | gfar_write(®s->gaddr0, 0x0); |
2168 | gfar_write(®s->gaddr1, 0x0); | |
2169 | gfar_write(®s->gaddr2, 0x0); | |
2170 | gfar_write(®s->gaddr3, 0x0); | |
2171 | gfar_write(®s->gaddr4, 0x0); | |
2172 | gfar_write(®s->gaddr5, 0x0); | |
2173 | gfar_write(®s->gaddr6, 0x0); | |
2174 | gfar_write(®s->gaddr7, 0x0); | |
2175 | ||
7f7f5316 AF |
2176 | /* If we have extended hash tables, we need to |
2177 | * clear the exact match registers to prepare for | |
2178 | * setting them */ | |
2179 | if (priv->extended_hash) { | |
2180 | em_num = GFAR_EM_NUM + 1; | |
2181 | gfar_clear_exact_match(dev); | |
2182 | idx = 1; | |
2183 | } else { | |
2184 | idx = 0; | |
2185 | em_num = 0; | |
2186 | } | |
2187 | ||
1da177e4 LT |
2188 | if(dev->mc_count == 0) |
2189 | return; | |
2190 | ||
2191 | /* Parse the list, and set the appropriate bits */ | |
2192 | for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) { | |
7f7f5316 AF |
2193 | if (idx < em_num) { |
2194 | gfar_set_mac_for_addr(dev, idx, | |
2195 | mc_ptr->dmi_addr); | |
2196 | idx++; | |
2197 | } else | |
2198 | gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr); | |
1da177e4 LT |
2199 | } |
2200 | } | |
2201 | ||
2202 | return; | |
2203 | } | |
2204 | ||
7f7f5316 AF |
2205 | |
2206 | /* Clears each of the exact match registers to zero, so they | |
2207 | * don't interfere with normal reception */ | |
2208 | static void gfar_clear_exact_match(struct net_device *dev) | |
2209 | { | |
2210 | int idx; | |
2211 | u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0}; | |
2212 | ||
2213 | for(idx = 1;idx < GFAR_EM_NUM + 1;idx++) | |
2214 | gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr); | |
2215 | } | |
2216 | ||
1da177e4 LT |
2217 | /* Set the appropriate hash bit for the given addr */ |
2218 | /* The algorithm works like so: | |
2219 | * 1) Take the Destination Address (ie the multicast address), and | |
2220 | * do a CRC on it (little endian), and reverse the bits of the | |
2221 | * result. | |
2222 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
2223 | * table. The table is controlled through 8 32-bit registers: | |
2224 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
2225 | * gaddr7. This means that the 3 most significant bits in the | |
2226 | * hash index which gaddr register to use, and the 5 other bits | |
2227 | * indicate which bit (assuming an IBM numbering scheme, which | |
2228 | * for PowerPC (tm) is usually the case) in the register holds | |
2229 | * the entry. */ | |
2230 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) | |
2231 | { | |
2232 | u32 tempval; | |
2233 | struct gfar_private *priv = netdev_priv(dev); | |
1da177e4 | 2234 | u32 result = ether_crc(MAC_ADDR_LEN, addr); |
0bbaf069 KG |
2235 | int width = priv->hash_width; |
2236 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
2237 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
2238 | u32 value = (1 << (31-whichbit)); |
2239 | ||
0bbaf069 | 2240 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 2241 | tempval |= value; |
0bbaf069 | 2242 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
2243 | |
2244 | return; | |
2245 | } | |
2246 | ||
7f7f5316 AF |
2247 | |
2248 | /* There are multiple MAC Address register pairs on some controllers | |
2249 | * This function sets the numth pair to a given address | |
2250 | */ | |
2251 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr) | |
2252 | { | |
2253 | struct gfar_private *priv = netdev_priv(dev); | |
2254 | int idx; | |
2255 | char tmpbuf[MAC_ADDR_LEN]; | |
2256 | u32 tempval; | |
cc8c6e37 | 2257 | u32 __iomem *macptr = &priv->regs->macstnaddr1; |
7f7f5316 AF |
2258 | |
2259 | macptr += num*2; | |
2260 | ||
2261 | /* Now copy it into the mac registers backwards, cuz */ | |
2262 | /* little endian is silly */ | |
2263 | for (idx = 0; idx < MAC_ADDR_LEN; idx++) | |
2264 | tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx]; | |
2265 | ||
2266 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
2267 | ||
2268 | tempval = *((u32 *) (tmpbuf + 4)); | |
2269 | ||
2270 | gfar_write(macptr+1, tempval); | |
2271 | } | |
2272 | ||
1da177e4 | 2273 | /* GFAR error interrupt handler */ |
7d12e780 | 2274 | static irqreturn_t gfar_error(int irq, void *dev_id) |
1da177e4 LT |
2275 | { |
2276 | struct net_device *dev = dev_id; | |
2277 | struct gfar_private *priv = netdev_priv(dev); | |
2278 | ||
2279 | /* Save ievent for future reference */ | |
2280 | u32 events = gfar_read(&priv->regs->ievent); | |
2281 | ||
2282 | /* Clear IEVENT */ | |
d87eb127 SW |
2283 | gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK); |
2284 | ||
2285 | /* Magic Packet is not an error. */ | |
b31a1d8b | 2286 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
2287 | (events & IEVENT_MAG)) |
2288 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
2289 | |
2290 | /* Hmm... */ | |
0bbaf069 KG |
2291 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
2292 | printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
538cc7ee | 2293 | dev->name, events, gfar_read(&priv->regs->imask)); |
1da177e4 LT |
2294 | |
2295 | /* Update the error counters */ | |
2296 | if (events & IEVENT_TXE) { | |
09f75cd7 | 2297 | dev->stats.tx_errors++; |
1da177e4 LT |
2298 | |
2299 | if (events & IEVENT_LC) | |
09f75cd7 | 2300 | dev->stats.tx_window_errors++; |
1da177e4 | 2301 | if (events & IEVENT_CRL) |
09f75cd7 | 2302 | dev->stats.tx_aborted_errors++; |
1da177e4 | 2303 | if (events & IEVENT_XFUN) { |
0bbaf069 | 2304 | if (netif_msg_tx_err(priv)) |
538cc7ee SS |
2305 | printk(KERN_DEBUG "%s: TX FIFO underrun, " |
2306 | "packet dropped.\n", dev->name); | |
09f75cd7 | 2307 | dev->stats.tx_dropped++; |
1da177e4 LT |
2308 | priv->extra_stats.tx_underrun++; |
2309 | ||
2310 | /* Reactivate the Tx Queues */ | |
2311 | gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT); | |
2312 | } | |
0bbaf069 KG |
2313 | if (netif_msg_tx_err(priv)) |
2314 | printk(KERN_DEBUG "%s: Transmit Error\n", dev->name); | |
1da177e4 LT |
2315 | } |
2316 | if (events & IEVENT_BSY) { | |
09f75cd7 | 2317 | dev->stats.rx_errors++; |
1da177e4 LT |
2318 | priv->extra_stats.rx_bsy++; |
2319 | ||
7d12e780 | 2320 | gfar_receive(irq, dev_id); |
1da177e4 | 2321 | |
0bbaf069 | 2322 | if (netif_msg_rx_err(priv)) |
538cc7ee SS |
2323 | printk(KERN_DEBUG "%s: busy error (rstat: %x)\n", |
2324 | dev->name, gfar_read(&priv->regs->rstat)); | |
1da177e4 LT |
2325 | } |
2326 | if (events & IEVENT_BABR) { | |
09f75cd7 | 2327 | dev->stats.rx_errors++; |
1da177e4 LT |
2328 | priv->extra_stats.rx_babr++; |
2329 | ||
0bbaf069 | 2330 | if (netif_msg_rx_err(priv)) |
538cc7ee | 2331 | printk(KERN_DEBUG "%s: babbling RX error\n", dev->name); |
1da177e4 LT |
2332 | } |
2333 | if (events & IEVENT_EBERR) { | |
2334 | priv->extra_stats.eberr++; | |
0bbaf069 | 2335 | if (netif_msg_rx_err(priv)) |
538cc7ee | 2336 | printk(KERN_DEBUG "%s: bus error\n", dev->name); |
1da177e4 | 2337 | } |
0bbaf069 | 2338 | if ((events & IEVENT_RXC) && netif_msg_rx_status(priv)) |
538cc7ee | 2339 | printk(KERN_DEBUG "%s: control frame\n", dev->name); |
1da177e4 LT |
2340 | |
2341 | if (events & IEVENT_BABT) { | |
2342 | priv->extra_stats.tx_babt++; | |
0bbaf069 | 2343 | if (netif_msg_tx_err(priv)) |
538cc7ee | 2344 | printk(KERN_DEBUG "%s: babbling TX error\n", dev->name); |
1da177e4 LT |
2345 | } |
2346 | return IRQ_HANDLED; | |
2347 | } | |
2348 | ||
72abb461 KS |
2349 | /* work with hotplug and coldplug */ |
2350 | MODULE_ALIAS("platform:fsl-gianfar"); | |
2351 | ||
b31a1d8b AF |
2352 | static struct of_device_id gfar_match[] = |
2353 | { | |
2354 | { | |
2355 | .type = "network", | |
2356 | .compatible = "gianfar", | |
2357 | }, | |
2358 | {}, | |
2359 | }; | |
2360 | ||
1da177e4 | 2361 | /* Structure for a device driver */ |
b31a1d8b AF |
2362 | static struct of_platform_driver gfar_driver = { |
2363 | .name = "fsl-gianfar", | |
2364 | .match_table = gfar_match, | |
2365 | ||
1da177e4 LT |
2366 | .probe = gfar_probe, |
2367 | .remove = gfar_remove, | |
d87eb127 SW |
2368 | .suspend = gfar_suspend, |
2369 | .resume = gfar_resume, | |
1da177e4 LT |
2370 | }; |
2371 | ||
2372 | static int __init gfar_init(void) | |
2373 | { | |
1577ecef | 2374 | return of_register_platform_driver(&gfar_driver); |
1da177e4 LT |
2375 | } |
2376 | ||
2377 | static void __exit gfar_exit(void) | |
2378 | { | |
b31a1d8b | 2379 | of_unregister_platform_driver(&gfar_driver); |
1da177e4 LT |
2380 | } |
2381 | ||
2382 | module_init(gfar_init); | |
2383 | module_exit(gfar_exit); | |
2384 |