Commit | Line | Data |
---|---|---|
0bbaf069 | 1 | /* |
1da177e4 LT |
2 | * drivers/net/gianfar.c |
3 | * | |
4 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
5 | * This driver is designed for the non-CPM ethernet controllers |
6 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
7 | * Based on 8260_io/fcc_enet.c |
8 | * | |
9 | * Author: Andy Fleming | |
4c8d3d99 | 10 | * Maintainer: Kumar Gala |
1da177e4 | 11 | * |
e8a2b6a4 | 12 | * Copyright (c) 2002-2006 Freescale Semiconductor, Inc. |
538cc7ee | 13 | * Copyright (c) 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
1da177e4 | 64 | #include <linux/kernel.h> |
1da177e4 LT |
65 | #include <linux/string.h> |
66 | #include <linux/errno.h> | |
bb40dcbb | 67 | #include <linux/unistd.h> |
1da177e4 LT |
68 | #include <linux/slab.h> |
69 | #include <linux/interrupt.h> | |
70 | #include <linux/init.h> | |
71 | #include <linux/delay.h> | |
72 | #include <linux/netdevice.h> | |
73 | #include <linux/etherdevice.h> | |
74 | #include <linux/skbuff.h> | |
0bbaf069 | 75 | #include <linux/if_vlan.h> |
1da177e4 LT |
76 | #include <linux/spinlock.h> |
77 | #include <linux/mm.h> | |
fe192a49 | 78 | #include <linux/of_mdio.h> |
b31a1d8b | 79 | #include <linux/of_platform.h> |
0bbaf069 KG |
80 | #include <linux/ip.h> |
81 | #include <linux/tcp.h> | |
82 | #include <linux/udp.h> | |
9c07b884 | 83 | #include <linux/in.h> |
1da177e4 LT |
84 | |
85 | #include <asm/io.h> | |
86 | #include <asm/irq.h> | |
87 | #include <asm/uaccess.h> | |
88 | #include <linux/module.h> | |
1da177e4 LT |
89 | #include <linux/dma-mapping.h> |
90 | #include <linux/crc32.h> | |
bb40dcbb AF |
91 | #include <linux/mii.h> |
92 | #include <linux/phy.h> | |
b31a1d8b AF |
93 | #include <linux/phy_fixed.h> |
94 | #include <linux/of.h> | |
1da177e4 LT |
95 | |
96 | #include "gianfar.h" | |
1577ecef | 97 | #include "fsl_pq_mdio.h" |
1da177e4 LT |
98 | |
99 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 LT |
100 | #undef BRIEF_GFAR_ERRORS |
101 | #undef VERBOSE_GFAR_ERRORS | |
102 | ||
1da177e4 | 103 | const char gfar_driver_name[] = "Gianfar Ethernet"; |
7f7f5316 | 104 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 105 | |
1da177e4 LT |
106 | static int gfar_enet_open(struct net_device *dev); |
107 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 108 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
109 | static void gfar_timeout(struct net_device *dev); |
110 | static int gfar_close(struct net_device *dev); | |
815b97c6 AF |
111 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
112 | static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp, | |
113 | struct sk_buff *skb); | |
1da177e4 LT |
114 | static int gfar_set_mac_address(struct net_device *dev); |
115 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
116 | static irqreturn_t gfar_error(int irq, void *dev_id); |
117 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
118 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
119 | static void adjust_link(struct net_device *dev); |
120 | static void init_registers(struct net_device *dev); | |
121 | static int init_phy(struct net_device *dev); | |
b31a1d8b AF |
122 | static int gfar_probe(struct of_device *ofdev, |
123 | const struct of_device_id *match); | |
124 | static int gfar_remove(struct of_device *ofdev); | |
bb40dcbb | 125 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
126 | static void gfar_set_multi(struct net_device *dev); |
127 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 128 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 129 | static int gfar_poll(struct napi_struct *napi, int budget); |
f2d71c2d VW |
130 | #ifdef CONFIG_NET_POLL_CONTROLLER |
131 | static void gfar_netpoll(struct net_device *dev); | |
132 | #endif | |
0bbaf069 | 133 | int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit); |
f162b9d5 | 134 | static int gfar_clean_tx_ring(struct net_device *dev); |
2c2db48a DH |
135 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
136 | int amount_pull); | |
0bbaf069 KG |
137 | static void gfar_vlan_rx_register(struct net_device *netdev, |
138 | struct vlan_group *grp); | |
7f7f5316 | 139 | void gfar_halt(struct net_device *dev); |
d87eb127 | 140 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
141 | void gfar_start(struct net_device *dev); |
142 | static void gfar_clear_exact_match(struct net_device *dev); | |
143 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr); | |
26ccfc37 | 144 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 145 | |
1da177e4 LT |
146 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
147 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
148 | MODULE_LICENSE("GPL"); | |
149 | ||
826aa4a0 AV |
150 | static int gfar_alloc_skb_resources(struct net_device *ndev) |
151 | { | |
152 | struct txbd8 *txbdp; | |
153 | struct rxbd8 *rxbdp; | |
826aa4a0 AV |
154 | void *vaddr; |
155 | int i; | |
156 | struct gfar_private *priv = netdev_priv(ndev); | |
157 | struct device *dev = &priv->ofdev->dev; | |
826aa4a0 AV |
158 | |
159 | /* Allocate memory for the buffer descriptors */ | |
160 | vaddr = dma_alloc_coherent(dev, sizeof(*txbdp) * priv->tx_ring_size + | |
161 | sizeof(*rxbdp) * priv->rx_ring_size, | |
32c513bc | 162 | &priv->tx_bd_dma_base, GFP_KERNEL); |
826aa4a0 AV |
163 | if (!vaddr) { |
164 | if (netif_msg_ifup(priv)) | |
165 | pr_err("%s: Could not allocate buffer descriptors!\n", | |
166 | ndev->name); | |
167 | return -ENOMEM; | |
168 | } | |
169 | ||
170 | priv->tx_bd_base = vaddr; | |
171 | ||
826aa4a0 | 172 | /* Start the rx descriptor ring where the tx ring leaves off */ |
826aa4a0 AV |
173 | vaddr = vaddr + sizeof(*txbdp) * priv->tx_ring_size; |
174 | priv->rx_bd_base = vaddr; | |
826aa4a0 AV |
175 | |
176 | /* Setup the skbuff rings */ | |
177 | priv->tx_skbuff = kmalloc(sizeof(*priv->tx_skbuff) * | |
178 | priv->tx_ring_size, GFP_KERNEL); | |
179 | if (!priv->tx_skbuff) { | |
180 | if (netif_msg_ifup(priv)) | |
181 | pr_err("%s: Could not allocate tx_skbuff\n", | |
182 | ndev->name); | |
183 | goto cleanup; | |
184 | } | |
185 | ||
186 | for (i = 0; i < priv->tx_ring_size; i++) | |
187 | priv->tx_skbuff[i] = NULL; | |
188 | ||
189 | priv->rx_skbuff = kmalloc(sizeof(*priv->rx_skbuff) * | |
190 | priv->rx_ring_size, GFP_KERNEL); | |
191 | if (!priv->rx_skbuff) { | |
192 | if (netif_msg_ifup(priv)) | |
193 | pr_err("%s: Could not allocate rx_skbuff\n", | |
194 | ndev->name); | |
195 | goto cleanup; | |
196 | } | |
197 | ||
198 | for (i = 0; i < priv->rx_ring_size; i++) | |
199 | priv->rx_skbuff[i] = NULL; | |
200 | ||
201 | /* Initialize some variables in our dev structure */ | |
202 | priv->num_txbdfree = priv->tx_ring_size; | |
203 | priv->dirty_tx = priv->cur_tx = priv->tx_bd_base; | |
204 | priv->cur_rx = priv->rx_bd_base; | |
205 | priv->skb_curtx = priv->skb_dirtytx = 0; | |
206 | priv->skb_currx = 0; | |
207 | ||
208 | /* Initialize Transmit Descriptor Ring */ | |
209 | txbdp = priv->tx_bd_base; | |
210 | for (i = 0; i < priv->tx_ring_size; i++) { | |
211 | txbdp->lstatus = 0; | |
212 | txbdp->bufPtr = 0; | |
213 | txbdp++; | |
214 | } | |
215 | ||
216 | /* Set the last descriptor in the ring to indicate wrap */ | |
217 | txbdp--; | |
218 | txbdp->status |= TXBD_WRAP; | |
219 | ||
220 | rxbdp = priv->rx_bd_base; | |
221 | for (i = 0; i < priv->rx_ring_size; i++) { | |
222 | struct sk_buff *skb; | |
223 | ||
224 | skb = gfar_new_skb(ndev); | |
225 | if (!skb) { | |
226 | pr_err("%s: Can't allocate RX buffers\n", ndev->name); | |
227 | goto cleanup; | |
228 | } | |
229 | ||
230 | priv->rx_skbuff[i] = skb; | |
231 | ||
232 | gfar_new_rxbdp(ndev, rxbdp, skb); | |
233 | ||
234 | rxbdp++; | |
235 | } | |
236 | ||
237 | return 0; | |
238 | ||
239 | cleanup: | |
240 | free_skb_resources(priv); | |
241 | return -ENOMEM; | |
242 | } | |
243 | ||
244 | static void gfar_init_mac(struct net_device *ndev) | |
245 | { | |
246 | struct gfar_private *priv = netdev_priv(ndev); | |
247 | struct gfar __iomem *regs = priv->regs; | |
248 | u32 rctrl = 0; | |
249 | u32 tctrl = 0; | |
250 | u32 attrs = 0; | |
251 | ||
32c513bc AV |
252 | /* enet DMA only understands physical addresses */ |
253 | gfar_write(®s->tbase0, priv->tx_bd_dma_base); | |
254 | gfar_write(®s->rbase0, priv->tx_bd_dma_base + | |
255 | sizeof(*priv->tx_bd_base) * | |
256 | priv->tx_ring_size); | |
257 | ||
826aa4a0 AV |
258 | /* Configure the coalescing support */ |
259 | gfar_write(®s->txic, 0); | |
260 | if (priv->txcoalescing) | |
261 | gfar_write(®s->txic, priv->txic); | |
262 | ||
263 | gfar_write(®s->rxic, 0); | |
264 | if (priv->rxcoalescing) | |
265 | gfar_write(®s->rxic, priv->rxic); | |
266 | ||
267 | if (priv->rx_csum_enable) | |
268 | rctrl |= RCTRL_CHECKSUMMING; | |
269 | ||
270 | if (priv->extended_hash) { | |
271 | rctrl |= RCTRL_EXTHASH; | |
272 | ||
273 | gfar_clear_exact_match(ndev); | |
274 | rctrl |= RCTRL_EMEN; | |
275 | } | |
276 | ||
277 | if (priv->padding) { | |
278 | rctrl &= ~RCTRL_PAL_MASK; | |
279 | rctrl |= RCTRL_PADDING(priv->padding); | |
280 | } | |
281 | ||
282 | /* keep vlan related bits if it's enabled */ | |
283 | if (priv->vlgrp) { | |
284 | rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; | |
285 | tctrl |= TCTRL_VLINS; | |
286 | } | |
287 | ||
288 | /* Init rctrl based on our settings */ | |
289 | gfar_write(®s->rctrl, rctrl); | |
290 | ||
291 | if (ndev->features & NETIF_F_IP_CSUM) | |
292 | tctrl |= TCTRL_INIT_CSUM; | |
293 | ||
294 | gfar_write(®s->tctrl, tctrl); | |
295 | ||
296 | /* Set the extraction length and index */ | |
297 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
298 | ATTRELI_EI(priv->rx_stash_index); | |
299 | ||
300 | gfar_write(®s->attreli, attrs); | |
301 | ||
302 | /* Start with defaults, and add stashing or locking | |
303 | * depending on the approprate variables */ | |
304 | attrs = ATTR_INIT_SETTINGS; | |
305 | ||
306 | if (priv->bd_stash_en) | |
307 | attrs |= ATTR_BDSTASH; | |
308 | ||
309 | if (priv->rx_stash_size != 0) | |
310 | attrs |= ATTR_BUFSTASH; | |
311 | ||
312 | gfar_write(®s->attr, attrs); | |
313 | ||
314 | gfar_write(®s->fifo_tx_thr, priv->fifo_threshold); | |
315 | gfar_write(®s->fifo_tx_starve, priv->fifo_starve); | |
316 | gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
317 | } | |
318 | ||
26ccfc37 AF |
319 | static const struct net_device_ops gfar_netdev_ops = { |
320 | .ndo_open = gfar_enet_open, | |
321 | .ndo_start_xmit = gfar_start_xmit, | |
322 | .ndo_stop = gfar_close, | |
323 | .ndo_change_mtu = gfar_change_mtu, | |
324 | .ndo_set_multicast_list = gfar_set_multi, | |
325 | .ndo_tx_timeout = gfar_timeout, | |
326 | .ndo_do_ioctl = gfar_ioctl, | |
327 | .ndo_vlan_rx_register = gfar_vlan_rx_register, | |
240c102d BH |
328 | .ndo_set_mac_address = eth_mac_addr, |
329 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
330 | #ifdef CONFIG_NET_POLL_CONTROLLER |
331 | .ndo_poll_controller = gfar_netpoll, | |
332 | #endif | |
333 | }; | |
334 | ||
7f7f5316 AF |
335 | /* Returns 1 if incoming frames use an FCB */ |
336 | static inline int gfar_uses_fcb(struct gfar_private *priv) | |
0bbaf069 | 337 | { |
77ecaf2d | 338 | return priv->vlgrp || priv->rx_csum_enable; |
0bbaf069 | 339 | } |
bb40dcbb | 340 | |
b31a1d8b AF |
341 | static int gfar_of_init(struct net_device *dev) |
342 | { | |
b31a1d8b AF |
343 | const char *model; |
344 | const char *ctype; | |
345 | const void *mac_addr; | |
b31a1d8b AF |
346 | u64 addr, size; |
347 | int err = 0; | |
348 | struct gfar_private *priv = netdev_priv(dev); | |
349 | struct device_node *np = priv->node; | |
4d7902f2 AF |
350 | const u32 *stash; |
351 | const u32 *stash_len; | |
352 | const u32 *stash_idx; | |
b31a1d8b AF |
353 | |
354 | if (!np || !of_device_is_available(np)) | |
355 | return -ENODEV; | |
356 | ||
357 | /* get a pointer to the register memory */ | |
358 | addr = of_translate_address(np, of_get_address(np, 0, &size, NULL)); | |
359 | priv->regs = ioremap(addr, size); | |
360 | ||
361 | if (priv->regs == NULL) | |
362 | return -ENOMEM; | |
363 | ||
364 | priv->interruptTransmit = irq_of_parse_and_map(np, 0); | |
365 | ||
366 | model = of_get_property(np, "model", NULL); | |
367 | ||
368 | /* If we aren't the FEC we have multiple interrupts */ | |
369 | if (model && strcasecmp(model, "FEC")) { | |
370 | priv->interruptReceive = irq_of_parse_and_map(np, 1); | |
371 | ||
372 | priv->interruptError = irq_of_parse_and_map(np, 2); | |
373 | ||
374 | if (priv->interruptTransmit < 0 || | |
375 | priv->interruptReceive < 0 || | |
376 | priv->interruptError < 0) { | |
377 | err = -EINVAL; | |
378 | goto err_out; | |
379 | } | |
380 | } | |
381 | ||
4d7902f2 AF |
382 | stash = of_get_property(np, "bd-stash", NULL); |
383 | ||
384 | if(stash) { | |
385 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; | |
386 | priv->bd_stash_en = 1; | |
387 | } | |
388 | ||
389 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
390 | ||
391 | if (stash_len) | |
392 | priv->rx_stash_size = *stash_len; | |
393 | ||
394 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
395 | ||
396 | if (stash_idx) | |
397 | priv->rx_stash_index = *stash_idx; | |
398 | ||
399 | if (stash_len || stash_idx) | |
400 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
401 | ||
b31a1d8b AF |
402 | mac_addr = of_get_mac_address(np); |
403 | if (mac_addr) | |
404 | memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN); | |
405 | ||
406 | if (model && !strcasecmp(model, "TSEC")) | |
407 | priv->device_flags = | |
408 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
409 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
410 | FSL_GIANFAR_DEV_HAS_RMON | | |
411 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
412 | if (model && !strcasecmp(model, "eTSEC")) | |
413 | priv->device_flags = | |
414 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
415 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
416 | FSL_GIANFAR_DEV_HAS_RMON | | |
417 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
2c2db48a | 418 | FSL_GIANFAR_DEV_HAS_PADDING | |
b31a1d8b AF |
419 | FSL_GIANFAR_DEV_HAS_CSUM | |
420 | FSL_GIANFAR_DEV_HAS_VLAN | | |
421 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
422 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH; | |
423 | ||
424 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
425 | ||
426 | /* We only care about rgmii-id. The rest are autodetected */ | |
427 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
428 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
429 | else | |
430 | priv->interface = PHY_INTERFACE_MODE_MII; | |
431 | ||
432 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
433 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
434 | ||
fe192a49 | 435 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
b31a1d8b AF |
436 | |
437 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 438 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
439 | |
440 | return 0; | |
441 | ||
442 | err_out: | |
443 | iounmap(priv->regs); | |
444 | return err; | |
445 | } | |
446 | ||
0faac9f7 CW |
447 | /* Ioctl MII Interface */ |
448 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
449 | { | |
450 | struct gfar_private *priv = netdev_priv(dev); | |
451 | ||
452 | if (!netif_running(dev)) | |
453 | return -EINVAL; | |
454 | ||
455 | if (!priv->phydev) | |
456 | return -ENODEV; | |
457 | ||
458 | return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); | |
459 | } | |
460 | ||
bb40dcbb AF |
461 | /* Set up the ethernet device structure, private data, |
462 | * and anything else we need before we start */ | |
b31a1d8b AF |
463 | static int gfar_probe(struct of_device *ofdev, |
464 | const struct of_device_id *match) | |
1da177e4 LT |
465 | { |
466 | u32 tempval; | |
467 | struct net_device *dev = NULL; | |
468 | struct gfar_private *priv = NULL; | |
c50a5d9a DH |
469 | int err = 0; |
470 | int len_devname; | |
1da177e4 LT |
471 | |
472 | /* Create an ethernet device instance */ | |
473 | dev = alloc_etherdev(sizeof (*priv)); | |
474 | ||
bb40dcbb | 475 | if (NULL == dev) |
1da177e4 LT |
476 | return -ENOMEM; |
477 | ||
478 | priv = netdev_priv(dev); | |
4826857f KG |
479 | priv->ndev = dev; |
480 | priv->ofdev = ofdev; | |
b31a1d8b | 481 | priv->node = ofdev->node; |
4826857f | 482 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 483 | |
b31a1d8b | 484 | err = gfar_of_init(dev); |
1da177e4 | 485 | |
b31a1d8b | 486 | if (err) |
1da177e4 | 487 | goto regs_fail; |
1da177e4 | 488 | |
fef6108d AF |
489 | spin_lock_init(&priv->txlock); |
490 | spin_lock_init(&priv->rxlock); | |
d87eb127 | 491 | spin_lock_init(&priv->bflock); |
ab939905 | 492 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 493 | |
b31a1d8b | 494 | dev_set_drvdata(&ofdev->dev, priv); |
1da177e4 LT |
495 | |
496 | /* Stop the DMA engine now, in case it was running before */ | |
497 | /* (The firmware could have used it, and left it running). */ | |
257d938a | 498 | gfar_halt(dev); |
1da177e4 LT |
499 | |
500 | /* Reset MAC layer */ | |
501 | gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); | |
502 | ||
b98ac702 AF |
503 | /* We need to delay at least 3 TX clocks */ |
504 | udelay(2); | |
505 | ||
1da177e4 LT |
506 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
507 | gfar_write(&priv->regs->maccfg1, tempval); | |
508 | ||
509 | /* Initialize MACCFG2. */ | |
510 | gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS); | |
511 | ||
512 | /* Initialize ECNTRL */ | |
513 | gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS); | |
514 | ||
1da177e4 LT |
515 | /* Set the dev->base_addr to the gfar reg region */ |
516 | dev->base_addr = (unsigned long) (priv->regs); | |
517 | ||
b31a1d8b | 518 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 LT |
519 | |
520 | /* Fill in the dev structure */ | |
1da177e4 | 521 | dev->watchdog_timeo = TX_TIMEOUT; |
bea3348e | 522 | netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT); |
1da177e4 | 523 | dev->mtu = 1500; |
1da177e4 | 524 | |
26ccfc37 | 525 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
526 | dev->ethtool_ops = &gfar_ethtool_ops; |
527 | ||
b31a1d8b | 528 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
0bbaf069 | 529 | priv->rx_csum_enable = 1; |
4669bc90 | 530 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA; |
0bbaf069 KG |
531 | } else |
532 | priv->rx_csum_enable = 0; | |
533 | ||
534 | priv->vlgrp = NULL; | |
1da177e4 | 535 | |
26ccfc37 | 536 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) |
0bbaf069 | 537 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
0bbaf069 | 538 | |
b31a1d8b | 539 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
540 | priv->extended_hash = 1; |
541 | priv->hash_width = 9; | |
542 | ||
543 | priv->hash_regs[0] = &priv->regs->igaddr0; | |
544 | priv->hash_regs[1] = &priv->regs->igaddr1; | |
545 | priv->hash_regs[2] = &priv->regs->igaddr2; | |
546 | priv->hash_regs[3] = &priv->regs->igaddr3; | |
547 | priv->hash_regs[4] = &priv->regs->igaddr4; | |
548 | priv->hash_regs[5] = &priv->regs->igaddr5; | |
549 | priv->hash_regs[6] = &priv->regs->igaddr6; | |
550 | priv->hash_regs[7] = &priv->regs->igaddr7; | |
551 | priv->hash_regs[8] = &priv->regs->gaddr0; | |
552 | priv->hash_regs[9] = &priv->regs->gaddr1; | |
553 | priv->hash_regs[10] = &priv->regs->gaddr2; | |
554 | priv->hash_regs[11] = &priv->regs->gaddr3; | |
555 | priv->hash_regs[12] = &priv->regs->gaddr4; | |
556 | priv->hash_regs[13] = &priv->regs->gaddr5; | |
557 | priv->hash_regs[14] = &priv->regs->gaddr6; | |
558 | priv->hash_regs[15] = &priv->regs->gaddr7; | |
559 | ||
560 | } else { | |
561 | priv->extended_hash = 0; | |
562 | priv->hash_width = 8; | |
563 | ||
564 | priv->hash_regs[0] = &priv->regs->gaddr0; | |
1577ecef | 565 | priv->hash_regs[1] = &priv->regs->gaddr1; |
0bbaf069 KG |
566 | priv->hash_regs[2] = &priv->regs->gaddr2; |
567 | priv->hash_regs[3] = &priv->regs->gaddr3; | |
568 | priv->hash_regs[4] = &priv->regs->gaddr4; | |
569 | priv->hash_regs[5] = &priv->regs->gaddr5; | |
570 | priv->hash_regs[6] = &priv->regs->gaddr6; | |
571 | priv->hash_regs[7] = &priv->regs->gaddr7; | |
572 | } | |
573 | ||
b31a1d8b | 574 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
575 | priv->padding = DEFAULT_PADDING; |
576 | else | |
577 | priv->padding = 0; | |
578 | ||
0bbaf069 KG |
579 | if (dev->features & NETIF_F_IP_CSUM) |
580 | dev->hard_header_len += GMAC_FCB_LEN; | |
1da177e4 LT |
581 | |
582 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; | |
1da177e4 LT |
583 | priv->tx_ring_size = DEFAULT_TX_RING_SIZE; |
584 | priv->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
4669bc90 | 585 | priv->num_txbdfree = DEFAULT_TX_RING_SIZE; |
1da177e4 LT |
586 | |
587 | priv->txcoalescing = DEFAULT_TX_COALESCE; | |
b46a8454 | 588 | priv->txic = DEFAULT_TXIC; |
1da177e4 | 589 | priv->rxcoalescing = DEFAULT_RX_COALESCE; |
b46a8454 | 590 | priv->rxic = DEFAULT_RXIC; |
1da177e4 | 591 | |
0bbaf069 KG |
592 | /* Enable most messages by default */ |
593 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
594 | ||
d3eab82b TP |
595 | /* Carrier starts down, phylib will bring it up */ |
596 | netif_carrier_off(dev); | |
597 | ||
1da177e4 LT |
598 | err = register_netdev(dev); |
599 | ||
600 | if (err) { | |
601 | printk(KERN_ERR "%s: Cannot register net device, aborting.\n", | |
602 | dev->name); | |
603 | goto register_fail; | |
604 | } | |
605 | ||
2884e5cc AV |
606 | device_init_wakeup(&dev->dev, |
607 | priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
608 | ||
c50a5d9a DH |
609 | /* fill out IRQ number and name fields */ |
610 | len_devname = strlen(dev->name); | |
611 | strncpy(&priv->int_name_tx[0], dev->name, len_devname); | |
612 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { | |
613 | strncpy(&priv->int_name_tx[len_devname], | |
614 | "_tx", sizeof("_tx") + 1); | |
615 | ||
616 | strncpy(&priv->int_name_rx[0], dev->name, len_devname); | |
617 | strncpy(&priv->int_name_rx[len_devname], | |
618 | "_rx", sizeof("_rx") + 1); | |
619 | ||
620 | strncpy(&priv->int_name_er[0], dev->name, len_devname); | |
621 | strncpy(&priv->int_name_er[len_devname], | |
622 | "_er", sizeof("_er") + 1); | |
623 | } else | |
624 | priv->int_name_tx[len_devname] = '\0'; | |
625 | ||
7f7f5316 AF |
626 | /* Create all the sysfs files */ |
627 | gfar_init_sysfs(dev); | |
628 | ||
1da177e4 | 629 | /* Print out the device info */ |
e174961c | 630 | printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr); |
1da177e4 LT |
631 | |
632 | /* Even more device info helps when determining which kernel */ | |
7f7f5316 | 633 | /* provided which set of benchmarks. */ |
1da177e4 | 634 | printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name); |
1da177e4 LT |
635 | printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n", |
636 | dev->name, priv->rx_ring_size, priv->tx_ring_size); | |
637 | ||
638 | return 0; | |
639 | ||
640 | register_fail: | |
cc8c6e37 | 641 | iounmap(priv->regs); |
1da177e4 | 642 | regs_fail: |
fe192a49 GL |
643 | if (priv->phy_node) |
644 | of_node_put(priv->phy_node); | |
645 | if (priv->tbi_node) | |
646 | of_node_put(priv->tbi_node); | |
1da177e4 | 647 | free_netdev(dev); |
bb40dcbb | 648 | return err; |
1da177e4 LT |
649 | } |
650 | ||
b31a1d8b | 651 | static int gfar_remove(struct of_device *ofdev) |
1da177e4 | 652 | { |
b31a1d8b | 653 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
1da177e4 | 654 | |
fe192a49 GL |
655 | if (priv->phy_node) |
656 | of_node_put(priv->phy_node); | |
657 | if (priv->tbi_node) | |
658 | of_node_put(priv->tbi_node); | |
659 | ||
b31a1d8b | 660 | dev_set_drvdata(&ofdev->dev, NULL); |
1da177e4 | 661 | |
d9d8e041 | 662 | unregister_netdev(priv->ndev); |
cc8c6e37 | 663 | iounmap(priv->regs); |
4826857f | 664 | free_netdev(priv->ndev); |
1da177e4 LT |
665 | |
666 | return 0; | |
667 | } | |
668 | ||
d87eb127 | 669 | #ifdef CONFIG_PM |
b31a1d8b | 670 | static int gfar_suspend(struct of_device *ofdev, pm_message_t state) |
d87eb127 | 671 | { |
b31a1d8b | 672 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
29ded5f7 | 673 | struct net_device *dev = priv->ndev; |
d87eb127 SW |
674 | unsigned long flags; |
675 | u32 tempval; | |
676 | ||
677 | int magic_packet = priv->wol_en && | |
b31a1d8b | 678 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 SW |
679 | |
680 | netif_device_detach(dev); | |
681 | ||
682 | if (netif_running(dev)) { | |
683 | spin_lock_irqsave(&priv->txlock, flags); | |
684 | spin_lock(&priv->rxlock); | |
685 | ||
686 | gfar_halt_nodisable(dev); | |
687 | ||
688 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
689 | tempval = gfar_read(&priv->regs->maccfg1); | |
690 | ||
691 | tempval &= ~MACCFG1_TX_EN; | |
692 | ||
693 | if (!magic_packet) | |
694 | tempval &= ~MACCFG1_RX_EN; | |
695 | ||
696 | gfar_write(&priv->regs->maccfg1, tempval); | |
697 | ||
698 | spin_unlock(&priv->rxlock); | |
699 | spin_unlock_irqrestore(&priv->txlock, flags); | |
700 | ||
d87eb127 | 701 | napi_disable(&priv->napi); |
d87eb127 SW |
702 | |
703 | if (magic_packet) { | |
704 | /* Enable interrupt on Magic Packet */ | |
705 | gfar_write(&priv->regs->imask, IMASK_MAG); | |
706 | ||
707 | /* Enable Magic Packet mode */ | |
708 | tempval = gfar_read(&priv->regs->maccfg2); | |
709 | tempval |= MACCFG2_MPEN; | |
710 | gfar_write(&priv->regs->maccfg2, tempval); | |
711 | } else { | |
712 | phy_stop(priv->phydev); | |
713 | } | |
714 | } | |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
b31a1d8b | 719 | static int gfar_resume(struct of_device *ofdev) |
d87eb127 | 720 | { |
b31a1d8b | 721 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
29ded5f7 | 722 | struct net_device *dev = priv->ndev; |
d87eb127 SW |
723 | unsigned long flags; |
724 | u32 tempval; | |
725 | int magic_packet = priv->wol_en && | |
b31a1d8b | 726 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 SW |
727 | |
728 | if (!netif_running(dev)) { | |
729 | netif_device_attach(dev); | |
730 | return 0; | |
731 | } | |
732 | ||
733 | if (!magic_packet && priv->phydev) | |
734 | phy_start(priv->phydev); | |
735 | ||
736 | /* Disable Magic Packet mode, in case something | |
737 | * else woke us up. | |
738 | */ | |
739 | ||
740 | spin_lock_irqsave(&priv->txlock, flags); | |
741 | spin_lock(&priv->rxlock); | |
742 | ||
743 | tempval = gfar_read(&priv->regs->maccfg2); | |
744 | tempval &= ~MACCFG2_MPEN; | |
745 | gfar_write(&priv->regs->maccfg2, tempval); | |
746 | ||
747 | gfar_start(dev); | |
748 | ||
749 | spin_unlock(&priv->rxlock); | |
750 | spin_unlock_irqrestore(&priv->txlock, flags); | |
751 | ||
752 | netif_device_attach(dev); | |
753 | ||
d87eb127 | 754 | napi_enable(&priv->napi); |
d87eb127 SW |
755 | |
756 | return 0; | |
757 | } | |
758 | #else | |
759 | #define gfar_suspend NULL | |
760 | #define gfar_resume NULL | |
761 | #endif | |
1da177e4 | 762 | |
e8a2b6a4 AF |
763 | /* Reads the controller's registers to determine what interface |
764 | * connects it to the PHY. | |
765 | */ | |
766 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
767 | { | |
768 | struct gfar_private *priv = netdev_priv(dev); | |
769 | u32 ecntrl = gfar_read(&priv->regs->ecntrl); | |
770 | ||
771 | if (ecntrl & ECNTRL_SGMII_MODE) | |
772 | return PHY_INTERFACE_MODE_SGMII; | |
773 | ||
774 | if (ecntrl & ECNTRL_TBI_MODE) { | |
775 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
776 | return PHY_INTERFACE_MODE_RTBI; | |
777 | else | |
778 | return PHY_INTERFACE_MODE_TBI; | |
779 | } | |
780 | ||
781 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
782 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) | |
783 | return PHY_INTERFACE_MODE_RMII; | |
7132ab7f | 784 | else { |
b31a1d8b | 785 | phy_interface_t interface = priv->interface; |
7132ab7f AF |
786 | |
787 | /* | |
788 | * This isn't autodetected right now, so it must | |
789 | * be set by the device tree or platform code. | |
790 | */ | |
791 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
792 | return PHY_INTERFACE_MODE_RGMII_ID; | |
793 | ||
e8a2b6a4 | 794 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 795 | } |
e8a2b6a4 AF |
796 | } |
797 | ||
b31a1d8b | 798 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
799 | return PHY_INTERFACE_MODE_GMII; |
800 | ||
801 | return PHY_INTERFACE_MODE_MII; | |
802 | } | |
803 | ||
804 | ||
bb40dcbb AF |
805 | /* Initializes driver's PHY state, and attaches to the PHY. |
806 | * Returns 0 on success. | |
1da177e4 LT |
807 | */ |
808 | static int init_phy(struct net_device *dev) | |
809 | { | |
810 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 811 | uint gigabit_support = |
b31a1d8b | 812 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb | 813 | SUPPORTED_1000baseT_Full : 0; |
e8a2b6a4 | 814 | phy_interface_t interface; |
1da177e4 LT |
815 | |
816 | priv->oldlink = 0; | |
817 | priv->oldspeed = 0; | |
818 | priv->oldduplex = -1; | |
819 | ||
e8a2b6a4 AF |
820 | interface = gfar_get_interface(dev); |
821 | ||
1db780f8 AV |
822 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, |
823 | interface); | |
824 | if (!priv->phydev) | |
825 | priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, | |
826 | interface); | |
827 | if (!priv->phydev) { | |
828 | dev_err(&dev->dev, "could not attach to PHY\n"); | |
829 | return -ENODEV; | |
fe192a49 | 830 | } |
1da177e4 | 831 | |
d3c12873 KJ |
832 | if (interface == PHY_INTERFACE_MODE_SGMII) |
833 | gfar_configure_serdes(dev); | |
834 | ||
bb40dcbb | 835 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
836 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
837 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
838 | |
839 | return 0; | |
1da177e4 LT |
840 | } |
841 | ||
d0313587 PG |
842 | /* |
843 | * Initialize TBI PHY interface for communicating with the | |
844 | * SERDES lynx PHY on the chip. We communicate with this PHY | |
845 | * through the MDIO bus on each controller, treating it as a | |
846 | * "normal" PHY at the address found in the TBIPA register. We assume | |
847 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
848 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
849 | * value doesn't matter, as there are no other PHYs on the bus. | |
850 | */ | |
d3c12873 KJ |
851 | static void gfar_configure_serdes(struct net_device *dev) |
852 | { | |
853 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
854 | struct phy_device *tbiphy; |
855 | ||
856 | if (!priv->tbi_node) { | |
857 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
858 | "device tree specify a tbi-handle\n"); | |
859 | return; | |
860 | } | |
c132419e | 861 | |
fe192a49 GL |
862 | tbiphy = of_phy_find_device(priv->tbi_node); |
863 | if (!tbiphy) { | |
864 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
865 | return; |
866 | } | |
d3c12873 | 867 | |
b31a1d8b AF |
868 | /* |
869 | * If the link is already up, we must already be ok, and don't need to | |
bdb59f94 TP |
870 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
871 | * everything for us? Resetting it takes the link down and requires | |
872 | * several seconds for it to come back. | |
873 | */ | |
fe192a49 | 874 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 875 | return; |
d3c12873 | 876 | |
d0313587 | 877 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 878 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 879 | |
fe192a49 | 880 | phy_write(tbiphy, MII_ADVERTISE, |
d3c12873 KJ |
881 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
882 | ADVERTISE_1000XPSE_ASYM); | |
883 | ||
fe192a49 | 884 | phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE | |
d3c12873 KJ |
885 | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000); |
886 | } | |
887 | ||
1da177e4 LT |
888 | static void init_registers(struct net_device *dev) |
889 | { | |
890 | struct gfar_private *priv = netdev_priv(dev); | |
891 | ||
892 | /* Clear IEVENT */ | |
893 | gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR); | |
894 | ||
895 | /* Initialize IMASK */ | |
896 | gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR); | |
897 | ||
898 | /* Init hash registers to zero */ | |
0bbaf069 KG |
899 | gfar_write(&priv->regs->igaddr0, 0); |
900 | gfar_write(&priv->regs->igaddr1, 0); | |
901 | gfar_write(&priv->regs->igaddr2, 0); | |
902 | gfar_write(&priv->regs->igaddr3, 0); | |
903 | gfar_write(&priv->regs->igaddr4, 0); | |
904 | gfar_write(&priv->regs->igaddr5, 0); | |
905 | gfar_write(&priv->regs->igaddr6, 0); | |
906 | gfar_write(&priv->regs->igaddr7, 0); | |
1da177e4 LT |
907 | |
908 | gfar_write(&priv->regs->gaddr0, 0); | |
909 | gfar_write(&priv->regs->gaddr1, 0); | |
910 | gfar_write(&priv->regs->gaddr2, 0); | |
911 | gfar_write(&priv->regs->gaddr3, 0); | |
912 | gfar_write(&priv->regs->gaddr4, 0); | |
913 | gfar_write(&priv->regs->gaddr5, 0); | |
914 | gfar_write(&priv->regs->gaddr6, 0); | |
915 | gfar_write(&priv->regs->gaddr7, 0); | |
916 | ||
1da177e4 | 917 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 918 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
cc8c6e37 | 919 | memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
920 | |
921 | /* Mask off the CAM interrupts */ | |
922 | gfar_write(&priv->regs->rmon.cam1, 0xffffffff); | |
923 | gfar_write(&priv->regs->rmon.cam2, 0xffffffff); | |
924 | } | |
925 | ||
926 | /* Initialize the max receive buffer length */ | |
927 | gfar_write(&priv->regs->mrblr, priv->rx_buffer_size); | |
928 | ||
1da177e4 LT |
929 | /* Initialize the Minimum Frame Length Register */ |
930 | gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS); | |
1da177e4 LT |
931 | } |
932 | ||
0bbaf069 KG |
933 | |
934 | /* Halt the receive and transmit queues */ | |
d87eb127 | 935 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
936 | { |
937 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 938 | struct gfar __iomem *regs = priv->regs; |
1da177e4 LT |
939 | u32 tempval; |
940 | ||
1da177e4 LT |
941 | /* Mask all interrupts */ |
942 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
943 | ||
944 | /* Clear all interrupts */ | |
945 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
946 | ||
947 | /* Stop the DMA, and wait for it to stop */ | |
948 | tempval = gfar_read(&priv->regs->dmactrl); | |
949 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) | |
950 | != (DMACTRL_GRS | DMACTRL_GTS)) { | |
951 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); | |
952 | gfar_write(&priv->regs->dmactrl, tempval); | |
953 | ||
954 | while (!(gfar_read(&priv->regs->ievent) & | |
955 | (IEVENT_GRSC | IEVENT_GTSC))) | |
956 | cpu_relax(); | |
957 | } | |
d87eb127 | 958 | } |
d87eb127 SW |
959 | |
960 | /* Halt the receive and transmit queues */ | |
961 | void gfar_halt(struct net_device *dev) | |
962 | { | |
963 | struct gfar_private *priv = netdev_priv(dev); | |
964 | struct gfar __iomem *regs = priv->regs; | |
965 | u32 tempval; | |
1da177e4 | 966 | |
2a54adc3 SW |
967 | gfar_halt_nodisable(dev); |
968 | ||
1da177e4 LT |
969 | /* Disable Rx and Tx */ |
970 | tempval = gfar_read(®s->maccfg1); | |
971 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
972 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
973 | } |
974 | ||
975 | void stop_gfar(struct net_device *dev) | |
976 | { | |
977 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 KG |
978 | unsigned long flags; |
979 | ||
bb40dcbb AF |
980 | phy_stop(priv->phydev); |
981 | ||
0bbaf069 | 982 | /* Lock it down */ |
fef6108d AF |
983 | spin_lock_irqsave(&priv->txlock, flags); |
984 | spin_lock(&priv->rxlock); | |
0bbaf069 | 985 | |
0bbaf069 | 986 | gfar_halt(dev); |
1da177e4 | 987 | |
fef6108d AF |
988 | spin_unlock(&priv->rxlock); |
989 | spin_unlock_irqrestore(&priv->txlock, flags); | |
1da177e4 LT |
990 | |
991 | /* Free the IRQs */ | |
b31a1d8b | 992 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
1da177e4 LT |
993 | free_irq(priv->interruptError, dev); |
994 | free_irq(priv->interruptTransmit, dev); | |
995 | free_irq(priv->interruptReceive, dev); | |
996 | } else { | |
1577ecef | 997 | free_irq(priv->interruptTransmit, dev); |
1da177e4 LT |
998 | } |
999 | ||
1000 | free_skb_resources(priv); | |
1da177e4 LT |
1001 | } |
1002 | ||
1003 | /* If there are any tx skbs or rx skbs still around, free them. | |
1004 | * Then free tx_skbuff and rx_skbuff */ | |
bb40dcbb | 1005 | static void free_skb_resources(struct gfar_private *priv) |
1da177e4 | 1006 | { |
e69edd21 | 1007 | struct device *dev = &priv->ofdev->dev; |
1da177e4 LT |
1008 | struct rxbd8 *rxbdp; |
1009 | struct txbd8 *txbdp; | |
4669bc90 | 1010 | int i, j; |
1da177e4 LT |
1011 | |
1012 | /* Go through all the buffer descriptors and free their data buffers */ | |
1013 | txbdp = priv->tx_bd_base; | |
1014 | ||
e69edd21 AV |
1015 | if (!priv->tx_skbuff) |
1016 | goto skip_tx_skbuff; | |
1017 | ||
1da177e4 | 1018 | for (i = 0; i < priv->tx_ring_size; i++) { |
4669bc90 DH |
1019 | if (!priv->tx_skbuff[i]) |
1020 | continue; | |
1da177e4 | 1021 | |
4826857f | 1022 | dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr, |
4669bc90 DH |
1023 | txbdp->length, DMA_TO_DEVICE); |
1024 | txbdp->lstatus = 0; | |
1025 | for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) { | |
1026 | txbdp++; | |
4826857f | 1027 | dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr, |
4669bc90 | 1028 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 1029 | } |
ad5da7ab | 1030 | txbdp++; |
4669bc90 DH |
1031 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
1032 | priv->tx_skbuff[i] = NULL; | |
1da177e4 LT |
1033 | } |
1034 | ||
1035 | kfree(priv->tx_skbuff); | |
e69edd21 | 1036 | skip_tx_skbuff: |
1da177e4 LT |
1037 | |
1038 | rxbdp = priv->rx_bd_base; | |
1039 | ||
e69edd21 AV |
1040 | if (!priv->rx_skbuff) |
1041 | goto skip_rx_skbuff; | |
1da177e4 | 1042 | |
e69edd21 AV |
1043 | for (i = 0; i < priv->rx_ring_size; i++) { |
1044 | if (priv->rx_skbuff[i]) { | |
1045 | dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr, | |
1046 | priv->rx_buffer_size, | |
1047 | DMA_FROM_DEVICE); | |
1048 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
1049 | priv->rx_skbuff[i] = NULL; | |
1da177e4 LT |
1050 | } |
1051 | ||
e69edd21 AV |
1052 | rxbdp->lstatus = 0; |
1053 | rxbdp->bufPtr = 0; | |
1054 | rxbdp++; | |
1da177e4 | 1055 | } |
e69edd21 AV |
1056 | |
1057 | kfree(priv->rx_skbuff); | |
1058 | skip_rx_skbuff: | |
1059 | ||
1060 | dma_free_coherent(dev, sizeof(*txbdp) * priv->tx_ring_size + | |
1061 | sizeof(*rxbdp) * priv->rx_ring_size, | |
32c513bc | 1062 | priv->tx_bd_base, priv->tx_bd_dma_base); |
1da177e4 LT |
1063 | } |
1064 | ||
0bbaf069 KG |
1065 | void gfar_start(struct net_device *dev) |
1066 | { | |
1067 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 1068 | struct gfar __iomem *regs = priv->regs; |
0bbaf069 KG |
1069 | u32 tempval; |
1070 | ||
1071 | /* Enable Rx and Tx in MACCFG1 */ | |
1072 | tempval = gfar_read(®s->maccfg1); | |
1073 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1074 | gfar_write(®s->maccfg1, tempval); | |
1075 | ||
1076 | /* Initialize DMACTRL to have WWR and WOP */ | |
1077 | tempval = gfar_read(&priv->regs->dmactrl); | |
1078 | tempval |= DMACTRL_INIT_SETTINGS; | |
1079 | gfar_write(&priv->regs->dmactrl, tempval); | |
1080 | ||
0bbaf069 KG |
1081 | /* Make sure we aren't stopped */ |
1082 | tempval = gfar_read(&priv->regs->dmactrl); | |
1083 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); | |
1084 | gfar_write(&priv->regs->dmactrl, tempval); | |
1085 | ||
fef6108d AF |
1086 | /* Clear THLT/RHLT, so that the DMA starts polling now */ |
1087 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT); | |
1088 | gfar_write(®s->rstat, RSTAT_CLEAR_RHALT); | |
1089 | ||
0bbaf069 KG |
1090 | /* Unmask the interrupts we look for */ |
1091 | gfar_write(®s->imask, IMASK_DEFAULT); | |
12dea57b DH |
1092 | |
1093 | dev->trans_start = jiffies; | |
0bbaf069 KG |
1094 | } |
1095 | ||
1da177e4 | 1096 | /* Bring the controller up and running */ |
ccc05c6e | 1097 | int startup_gfar(struct net_device *ndev) |
1da177e4 | 1098 | { |
ccc05c6e | 1099 | struct gfar_private *priv = netdev_priv(ndev); |
cc8c6e37 | 1100 | struct gfar __iomem *regs = priv->regs; |
ccc05c6e | 1101 | int err; |
1da177e4 LT |
1102 | |
1103 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1104 | ||
826aa4a0 AV |
1105 | err = gfar_alloc_skb_resources(ndev); |
1106 | if (err) | |
1107 | return err; | |
815b97c6 | 1108 | |
826aa4a0 | 1109 | gfar_init_mac(ndev); |
1da177e4 | 1110 | |
1da177e4 LT |
1111 | /* If the device has multiple interrupts, register for |
1112 | * them. Otherwise, only register for the one */ | |
b31a1d8b | 1113 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1114 | /* Install our interrupt handlers for Error, |
1da177e4 | 1115 | * Transmit, and Receive */ |
ccc05c6e AV |
1116 | err = request_irq(priv->interruptError, gfar_error, 0, |
1117 | priv->int_name_er, ndev); | |
1118 | if (err) { | |
0bbaf069 | 1119 | if (netif_msg_intr(priv)) |
ccc05c6e AV |
1120 | pr_err("%s: Can't get IRQ %d\n", ndev->name, |
1121 | priv->interruptError); | |
1da177e4 LT |
1122 | goto err_irq_fail; |
1123 | } | |
1124 | ||
ccc05c6e AV |
1125 | err = request_irq(priv->interruptTransmit, gfar_transmit, 0, |
1126 | priv->int_name_tx, ndev); | |
1127 | if (err) { | |
0bbaf069 | 1128 | if (netif_msg_intr(priv)) |
ccc05c6e AV |
1129 | pr_err("%s: Can't get IRQ %d\n", ndev->name, |
1130 | priv->interruptTransmit); | |
1da177e4 LT |
1131 | goto tx_irq_fail; |
1132 | } | |
1133 | ||
ccc05c6e AV |
1134 | err = request_irq(priv->interruptReceive, gfar_receive, 0, |
1135 | priv->int_name_rx, ndev); | |
1136 | if (err) { | |
0bbaf069 | 1137 | if (netif_msg_intr(priv)) |
ccc05c6e AV |
1138 | pr_err("%s: Can't get IRQ %d (receive0)\n", |
1139 | ndev->name, priv->interruptReceive); | |
1da177e4 LT |
1140 | goto rx_irq_fail; |
1141 | } | |
1142 | } else { | |
ccc05c6e AV |
1143 | err = request_irq(priv->interruptTransmit, gfar_interrupt, |
1144 | 0, priv->int_name_tx, ndev); | |
1145 | if (err) { | |
0bbaf069 | 1146 | if (netif_msg_intr(priv)) |
ccc05c6e AV |
1147 | pr_err("%s: Can't get IRQ %d\n", ndev->name, |
1148 | priv->interruptTransmit); | |
1da177e4 LT |
1149 | goto err_irq_fail; |
1150 | } | |
1151 | } | |
1152 | ||
7f7f5316 | 1153 | /* Start the controller */ |
ccc05c6e | 1154 | gfar_start(ndev); |
1da177e4 | 1155 | |
826aa4a0 AV |
1156 | phy_start(priv->phydev); |
1157 | ||
1da177e4 LT |
1158 | return 0; |
1159 | ||
1160 | rx_irq_fail: | |
ccc05c6e | 1161 | free_irq(priv->interruptTransmit, ndev); |
1da177e4 | 1162 | tx_irq_fail: |
ccc05c6e | 1163 | free_irq(priv->interruptError, ndev); |
1da177e4 | 1164 | err_irq_fail: |
e69edd21 | 1165 | free_skb_resources(priv); |
1da177e4 LT |
1166 | return err; |
1167 | } | |
1168 | ||
1169 | /* Called when something needs to use the ethernet device */ | |
1170 | /* Returns 0 for success. */ | |
1171 | static int gfar_enet_open(struct net_device *dev) | |
1172 | { | |
94e8cc35 | 1173 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1174 | int err; |
1175 | ||
bea3348e SH |
1176 | napi_enable(&priv->napi); |
1177 | ||
0fd56bb5 AF |
1178 | skb_queue_head_init(&priv->rx_recycle); |
1179 | ||
1da177e4 LT |
1180 | /* Initialize a bunch of registers */ |
1181 | init_registers(dev); | |
1182 | ||
1183 | gfar_set_mac_address(dev); | |
1184 | ||
1185 | err = init_phy(dev); | |
1186 | ||
bea3348e SH |
1187 | if(err) { |
1188 | napi_disable(&priv->napi); | |
1da177e4 | 1189 | return err; |
bea3348e | 1190 | } |
1da177e4 LT |
1191 | |
1192 | err = startup_gfar(dev); | |
db0e8e3f | 1193 | if (err) { |
bea3348e | 1194 | napi_disable(&priv->napi); |
db0e8e3f AV |
1195 | return err; |
1196 | } | |
1da177e4 LT |
1197 | |
1198 | netif_start_queue(dev); | |
1199 | ||
2884e5cc AV |
1200 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
1201 | ||
1da177e4 LT |
1202 | return err; |
1203 | } | |
1204 | ||
54dc79fe | 1205 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 1206 | { |
54dc79fe | 1207 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
1208 | |
1209 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 1210 | |
0bbaf069 KG |
1211 | return fcb; |
1212 | } | |
1213 | ||
1214 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb) | |
1215 | { | |
7f7f5316 | 1216 | u8 flags = 0; |
0bbaf069 KG |
1217 | |
1218 | /* If we're here, it's a IP packet with a TCP or UDP | |
1219 | * payload. We set it to checksum, using a pseudo-header | |
1220 | * we provide | |
1221 | */ | |
7f7f5316 | 1222 | flags = TXFCB_DEFAULT; |
0bbaf069 | 1223 | |
7f7f5316 AF |
1224 | /* Tell the controller what the protocol is */ |
1225 | /* And provide the already calculated phcs */ | |
eddc9ec5 | 1226 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 1227 | flags |= TXFCB_UDP; |
4bedb452 | 1228 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 1229 | } else |
8da32de5 | 1230 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
1231 | |
1232 | /* l3os is the distance between the start of the | |
1233 | * frame (skb->data) and the start of the IP hdr. | |
1234 | * l4os is the distance between the start of the | |
1235 | * l3 hdr and the l4 hdr */ | |
bbe735e4 | 1236 | fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN); |
cfe1fc77 | 1237 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 1238 | |
7f7f5316 | 1239 | fcb->flags = flags; |
0bbaf069 KG |
1240 | } |
1241 | ||
7f7f5316 | 1242 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 1243 | { |
7f7f5316 | 1244 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
1245 | fcb->vlctl = vlan_tx_tag_get(skb); |
1246 | } | |
1247 | ||
4669bc90 DH |
1248 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
1249 | struct txbd8 *base, int ring_size) | |
1250 | { | |
1251 | struct txbd8 *new_bd = bdp + stride; | |
1252 | ||
1253 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
1254 | } | |
1255 | ||
1256 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
1257 | int ring_size) | |
1258 | { | |
1259 | return skip_txbd(bdp, 1, base, ring_size); | |
1260 | } | |
1261 | ||
1da177e4 LT |
1262 | /* This is called by the kernel when a frame is ready for transmission. */ |
1263 | /* It is pointed to by the dev->hard_start_xmit function pointer */ | |
1264 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1265 | { | |
1266 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1267 | struct txfcb *fcb = NULL; |
4669bc90 | 1268 | struct txbd8 *txbdp, *txbdp_start, *base; |
5a5efed4 | 1269 | u32 lstatus; |
4669bc90 DH |
1270 | int i; |
1271 | u32 bufaddr; | |
fef6108d | 1272 | unsigned long flags; |
4669bc90 DH |
1273 | unsigned int nr_frags, length; |
1274 | ||
1275 | base = priv->tx_bd_base; | |
1276 | ||
5b28beaf LY |
1277 | /* make space for additional header when fcb is needed */ |
1278 | if (((skb->ip_summed == CHECKSUM_PARTIAL) || | |
1279 | (priv->vlgrp && vlan_tx_tag_present(skb))) && | |
1280 | (skb_headroom(skb) < GMAC_FCB_LEN)) { | |
54dc79fe SH |
1281 | struct sk_buff *skb_new; |
1282 | ||
1283 | skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN); | |
1284 | if (!skb_new) { | |
1285 | dev->stats.tx_errors++; | |
bd14ba84 | 1286 | kfree_skb(skb); |
54dc79fe SH |
1287 | return NETDEV_TX_OK; |
1288 | } | |
1289 | kfree_skb(skb); | |
1290 | skb = skb_new; | |
1291 | } | |
1292 | ||
4669bc90 DH |
1293 | /* total number of fragments in the SKB */ |
1294 | nr_frags = skb_shinfo(skb)->nr_frags; | |
1295 | ||
1296 | spin_lock_irqsave(&priv->txlock, flags); | |
1297 | ||
1298 | /* check if there is space to queue this packet */ | |
7958a453 | 1299 | if ((nr_frags+1) > priv->num_txbdfree) { |
4669bc90 DH |
1300 | /* no space, stop the queue */ |
1301 | netif_stop_queue(dev); | |
1302 | dev->stats.tx_fifo_errors++; | |
1303 | spin_unlock_irqrestore(&priv->txlock, flags); | |
1304 | return NETDEV_TX_BUSY; | |
1305 | } | |
1da177e4 LT |
1306 | |
1307 | /* Update transmit stats */ | |
09f75cd7 | 1308 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 1309 | |
4669bc90 | 1310 | txbdp = txbdp_start = priv->cur_tx; |
1da177e4 | 1311 | |
4669bc90 DH |
1312 | if (nr_frags == 0) { |
1313 | lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1314 | } else { | |
1315 | /* Place the fragment addresses and lengths into the TxBDs */ | |
1316 | for (i = 0; i < nr_frags; i++) { | |
1317 | /* Point at the next BD, wrapping as needed */ | |
1318 | txbdp = next_txbd(txbdp, base, priv->tx_ring_size); | |
1319 | ||
1320 | length = skb_shinfo(skb)->frags[i].size; | |
1321 | ||
1322 | lstatus = txbdp->lstatus | length | | |
1323 | BD_LFLAG(TXBD_READY); | |
1324 | ||
1325 | /* Handle the last BD specially */ | |
1326 | if (i == nr_frags - 1) | |
1327 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 1328 | |
4826857f | 1329 | bufaddr = dma_map_page(&priv->ofdev->dev, |
4669bc90 DH |
1330 | skb_shinfo(skb)->frags[i].page, |
1331 | skb_shinfo(skb)->frags[i].page_offset, | |
1332 | length, | |
1333 | DMA_TO_DEVICE); | |
1334 | ||
1335 | /* set the TxBD length and buffer pointer */ | |
1336 | txbdp->bufPtr = bufaddr; | |
1337 | txbdp->lstatus = lstatus; | |
1338 | } | |
1339 | ||
1340 | lstatus = txbdp_start->lstatus; | |
1341 | } | |
1da177e4 | 1342 | |
0bbaf069 | 1343 | /* Set up checksumming */ |
12dea57b | 1344 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
54dc79fe SH |
1345 | fcb = gfar_add_fcb(skb); |
1346 | lstatus |= BD_LFLAG(TXBD_TOE); | |
1347 | gfar_tx_checksum(skb, fcb); | |
0bbaf069 KG |
1348 | } |
1349 | ||
77ecaf2d | 1350 | if (priv->vlgrp && vlan_tx_tag_present(skb)) { |
54dc79fe SH |
1351 | if (unlikely(NULL == fcb)) { |
1352 | fcb = gfar_add_fcb(skb); | |
5a5efed4 | 1353 | lstatus |= BD_LFLAG(TXBD_TOE); |
7f7f5316 | 1354 | } |
54dc79fe SH |
1355 | |
1356 | gfar_tx_vlan(skb, fcb); | |
0bbaf069 KG |
1357 | } |
1358 | ||
4669bc90 | 1359 | /* setup the TxBD length and buffer pointer for the first BD */ |
1da177e4 | 1360 | priv->tx_skbuff[priv->skb_curtx] = skb; |
4826857f | 1361 | txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, |
4669bc90 | 1362 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 1363 | |
4669bc90 | 1364 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); |
1da177e4 | 1365 | |
4669bc90 DH |
1366 | /* |
1367 | * The powerpc-specific eieio() is used, as wmb() has too strong | |
3b6330ce SW |
1368 | * semantics (it requires synchronization between cacheable and |
1369 | * uncacheable mappings, which eieio doesn't provide and which we | |
1370 | * don't need), thus requiring a more expensive sync instruction. At | |
1371 | * some point, the set of architecture-independent barrier functions | |
1372 | * should be expanded to include weaker barriers. | |
1373 | */ | |
3b6330ce | 1374 | eieio(); |
7f7f5316 | 1375 | |
4669bc90 DH |
1376 | txbdp_start->lstatus = lstatus; |
1377 | ||
1378 | /* Update the current skb pointer to the next entry we will use | |
1379 | * (wrapping if necessary) */ | |
1380 | priv->skb_curtx = (priv->skb_curtx + 1) & | |
1381 | TX_RING_MOD_MASK(priv->tx_ring_size); | |
1382 | ||
1383 | priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size); | |
1384 | ||
1385 | /* reduce TxBD free count */ | |
1386 | priv->num_txbdfree -= (nr_frags + 1); | |
1387 | ||
1388 | dev->trans_start = jiffies; | |
1da177e4 LT |
1389 | |
1390 | /* If the next BD still needs to be cleaned up, then the bds | |
1391 | are full. We need to tell the kernel to stop sending us stuff. */ | |
4669bc90 | 1392 | if (!priv->num_txbdfree) { |
1da177e4 LT |
1393 | netif_stop_queue(dev); |
1394 | ||
09f75cd7 | 1395 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
1396 | } |
1397 | ||
1da177e4 LT |
1398 | /* Tell the DMA to go go go */ |
1399 | gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT); | |
1400 | ||
1401 | /* Unlock priv */ | |
fef6108d | 1402 | spin_unlock_irqrestore(&priv->txlock, flags); |
1da177e4 | 1403 | |
54dc79fe | 1404 | return NETDEV_TX_OK; |
1da177e4 LT |
1405 | } |
1406 | ||
1407 | /* Stops the kernel queue, and halts the controller */ | |
1408 | static int gfar_close(struct net_device *dev) | |
1409 | { | |
1410 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e SH |
1411 | |
1412 | napi_disable(&priv->napi); | |
1413 | ||
0fd56bb5 | 1414 | skb_queue_purge(&priv->rx_recycle); |
ab939905 | 1415 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
1416 | stop_gfar(dev); |
1417 | ||
bb40dcbb AF |
1418 | /* Disconnect from the PHY */ |
1419 | phy_disconnect(priv->phydev); | |
1420 | priv->phydev = NULL; | |
1da177e4 LT |
1421 | |
1422 | netif_stop_queue(dev); | |
1423 | ||
1424 | return 0; | |
1425 | } | |
1426 | ||
1da177e4 | 1427 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 1428 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 1429 | { |
7f7f5316 | 1430 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
1431 | |
1432 | return 0; | |
1433 | } | |
1434 | ||
1435 | ||
0bbaf069 KG |
1436 | /* Enables and disables VLAN insertion/extraction */ |
1437 | static void gfar_vlan_rx_register(struct net_device *dev, | |
1438 | struct vlan_group *grp) | |
1439 | { | |
1440 | struct gfar_private *priv = netdev_priv(dev); | |
1441 | unsigned long flags; | |
1442 | u32 tempval; | |
1443 | ||
fef6108d | 1444 | spin_lock_irqsave(&priv->rxlock, flags); |
0bbaf069 | 1445 | |
cd1f55a5 | 1446 | priv->vlgrp = grp; |
0bbaf069 KG |
1447 | |
1448 | if (grp) { | |
1449 | /* Enable VLAN tag insertion */ | |
1450 | tempval = gfar_read(&priv->regs->tctrl); | |
1451 | tempval |= TCTRL_VLINS; | |
1452 | ||
1453 | gfar_write(&priv->regs->tctrl, tempval); | |
6aa20a22 | 1454 | |
0bbaf069 KG |
1455 | /* Enable VLAN tag extraction */ |
1456 | tempval = gfar_read(&priv->regs->rctrl); | |
77ecaf2d | 1457 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); |
0bbaf069 KG |
1458 | gfar_write(&priv->regs->rctrl, tempval); |
1459 | } else { | |
1460 | /* Disable VLAN tag insertion */ | |
1461 | tempval = gfar_read(&priv->regs->tctrl); | |
1462 | tempval &= ~TCTRL_VLINS; | |
1463 | gfar_write(&priv->regs->tctrl, tempval); | |
1464 | ||
1465 | /* Disable VLAN tag extraction */ | |
1466 | tempval = gfar_read(&priv->regs->rctrl); | |
1467 | tempval &= ~RCTRL_VLEX; | |
77ecaf2d DH |
1468 | /* If parse is no longer required, then disable parser */ |
1469 | if (tempval & RCTRL_REQ_PARSER) | |
1470 | tempval |= RCTRL_PRSDEP_INIT; | |
1471 | else | |
1472 | tempval &= ~RCTRL_PRSDEP_INIT; | |
0bbaf069 KG |
1473 | gfar_write(&priv->regs->rctrl, tempval); |
1474 | } | |
1475 | ||
77ecaf2d DH |
1476 | gfar_change_mtu(dev, dev->mtu); |
1477 | ||
fef6108d | 1478 | spin_unlock_irqrestore(&priv->rxlock, flags); |
0bbaf069 KG |
1479 | } |
1480 | ||
1da177e4 LT |
1481 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
1482 | { | |
1483 | int tempsize, tempval; | |
1484 | struct gfar_private *priv = netdev_priv(dev); | |
1485 | int oldsize = priv->rx_buffer_size; | |
0bbaf069 KG |
1486 | int frame_size = new_mtu + ETH_HLEN; |
1487 | ||
77ecaf2d | 1488 | if (priv->vlgrp) |
faa89577 | 1489 | frame_size += VLAN_HLEN; |
0bbaf069 | 1490 | |
1da177e4 | 1491 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
0bbaf069 KG |
1492 | if (netif_msg_drv(priv)) |
1493 | printk(KERN_ERR "%s: Invalid MTU setting\n", | |
1494 | dev->name); | |
1da177e4 LT |
1495 | return -EINVAL; |
1496 | } | |
1497 | ||
77ecaf2d DH |
1498 | if (gfar_uses_fcb(priv)) |
1499 | frame_size += GMAC_FCB_LEN; | |
1500 | ||
1501 | frame_size += priv->padding; | |
1502 | ||
1da177e4 LT |
1503 | tempsize = |
1504 | (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + | |
1505 | INCREMENTAL_BUFFER_SIZE; | |
1506 | ||
1507 | /* Only stop and start the controller if it isn't already | |
7f7f5316 | 1508 | * stopped, and we changed something */ |
1da177e4 LT |
1509 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
1510 | stop_gfar(dev); | |
1511 | ||
1512 | priv->rx_buffer_size = tempsize; | |
1513 | ||
1514 | dev->mtu = new_mtu; | |
1515 | ||
1516 | gfar_write(&priv->regs->mrblr, priv->rx_buffer_size); | |
1517 | gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size); | |
1518 | ||
1519 | /* If the mtu is larger than the max size for standard | |
1520 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
1521 | * to allow huge frames, and to check the length */ | |
1522 | tempval = gfar_read(&priv->regs->maccfg2); | |
1523 | ||
1524 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE) | |
1525 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
1526 | else | |
1527 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
1528 | ||
1529 | gfar_write(&priv->regs->maccfg2, tempval); | |
1530 | ||
1531 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
1532 | startup_gfar(dev); | |
1533 | ||
1534 | return 0; | |
1535 | } | |
1536 | ||
ab939905 | 1537 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
1538 | * transmitted after a set amount of time. |
1539 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
1540 | * starting over will fix the problem. |
1541 | */ | |
1542 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 1543 | { |
ab939905 SS |
1544 | struct gfar_private *priv = container_of(work, struct gfar_private, |
1545 | reset_task); | |
4826857f | 1546 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
1547 | |
1548 | if (dev->flags & IFF_UP) { | |
cbea2707 | 1549 | netif_stop_queue(dev); |
1da177e4 LT |
1550 | stop_gfar(dev); |
1551 | startup_gfar(dev); | |
cbea2707 | 1552 | netif_start_queue(dev); |
1da177e4 LT |
1553 | } |
1554 | ||
263ba320 | 1555 | netif_tx_schedule_all(dev); |
1da177e4 LT |
1556 | } |
1557 | ||
ab939905 SS |
1558 | static void gfar_timeout(struct net_device *dev) |
1559 | { | |
1560 | struct gfar_private *priv = netdev_priv(dev); | |
1561 | ||
1562 | dev->stats.tx_errors++; | |
1563 | schedule_work(&priv->reset_task); | |
1564 | } | |
1565 | ||
1da177e4 | 1566 | /* Interrupt Handler for Transmit complete */ |
f162b9d5 | 1567 | static int gfar_clean_tx_ring(struct net_device *dev) |
1da177e4 | 1568 | { |
d080cd63 | 1569 | struct gfar_private *priv = netdev_priv(dev); |
4669bc90 DH |
1570 | struct txbd8 *bdp; |
1571 | struct txbd8 *lbdp = NULL; | |
1572 | struct txbd8 *base = priv->tx_bd_base; | |
1573 | struct sk_buff *skb; | |
1574 | int skb_dirtytx; | |
1575 | int tx_ring_size = priv->tx_ring_size; | |
1576 | int frags = 0; | |
1577 | int i; | |
d080cd63 | 1578 | int howmany = 0; |
4669bc90 | 1579 | u32 lstatus; |
1da177e4 | 1580 | |
1da177e4 | 1581 | bdp = priv->dirty_tx; |
4669bc90 | 1582 | skb_dirtytx = priv->skb_dirtytx; |
1da177e4 | 1583 | |
4669bc90 DH |
1584 | while ((skb = priv->tx_skbuff[skb_dirtytx])) { |
1585 | frags = skb_shinfo(skb)->nr_frags; | |
1586 | lbdp = skip_txbd(bdp, frags, base, tx_ring_size); | |
1da177e4 | 1587 | |
4669bc90 | 1588 | lstatus = lbdp->lstatus; |
1da177e4 | 1589 | |
4669bc90 DH |
1590 | /* Only clean completed frames */ |
1591 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
1592 | (lstatus & BD_LENGTH_MASK)) | |
1593 | break; | |
1594 | ||
4826857f | 1595 | dma_unmap_single(&priv->ofdev->dev, |
4669bc90 DH |
1596 | bdp->bufPtr, |
1597 | bdp->length, | |
1598 | DMA_TO_DEVICE); | |
81183059 | 1599 | |
4669bc90 DH |
1600 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
1601 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 1602 | |
4669bc90 | 1603 | for (i = 0; i < frags; i++) { |
4826857f | 1604 | dma_unmap_page(&priv->ofdev->dev, |
4669bc90 DH |
1605 | bdp->bufPtr, |
1606 | bdp->length, | |
1607 | DMA_TO_DEVICE); | |
1608 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
1609 | bdp = next_txbd(bdp, base, tx_ring_size); | |
1610 | } | |
1da177e4 | 1611 | |
0fd56bb5 AF |
1612 | /* |
1613 | * If there's room in the queue (limit it to rx_buffer_size) | |
1614 | * we add this skb back into the pool, if it's the right size | |
1615 | */ | |
1616 | if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size && | |
1617 | skb_recycle_check(skb, priv->rx_buffer_size + | |
1618 | RXBUF_ALIGNMENT)) | |
1619 | __skb_queue_head(&priv->rx_recycle, skb); | |
1620 | else | |
1621 | dev_kfree_skb_any(skb); | |
1622 | ||
4669bc90 | 1623 | priv->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 1624 | |
4669bc90 DH |
1625 | skb_dirtytx = (skb_dirtytx + 1) & |
1626 | TX_RING_MOD_MASK(tx_ring_size); | |
1627 | ||
1628 | howmany++; | |
1629 | priv->num_txbdfree += frags + 1; | |
1630 | } | |
1da177e4 | 1631 | |
4669bc90 DH |
1632 | /* If we freed a buffer, we can restart transmission, if necessary */ |
1633 | if (netif_queue_stopped(dev) && priv->num_txbdfree) | |
1634 | netif_wake_queue(dev); | |
1da177e4 | 1635 | |
4669bc90 DH |
1636 | /* Update dirty indicators */ |
1637 | priv->skb_dirtytx = skb_dirtytx; | |
1638 | priv->dirty_tx = bdp; | |
1da177e4 | 1639 | |
d080cd63 DH |
1640 | dev->stats.tx_packets += howmany; |
1641 | ||
1642 | return howmany; | |
1643 | } | |
1644 | ||
8c7396ae | 1645 | static void gfar_schedule_cleanup(struct net_device *dev) |
d080cd63 | 1646 | { |
d080cd63 | 1647 | struct gfar_private *priv = netdev_priv(dev); |
a6d0b91a AV |
1648 | unsigned long flags; |
1649 | ||
1650 | spin_lock_irqsave(&priv->txlock, flags); | |
1651 | spin_lock(&priv->rxlock); | |
1652 | ||
288379f0 | 1653 | if (napi_schedule_prep(&priv->napi)) { |
8c7396ae | 1654 | gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED); |
288379f0 | 1655 | __napi_schedule(&priv->napi); |
8707bdd4 JP |
1656 | } else { |
1657 | /* | |
1658 | * Clear IEVENT, so interrupts aren't called again | |
1659 | * because of the packets that have already arrived. | |
1660 | */ | |
1661 | gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK); | |
2f448911 | 1662 | } |
a6d0b91a AV |
1663 | |
1664 | spin_unlock(&priv->rxlock); | |
1665 | spin_unlock_irqrestore(&priv->txlock, flags); | |
8c7396ae | 1666 | } |
1da177e4 | 1667 | |
8c7396ae DH |
1668 | /* Interrupt Handler for Transmit complete */ |
1669 | static irqreturn_t gfar_transmit(int irq, void *dev_id) | |
1670 | { | |
1671 | gfar_schedule_cleanup((struct net_device *)dev_id); | |
1da177e4 LT |
1672 | return IRQ_HANDLED; |
1673 | } | |
1674 | ||
815b97c6 AF |
1675 | static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp, |
1676 | struct sk_buff *skb) | |
1677 | { | |
1678 | struct gfar_private *priv = netdev_priv(dev); | |
5a5efed4 | 1679 | u32 lstatus; |
815b97c6 | 1680 | |
4826857f | 1681 | bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, |
815b97c6 AF |
1682 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
1683 | ||
5a5efed4 | 1684 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); |
815b97c6 AF |
1685 | |
1686 | if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1) | |
5a5efed4 | 1687 | lstatus |= BD_LFLAG(RXBD_WRAP); |
815b97c6 AF |
1688 | |
1689 | eieio(); | |
1690 | ||
5a5efed4 | 1691 | bdp->lstatus = lstatus; |
815b97c6 AF |
1692 | } |
1693 | ||
1694 | ||
1695 | struct sk_buff * gfar_new_skb(struct net_device *dev) | |
1da177e4 | 1696 | { |
7f7f5316 | 1697 | unsigned int alignamount; |
1da177e4 LT |
1698 | struct gfar_private *priv = netdev_priv(dev); |
1699 | struct sk_buff *skb = NULL; | |
1da177e4 | 1700 | |
0fd56bb5 AF |
1701 | skb = __skb_dequeue(&priv->rx_recycle); |
1702 | if (!skb) | |
1703 | skb = netdev_alloc_skb(dev, | |
1704 | priv->rx_buffer_size + RXBUF_ALIGNMENT); | |
1da177e4 | 1705 | |
815b97c6 | 1706 | if (!skb) |
1da177e4 LT |
1707 | return NULL; |
1708 | ||
7f7f5316 | 1709 | alignamount = RXBUF_ALIGNMENT - |
bea3348e | 1710 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)); |
7f7f5316 | 1711 | |
1da177e4 LT |
1712 | /* We need the data buffer to be aligned properly. We will reserve |
1713 | * as many bytes as needed to align the data properly | |
1714 | */ | |
7f7f5316 | 1715 | skb_reserve(skb, alignamount); |
1da177e4 | 1716 | |
1da177e4 LT |
1717 | return skb; |
1718 | } | |
1719 | ||
298e1a9e | 1720 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 1721 | { |
298e1a9e | 1722 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 1723 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
1724 | struct gfar_extra_stats *estats = &priv->extra_stats; |
1725 | ||
1726 | /* If the packet was truncated, none of the other errors | |
1727 | * matter */ | |
1728 | if (status & RXBD_TRUNCATED) { | |
1729 | stats->rx_length_errors++; | |
1730 | ||
1731 | estats->rx_trunc++; | |
1732 | ||
1733 | return; | |
1734 | } | |
1735 | /* Count the errors, if there were any */ | |
1736 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
1737 | stats->rx_length_errors++; | |
1738 | ||
1739 | if (status & RXBD_LARGE) | |
1740 | estats->rx_large++; | |
1741 | else | |
1742 | estats->rx_short++; | |
1743 | } | |
1744 | if (status & RXBD_NONOCTET) { | |
1745 | stats->rx_frame_errors++; | |
1746 | estats->rx_nonoctet++; | |
1747 | } | |
1748 | if (status & RXBD_CRCERR) { | |
1749 | estats->rx_crcerr++; | |
1750 | stats->rx_crc_errors++; | |
1751 | } | |
1752 | if (status & RXBD_OVERRUN) { | |
1753 | estats->rx_overrun++; | |
1754 | stats->rx_crc_errors++; | |
1755 | } | |
1756 | } | |
1757 | ||
7d12e780 | 1758 | irqreturn_t gfar_receive(int irq, void *dev_id) |
1da177e4 | 1759 | { |
8c7396ae | 1760 | gfar_schedule_cleanup((struct net_device *)dev_id); |
1da177e4 LT |
1761 | return IRQ_HANDLED; |
1762 | } | |
1763 | ||
0bbaf069 KG |
1764 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
1765 | { | |
1766 | /* If valid headers were found, and valid sums | |
1767 | * were verified, then we tell the kernel that no | |
1768 | * checksumming is necessary. Otherwise, it is */ | |
7f7f5316 | 1769 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
1770 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
1771 | else | |
1772 | skb->ip_summed = CHECKSUM_NONE; | |
1773 | } | |
1774 | ||
1775 | ||
1da177e4 LT |
1776 | /* gfar_process_frame() -- handle one incoming packet if skb |
1777 | * isn't NULL. */ | |
1778 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, | |
2c2db48a | 1779 | int amount_pull) |
1da177e4 LT |
1780 | { |
1781 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1782 | struct rxfcb *fcb = NULL; |
1da177e4 | 1783 | |
2c2db48a | 1784 | int ret; |
1da177e4 | 1785 | |
2c2db48a DH |
1786 | /* fcb is at the beginning if exists */ |
1787 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 1788 | |
2c2db48a DH |
1789 | /* Remove the FCB from the skb */ |
1790 | /* Remove the padded bytes, if there are any */ | |
1791 | if (amount_pull) | |
1792 | skb_pull(skb, amount_pull); | |
0bbaf069 | 1793 | |
2c2db48a DH |
1794 | if (priv->rx_csum_enable) |
1795 | gfar_rx_checksum(skb, fcb); | |
0bbaf069 | 1796 | |
2c2db48a DH |
1797 | /* Tell the skb what kind of packet this is */ |
1798 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 1799 | |
2c2db48a DH |
1800 | /* Send the packet up the stack */ |
1801 | if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) | |
1802 | ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl); | |
1803 | else | |
1804 | ret = netif_receive_skb(skb); | |
0bbaf069 | 1805 | |
2c2db48a DH |
1806 | if (NET_RX_DROP == ret) |
1807 | priv->extra_stats.kernel_dropped++; | |
1da177e4 LT |
1808 | |
1809 | return 0; | |
1810 | } | |
1811 | ||
1812 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
0bbaf069 | 1813 | * until the budget/quota has been reached. Returns the number |
1da177e4 LT |
1814 | * of frames handled |
1815 | */ | |
0bbaf069 | 1816 | int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit) |
1da177e4 | 1817 | { |
31de198b | 1818 | struct rxbd8 *bdp, *base; |
1da177e4 | 1819 | struct sk_buff *skb; |
2c2db48a DH |
1820 | int pkt_len; |
1821 | int amount_pull; | |
1da177e4 LT |
1822 | int howmany = 0; |
1823 | struct gfar_private *priv = netdev_priv(dev); | |
1824 | ||
1825 | /* Get the first full descriptor */ | |
1826 | bdp = priv->cur_rx; | |
31de198b | 1827 | base = priv->rx_bd_base; |
1da177e4 | 1828 | |
2c2db48a DH |
1829 | amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) + |
1830 | priv->padding; | |
1831 | ||
1da177e4 | 1832 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 1833 | struct sk_buff *newskb; |
3b6330ce | 1834 | rmb(); |
815b97c6 AF |
1835 | |
1836 | /* Add another skb for the future */ | |
1837 | newskb = gfar_new_skb(dev); | |
1838 | ||
1da177e4 LT |
1839 | skb = priv->rx_skbuff[priv->skb_currx]; |
1840 | ||
4826857f | 1841 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, |
81183059 AF |
1842 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
1843 | ||
815b97c6 AF |
1844 | /* We drop the frame if we failed to allocate a new buffer */ |
1845 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
1846 | bdp->status & RXBD_ERR)) { | |
1847 | count_errors(bdp->status, dev); | |
1848 | ||
1849 | if (unlikely(!newskb)) | |
1850 | newskb = skb; | |
4e2fd555 LB |
1851 | else if (skb) { |
1852 | /* | |
1853 | * We need to reset ->data to what it | |
1854 | * was before gfar_new_skb() re-aligned | |
1855 | * it to an RXBUF_ALIGNMENT boundary | |
1856 | * before we put the skb back on the | |
1857 | * recycle list. | |
1858 | */ | |
1859 | skb->data = skb->head + NET_SKB_PAD; | |
0fd56bb5 | 1860 | __skb_queue_head(&priv->rx_recycle, skb); |
4e2fd555 | 1861 | } |
815b97c6 | 1862 | } else { |
1da177e4 | 1863 | /* Increment the number of packets */ |
09f75cd7 | 1864 | dev->stats.rx_packets++; |
1da177e4 LT |
1865 | howmany++; |
1866 | ||
2c2db48a DH |
1867 | if (likely(skb)) { |
1868 | pkt_len = bdp->length - ETH_FCS_LEN; | |
1869 | /* Remove the FCS from the packet length */ | |
1870 | skb_put(skb, pkt_len); | |
1871 | dev->stats.rx_bytes += pkt_len; | |
1da177e4 | 1872 | |
1577ecef AF |
1873 | if (in_irq() || irqs_disabled()) |
1874 | printk("Interrupt problem!\n"); | |
2c2db48a DH |
1875 | gfar_process_frame(dev, skb, amount_pull); |
1876 | ||
1877 | } else { | |
1878 | if (netif_msg_rx_err(priv)) | |
1879 | printk(KERN_WARNING | |
1880 | "%s: Missing skb!\n", dev->name); | |
1881 | dev->stats.rx_dropped++; | |
1882 | priv->extra_stats.rx_skbmissing++; | |
1883 | } | |
1da177e4 | 1884 | |
1da177e4 LT |
1885 | } |
1886 | ||
815b97c6 | 1887 | priv->rx_skbuff[priv->skb_currx] = newskb; |
1da177e4 | 1888 | |
815b97c6 AF |
1889 | /* Setup the new bdp */ |
1890 | gfar_new_rxbdp(dev, bdp, newskb); | |
1da177e4 LT |
1891 | |
1892 | /* Update to the next pointer */ | |
31de198b | 1893 | bdp = next_bd(bdp, base, priv->rx_ring_size); |
1da177e4 LT |
1894 | |
1895 | /* update to point at the next skb */ | |
1896 | priv->skb_currx = | |
815b97c6 AF |
1897 | (priv->skb_currx + 1) & |
1898 | RX_RING_MOD_MASK(priv->rx_ring_size); | |
1da177e4 LT |
1899 | } |
1900 | ||
1901 | /* Update the current rxbd pointer to be the next one */ | |
1902 | priv->cur_rx = bdp; | |
1903 | ||
1da177e4 LT |
1904 | return howmany; |
1905 | } | |
1906 | ||
bea3348e | 1907 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 1908 | { |
bea3348e | 1909 | struct gfar_private *priv = container_of(napi, struct gfar_private, napi); |
4826857f | 1910 | struct net_device *dev = priv->ndev; |
42199884 AF |
1911 | int tx_cleaned = 0; |
1912 | int rx_cleaned = 0; | |
d080cd63 DH |
1913 | unsigned long flags; |
1914 | ||
8c7396ae DH |
1915 | /* Clear IEVENT, so interrupts aren't called again |
1916 | * because of the packets that have already arrived */ | |
1917 | gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK); | |
1918 | ||
d080cd63 DH |
1919 | /* If we fail to get the lock, don't bother with the TX BDs */ |
1920 | if (spin_trylock_irqsave(&priv->txlock, flags)) { | |
42199884 | 1921 | tx_cleaned = gfar_clean_tx_ring(dev); |
d080cd63 DH |
1922 | spin_unlock_irqrestore(&priv->txlock, flags); |
1923 | } | |
1da177e4 | 1924 | |
42199884 | 1925 | rx_cleaned = gfar_clean_rx_ring(dev, budget); |
1da177e4 | 1926 | |
42199884 AF |
1927 | if (tx_cleaned) |
1928 | return budget; | |
1929 | ||
1930 | if (rx_cleaned < budget) { | |
288379f0 | 1931 | napi_complete(napi); |
1da177e4 LT |
1932 | |
1933 | /* Clear the halt bit in RSTAT */ | |
1934 | gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT); | |
1935 | ||
1936 | gfar_write(&priv->regs->imask, IMASK_DEFAULT); | |
1937 | ||
1938 | /* If we are coalescing interrupts, update the timer */ | |
1939 | /* Otherwise, clear it */ | |
2f448911 AF |
1940 | if (likely(priv->rxcoalescing)) { |
1941 | gfar_write(&priv->regs->rxic, 0); | |
b46a8454 | 1942 | gfar_write(&priv->regs->rxic, priv->rxic); |
2f448911 | 1943 | } |
8c7396ae DH |
1944 | if (likely(priv->txcoalescing)) { |
1945 | gfar_write(&priv->regs->txic, 0); | |
1946 | gfar_write(&priv->regs->txic, priv->txic); | |
1947 | } | |
1da177e4 LT |
1948 | } |
1949 | ||
42199884 | 1950 | return rx_cleaned; |
1da177e4 | 1951 | } |
1da177e4 | 1952 | |
f2d71c2d VW |
1953 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1954 | /* | |
1955 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
1956 | * without having to re-enable interrupts. It's not called while | |
1957 | * the interrupt routine is executing. | |
1958 | */ | |
1959 | static void gfar_netpoll(struct net_device *dev) | |
1960 | { | |
1961 | struct gfar_private *priv = netdev_priv(dev); | |
1962 | ||
1963 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 1964 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
f2d71c2d VW |
1965 | disable_irq(priv->interruptTransmit); |
1966 | disable_irq(priv->interruptReceive); | |
1967 | disable_irq(priv->interruptError); | |
1968 | gfar_interrupt(priv->interruptTransmit, dev); | |
1969 | enable_irq(priv->interruptError); | |
1970 | enable_irq(priv->interruptReceive); | |
1971 | enable_irq(priv->interruptTransmit); | |
1972 | } else { | |
1973 | disable_irq(priv->interruptTransmit); | |
1974 | gfar_interrupt(priv->interruptTransmit, dev); | |
1975 | enable_irq(priv->interruptTransmit); | |
1976 | } | |
1977 | } | |
1978 | #endif | |
1979 | ||
1da177e4 | 1980 | /* The interrupt handler for devices with one interrupt */ |
7d12e780 | 1981 | static irqreturn_t gfar_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1982 | { |
1983 | struct net_device *dev = dev_id; | |
1984 | struct gfar_private *priv = netdev_priv(dev); | |
1985 | ||
1986 | /* Save ievent for future reference */ | |
1987 | u32 events = gfar_read(&priv->regs->ievent); | |
1988 | ||
1da177e4 | 1989 | /* Check for reception */ |
538cc7ee | 1990 | if (events & IEVENT_RX_MASK) |
7d12e780 | 1991 | gfar_receive(irq, dev_id); |
1da177e4 LT |
1992 | |
1993 | /* Check for transmit completion */ | |
538cc7ee | 1994 | if (events & IEVENT_TX_MASK) |
7d12e780 | 1995 | gfar_transmit(irq, dev_id); |
1da177e4 | 1996 | |
538cc7ee SS |
1997 | /* Check for errors */ |
1998 | if (events & IEVENT_ERR_MASK) | |
1999 | gfar_error(irq, dev_id); | |
1da177e4 LT |
2000 | |
2001 | return IRQ_HANDLED; | |
2002 | } | |
2003 | ||
1da177e4 LT |
2004 | /* Called every time the controller might need to be made |
2005 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 2006 | * information through variables in the phydev structure, and this |
1da177e4 LT |
2007 | * function converts those variables into the appropriate |
2008 | * register values, and can bring down the device if needed. | |
2009 | */ | |
2010 | static void adjust_link(struct net_device *dev) | |
2011 | { | |
2012 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 2013 | struct gfar __iomem *regs = priv->regs; |
bb40dcbb AF |
2014 | unsigned long flags; |
2015 | struct phy_device *phydev = priv->phydev; | |
2016 | int new_state = 0; | |
2017 | ||
fef6108d | 2018 | spin_lock_irqsave(&priv->txlock, flags); |
bb40dcbb AF |
2019 | if (phydev->link) { |
2020 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 2021 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 2022 | |
1da177e4 LT |
2023 | /* Now we make sure that we can be in full duplex mode. |
2024 | * If not, we operate in half-duplex mode. */ | |
bb40dcbb AF |
2025 | if (phydev->duplex != priv->oldduplex) { |
2026 | new_state = 1; | |
2027 | if (!(phydev->duplex)) | |
1da177e4 | 2028 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 2029 | else |
1da177e4 | 2030 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 2031 | |
bb40dcbb | 2032 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
2033 | } |
2034 | ||
bb40dcbb AF |
2035 | if (phydev->speed != priv->oldspeed) { |
2036 | new_state = 1; | |
2037 | switch (phydev->speed) { | |
1da177e4 | 2038 | case 1000: |
1da177e4 LT |
2039 | tempval = |
2040 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
2041 | |
2042 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2043 | break; |
2044 | case 100: | |
2045 | case 10: | |
1da177e4 LT |
2046 | tempval = |
2047 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
2048 | |
2049 | /* Reduced mode distinguishes | |
2050 | * between 10 and 100 */ | |
2051 | if (phydev->speed == SPEED_100) | |
2052 | ecntrl |= ECNTRL_R100; | |
2053 | else | |
2054 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2055 | break; |
2056 | default: | |
0bbaf069 KG |
2057 | if (netif_msg_link(priv)) |
2058 | printk(KERN_WARNING | |
bb40dcbb AF |
2059 | "%s: Ack! Speed (%d) is not 10/100/1000!\n", |
2060 | dev->name, phydev->speed); | |
1da177e4 LT |
2061 | break; |
2062 | } | |
2063 | ||
bb40dcbb | 2064 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
2065 | } |
2066 | ||
bb40dcbb | 2067 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 2068 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 2069 | |
1da177e4 | 2070 | if (!priv->oldlink) { |
bb40dcbb | 2071 | new_state = 1; |
1da177e4 | 2072 | priv->oldlink = 1; |
1da177e4 | 2073 | } |
bb40dcbb AF |
2074 | } else if (priv->oldlink) { |
2075 | new_state = 1; | |
2076 | priv->oldlink = 0; | |
2077 | priv->oldspeed = 0; | |
2078 | priv->oldduplex = -1; | |
1da177e4 | 2079 | } |
1da177e4 | 2080 | |
bb40dcbb AF |
2081 | if (new_state && netif_msg_link(priv)) |
2082 | phy_print_status(phydev); | |
2083 | ||
fef6108d | 2084 | spin_unlock_irqrestore(&priv->txlock, flags); |
bb40dcbb | 2085 | } |
1da177e4 LT |
2086 | |
2087 | /* Update the hash table based on the current list of multicast | |
2088 | * addresses we subscribe to. Also, change the promiscuity of | |
2089 | * the device based on the flags (this function is called | |
2090 | * whenever dev->flags is changed */ | |
2091 | static void gfar_set_multi(struct net_device *dev) | |
2092 | { | |
2093 | struct dev_mc_list *mc_ptr; | |
2094 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 2095 | struct gfar __iomem *regs = priv->regs; |
1da177e4 LT |
2096 | u32 tempval; |
2097 | ||
2098 | if(dev->flags & IFF_PROMISC) { | |
1da177e4 LT |
2099 | /* Set RCTRL to PROM */ |
2100 | tempval = gfar_read(®s->rctrl); | |
2101 | tempval |= RCTRL_PROM; | |
2102 | gfar_write(®s->rctrl, tempval); | |
2103 | } else { | |
2104 | /* Set RCTRL to not PROM */ | |
2105 | tempval = gfar_read(®s->rctrl); | |
2106 | tempval &= ~(RCTRL_PROM); | |
2107 | gfar_write(®s->rctrl, tempval); | |
2108 | } | |
6aa20a22 | 2109 | |
1da177e4 LT |
2110 | if(dev->flags & IFF_ALLMULTI) { |
2111 | /* Set the hash to rx all multicast frames */ | |
0bbaf069 KG |
2112 | gfar_write(®s->igaddr0, 0xffffffff); |
2113 | gfar_write(®s->igaddr1, 0xffffffff); | |
2114 | gfar_write(®s->igaddr2, 0xffffffff); | |
2115 | gfar_write(®s->igaddr3, 0xffffffff); | |
2116 | gfar_write(®s->igaddr4, 0xffffffff); | |
2117 | gfar_write(®s->igaddr5, 0xffffffff); | |
2118 | gfar_write(®s->igaddr6, 0xffffffff); | |
2119 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
2120 | gfar_write(®s->gaddr0, 0xffffffff); |
2121 | gfar_write(®s->gaddr1, 0xffffffff); | |
2122 | gfar_write(®s->gaddr2, 0xffffffff); | |
2123 | gfar_write(®s->gaddr3, 0xffffffff); | |
2124 | gfar_write(®s->gaddr4, 0xffffffff); | |
2125 | gfar_write(®s->gaddr5, 0xffffffff); | |
2126 | gfar_write(®s->gaddr6, 0xffffffff); | |
2127 | gfar_write(®s->gaddr7, 0xffffffff); | |
2128 | } else { | |
7f7f5316 AF |
2129 | int em_num; |
2130 | int idx; | |
2131 | ||
1da177e4 | 2132 | /* zero out the hash */ |
0bbaf069 KG |
2133 | gfar_write(®s->igaddr0, 0x0); |
2134 | gfar_write(®s->igaddr1, 0x0); | |
2135 | gfar_write(®s->igaddr2, 0x0); | |
2136 | gfar_write(®s->igaddr3, 0x0); | |
2137 | gfar_write(®s->igaddr4, 0x0); | |
2138 | gfar_write(®s->igaddr5, 0x0); | |
2139 | gfar_write(®s->igaddr6, 0x0); | |
2140 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
2141 | gfar_write(®s->gaddr0, 0x0); |
2142 | gfar_write(®s->gaddr1, 0x0); | |
2143 | gfar_write(®s->gaddr2, 0x0); | |
2144 | gfar_write(®s->gaddr3, 0x0); | |
2145 | gfar_write(®s->gaddr4, 0x0); | |
2146 | gfar_write(®s->gaddr5, 0x0); | |
2147 | gfar_write(®s->gaddr6, 0x0); | |
2148 | gfar_write(®s->gaddr7, 0x0); | |
2149 | ||
7f7f5316 AF |
2150 | /* If we have extended hash tables, we need to |
2151 | * clear the exact match registers to prepare for | |
2152 | * setting them */ | |
2153 | if (priv->extended_hash) { | |
2154 | em_num = GFAR_EM_NUM + 1; | |
2155 | gfar_clear_exact_match(dev); | |
2156 | idx = 1; | |
2157 | } else { | |
2158 | idx = 0; | |
2159 | em_num = 0; | |
2160 | } | |
2161 | ||
1da177e4 LT |
2162 | if(dev->mc_count == 0) |
2163 | return; | |
2164 | ||
2165 | /* Parse the list, and set the appropriate bits */ | |
2166 | for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) { | |
7f7f5316 AF |
2167 | if (idx < em_num) { |
2168 | gfar_set_mac_for_addr(dev, idx, | |
2169 | mc_ptr->dmi_addr); | |
2170 | idx++; | |
2171 | } else | |
2172 | gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr); | |
1da177e4 LT |
2173 | } |
2174 | } | |
2175 | ||
2176 | return; | |
2177 | } | |
2178 | ||
7f7f5316 AF |
2179 | |
2180 | /* Clears each of the exact match registers to zero, so they | |
2181 | * don't interfere with normal reception */ | |
2182 | static void gfar_clear_exact_match(struct net_device *dev) | |
2183 | { | |
2184 | int idx; | |
2185 | u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0}; | |
2186 | ||
2187 | for(idx = 1;idx < GFAR_EM_NUM + 1;idx++) | |
2188 | gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr); | |
2189 | } | |
2190 | ||
1da177e4 LT |
2191 | /* Set the appropriate hash bit for the given addr */ |
2192 | /* The algorithm works like so: | |
2193 | * 1) Take the Destination Address (ie the multicast address), and | |
2194 | * do a CRC on it (little endian), and reverse the bits of the | |
2195 | * result. | |
2196 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
2197 | * table. The table is controlled through 8 32-bit registers: | |
2198 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
2199 | * gaddr7. This means that the 3 most significant bits in the | |
2200 | * hash index which gaddr register to use, and the 5 other bits | |
2201 | * indicate which bit (assuming an IBM numbering scheme, which | |
2202 | * for PowerPC (tm) is usually the case) in the register holds | |
2203 | * the entry. */ | |
2204 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) | |
2205 | { | |
2206 | u32 tempval; | |
2207 | struct gfar_private *priv = netdev_priv(dev); | |
1da177e4 | 2208 | u32 result = ether_crc(MAC_ADDR_LEN, addr); |
0bbaf069 KG |
2209 | int width = priv->hash_width; |
2210 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
2211 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
2212 | u32 value = (1 << (31-whichbit)); |
2213 | ||
0bbaf069 | 2214 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 2215 | tempval |= value; |
0bbaf069 | 2216 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
2217 | |
2218 | return; | |
2219 | } | |
2220 | ||
7f7f5316 AF |
2221 | |
2222 | /* There are multiple MAC Address register pairs on some controllers | |
2223 | * This function sets the numth pair to a given address | |
2224 | */ | |
2225 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr) | |
2226 | { | |
2227 | struct gfar_private *priv = netdev_priv(dev); | |
2228 | int idx; | |
2229 | char tmpbuf[MAC_ADDR_LEN]; | |
2230 | u32 tempval; | |
cc8c6e37 | 2231 | u32 __iomem *macptr = &priv->regs->macstnaddr1; |
7f7f5316 AF |
2232 | |
2233 | macptr += num*2; | |
2234 | ||
2235 | /* Now copy it into the mac registers backwards, cuz */ | |
2236 | /* little endian is silly */ | |
2237 | for (idx = 0; idx < MAC_ADDR_LEN; idx++) | |
2238 | tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx]; | |
2239 | ||
2240 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
2241 | ||
2242 | tempval = *((u32 *) (tmpbuf + 4)); | |
2243 | ||
2244 | gfar_write(macptr+1, tempval); | |
2245 | } | |
2246 | ||
1da177e4 | 2247 | /* GFAR error interrupt handler */ |
7d12e780 | 2248 | static irqreturn_t gfar_error(int irq, void *dev_id) |
1da177e4 LT |
2249 | { |
2250 | struct net_device *dev = dev_id; | |
2251 | struct gfar_private *priv = netdev_priv(dev); | |
2252 | ||
2253 | /* Save ievent for future reference */ | |
2254 | u32 events = gfar_read(&priv->regs->ievent); | |
2255 | ||
2256 | /* Clear IEVENT */ | |
d87eb127 SW |
2257 | gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK); |
2258 | ||
2259 | /* Magic Packet is not an error. */ | |
b31a1d8b | 2260 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
2261 | (events & IEVENT_MAG)) |
2262 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
2263 | |
2264 | /* Hmm... */ | |
0bbaf069 KG |
2265 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
2266 | printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
538cc7ee | 2267 | dev->name, events, gfar_read(&priv->regs->imask)); |
1da177e4 LT |
2268 | |
2269 | /* Update the error counters */ | |
2270 | if (events & IEVENT_TXE) { | |
09f75cd7 | 2271 | dev->stats.tx_errors++; |
1da177e4 LT |
2272 | |
2273 | if (events & IEVENT_LC) | |
09f75cd7 | 2274 | dev->stats.tx_window_errors++; |
1da177e4 | 2275 | if (events & IEVENT_CRL) |
09f75cd7 | 2276 | dev->stats.tx_aborted_errors++; |
1da177e4 | 2277 | if (events & IEVENT_XFUN) { |
0bbaf069 | 2278 | if (netif_msg_tx_err(priv)) |
538cc7ee SS |
2279 | printk(KERN_DEBUG "%s: TX FIFO underrun, " |
2280 | "packet dropped.\n", dev->name); | |
09f75cd7 | 2281 | dev->stats.tx_dropped++; |
1da177e4 LT |
2282 | priv->extra_stats.tx_underrun++; |
2283 | ||
2284 | /* Reactivate the Tx Queues */ | |
2285 | gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT); | |
2286 | } | |
0bbaf069 KG |
2287 | if (netif_msg_tx_err(priv)) |
2288 | printk(KERN_DEBUG "%s: Transmit Error\n", dev->name); | |
1da177e4 LT |
2289 | } |
2290 | if (events & IEVENT_BSY) { | |
09f75cd7 | 2291 | dev->stats.rx_errors++; |
1da177e4 LT |
2292 | priv->extra_stats.rx_bsy++; |
2293 | ||
7d12e780 | 2294 | gfar_receive(irq, dev_id); |
1da177e4 | 2295 | |
0bbaf069 | 2296 | if (netif_msg_rx_err(priv)) |
538cc7ee SS |
2297 | printk(KERN_DEBUG "%s: busy error (rstat: %x)\n", |
2298 | dev->name, gfar_read(&priv->regs->rstat)); | |
1da177e4 LT |
2299 | } |
2300 | if (events & IEVENT_BABR) { | |
09f75cd7 | 2301 | dev->stats.rx_errors++; |
1da177e4 LT |
2302 | priv->extra_stats.rx_babr++; |
2303 | ||
0bbaf069 | 2304 | if (netif_msg_rx_err(priv)) |
538cc7ee | 2305 | printk(KERN_DEBUG "%s: babbling RX error\n", dev->name); |
1da177e4 LT |
2306 | } |
2307 | if (events & IEVENT_EBERR) { | |
2308 | priv->extra_stats.eberr++; | |
0bbaf069 | 2309 | if (netif_msg_rx_err(priv)) |
538cc7ee | 2310 | printk(KERN_DEBUG "%s: bus error\n", dev->name); |
1da177e4 | 2311 | } |
0bbaf069 | 2312 | if ((events & IEVENT_RXC) && netif_msg_rx_status(priv)) |
538cc7ee | 2313 | printk(KERN_DEBUG "%s: control frame\n", dev->name); |
1da177e4 LT |
2314 | |
2315 | if (events & IEVENT_BABT) { | |
2316 | priv->extra_stats.tx_babt++; | |
0bbaf069 | 2317 | if (netif_msg_tx_err(priv)) |
538cc7ee | 2318 | printk(KERN_DEBUG "%s: babbling TX error\n", dev->name); |
1da177e4 LT |
2319 | } |
2320 | return IRQ_HANDLED; | |
2321 | } | |
2322 | ||
72abb461 KS |
2323 | /* work with hotplug and coldplug */ |
2324 | MODULE_ALIAS("platform:fsl-gianfar"); | |
2325 | ||
b31a1d8b AF |
2326 | static struct of_device_id gfar_match[] = |
2327 | { | |
2328 | { | |
2329 | .type = "network", | |
2330 | .compatible = "gianfar", | |
2331 | }, | |
2332 | {}, | |
2333 | }; | |
2334 | ||
1da177e4 | 2335 | /* Structure for a device driver */ |
b31a1d8b AF |
2336 | static struct of_platform_driver gfar_driver = { |
2337 | .name = "fsl-gianfar", | |
2338 | .match_table = gfar_match, | |
2339 | ||
1da177e4 LT |
2340 | .probe = gfar_probe, |
2341 | .remove = gfar_remove, | |
d87eb127 SW |
2342 | .suspend = gfar_suspend, |
2343 | .resume = gfar_resume, | |
1da177e4 LT |
2344 | }; |
2345 | ||
2346 | static int __init gfar_init(void) | |
2347 | { | |
1577ecef | 2348 | return of_register_platform_driver(&gfar_driver); |
1da177e4 LT |
2349 | } |
2350 | ||
2351 | static void __exit gfar_exit(void) | |
2352 | { | |
b31a1d8b | 2353 | of_unregister_platform_driver(&gfar_driver); |
1da177e4 LT |
2354 | } |
2355 | ||
2356 | module_init(gfar_init); | |
2357 | module_exit(gfar_exit); | |
2358 |