Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
1da177e4 LT |
20 | */ |
21 | ||
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/kernel.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/skbuff.h> | |
36 | #include <linux/spinlock.h> | |
37 | #include <linux/workqueue.h> | |
38 | #include <linux/bitops.h> | |
6f501b17 SH |
39 | #include <linux/io.h> |
40 | #include <linux/irq.h> | |
196719ec | 41 | #include <linux/clk.h> |
ead73183 | 42 | #include <linux/platform_device.h> |
e6b043d5 | 43 | #include <linux/phy.h> |
5eb32bd0 | 44 | #include <linux/fec.h> |
1da177e4 | 45 | |
080853af | 46 | #include <asm/cacheflush.h> |
196719ec SH |
47 | |
48 | #ifndef CONFIG_ARCH_MXC | |
1da177e4 LT |
49 | #include <asm/coldfire.h> |
50 | #include <asm/mcfsim.h> | |
196719ec | 51 | #endif |
6f501b17 | 52 | |
1da177e4 | 53 | #include "fec.h" |
1da177e4 | 54 | |
196719ec SH |
55 | #ifdef CONFIG_ARCH_MXC |
56 | #include <mach/hardware.h> | |
57 | #define FEC_ALIGNMENT 0xf | |
58 | #else | |
59 | #define FEC_ALIGNMENT 0x3 | |
60 | #endif | |
61 | ||
49da97dc SG |
62 | static unsigned char macaddr[ETH_ALEN]; |
63 | module_param_array(macaddr, byte, NULL, 0); | |
64 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 65 | |
49da97dc | 66 | #if defined(CONFIG_M5272) |
1da177e4 LT |
67 | /* |
68 | * Some hardware gets it MAC address out of local flash memory. | |
69 | * if this is non-zero then assume it is the address to get MAC from. | |
70 | */ | |
71 | #if defined(CONFIG_NETtel) | |
72 | #define FEC_FLASHMAC 0xf0006006 | |
73 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
74 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
75 | #elif defined(CONFIG_CANCam) |
76 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
77 | #elif defined (CONFIG_M5272C3) |
78 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
79 | #elif defined(CONFIG_MOD5272) | |
80 | #define FEC_FLASHMAC 0xffc0406b | |
1da177e4 LT |
81 | #else |
82 | #define FEC_FLASHMAC 0 | |
83 | #endif | |
43be6366 | 84 | #endif /* CONFIG_M5272 */ |
ead73183 | 85 | |
1da177e4 LT |
86 | /* The number of Tx and Rx buffers. These are allocated from the page |
87 | * pool. The code may assume these are power of two, so it it best | |
88 | * to keep them that size. | |
89 | * We don't need to allocate pages for the transmitter. We just use | |
90 | * the skbuffer directly. | |
91 | */ | |
92 | #define FEC_ENET_RX_PAGES 8 | |
93 | #define FEC_ENET_RX_FRSIZE 2048 | |
94 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | |
95 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | |
96 | #define FEC_ENET_TX_FRSIZE 2048 | |
97 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) | |
98 | #define TX_RING_SIZE 16 /* Must be power of two */ | |
99 | #define TX_RING_MOD_MASK 15 /* for this to work */ | |
100 | ||
562d2f8c | 101 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
6b265293 | 102 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
103 | #endif |
104 | ||
22f6b860 | 105 | /* Interrupt events/masks. */ |
1da177e4 LT |
106 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
107 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
108 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
109 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
110 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
111 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
112 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
113 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
114 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
115 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
116 | ||
4bee1f9a WS |
117 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
118 | ||
1da177e4 LT |
119 | /* The FEC stores dest/src/type, data, and checksum for receive packets. |
120 | */ | |
121 | #define PKT_MAXBUF_SIZE 1518 | |
122 | #define PKT_MINBUF_SIZE 64 | |
123 | #define PKT_MAXBLR_SIZE 1520 | |
124 | ||
125 | ||
126 | /* | |
6b265293 | 127 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
128 | * size bits. Other FEC hardware does not, so we need to take that into |
129 | * account when setting it. | |
130 | */ | |
562d2f8c | 131 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
196719ec | 132 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC) |
1da177e4 LT |
133 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
134 | #else | |
135 | #define OPT_FRAME_SIZE 0 | |
136 | #endif | |
137 | ||
138 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | |
139 | * tx_bd_base always point to the base of the buffer descriptors. The | |
140 | * cur_rx and cur_tx point to the currently available buffer. | |
141 | * The dirty_tx tracks the current buffer that is being sent by the | |
142 | * controller. The cur_tx and dirty_tx are equal under both completely | |
143 | * empty and completely full conditions. The empty/ready indicator in | |
144 | * the buffer descriptor determines the actual condition. | |
145 | */ | |
146 | struct fec_enet_private { | |
147 | /* Hardware registers of the FEC device */ | |
f44d6305 | 148 | void __iomem *hwp; |
1da177e4 | 149 | |
cb84d6e7 GU |
150 | struct net_device *netdev; |
151 | ||
ead73183 SH |
152 | struct clk *clk; |
153 | ||
1da177e4 LT |
154 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
155 | unsigned char *tx_bounce[TX_RING_SIZE]; | |
156 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
f0b3fbea | 157 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; |
1da177e4 LT |
158 | ushort skb_cur; |
159 | ushort skb_dirty; | |
160 | ||
22f6b860 | 161 | /* CPM dual port RAM relative addresses */ |
4661e75b | 162 | dma_addr_t bd_dma; |
22f6b860 | 163 | /* Address of Rx and Tx buffers */ |
2e28532f SH |
164 | struct bufdesc *rx_bd_base; |
165 | struct bufdesc *tx_bd_base; | |
166 | /* The next free ring entry */ | |
167 | struct bufdesc *cur_rx, *cur_tx; | |
22f6b860 | 168 | /* The ring entries to be free()ed */ |
2e28532f SH |
169 | struct bufdesc *dirty_tx; |
170 | ||
1da177e4 | 171 | uint tx_full; |
3b2b74ca SS |
172 | /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ |
173 | spinlock_t hw_lock; | |
1da177e4 | 174 | |
e6b043d5 | 175 | struct platform_device *pdev; |
1da177e4 | 176 | |
e6b043d5 | 177 | int opened; |
1da177e4 | 178 | |
e6b043d5 BW |
179 | /* Phylib and MDIO interface */ |
180 | struct mii_bus *mii_bus; | |
181 | struct phy_device *phy_dev; | |
182 | int mii_timeout; | |
183 | uint phy_speed; | |
5eb32bd0 | 184 | phy_interface_t phy_interface; |
1da177e4 | 185 | int link; |
1da177e4 | 186 | int full_duplex; |
97b72e43 | 187 | struct completion mdio_done; |
1da177e4 LT |
188 | }; |
189 | ||
7d12e780 | 190 | static irqreturn_t fec_enet_interrupt(int irq, void * dev_id); |
1da177e4 LT |
191 | static void fec_enet_tx(struct net_device *dev); |
192 | static void fec_enet_rx(struct net_device *dev); | |
193 | static int fec_enet_close(struct net_device *dev); | |
1da177e4 LT |
194 | static void fec_restart(struct net_device *dev, int duplex); |
195 | static void fec_stop(struct net_device *dev); | |
1da177e4 | 196 | |
e6b043d5 BW |
197 | /* FEC MII MMFR bits definition */ |
198 | #define FEC_MMFR_ST (1 << 30) | |
199 | #define FEC_MMFR_OP_READ (2 << 28) | |
200 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
201 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
202 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
203 | #define FEC_MMFR_TA (2 << 16) | |
204 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 205 | |
97b72e43 | 206 | #define FEC_MII_TIMEOUT 1000 /* us */ |
1da177e4 | 207 | |
22f6b860 SH |
208 | /* Transmitter timeout */ |
209 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 210 | |
c7621cb3 | 211 | static netdev_tx_t |
1da177e4 LT |
212 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) |
213 | { | |
f44d6305 | 214 | struct fec_enet_private *fep = netdev_priv(dev); |
2e28532f | 215 | struct bufdesc *bdp; |
9555b31e | 216 | void *bufaddr; |
0e702ab3 | 217 | unsigned short status; |
3b2b74ca | 218 | unsigned long flags; |
1da177e4 | 219 | |
1da177e4 LT |
220 | if (!fep->link) { |
221 | /* Link is down or autonegotiation is in progress. */ | |
5b548140 | 222 | return NETDEV_TX_BUSY; |
1da177e4 LT |
223 | } |
224 | ||
3b2b74ca | 225 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 LT |
226 | /* Fill in a Tx ring entry */ |
227 | bdp = fep->cur_tx; | |
228 | ||
0e702ab3 | 229 | status = bdp->cbd_sc; |
22f6b860 | 230 | |
0e702ab3 | 231 | if (status & BD_ENET_TX_READY) { |
1da177e4 LT |
232 | /* Ooops. All transmit buffers are full. Bail out. |
233 | * This should not happen, since dev->tbusy should be set. | |
234 | */ | |
235 | printk("%s: tx queue full!.\n", dev->name); | |
3b2b74ca | 236 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
5b548140 | 237 | return NETDEV_TX_BUSY; |
1da177e4 | 238 | } |
1da177e4 | 239 | |
22f6b860 | 240 | /* Clear all of the status flags */ |
0e702ab3 | 241 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 242 | |
22f6b860 | 243 | /* Set buffer length and buffer pointer */ |
9555b31e | 244 | bufaddr = skb->data; |
1da177e4 LT |
245 | bdp->cbd_datlen = skb->len; |
246 | ||
247 | /* | |
22f6b860 SH |
248 | * On some FEC implementations data must be aligned on |
249 | * 4-byte boundaries. Use bounce buffers to copy data | |
250 | * and get it aligned. Ugh. | |
1da177e4 | 251 | */ |
9555b31e | 252 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
1da177e4 LT |
253 | unsigned int index; |
254 | index = bdp - fep->tx_bd_base; | |
6989f512 | 255 | memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len); |
9555b31e | 256 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
257 | } |
258 | ||
22f6b860 | 259 | /* Save skb pointer */ |
1da177e4 LT |
260 | fep->tx_skbuff[fep->skb_cur] = skb; |
261 | ||
09f75cd7 | 262 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 263 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
6aa20a22 | 264 | |
1da177e4 LT |
265 | /* Push the data cache so the CPM does not get stale memory |
266 | * data. | |
267 | */ | |
9555b31e | 268 | bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr, |
f0b3fbea | 269 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 270 | |
0e702ab3 GU |
271 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
272 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 273 | */ |
0e702ab3 | 274 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 275 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 276 | bdp->cbd_sc = status; |
1da177e4 | 277 | |
1da177e4 | 278 | /* Trigger transmission start */ |
f44d6305 | 279 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); |
1da177e4 | 280 | |
22f6b860 SH |
281 | /* If this was the last BD in the ring, start at the beginning again. */ |
282 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 283 | bdp = fep->tx_bd_base; |
22f6b860 | 284 | else |
1da177e4 | 285 | bdp++; |
1da177e4 LT |
286 | |
287 | if (bdp == fep->dirty_tx) { | |
288 | fep->tx_full = 1; | |
289 | netif_stop_queue(dev); | |
290 | } | |
291 | ||
2e28532f | 292 | fep->cur_tx = bdp; |
1da177e4 | 293 | |
3b2b74ca | 294 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
1da177e4 | 295 | |
6ed10654 | 296 | return NETDEV_TX_OK; |
1da177e4 LT |
297 | } |
298 | ||
299 | static void | |
300 | fec_timeout(struct net_device *dev) | |
301 | { | |
302 | struct fec_enet_private *fep = netdev_priv(dev); | |
303 | ||
09f75cd7 | 304 | dev->stats.tx_errors++; |
1da177e4 | 305 | |
7dd6a2aa | 306 | fec_restart(dev, fep->full_duplex); |
1da177e4 LT |
307 | netif_wake_queue(dev); |
308 | } | |
309 | ||
1da177e4 | 310 | static irqreturn_t |
7d12e780 | 311 | fec_enet_interrupt(int irq, void * dev_id) |
1da177e4 LT |
312 | { |
313 | struct net_device *dev = dev_id; | |
f44d6305 | 314 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 | 315 | uint int_events; |
3b2b74ca | 316 | irqreturn_t ret = IRQ_NONE; |
1da177e4 | 317 | |
3b2b74ca | 318 | do { |
f44d6305 SH |
319 | int_events = readl(fep->hwp + FEC_IEVENT); |
320 | writel(int_events, fep->hwp + FEC_IEVENT); | |
1da177e4 | 321 | |
1da177e4 | 322 | if (int_events & FEC_ENET_RXF) { |
3b2b74ca | 323 | ret = IRQ_HANDLED; |
1da177e4 LT |
324 | fec_enet_rx(dev); |
325 | } | |
326 | ||
327 | /* Transmit OK, or non-fatal error. Update the buffer | |
f44d6305 SH |
328 | * descriptors. FEC handles all errors, we just discover |
329 | * them as part of the transmit process. | |
330 | */ | |
1da177e4 | 331 | if (int_events & FEC_ENET_TXF) { |
3b2b74ca | 332 | ret = IRQ_HANDLED; |
1da177e4 LT |
333 | fec_enet_tx(dev); |
334 | } | |
97b72e43 BS |
335 | |
336 | if (int_events & FEC_ENET_MII) { | |
337 | ret = IRQ_HANDLED; | |
338 | complete(&fep->mdio_done); | |
339 | } | |
3b2b74ca SS |
340 | } while (int_events); |
341 | ||
342 | return ret; | |
1da177e4 LT |
343 | } |
344 | ||
345 | ||
346 | static void | |
347 | fec_enet_tx(struct net_device *dev) | |
348 | { | |
349 | struct fec_enet_private *fep; | |
2e28532f | 350 | struct bufdesc *bdp; |
0e702ab3 | 351 | unsigned short status; |
1da177e4 LT |
352 | struct sk_buff *skb; |
353 | ||
354 | fep = netdev_priv(dev); | |
81538e74 | 355 | spin_lock(&fep->hw_lock); |
1da177e4 LT |
356 | bdp = fep->dirty_tx; |
357 | ||
0e702ab3 | 358 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
f0b3fbea SH |
359 | if (bdp == fep->cur_tx && fep->tx_full == 0) |
360 | break; | |
361 | ||
362 | dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); | |
363 | bdp->cbd_bufaddr = 0; | |
1da177e4 LT |
364 | |
365 | skb = fep->tx_skbuff[fep->skb_dirty]; | |
366 | /* Check for errors. */ | |
0e702ab3 | 367 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
368 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
369 | BD_ENET_TX_CSL)) { | |
09f75cd7 | 370 | dev->stats.tx_errors++; |
0e702ab3 | 371 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
09f75cd7 | 372 | dev->stats.tx_heartbeat_errors++; |
0e702ab3 | 373 | if (status & BD_ENET_TX_LC) /* Late collision */ |
09f75cd7 | 374 | dev->stats.tx_window_errors++; |
0e702ab3 | 375 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
09f75cd7 | 376 | dev->stats.tx_aborted_errors++; |
0e702ab3 | 377 | if (status & BD_ENET_TX_UN) /* Underrun */ |
09f75cd7 | 378 | dev->stats.tx_fifo_errors++; |
0e702ab3 | 379 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
09f75cd7 | 380 | dev->stats.tx_carrier_errors++; |
1da177e4 | 381 | } else { |
09f75cd7 | 382 | dev->stats.tx_packets++; |
1da177e4 LT |
383 | } |
384 | ||
0e702ab3 | 385 | if (status & BD_ENET_TX_READY) |
1da177e4 | 386 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
22f6b860 | 387 | |
1da177e4 LT |
388 | /* Deferred means some collisions occurred during transmit, |
389 | * but we eventually sent the packet OK. | |
390 | */ | |
0e702ab3 | 391 | if (status & BD_ENET_TX_DEF) |
09f75cd7 | 392 | dev->stats.collisions++; |
6aa20a22 | 393 | |
22f6b860 | 394 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 LT |
395 | dev_kfree_skb_any(skb); |
396 | fep->tx_skbuff[fep->skb_dirty] = NULL; | |
397 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
6aa20a22 | 398 | |
22f6b860 | 399 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 400 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
401 | bdp = fep->tx_bd_base; |
402 | else | |
403 | bdp++; | |
6aa20a22 | 404 | |
22f6b860 | 405 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 LT |
406 | */ |
407 | if (fep->tx_full) { | |
408 | fep->tx_full = 0; | |
409 | if (netif_queue_stopped(dev)) | |
410 | netif_wake_queue(dev); | |
411 | } | |
412 | } | |
2e28532f | 413 | fep->dirty_tx = bdp; |
81538e74 | 414 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
415 | } |
416 | ||
417 | ||
418 | /* During a receive, the cur_rx points to the current incoming buffer. | |
419 | * When we update through the ring, if the next incoming buffer has | |
420 | * not been given to the system, we just set the empty indicator, | |
421 | * effectively tossing the packet. | |
422 | */ | |
423 | static void | |
424 | fec_enet_rx(struct net_device *dev) | |
425 | { | |
f44d6305 | 426 | struct fec_enet_private *fep = netdev_priv(dev); |
2e28532f | 427 | struct bufdesc *bdp; |
0e702ab3 | 428 | unsigned short status; |
1da177e4 LT |
429 | struct sk_buff *skb; |
430 | ushort pkt_len; | |
431 | __u8 *data; | |
6aa20a22 | 432 | |
0e702ab3 GU |
433 | #ifdef CONFIG_M532x |
434 | flush_cache_all(); | |
6aa20a22 | 435 | #endif |
1da177e4 | 436 | |
81538e74 | 437 | spin_lock(&fep->hw_lock); |
3b2b74ca | 438 | |
1da177e4 LT |
439 | /* First, grab all of the stats for the incoming packet. |
440 | * These get messed up if we get called due to a busy condition. | |
441 | */ | |
442 | bdp = fep->cur_rx; | |
443 | ||
22f6b860 | 444 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 445 | |
22f6b860 SH |
446 | /* Since we have allocated space to hold a complete frame, |
447 | * the last indicator should be set. | |
448 | */ | |
449 | if ((status & BD_ENET_RX_LAST) == 0) | |
450 | printk("FEC ENET: rcv is not +last\n"); | |
1da177e4 | 451 | |
22f6b860 SH |
452 | if (!fep->opened) |
453 | goto rx_processing_done; | |
1da177e4 | 454 | |
22f6b860 SH |
455 | /* Check for errors. */ |
456 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 457 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
22f6b860 SH |
458 | dev->stats.rx_errors++; |
459 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { | |
460 | /* Frame too long or too short. */ | |
461 | dev->stats.rx_length_errors++; | |
462 | } | |
463 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
464 | dev->stats.rx_frame_errors++; | |
465 | if (status & BD_ENET_RX_CR) /* CRC Error */ | |
466 | dev->stats.rx_crc_errors++; | |
467 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ | |
468 | dev->stats.rx_fifo_errors++; | |
1da177e4 | 469 | } |
1da177e4 | 470 | |
22f6b860 SH |
471 | /* Report late collisions as a frame error. |
472 | * On this error, the BD is closed, but we don't know what we | |
473 | * have in the buffer. So, just drop this frame on the floor. | |
474 | */ | |
475 | if (status & BD_ENET_RX_CL) { | |
476 | dev->stats.rx_errors++; | |
477 | dev->stats.rx_frame_errors++; | |
478 | goto rx_processing_done; | |
479 | } | |
1da177e4 | 480 | |
22f6b860 SH |
481 | /* Process the incoming frame. */ |
482 | dev->stats.rx_packets++; | |
483 | pkt_len = bdp->cbd_datlen; | |
484 | dev->stats.rx_bytes += pkt_len; | |
485 | data = (__u8*)__va(bdp->cbd_bufaddr); | |
1da177e4 | 486 | |
f0b3fbea SH |
487 | dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen, |
488 | DMA_FROM_DEVICE); | |
ccdc4f19 | 489 | |
22f6b860 SH |
490 | /* This does 16 byte alignment, exactly what we need. |
491 | * The packet length includes FCS, but we don't want to | |
492 | * include that when passing upstream as it messes up | |
493 | * bridging applications. | |
494 | */ | |
8549889c | 495 | skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 496 | |
8549889c | 497 | if (unlikely(!skb)) { |
22f6b860 SH |
498 | printk("%s: Memory squeeze, dropping packet.\n", |
499 | dev->name); | |
500 | dev->stats.rx_dropped++; | |
501 | } else { | |
8549889c | 502 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 SH |
503 | skb_put(skb, pkt_len - 4); /* Make room */ |
504 | skb_copy_to_linear_data(skb, data, pkt_len - 4); | |
505 | skb->protocol = eth_type_trans(skb, dev); | |
506 | netif_rx(skb); | |
507 | } | |
f0b3fbea SH |
508 | |
509 | bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen, | |
510 | DMA_FROM_DEVICE); | |
22f6b860 SH |
511 | rx_processing_done: |
512 | /* Clear the status flags for this buffer */ | |
513 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 514 | |
22f6b860 SH |
515 | /* Mark the buffer empty */ |
516 | status |= BD_ENET_RX_EMPTY; | |
517 | bdp->cbd_sc = status; | |
6aa20a22 | 518 | |
22f6b860 SH |
519 | /* Update BD pointer to next entry */ |
520 | if (status & BD_ENET_RX_WRAP) | |
521 | bdp = fep->rx_bd_base; | |
522 | else | |
523 | bdp++; | |
524 | /* Doing this here will keep the FEC running while we process | |
525 | * incoming frames. On a heavily loaded network, we should be | |
526 | * able to keep up at the expense of system resources. | |
527 | */ | |
528 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
529 | } | |
2e28532f | 530 | fep->cur_rx = bdp; |
1da177e4 | 531 | |
81538e74 | 532 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
533 | } |
534 | ||
e6b043d5 | 535 | /* ------------------------------------------------------------------------- */ |
e6b043d5 | 536 | static void __inline__ fec_get_mac(struct net_device *dev) |
1da177e4 | 537 | { |
e6b043d5 | 538 | struct fec_enet_private *fep = netdev_priv(dev); |
49da97dc | 539 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
e6b043d5 | 540 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 541 | |
49da97dc SG |
542 | /* |
543 | * try to get mac address in following order: | |
544 | * | |
545 | * 1) module parameter via kernel command line in form | |
546 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
547 | */ | |
548 | iap = macaddr; | |
549 | ||
550 | /* | |
551 | * 2) from flash or fuse (via platform data) | |
552 | */ | |
553 | if (!is_valid_ether_addr(iap)) { | |
554 | #ifdef CONFIG_M5272 | |
555 | if (FEC_FLASHMAC) | |
556 | iap = (unsigned char *)FEC_FLASHMAC; | |
557 | #else | |
558 | if (pdata) | |
559 | memcpy(iap, pdata->mac, ETH_ALEN); | |
560 | #endif | |
561 | } | |
562 | ||
563 | /* | |
564 | * 3) FEC mac registers set by bootloader | |
565 | */ | |
566 | if (!is_valid_ether_addr(iap)) { | |
567 | *((unsigned long *) &tmpaddr[0]) = | |
568 | be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); | |
569 | *((unsigned short *) &tmpaddr[4]) = | |
570 | be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 571 | iap = &tmpaddr[0]; |
1da177e4 LT |
572 | } |
573 | ||
e6b043d5 | 574 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 575 | |
49da97dc SG |
576 | /* Adjust MAC if using macaddr */ |
577 | if (iap == macaddr) | |
578 | dev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id; | |
1da177e4 LT |
579 | } |
580 | ||
e6b043d5 | 581 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 582 | |
e6b043d5 BW |
583 | /* |
584 | * Phy section | |
585 | */ | |
586 | static void fec_enet_adjust_link(struct net_device *dev) | |
1da177e4 LT |
587 | { |
588 | struct fec_enet_private *fep = netdev_priv(dev); | |
e6b043d5 BW |
589 | struct phy_device *phy_dev = fep->phy_dev; |
590 | unsigned long flags; | |
1da177e4 | 591 | |
e6b043d5 | 592 | int status_change = 0; |
1da177e4 | 593 | |
e6b043d5 | 594 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 | 595 | |
e6b043d5 BW |
596 | /* Prevent a state halted on mii error */ |
597 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
598 | phy_dev->state = PHY_RESUMING; | |
599 | goto spin_unlock; | |
600 | } | |
1da177e4 | 601 | |
e6b043d5 BW |
602 | /* Duplex link change */ |
603 | if (phy_dev->link) { | |
604 | if (fep->full_duplex != phy_dev->duplex) { | |
605 | fec_restart(dev, phy_dev->duplex); | |
606 | status_change = 1; | |
607 | } | |
608 | } | |
1da177e4 | 609 | |
e6b043d5 BW |
610 | /* Link on or off change */ |
611 | if (phy_dev->link != fep->link) { | |
612 | fep->link = phy_dev->link; | |
613 | if (phy_dev->link) | |
614 | fec_restart(dev, phy_dev->duplex); | |
1da177e4 | 615 | else |
e6b043d5 BW |
616 | fec_stop(dev); |
617 | status_change = 1; | |
1da177e4 | 618 | } |
6aa20a22 | 619 | |
e6b043d5 BW |
620 | spin_unlock: |
621 | spin_unlock_irqrestore(&fep->hw_lock, flags); | |
1da177e4 | 622 | |
e6b043d5 BW |
623 | if (status_change) |
624 | phy_print_status(phy_dev); | |
625 | } | |
1da177e4 | 626 | |
e6b043d5 | 627 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 628 | { |
e6b043d5 | 629 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 630 | unsigned long time_left; |
1da177e4 | 631 | |
e6b043d5 | 632 | fep->mii_timeout = 0; |
97b72e43 | 633 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
634 | |
635 | /* start a read op */ | |
636 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
637 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
638 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
639 | ||
640 | /* wait for end of transfer */ | |
97b72e43 BS |
641 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
642 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
643 | if (time_left == 0) { | |
644 | fep->mii_timeout = 1; | |
645 | printk(KERN_ERR "FEC: MDIO read timeout\n"); | |
646 | return -ETIMEDOUT; | |
1da177e4 | 647 | } |
1da177e4 | 648 | |
e6b043d5 BW |
649 | /* return value */ |
650 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 651 | } |
6aa20a22 | 652 | |
e6b043d5 BW |
653 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
654 | u16 value) | |
1da177e4 | 655 | { |
e6b043d5 | 656 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 657 | unsigned long time_left; |
1da177e4 | 658 | |
e6b043d5 | 659 | fep->mii_timeout = 0; |
97b72e43 | 660 | init_completion(&fep->mdio_done); |
1da177e4 | 661 | |
862f0982 SG |
662 | /* start a write op */ |
663 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
664 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
665 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
666 | fep->hwp + FEC_MII_DATA); | |
667 | ||
668 | /* wait for end of transfer */ | |
97b72e43 BS |
669 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
670 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
671 | if (time_left == 0) { | |
672 | fep->mii_timeout = 1; | |
673 | printk(KERN_ERR "FEC: MDIO write timeout\n"); | |
674 | return -ETIMEDOUT; | |
e6b043d5 | 675 | } |
1da177e4 | 676 | |
e6b043d5 BW |
677 | return 0; |
678 | } | |
1da177e4 | 679 | |
e6b043d5 | 680 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 681 | { |
e6b043d5 | 682 | return 0; |
1da177e4 LT |
683 | } |
684 | ||
e6b043d5 | 685 | static int fec_enet_mii_probe(struct net_device *dev) |
562d2f8c | 686 | { |
4cf1653a | 687 | struct fec_enet_private *fep = netdev_priv(dev); |
e6b043d5 | 688 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
689 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
690 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
691 | int phy_id; | |
562d2f8c | 692 | |
418bd0d4 BW |
693 | fep->phy_dev = NULL; |
694 | ||
6fcc040f GU |
695 | /* check for attached phy */ |
696 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
697 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
698 | continue; | |
699 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
700 | continue; | |
701 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
702 | continue; | |
703 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); | |
704 | break; | |
e6b043d5 | 705 | } |
1da177e4 | 706 | |
6fcc040f GU |
707 | if (phy_id >= PHY_MAX_ADDR) { |
708 | printk(KERN_INFO "%s: no PHY, assuming direct connection " | |
709 | "to switch\n", dev->name); | |
710 | strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); | |
711 | phy_id = 0; | |
712 | } | |
713 | ||
714 | snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id); | |
715 | phy_dev = phy_connect(dev, phy_name, &fec_enet_adjust_link, 0, | |
716 | PHY_INTERFACE_MODE_MII); | |
717 | if (IS_ERR(phy_dev)) { | |
718 | printk(KERN_ERR "%s: could not attach to PHY\n", dev->name); | |
719 | return PTR_ERR(phy_dev); | |
e6b043d5 | 720 | } |
1da177e4 | 721 | |
e6b043d5 BW |
722 | /* mask with MAC supported features */ |
723 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
724 | phy_dev->advertising = phy_dev->supported; | |
1da177e4 | 725 | |
e6b043d5 BW |
726 | fep->phy_dev = phy_dev; |
727 | fep->link = 0; | |
728 | fep->full_duplex = 0; | |
1da177e4 | 729 | |
418bd0d4 BW |
730 | printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] " |
731 | "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name, | |
732 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), | |
733 | fep->phy_dev->irq); | |
734 | ||
e6b043d5 | 735 | return 0; |
1da177e4 LT |
736 | } |
737 | ||
e6b043d5 | 738 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 739 | { |
e6b043d5 | 740 | struct net_device *dev = platform_get_drvdata(pdev); |
562d2f8c | 741 | struct fec_enet_private *fep = netdev_priv(dev); |
e6b043d5 | 742 | int err = -ENXIO, i; |
6b265293 | 743 | |
e6b043d5 | 744 | fep->mii_timeout = 0; |
1da177e4 | 745 | |
e6b043d5 BW |
746 | /* |
747 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
748 | */ | |
749 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1; | |
750 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
1da177e4 | 751 | |
e6b043d5 BW |
752 | fep->mii_bus = mdiobus_alloc(); |
753 | if (fep->mii_bus == NULL) { | |
754 | err = -ENOMEM; | |
755 | goto err_out; | |
1da177e4 LT |
756 | } |
757 | ||
e6b043d5 BW |
758 | fep->mii_bus->name = "fec_enet_mii_bus"; |
759 | fep->mii_bus->read = fec_enet_mdio_read; | |
760 | fep->mii_bus->write = fec_enet_mdio_write; | |
761 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
6fcc040f | 762 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id + 1); |
e6b043d5 BW |
763 | fep->mii_bus->priv = fep; |
764 | fep->mii_bus->parent = &pdev->dev; | |
765 | ||
766 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
767 | if (!fep->mii_bus->irq) { | |
768 | err = -ENOMEM; | |
769 | goto err_out_free_mdiobus; | |
1da177e4 LT |
770 | } |
771 | ||
e6b043d5 BW |
772 | for (i = 0; i < PHY_MAX_ADDR; i++) |
773 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 774 | |
e6b043d5 | 775 | platform_set_drvdata(dev, fep->mii_bus); |
1da177e4 | 776 | |
e6b043d5 BW |
777 | if (mdiobus_register(fep->mii_bus)) |
778 | goto err_out_free_mdio_irq; | |
1da177e4 | 779 | |
e6b043d5 | 780 | return 0; |
1da177e4 | 781 | |
e6b043d5 BW |
782 | err_out_free_mdio_irq: |
783 | kfree(fep->mii_bus->irq); | |
784 | err_out_free_mdiobus: | |
785 | mdiobus_free(fep->mii_bus); | |
786 | err_out: | |
787 | return err; | |
1da177e4 LT |
788 | } |
789 | ||
e6b043d5 | 790 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 791 | { |
e6b043d5 BW |
792 | if (fep->phy_dev) |
793 | phy_disconnect(fep->phy_dev); | |
794 | mdiobus_unregister(fep->mii_bus); | |
795 | kfree(fep->mii_bus->irq); | |
796 | mdiobus_free(fep->mii_bus); | |
1da177e4 LT |
797 | } |
798 | ||
e6b043d5 BW |
799 | static int fec_enet_get_settings(struct net_device *dev, |
800 | struct ethtool_cmd *cmd) | |
1da177e4 LT |
801 | { |
802 | struct fec_enet_private *fep = netdev_priv(dev); | |
e6b043d5 | 803 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 804 | |
e6b043d5 BW |
805 | if (!phydev) |
806 | return -ENODEV; | |
1da177e4 | 807 | |
e6b043d5 | 808 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
809 | } |
810 | ||
e6b043d5 BW |
811 | static int fec_enet_set_settings(struct net_device *dev, |
812 | struct ethtool_cmd *cmd) | |
1da177e4 LT |
813 | { |
814 | struct fec_enet_private *fep = netdev_priv(dev); | |
e6b043d5 | 815 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 816 | |
e6b043d5 BW |
817 | if (!phydev) |
818 | return -ENODEV; | |
1da177e4 | 819 | |
e6b043d5 | 820 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
821 | } |
822 | ||
e6b043d5 BW |
823 | static void fec_enet_get_drvinfo(struct net_device *dev, |
824 | struct ethtool_drvinfo *info) | |
1da177e4 | 825 | { |
e6b043d5 | 826 | struct fec_enet_private *fep = netdev_priv(dev); |
6aa20a22 | 827 | |
e6b043d5 BW |
828 | strcpy(info->driver, fep->pdev->dev.driver->name); |
829 | strcpy(info->version, "Revision: 1.0"); | |
830 | strcpy(info->bus_info, dev_name(&dev->dev)); | |
1da177e4 LT |
831 | } |
832 | ||
e6b043d5 BW |
833 | static struct ethtool_ops fec_enet_ethtool_ops = { |
834 | .get_settings = fec_enet_get_settings, | |
835 | .set_settings = fec_enet_set_settings, | |
836 | .get_drvinfo = fec_enet_get_drvinfo, | |
837 | .get_link = ethtool_op_get_link, | |
838 | }; | |
1da177e4 | 839 | |
e6b043d5 | 840 | static int fec_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
1da177e4 | 841 | { |
1da177e4 | 842 | struct fec_enet_private *fep = netdev_priv(dev); |
e6b043d5 | 843 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 844 | |
e6b043d5 BW |
845 | if (!netif_running(dev)) |
846 | return -EINVAL; | |
1da177e4 | 847 | |
e6b043d5 BW |
848 | if (!phydev) |
849 | return -ENODEV; | |
850 | ||
28b04113 | 851 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
852 | } |
853 | ||
f0b3fbea SH |
854 | static void fec_enet_free_buffers(struct net_device *dev) |
855 | { | |
856 | struct fec_enet_private *fep = netdev_priv(dev); | |
857 | int i; | |
858 | struct sk_buff *skb; | |
859 | struct bufdesc *bdp; | |
860 | ||
861 | bdp = fep->rx_bd_base; | |
862 | for (i = 0; i < RX_RING_SIZE; i++) { | |
863 | skb = fep->rx_skbuff[i]; | |
864 | ||
865 | if (bdp->cbd_bufaddr) | |
866 | dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, | |
867 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); | |
868 | if (skb) | |
869 | dev_kfree_skb(skb); | |
870 | bdp++; | |
871 | } | |
872 | ||
873 | bdp = fep->tx_bd_base; | |
874 | for (i = 0; i < TX_RING_SIZE; i++) | |
875 | kfree(fep->tx_bounce[i]); | |
876 | } | |
877 | ||
878 | static int fec_enet_alloc_buffers(struct net_device *dev) | |
879 | { | |
880 | struct fec_enet_private *fep = netdev_priv(dev); | |
881 | int i; | |
882 | struct sk_buff *skb; | |
883 | struct bufdesc *bdp; | |
884 | ||
885 | bdp = fep->rx_bd_base; | |
886 | for (i = 0; i < RX_RING_SIZE; i++) { | |
887 | skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE); | |
888 | if (!skb) { | |
889 | fec_enet_free_buffers(dev); | |
890 | return -ENOMEM; | |
891 | } | |
892 | fep->rx_skbuff[i] = skb; | |
893 | ||
894 | bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data, | |
895 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); | |
896 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
897 | bdp++; | |
898 | } | |
899 | ||
900 | /* Set the last buffer to wrap. */ | |
901 | bdp--; | |
902 | bdp->cbd_sc |= BD_SC_WRAP; | |
903 | ||
904 | bdp = fep->tx_bd_base; | |
905 | for (i = 0; i < TX_RING_SIZE; i++) { | |
906 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
907 | ||
908 | bdp->cbd_sc = 0; | |
909 | bdp->cbd_bufaddr = 0; | |
910 | bdp++; | |
911 | } | |
912 | ||
913 | /* Set the last buffer to wrap. */ | |
914 | bdp--; | |
915 | bdp->cbd_sc |= BD_SC_WRAP; | |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
1da177e4 LT |
920 | static int |
921 | fec_enet_open(struct net_device *dev) | |
922 | { | |
923 | struct fec_enet_private *fep = netdev_priv(dev); | |
f0b3fbea | 924 | int ret; |
1da177e4 LT |
925 | |
926 | /* I should reset the ring buffers here, but I don't yet know | |
927 | * a simple way to do that. | |
928 | */ | |
1da177e4 | 929 | |
f0b3fbea SH |
930 | ret = fec_enet_alloc_buffers(dev); |
931 | if (ret) | |
932 | return ret; | |
933 | ||
418bd0d4 BW |
934 | /* Probe and connect to PHY when open the interface */ |
935 | ret = fec_enet_mii_probe(dev); | |
936 | if (ret) { | |
937 | fec_enet_free_buffers(dev); | |
938 | return ret; | |
939 | } | |
e6b043d5 | 940 | phy_start(fep->phy_dev); |
1da177e4 LT |
941 | netif_start_queue(dev); |
942 | fep->opened = 1; | |
22f6b860 | 943 | return 0; |
1da177e4 LT |
944 | } |
945 | ||
946 | static int | |
947 | fec_enet_close(struct net_device *dev) | |
948 | { | |
949 | struct fec_enet_private *fep = netdev_priv(dev); | |
950 | ||
22f6b860 | 951 | /* Don't know what to do yet. */ |
1da177e4 LT |
952 | fep->opened = 0; |
953 | netif_stop_queue(dev); | |
954 | fec_stop(dev); | |
955 | ||
418bd0d4 BW |
956 | if (fep->phy_dev) |
957 | phy_disconnect(fep->phy_dev); | |
958 | ||
f0b3fbea SH |
959 | fec_enet_free_buffers(dev); |
960 | ||
1da177e4 LT |
961 | return 0; |
962 | } | |
963 | ||
1da177e4 LT |
964 | /* Set or clear the multicast filter for this adaptor. |
965 | * Skeleton taken from sunlance driver. | |
966 | * The CPM Ethernet implementation allows Multicast as well as individual | |
967 | * MAC address filtering. Some of the drivers check to make sure it is | |
968 | * a group multicast address, and discard those that are not. I guess I | |
969 | * will do the same for now, but just remove the test if you want | |
970 | * individual filtering as well (do the upper net layers want or support | |
971 | * this kind of feature?). | |
972 | */ | |
973 | ||
974 | #define HASH_BITS 6 /* #bits in hash */ | |
975 | #define CRC32_POLY 0xEDB88320 | |
976 | ||
977 | static void set_multicast_list(struct net_device *dev) | |
978 | { | |
f44d6305 | 979 | struct fec_enet_private *fep = netdev_priv(dev); |
22bedad3 | 980 | struct netdev_hw_addr *ha; |
48e2f183 | 981 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
982 | unsigned char hash; |
983 | ||
22f6b860 | 984 | if (dev->flags & IFF_PROMISC) { |
f44d6305 SH |
985 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
986 | tmp |= 0x8; | |
987 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
988 | return; |
989 | } | |
1da177e4 | 990 | |
4e831836 SH |
991 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
992 | tmp &= ~0x8; | |
993 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
994 | ||
995 | if (dev->flags & IFF_ALLMULTI) { | |
996 | /* Catch all multicast addresses, so set the | |
997 | * filter to all 1's | |
998 | */ | |
999 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1000 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1001 | ||
1002 | return; | |
1003 | } | |
1004 | ||
1005 | /* Clear filter and add the addresses in hash register | |
1006 | */ | |
1007 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1008 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1009 | ||
22bedad3 | 1010 | netdev_for_each_mc_addr(ha, dev) { |
4e831836 | 1011 | /* Only support group multicast for now */ |
22bedad3 | 1012 | if (!(ha->addr[0] & 1)) |
4e831836 SH |
1013 | continue; |
1014 | ||
1015 | /* calculate crc32 value of mac address */ | |
1016 | crc = 0xffffffff; | |
1017 | ||
22bedad3 JP |
1018 | for (i = 0; i < dev->addr_len; i++) { |
1019 | data = ha->addr[i]; | |
4e831836 SH |
1020 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1021 | crc = (crc >> 1) ^ | |
1022 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1023 | } |
1024 | } | |
4e831836 SH |
1025 | |
1026 | /* only upper 6 bits (HASH_BITS) are used | |
1027 | * which point to specific bit in he hash registers | |
1028 | */ | |
1029 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1030 | ||
1031 | if (hash > 31) { | |
1032 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1033 | tmp |= 1 << (hash - 32); | |
1034 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1035 | } else { | |
1036 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1037 | tmp |= 1 << hash; | |
1038 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1039 | } | |
1da177e4 LT |
1040 | } |
1041 | } | |
1042 | ||
22f6b860 | 1043 | /* Set a MAC change in hardware. */ |
009fda83 SH |
1044 | static int |
1045 | fec_set_mac_address(struct net_device *dev, void *p) | |
1da177e4 | 1046 | { |
f44d6305 | 1047 | struct fec_enet_private *fep = netdev_priv(dev); |
009fda83 SH |
1048 | struct sockaddr *addr = p; |
1049 | ||
1050 | if (!is_valid_ether_addr(addr->sa_data)) | |
1051 | return -EADDRNOTAVAIL; | |
1052 | ||
1053 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
1da177e4 | 1054 | |
f44d6305 SH |
1055 | writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) | |
1056 | (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24), | |
1057 | fep->hwp + FEC_ADDR_LOW); | |
1058 | writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24), | |
7cff0943 | 1059 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1060 | return 0; |
1da177e4 LT |
1061 | } |
1062 | ||
009fda83 SH |
1063 | static const struct net_device_ops fec_netdev_ops = { |
1064 | .ndo_open = fec_enet_open, | |
1065 | .ndo_stop = fec_enet_close, | |
1066 | .ndo_start_xmit = fec_enet_start_xmit, | |
1067 | .ndo_set_multicast_list = set_multicast_list, | |
635ecaa7 | 1068 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1069 | .ndo_validate_addr = eth_validate_addr, |
1070 | .ndo_tx_timeout = fec_timeout, | |
1071 | .ndo_set_mac_address = fec_set_mac_address, | |
e6b043d5 | 1072 | .ndo_do_ioctl = fec_enet_ioctl, |
009fda83 SH |
1073 | }; |
1074 | ||
1da177e4 LT |
1075 | /* |
1076 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 1077 | * |
1da177e4 | 1078 | */ |
8649a230 | 1079 | static int fec_enet_init(struct net_device *dev) |
1da177e4 LT |
1080 | { |
1081 | struct fec_enet_private *fep = netdev_priv(dev); | |
f0b3fbea | 1082 | struct bufdesc *cbd_base; |
633e7533 | 1083 | struct bufdesc *bdp; |
f0b3fbea | 1084 | int i; |
1da177e4 | 1085 | |
8d4dd5cf SH |
1086 | /* Allocate memory for buffer descriptors. */ |
1087 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
1088 | GFP_KERNEL); | |
1089 | if (!cbd_base) { | |
562d2f8c GU |
1090 | printk("FEC: allocate descriptor memory failed?\n"); |
1091 | return -ENOMEM; | |
1092 | } | |
1093 | ||
3b2b74ca | 1094 | spin_lock_init(&fep->hw_lock); |
3b2b74ca | 1095 | |
f44d6305 | 1096 | fep->hwp = (void __iomem *)dev->base_addr; |
cb84d6e7 | 1097 | fep->netdev = dev; |
1da177e4 | 1098 | |
49da97dc | 1099 | /* Get the Ethernet address */ |
1da177e4 LT |
1100 | fec_get_mac(dev); |
1101 | ||
8d4dd5cf | 1102 | /* Set receive and transmit descriptor base. */ |
1da177e4 LT |
1103 | fep->rx_bd_base = cbd_base; |
1104 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1105 | ||
22f6b860 | 1106 | /* The FEC Ethernet specific entries in the device structure */ |
1da177e4 | 1107 | dev->watchdog_timeo = TX_TIMEOUT; |
009fda83 | 1108 | dev->netdev_ops = &fec_netdev_ops; |
e6b043d5 | 1109 | dev->ethtool_ops = &fec_enet_ethtool_ops; |
633e7533 RH |
1110 | |
1111 | /* Initialize the receive buffer descriptors. */ | |
1112 | bdp = fep->rx_bd_base; | |
1113 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1114 | ||
1115 | /* Initialize the BD for every fragment in the page. */ | |
1116 | bdp->cbd_sc = 0; | |
1117 | bdp++; | |
1118 | } | |
1119 | ||
1120 | /* Set the last buffer to wrap */ | |
1121 | bdp--; | |
1122 | bdp->cbd_sc |= BD_SC_WRAP; | |
1123 | ||
1124 | /* ...and the same for transmit */ | |
1125 | bdp = fep->tx_bd_base; | |
1126 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1127 | ||
1128 | /* Initialize the BD for every fragment in the page. */ | |
1129 | bdp->cbd_sc = 0; | |
1130 | bdp->cbd_bufaddr = 0; | |
1131 | bdp++; | |
1132 | } | |
1133 | ||
1134 | /* Set the last buffer to wrap */ | |
1135 | bdp--; | |
1136 | bdp->cbd_sc |= BD_SC_WRAP; | |
1137 | ||
ead73183 | 1138 | fec_restart(dev, 0); |
1da177e4 | 1139 | |
1da177e4 LT |
1140 | return 0; |
1141 | } | |
1142 | ||
1143 | /* This function is called to start or restart the FEC during a link | |
1144 | * change. This only happens when switching between half and full | |
1145 | * duplex. | |
1146 | */ | |
1147 | static void | |
1148 | fec_restart(struct net_device *dev, int duplex) | |
1149 | { | |
f44d6305 | 1150 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 LT |
1151 | int i; |
1152 | ||
f44d6305 SH |
1153 | /* Whack a reset. We should wait for this. */ |
1154 | writel(1, fep->hwp + FEC_ECNTRL); | |
1da177e4 LT |
1155 | udelay(10); |
1156 | ||
f44d6305 SH |
1157 | /* Clear any outstanding interrupt. */ |
1158 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 1159 | |
f44d6305 SH |
1160 | /* Reset all multicast. */ |
1161 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1162 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
4f1ceb4b SH |
1163 | #ifndef CONFIG_M5272 |
1164 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
1165 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
1166 | #endif | |
1da177e4 | 1167 | |
f44d6305 SH |
1168 | /* Set maximum receive buffer size. */ |
1169 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 1170 | |
f44d6305 SH |
1171 | /* Set receive and transmit descriptor base. */ |
1172 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
2e28532f | 1173 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, |
f44d6305 | 1174 | fep->hwp + FEC_X_DES_START); |
1da177e4 LT |
1175 | |
1176 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
1177 | fep->cur_rx = fep->rx_bd_base; | |
1178 | ||
f44d6305 | 1179 | /* Reset SKB transmit buffers. */ |
1da177e4 | 1180 | fep->skb_cur = fep->skb_dirty = 0; |
22f6b860 SH |
1181 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { |
1182 | if (fep->tx_skbuff[i]) { | |
1da177e4 LT |
1183 | dev_kfree_skb_any(fep->tx_skbuff[i]); |
1184 | fep->tx_skbuff[i] = NULL; | |
1185 | } | |
1186 | } | |
1187 | ||
22f6b860 | 1188 | /* Enable MII mode */ |
1da177e4 | 1189 | if (duplex) { |
f44d6305 SH |
1190 | /* MII enable / FD enable */ |
1191 | writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL); | |
1192 | writel(0x04, fep->hwp + FEC_X_CNTRL); | |
f909b1ef | 1193 | } else { |
f44d6305 SH |
1194 | /* MII enable / No Rcv on Xmit */ |
1195 | writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL); | |
1196 | writel(0x0, fep->hwp + FEC_X_CNTRL); | |
1da177e4 LT |
1197 | } |
1198 | fep->full_duplex = duplex; | |
1199 | ||
22f6b860 | 1200 | /* Set MII speed */ |
f44d6305 | 1201 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1202 | |
5eb32bd0 BS |
1203 | #ifdef FEC_MIIGSK_ENR |
1204 | if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) { | |
1205 | /* disable the gasket and wait */ | |
1206 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
1207 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
1208 | udelay(1); | |
1209 | ||
1210 | /* configure the gasket: RMII, 50 MHz, no loopback, no echo */ | |
1211 | writel(1, fep->hwp + FEC_MIIGSK_CFGR); | |
1212 | ||
1213 | /* re-enable the gasket */ | |
1214 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
1215 | } | |
1216 | #endif | |
1217 | ||
22f6b860 | 1218 | /* And last, enable the transmit and receive processing */ |
f44d6305 SH |
1219 | writel(2, fep->hwp + FEC_ECNTRL); |
1220 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
6b265293 | 1221 | |
22f6b860 | 1222 | /* Enable interrupts we wish to service */ |
4bee1f9a | 1223 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); |
1da177e4 LT |
1224 | } |
1225 | ||
1226 | static void | |
1227 | fec_stop(struct net_device *dev) | |
1228 | { | |
f44d6305 | 1229 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 | 1230 | |
22f6b860 | 1231 | /* We cannot expect a graceful transmit stop without link !!! */ |
f44d6305 SH |
1232 | if (fep->link) { |
1233 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
677177c5 | 1234 | udelay(10); |
f44d6305 | 1235 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) |
677177c5 | 1236 | printk("fec_stop : Graceful transmit stop did not complete !\n"); |
f44d6305 | 1237 | } |
1da177e4 | 1238 | |
f44d6305 SH |
1239 | /* Whack a reset. We should wait for this. */ |
1240 | writel(1, fep->hwp + FEC_ECNTRL); | |
1da177e4 | 1241 | udelay(10); |
f44d6305 | 1242 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
4bee1f9a | 1243 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); |
1da177e4 LT |
1244 | } |
1245 | ||
ead73183 SH |
1246 | static int __devinit |
1247 | fec_probe(struct platform_device *pdev) | |
1248 | { | |
1249 | struct fec_enet_private *fep; | |
5eb32bd0 | 1250 | struct fec_platform_data *pdata; |
ead73183 SH |
1251 | struct net_device *ndev; |
1252 | int i, irq, ret = 0; | |
1253 | struct resource *r; | |
1254 | ||
1255 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1256 | if (!r) | |
1257 | return -ENXIO; | |
1258 | ||
1259 | r = request_mem_region(r->start, resource_size(r), pdev->name); | |
1260 | if (!r) | |
1261 | return -EBUSY; | |
1262 | ||
1263 | /* Init network device */ | |
1264 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
1265 | if (!ndev) | |
1266 | return -ENOMEM; | |
1267 | ||
1268 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1269 | ||
1270 | /* setup board info structure */ | |
1271 | fep = netdev_priv(ndev); | |
1272 | memset(fep, 0, sizeof(*fep)); | |
1273 | ||
1274 | ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r)); | |
e6b043d5 | 1275 | fep->pdev = pdev; |
ead73183 SH |
1276 | |
1277 | if (!ndev->base_addr) { | |
1278 | ret = -ENOMEM; | |
1279 | goto failed_ioremap; | |
1280 | } | |
1281 | ||
1282 | platform_set_drvdata(pdev, ndev); | |
1283 | ||
5eb32bd0 BS |
1284 | pdata = pdev->dev.platform_data; |
1285 | if (pdata) | |
1286 | fep->phy_interface = pdata->phy; | |
1287 | ||
ead73183 SH |
1288 | /* This device has up to three irqs on some platforms */ |
1289 | for (i = 0; i < 3; i++) { | |
1290 | irq = platform_get_irq(pdev, i); | |
1291 | if (i && irq < 0) | |
1292 | break; | |
1293 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); | |
1294 | if (ret) { | |
1295 | while (i >= 0) { | |
1296 | irq = platform_get_irq(pdev, i); | |
1297 | free_irq(irq, ndev); | |
1298 | i--; | |
1299 | } | |
1300 | goto failed_irq; | |
1301 | } | |
1302 | } | |
1303 | ||
1304 | fep->clk = clk_get(&pdev->dev, "fec_clk"); | |
1305 | if (IS_ERR(fep->clk)) { | |
1306 | ret = PTR_ERR(fep->clk); | |
1307 | goto failed_clk; | |
1308 | } | |
1309 | clk_enable(fep->clk); | |
1310 | ||
8649a230 | 1311 | ret = fec_enet_init(ndev); |
ead73183 SH |
1312 | if (ret) |
1313 | goto failed_init; | |
1314 | ||
e6b043d5 BW |
1315 | ret = fec_enet_mii_init(pdev); |
1316 | if (ret) | |
1317 | goto failed_mii_init; | |
1318 | ||
03c698c9 OS |
1319 | /* Carrier starts down, phylib will bring it up */ |
1320 | netif_carrier_off(ndev); | |
1321 | ||
ead73183 SH |
1322 | ret = register_netdev(ndev); |
1323 | if (ret) | |
1324 | goto failed_register; | |
1325 | ||
1326 | return 0; | |
1327 | ||
1328 | failed_register: | |
e6b043d5 BW |
1329 | fec_enet_mii_remove(fep); |
1330 | failed_mii_init: | |
ead73183 SH |
1331 | failed_init: |
1332 | clk_disable(fep->clk); | |
1333 | clk_put(fep->clk); | |
1334 | failed_clk: | |
1335 | for (i = 0; i < 3; i++) { | |
1336 | irq = platform_get_irq(pdev, i); | |
1337 | if (irq > 0) | |
1338 | free_irq(irq, ndev); | |
1339 | } | |
1340 | failed_irq: | |
1341 | iounmap((void __iomem *)ndev->base_addr); | |
1342 | failed_ioremap: | |
1343 | free_netdev(ndev); | |
1344 | ||
1345 | return ret; | |
1346 | } | |
1347 | ||
1348 | static int __devexit | |
1349 | fec_drv_remove(struct platform_device *pdev) | |
1350 | { | |
1351 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1352 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1353 | ||
1354 | platform_set_drvdata(pdev, NULL); | |
1355 | ||
1356 | fec_stop(ndev); | |
e6b043d5 | 1357 | fec_enet_mii_remove(fep); |
ead73183 SH |
1358 | clk_disable(fep->clk); |
1359 | clk_put(fep->clk); | |
1360 | iounmap((void __iomem *)ndev->base_addr); | |
1361 | unregister_netdev(ndev); | |
1362 | free_netdev(ndev); | |
1363 | return 0; | |
1364 | } | |
1365 | ||
59d4289b | 1366 | #ifdef CONFIG_PM |
ead73183 | 1367 | static int |
87cad5c3 | 1368 | fec_suspend(struct device *dev) |
ead73183 | 1369 | { |
87cad5c3 | 1370 | struct net_device *ndev = dev_get_drvdata(dev); |
ead73183 SH |
1371 | struct fec_enet_private *fep; |
1372 | ||
1373 | if (ndev) { | |
1374 | fep = netdev_priv(ndev); | |
bcc67771 SG |
1375 | if (netif_running(ndev)) { |
1376 | fec_stop(ndev); | |
1377 | netif_device_detach(ndev); | |
1378 | } | |
e3fe8558 | 1379 | clk_disable(fep->clk); |
ead73183 SH |
1380 | } |
1381 | return 0; | |
1382 | } | |
1383 | ||
1384 | static int | |
87cad5c3 | 1385 | fec_resume(struct device *dev) |
ead73183 | 1386 | { |
87cad5c3 | 1387 | struct net_device *ndev = dev_get_drvdata(dev); |
e3fe8558 | 1388 | struct fec_enet_private *fep; |
ead73183 SH |
1389 | |
1390 | if (ndev) { | |
e3fe8558 EB |
1391 | fep = netdev_priv(ndev); |
1392 | clk_enable(fep->clk); | |
bcc67771 SG |
1393 | if (netif_running(ndev)) { |
1394 | fec_restart(ndev, fep->full_duplex); | |
1395 | netif_device_attach(ndev); | |
1396 | } | |
ead73183 SH |
1397 | } |
1398 | return 0; | |
1399 | } | |
1400 | ||
59d4289b DK |
1401 | static const struct dev_pm_ops fec_pm_ops = { |
1402 | .suspend = fec_suspend, | |
1403 | .resume = fec_resume, | |
1404 | .freeze = fec_suspend, | |
1405 | .thaw = fec_resume, | |
1406 | .poweroff = fec_suspend, | |
1407 | .restore = fec_resume, | |
1408 | }; | |
87cad5c3 | 1409 | #endif |
59d4289b | 1410 | |
ead73183 SH |
1411 | static struct platform_driver fec_driver = { |
1412 | .driver = { | |
87cad5c3 EB |
1413 | .name = "fec", |
1414 | .owner = THIS_MODULE, | |
1415 | #ifdef CONFIG_PM | |
1416 | .pm = &fec_pm_ops, | |
1417 | #endif | |
ead73183 | 1418 | }, |
87cad5c3 EB |
1419 | .probe = fec_probe, |
1420 | .remove = __devexit_p(fec_drv_remove), | |
ead73183 SH |
1421 | }; |
1422 | ||
1423 | static int __init | |
1424 | fec_enet_module_init(void) | |
1425 | { | |
1426 | printk(KERN_INFO "FEC Ethernet Driver\n"); | |
1427 | ||
1428 | return platform_driver_register(&fec_driver); | |
1429 | } | |
1430 | ||
1431 | static void __exit | |
1432 | fec_enet_cleanup(void) | |
1433 | { | |
1434 | platform_driver_unregister(&fec_driver); | |
1435 | } | |
1436 | ||
1437 | module_exit(fec_enet_cleanup); | |
1da177e4 LT |
1438 | module_init(fec_enet_module_init); |
1439 | ||
1440 | MODULE_LICENSE("GPL"); |