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netdevice: safe convert to netdev_priv() #part-2
[linux-2.6-block.git] / drivers / net / fec.c
CommitLineData
1da177e4
LT		 1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
7dd6a2aa 5 * Right now, I am very wasteful with the buffers. I allocate memory
1da177e4
LT		 6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
562d2f8c
GU		 15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
7dd6a2aa
GU		 17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
677177c5 19 * Copyright (c) 2004-2006 Macq Electronique SA.
1da177e4
LT		 20 */
21
1da177e4
LT		 22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/string.h>
25#include <linux/ptrace.h>
26#include <linux/errno.h>
27#include <linux/ioport.h>
28#include <linux/slab.h>
29#include <linux/interrupt.h>
30#include <linux/pci.h>
31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
36#include <linux/spinlock.h>
37#include <linux/workqueue.h>
38#include <linux/bitops.h>
39
40#include <asm/irq.h>
41#include <asm/uaccess.h>
42#include <asm/io.h>
43#include <asm/pgtable.h>
080853af 44#include <asm/cacheflush.h>
1da177e4 45
1da177e4
LT		 46#include <asm/coldfire.h>
47#include <asm/mcfsim.h>
48#include "fec.h"
1da177e4
LT		 49
50#if defined(CONFIG_FEC2)
51#define FEC_MAX_PORTS 2
52#else
53#define FEC_MAX_PORTS 1
54#endif
55
87f4abb4 56#if defined(CONFIG_M5272)
c1d96156
SS		 57#define HAVE_mii_link_interrupt
58#endif
59
1da177e4
LT		 60/*
61 * Define the fixed address of the FEC hardware.
62 */
63static unsigned int fec_hw[] = {
64#if defined(CONFIG_M5272)
65 (MCF_MBAR + 0x840),
66#elif defined(CONFIG_M527x)
67 (MCF_MBAR + 0x1000),
68 (MCF_MBAR + 0x1800),
7dd6a2aa 69#elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
1da177e4 70 (MCF_MBAR + 0x1000),
562d2f8c
GU		 71#elif defined(CONFIG_M520x)
72 (MCF_MBAR+0x30000),
6b265293
MW		 73#elif defined(CONFIG_M532x)
74 (MCF_MBAR+0xfc030000),
1da177e4
LT		 75#else
76 &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec),
77#endif
78};
79
80static unsigned char fec_mac_default[] = {
81 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
82};
83
84/*
85 * Some hardware gets it MAC address out of local flash memory.
86 * if this is non-zero then assume it is the address to get MAC from.
87 */
88#if defined(CONFIG_NETtel)
89#define FEC_FLASHMAC 0xf0006006
90#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
91#define FEC_FLASHMAC 0xf0006000
1da177e4
LT		 92#elif defined(CONFIG_CANCam)
93#define FEC_FLASHMAC 0xf0020000
7dd6a2aa
GU		 94#elif defined (CONFIG_M5272C3)
95#define FEC_FLASHMAC (0xffe04000 + 4)
96#elif defined(CONFIG_MOD5272)
97#define FEC_FLASHMAC 0xffc0406b
1da177e4
LT		 98#else
99#define FEC_FLASHMAC 0
100#endif
101
1da177e4
LT		 102/* Forward declarations of some structures to support different PHYs
103*/
104
105typedef struct {
106 uint mii_data;
107 void (*funct)(uint mii_reg, struct net_device *dev);
108} phy_cmd_t;
109
110typedef struct {
111 uint id;
112 char *name;
113
114 const phy_cmd_t *config;
115 const phy_cmd_t *startup;
116 const phy_cmd_t *ack_int;
117 const phy_cmd_t *shutdown;
118} phy_info_t;
119
120/* The number of Tx and Rx buffers. These are allocated from the page
121 * pool. The code may assume these are power of two, so it it best
122 * to keep them that size.
123 * We don't need to allocate pages for the transmitter. We just use
124 * the skbuffer directly.
125 */
126#define FEC_ENET_RX_PAGES 8
127#define FEC_ENET_RX_FRSIZE 2048
128#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
129#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
130#define FEC_ENET_TX_FRSIZE 2048
131#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
132#define TX_RING_SIZE 16 /* Must be power of two */
133#define TX_RING_MOD_MASK 15 /* for this to work */
134
562d2f8c 135#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
6b265293 136#error "FEC: descriptor ring size constants too large"
562d2f8c
GU		 137#endif
138
1da177e4
LT		 139/* Interrupt events/masks.
140*/
141#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
142#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
143#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
144#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
145#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
146#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
147#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
148#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
149#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
150#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
151
152/* The FEC stores dest/src/type, data, and checksum for receive packets.
153 */
154#define PKT_MAXBUF_SIZE 1518
155#define PKT_MINBUF_SIZE 64
156#define PKT_MAXBLR_SIZE 1520
157
158
159/*
6b265293 160 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
1da177e4
LT		 161 * size bits. Other FEC hardware does not, so we need to take that into
162 * account when setting it.
163 */
562d2f8c 164#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
6b265293 165 defined(CONFIG_M520x) || defined(CONFIG_M532x)
1da177e4
LT		 166#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
167#else
168#define OPT_FRAME_SIZE 0
169#endif
170
171/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
172 * tx_bd_base always point to the base of the buffer descriptors. The
173 * cur_rx and cur_tx point to the currently available buffer.
174 * The dirty_tx tracks the current buffer that is being sent by the
175 * controller. The cur_tx and dirty_tx are equal under both completely
176 * empty and completely full conditions. The empty/ready indicator in
177 * the buffer descriptor determines the actual condition.
178 */
179struct fec_enet_private {
180 /* Hardware registers of the FEC device */
181 volatile fec_t *hwp;
182
cb84d6e7
GU		 183 struct net_device *netdev;
184
1da177e4
LT		 185 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
186 unsigned char *tx_bounce[TX_RING_SIZE];
187 struct sk_buff* tx_skbuff[TX_RING_SIZE];
188 ushort skb_cur;
189 ushort skb_dirty;
190
191 /* CPM dual port RAM relative addresses.
192 */
193 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
194 cbd_t *tx_bd_base;
195 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
196 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
1da177e4 197 uint tx_full;
3b2b74ca
SS		 198 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
199 spinlock_t hw_lock;
200 /* hold while accessing the mii_list_t() elements */
201 spinlock_t mii_lock;
1da177e4
LT		 202
203 uint phy_id;
204 uint phy_id_done;
205 uint phy_status;
206 uint phy_speed;
7dd6a2aa 207 phy_info_t const *phy;
1da177e4
LT		 208 struct work_struct phy_task;
209
210 uint sequence_done;
211 uint mii_phy_task_queued;
212
213 uint phy_addr;
214
215 int index;
216 int opened;
217 int link;
218 int old_link;
219 int full_duplex;
1da177e4
LT		 220};
221
222static int fec_enet_open(struct net_device *dev);
223static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
224static void fec_enet_mii(struct net_device *dev);
7d12e780 225static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
1da177e4
LT		 226static void fec_enet_tx(struct net_device *dev);
227static void fec_enet_rx(struct net_device *dev);
228static int fec_enet_close(struct net_device *dev);
1da177e4
LT		 229static void set_multicast_list(struct net_device *dev);
230static void fec_restart(struct net_device *dev, int duplex);
231static void fec_stop(struct net_device *dev);
232static void fec_set_mac_address(struct net_device *dev);
233
234
235/* MII processing. We keep this as simple as possible. Requests are
236 * placed on the list (if there is room). When the request is finished
237 * by the MII, an optional function may be called.
238 */
239typedef struct mii_list {
240 uint mii_regval;
241 void (*mii_func)(uint val, struct net_device *dev);
242 struct mii_list *mii_next;
243} mii_list_t;
244
245#define NMII 20
7dd6a2aa
GU		 246static mii_list_t mii_cmds[NMII];
247static mii_list_t *mii_free;
248static mii_list_t *mii_head;
249static mii_list_t *mii_tail;
1da177e4 250
6aa20a22 251static int mii_queue(struct net_device *dev, int request,
1da177e4
LT		 252 void (*func)(uint, struct net_device *));
253
254/* Make MII read/write commands for the FEC.
255*/
256#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
257#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
258 (VAL & 0xffff))
259#define mk_mii_end 0
260
261/* Transmitter timeout.
262*/
263#define TX_TIMEOUT (2*HZ)
264
265/* Register definitions for the PHY.
266*/
267
268#define MII_REG_CR 0 /* Control Register */
269#define MII_REG_SR 1 /* Status Register */
270#define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
271#define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
6aa20a22 272#define MII_REG_ANAR 4 /* A-N Advertisement Register */
1da177e4
LT		 273#define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
274#define MII_REG_ANER 6 /* A-N Expansion Register */
275#define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
276#define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
277
278/* values for phy_status */
279
280#define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
281#define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
282#define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
283#define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
6aa20a22 284#define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
1da177e4 285#define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
6aa20a22 286#define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
1da177e4
LT		 287
288#define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
289#define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
290#define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
291#define PHY_STAT_SPMASK 0xf000 /* mask for speed */
292#define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
6aa20a22 293#define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
1da177e4 294#define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
6aa20a22 295#define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
1da177e4
LT		 296
297
298static int
299fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
300{
301 struct fec_enet_private *fep;
302 volatile fec_t *fecp;
303 volatile cbd_t *bdp;
0e702ab3 304 unsigned short status;
3b2b74ca 305 unsigned long flags;
1da177e4
LT		 306
307 fep = netdev_priv(dev);
308 fecp = (volatile fec_t*)dev->base_addr;
309
310 if (!fep->link) {
311 /* Link is down or autonegotiation is in progress. */
312 return 1;
313 }
314
3b2b74ca 315 spin_lock_irqsave(&fep->hw_lock, flags);
1da177e4
LT		 316 /* Fill in a Tx ring entry */
317 bdp = fep->cur_tx;
318
0e702ab3 319 status = bdp->cbd_sc;
1da177e4 320#ifndef final_version
0e702ab3 321 if (status & BD_ENET_TX_READY) {
1da177e4
LT		 322 /* Ooops. All transmit buffers are full. Bail out.
323 * This should not happen, since dev->tbusy should be set.
324 */
325 printk("%s: tx queue full!.\n", dev->name);
3b2b74ca 326 spin_unlock_irqrestore(&fep->hw_lock, flags);
1da177e4
LT		 327 return 1;
328 }
329#endif
330
331 /* Clear all of the status flags.
332 */
0e702ab3 333 status &= ~BD_ENET_TX_STATS;
1da177e4
LT		 334
335 /* Set buffer length and buffer pointer.
336 */
337 bdp->cbd_bufaddr = __pa(skb->data);
338 bdp->cbd_datlen = skb->len;
339
340 /*
341 * On some FEC implementations data must be aligned on
342 * 4-byte boundaries. Use bounce buffers to copy data
343 * and get it aligned. Ugh.
344 */
345 if (bdp->cbd_bufaddr & 0x3) {
346 unsigned int index;
347 index = bdp - fep->tx_bd_base;
348 memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen);
349 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
350 }
351
352 /* Save skb pointer.
353 */
354 fep->tx_skbuff[fep->skb_cur] = skb;
355
09f75cd7 356 dev->stats.tx_bytes += skb->len;
1da177e4 357 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
6aa20a22 358
1da177e4
LT		 359 /* Push the data cache so the CPM does not get stale memory
360 * data.
361 */
362 flush_dcache_range((unsigned long)skb->data,
363 (unsigned long)skb->data + skb->len);
364
0e702ab3
GU		 365 /* Send it on its way. Tell FEC it's ready, interrupt when done,
366 * it's the last BD of the frame, and to put the CRC on the end.
1da177e4
LT		 367 */
368
0e702ab3 369 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
1da177e4 370 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
0e702ab3 371 bdp->cbd_sc = status;
1da177e4
LT		 372
373 dev->trans_start = jiffies;
374
375 /* Trigger transmission start */
0e702ab3 376 fecp->fec_x_des_active = 0;
1da177e4
LT		 377
378 /* If this was the last BD in the ring, start at the beginning again.
379 */
0e702ab3 380 if (status & BD_ENET_TX_WRAP) {
1da177e4
LT		 381 bdp = fep->tx_bd_base;
382 } else {
383 bdp++;
384 }
385
386 if (bdp == fep->dirty_tx) {
387 fep->tx_full = 1;
388 netif_stop_queue(dev);
389 }
390
391 fep->cur_tx = (cbd_t *)bdp;
392
3b2b74ca 393 spin_unlock_irqrestore(&fep->hw_lock, flags);
1da177e4
LT		 394
395 return 0;
396}
397
398static void
399fec_timeout(struct net_device *dev)
400{
401 struct fec_enet_private *fep = netdev_priv(dev);
402
403 printk("%s: transmit timed out.\n", dev->name);
09f75cd7 404 dev->stats.tx_errors++;
1da177e4
LT		 405#ifndef final_version
406 {
407 int i;
408 cbd_t *bdp;
409
410 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
411 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
412 (unsigned long)fep->dirty_tx,
413 (unsigned long)fep->cur_rx);
414
415 bdp = fep->tx_bd_base;
416 printk(" tx: %u buffers\n", TX_RING_SIZE);
417 for (i = 0 ; i < TX_RING_SIZE; i++) {
6aa20a22 418 printk(" %08x: %04x %04x %08x\n",
1da177e4
LT		 419 (uint) bdp,
420 bdp->cbd_sc,
421 bdp->cbd_datlen,
422 (int) bdp->cbd_bufaddr);
423 bdp++;
424 }
425
426 bdp = fep->rx_bd_base;
427 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
428 for (i = 0 ; i < RX_RING_SIZE; i++) {
429 printk(" %08x: %04x %04x %08x\n",
430 (uint) bdp,
431 bdp->cbd_sc,
432 bdp->cbd_datlen,
433 (int) bdp->cbd_bufaddr);
434 bdp++;
435 }
436 }
437#endif
7dd6a2aa 438 fec_restart(dev, fep->full_duplex);
1da177e4
LT		 439 netif_wake_queue(dev);
440}
441
442/* The interrupt handler.
443 * This is called from the MPC core interrupt.
444 */
445static irqreturn_t
7d12e780 446fec_enet_interrupt(int irq, void * dev_id)
1da177e4
LT		 447{
448 struct net_device *dev = dev_id;
449 volatile fec_t *fecp;
450 uint int_events;
3b2b74ca 451 irqreturn_t ret = IRQ_NONE;
1da177e4
LT		 452
453 fecp = (volatile fec_t*)dev->base_addr;
454
455 /* Get the interrupt events that caused us to be here.
456 */
3b2b74ca
SS		 457 do {
458 int_events = fecp->fec_ievent;
1da177e4
LT		 459 fecp->fec_ievent = int_events;
460
461 /* Handle receive event in its own function.
462 */
463 if (int_events & FEC_ENET_RXF) {
3b2b74ca 464 ret = IRQ_HANDLED;
1da177e4
LT		 465 fec_enet_rx(dev);
466 }
467
468 /* Transmit OK, or non-fatal error. Update the buffer
469 descriptors. FEC handles all errors, we just discover
470 them as part of the transmit process.
471 */
472 if (int_events & FEC_ENET_TXF) {
3b2b74ca 473 ret = IRQ_HANDLED;
1da177e4
LT		 474 fec_enet_tx(dev);
475 }
476
477 if (int_events & FEC_ENET_MII) {
3b2b74ca 478 ret = IRQ_HANDLED;
1da177e4
LT		 479 fec_enet_mii(dev);
480 }
6aa20a22 481
3b2b74ca
SS		 482 } while (int_events);
483
484 return ret;
1da177e4
LT		 485}
486
487
488static void
489fec_enet_tx(struct net_device *dev)
490{
491 struct fec_enet_private *fep;
492 volatile cbd_t *bdp;
0e702ab3 493 unsigned short status;
1da177e4
LT		 494 struct sk_buff *skb;
495
496 fep = netdev_priv(dev);
3b2b74ca 497 spin_lock_irq(&fep->hw_lock);
1da177e4
LT		 498 bdp = fep->dirty_tx;
499
0e702ab3 500 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
1da177e4
LT		 501 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
502
503 skb = fep->tx_skbuff[fep->skb_dirty];
504 /* Check for errors. */
0e702ab3 505 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1da177e4
LT		 506 BD_ENET_TX_RL | BD_ENET_TX_UN |
507 BD_ENET_TX_CSL)) {
09f75cd7 508 dev->stats.tx_errors++;
0e702ab3 509 if (status & BD_ENET_TX_HB) /* No heartbeat */
09f75cd7 510 dev->stats.tx_heartbeat_errors++;
0e702ab3 511 if (status & BD_ENET_TX_LC) /* Late collision */
09f75cd7 512 dev->stats.tx_window_errors++;
0e702ab3 513 if (status & BD_ENET_TX_RL) /* Retrans limit */
09f75cd7 514 dev->stats.tx_aborted_errors++;
0e702ab3 515 if (status & BD_ENET_TX_UN) /* Underrun */
09f75cd7 516 dev->stats.tx_fifo_errors++;
0e702ab3 517 if (status & BD_ENET_TX_CSL) /* Carrier lost */
09f75cd7 518 dev->stats.tx_carrier_errors++;
1da177e4 519 } else {
09f75cd7 520 dev->stats.tx_packets++;
1da177e4
LT		 521 }
522
523#ifndef final_version
0e702ab3 524 if (status & BD_ENET_TX_READY)
1da177e4
LT		 525 printk("HEY! Enet xmit interrupt and TX_READY.\n");
526#endif
527 /* Deferred means some collisions occurred during transmit,
528 * but we eventually sent the packet OK.
529 */
0e702ab3 530 if (status & BD_ENET_TX_DEF)
09f75cd7 531 dev->stats.collisions++;
6aa20a22 532
1da177e4
LT		 533 /* Free the sk buffer associated with this last transmit.
534 */
535 dev_kfree_skb_any(skb);
536 fep->tx_skbuff[fep->skb_dirty] = NULL;
537 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
6aa20a22 538
1da177e4
LT		 539 /* Update pointer to next buffer descriptor to be transmitted.
540 */
0e702ab3 541 if (status & BD_ENET_TX_WRAP)
1da177e4
LT		 542 bdp = fep->tx_bd_base;
543 else
544 bdp++;
6aa20a22 545
1da177e4
LT		 546 /* Since we have freed up a buffer, the ring is no longer
547 * full.
548 */
549 if (fep->tx_full) {
550 fep->tx_full = 0;
551 if (netif_queue_stopped(dev))
552 netif_wake_queue(dev);
553 }
554 }
555 fep->dirty_tx = (cbd_t *)bdp;
3b2b74ca 556 spin_unlock_irq(&fep->hw_lock);
1da177e4
LT		 557}
558
559
560/* During a receive, the cur_rx points to the current incoming buffer.
561 * When we update through the ring, if the next incoming buffer has
562 * not been given to the system, we just set the empty indicator,
563 * effectively tossing the packet.
564 */
565static void
566fec_enet_rx(struct net_device *dev)
567{
568 struct fec_enet_private *fep;
569 volatile fec_t *fecp;
570 volatile cbd_t *bdp;
0e702ab3 571 unsigned short status;
1da177e4
LT		 572 struct sk_buff *skb;
573 ushort pkt_len;
574 __u8 *data;
6aa20a22 575
0e702ab3
GU		 576#ifdef CONFIG_M532x
577 flush_cache_all();
6aa20a22 578#endif
1da177e4
LT		 579
580 fep = netdev_priv(dev);
581 fecp = (volatile fec_t*)dev->base_addr;
582
3b2b74ca
SS		 583 spin_lock_irq(&fep->hw_lock);
584
1da177e4
LT		 585 /* First, grab all of the stats for the incoming packet.
586 * These get messed up if we get called due to a busy condition.
587 */
588 bdp = fep->cur_rx;
589
0e702ab3 590while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1da177e4
LT		 591
592#ifndef final_version
593 /* Since we have allocated space to hold a complete frame,
594 * the last indicator should be set.
595 */
0e702ab3 596 if ((status & BD_ENET_RX_LAST) == 0)
1da177e4
LT		 597 printk("FEC ENET: rcv is not +last\n");
598#endif
599
600 if (!fep->opened)
601 goto rx_processing_done;
602
603 /* Check for errors. */
0e702ab3 604 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1da177e4 605 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
09f75cd7 606 dev->stats.rx_errors++;
0e702ab3 607 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1da177e4 608 /* Frame too long or too short. */
09f75cd7 609 dev->stats.rx_length_errors++;
1da177e4 610 }
0e702ab3 611 if (status & BD_ENET_RX_NO) /* Frame alignment */
09f75cd7 612 dev->stats.rx_frame_errors++;
0e702ab3 613 if (status & BD_ENET_RX_CR) /* CRC Error */
09f75cd7 614 dev->stats.rx_crc_errors++;
0e702ab3 615 if (status & BD_ENET_RX_OV) /* FIFO overrun */
09f75cd7 616 dev->stats.rx_fifo_errors++;
1da177e4
LT		 617 }
618
619 /* Report late collisions as a frame error.
620 * On this error, the BD is closed, but we don't know what we
621 * have in the buffer. So, just drop this frame on the floor.
622 */
0e702ab3 623 if (status & BD_ENET_RX_CL) {
09f75cd7
JG		 624 dev->stats.rx_errors++;
625 dev->stats.rx_frame_errors++;
1da177e4
LT		 626 goto rx_processing_done;
627 }
628
629 /* Process the incoming frame.
630 */
09f75cd7 631 dev->stats.rx_packets++;
1da177e4 632 pkt_len = bdp->cbd_datlen;
09f75cd7 633 dev->stats.rx_bytes += pkt_len;
1da177e4
LT		 634 data = (__u8*)__va(bdp->cbd_bufaddr);
635
636 /* This does 16 byte alignment, exactly what we need.
637 * The packet length includes FCS, but we don't want to
638 * include that when passing upstream as it messes up
639 * bridging applications.
640 */
641 skb = dev_alloc_skb(pkt_len-4);
642
643 if (skb == NULL) {
644 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
09f75cd7 645 dev->stats.rx_dropped++;
1da177e4 646 } else {
1da177e4 647 skb_put(skb,pkt_len-4); /* Make room */
8c7b7faa 648 skb_copy_to_linear_data(skb, data, pkt_len-4);
1da177e4
LT		 649 skb->protocol=eth_type_trans(skb,dev);
650 netif_rx(skb);
651 }
652 rx_processing_done:
653
654 /* Clear the status flags for this buffer.
655 */
0e702ab3 656 status &= ~BD_ENET_RX_STATS;
1da177e4
LT		 657
658 /* Mark the buffer empty.
659 */
0e702ab3
GU		 660 status |= BD_ENET_RX_EMPTY;
661 bdp->cbd_sc = status;
1da177e4
LT		 662
663 /* Update BD pointer to next entry.
664 */
0e702ab3 665 if (status & BD_ENET_RX_WRAP)
1da177e4
LT		 666 bdp = fep->rx_bd_base;
667 else
668 bdp++;
6aa20a22 669
1da177e4
LT		 670#if 1
671 /* Doing this here will keep the FEC running while we process
672 * incoming frames. On a heavily loaded network, we should be
673 * able to keep up at the expense of system resources.
674 */
0e702ab3 675 fecp->fec_r_des_active = 0;
1da177e4 676#endif
0e702ab3 677 } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
1da177e4
LT		 678 fep->cur_rx = (cbd_t *)bdp;
679
680#if 0
681 /* Doing this here will allow us to process all frames in the
682 * ring before the FEC is allowed to put more there. On a heavily
683 * loaded network, some frames may be lost. Unfortunately, this
684 * increases the interrupt overhead since we can potentially work
685 * our way back to the interrupt return only to come right back
686 * here.
687 */
0e702ab3 688 fecp->fec_r_des_active = 0;
1da177e4 689#endif
3b2b74ca
SS		 690
691 spin_unlock_irq(&fep->hw_lock);
1da177e4
LT		 692}
693
694
0e702ab3 695/* called from interrupt context */
1da177e4
LT		 696static void
697fec_enet_mii(struct net_device *dev)
698{
699 struct fec_enet_private *fep;
700 volatile fec_t *ep;
701 mii_list_t *mip;
702 uint mii_reg;
703
704 fep = netdev_priv(dev);
3b2b74ca
SS		 705 spin_lock_irq(&fep->mii_lock);
706
1da177e4
LT		 707 ep = fep->hwp;
708 mii_reg = ep->fec_mii_data;
0e702ab3 709
1da177e4
LT		 710 if ((mip = mii_head) == NULL) {
711 printk("MII and no head!\n");
0e702ab3 712 goto unlock;
1da177e4
LT		 713 }
714
715 if (mip->mii_func != NULL)
716 (*(mip->mii_func))(mii_reg, dev);
717
718 mii_head = mip->mii_next;
719 mip->mii_next = mii_free;
720 mii_free = mip;
721
722 if ((mip = mii_head) != NULL)
723 ep->fec_mii_data = mip->mii_regval;
0e702ab3
GU		 724
725unlock:
3b2b74ca 726 spin_unlock_irq(&fep->mii_lock);
1da177e4
LT		 727}
728
729static int
730mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
731{
732 struct fec_enet_private *fep;
733 unsigned long flags;
734 mii_list_t *mip;
735 int retval;
736
737 /* Add PHY address to register command.
738 */
739 fep = netdev_priv(dev);
3b2b74ca 740 spin_lock_irqsave(&fep->mii_lock, flags);
1da177e4 741
3b2b74ca 742 regval |= fep->phy_addr << 23;
1da177e4
LT		 743 retval = 0;
744
1da177e4
LT		 745 if ((mip = mii_free) != NULL) {
746 mii_free = mip->mii_next;
747 mip->mii_regval = regval;
748 mip->mii_func = func;
749 mip->mii_next = NULL;
750 if (mii_head) {
751 mii_tail->mii_next = mip;
752 mii_tail = mip;
f909b1ef 753 } else {
1da177e4
LT		 754 mii_head = mii_tail = mip;
755 fep->hwp->fec_mii_data = regval;
756 }
f909b1ef 757 } else {
1da177e4
LT		 758 retval = 1;
759 }
760
3b2b74ca
SS		 761 spin_unlock_irqrestore(&fep->mii_lock, flags);
762 return retval;
1da177e4
LT		 763}
764
765static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
766{
1da177e4
LT		 767 if(!c)
768 return;
769
be6cb66d
PDM		 770 for (; c->mii_data != mk_mii_end; c++)
771 mii_queue(dev, c->mii_data, c->funct);
1da177e4
LT		 772}
773
774static void mii_parse_sr(uint mii_reg, struct net_device *dev)
775{
776 struct fec_enet_private *fep = netdev_priv(dev);
777 volatile uint *s = &(fep->phy_status);
7dd6a2aa 778 uint status;
1da177e4 779
7dd6a2aa 780 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
1da177e4
LT		 781
782 if (mii_reg & 0x0004)
7dd6a2aa 783 status |= PHY_STAT_LINK;
1da177e4 784 if (mii_reg & 0x0010)
7dd6a2aa 785 status |= PHY_STAT_FAULT;
1da177e4 786 if (mii_reg & 0x0020)
7dd6a2aa 787 status |= PHY_STAT_ANC;
7dd6a2aa 788 *s = status;
1da177e4
LT		 789}
790
791static void mii_parse_cr(uint mii_reg, struct net_device *dev)
792{
793 struct fec_enet_private *fep = netdev_priv(dev);
794 volatile uint *s = &(fep->phy_status);
7dd6a2aa 795 uint status;
1da177e4 796
7dd6a2aa 797 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
1da177e4
LT		 798
799 if (mii_reg & 0x1000)
7dd6a2aa 800 status |= PHY_CONF_ANE;
1da177e4 801 if (mii_reg & 0x4000)
7dd6a2aa
GU		 802 status |= PHY_CONF_LOOP;
803 *s = status;
1da177e4
LT		 804}
805
806static void mii_parse_anar(uint mii_reg, struct net_device *dev)
807{
808 struct fec_enet_private *fep = netdev_priv(dev);
809 volatile uint *s = &(fep->phy_status);
7dd6a2aa 810 uint status;
1da177e4 811
7dd6a2aa 812 status = *s & ~(PHY_CONF_SPMASK);
1da177e4
LT		 813
814 if (mii_reg & 0x0020)
7dd6a2aa 815 status |= PHY_CONF_10HDX;
1da177e4 816 if (mii_reg & 0x0040)
7dd6a2aa 817 status |= PHY_CONF_10FDX;
1da177e4 818 if (mii_reg & 0x0080)
7dd6a2aa 819 status |= PHY_CONF_100HDX;
1da177e4 820 if (mii_reg & 0x00100)
7dd6a2aa
GU		 821 status |= PHY_CONF_100FDX;
822 *s = status;
1da177e4
LT		 823}
824
825/* ------------------------------------------------------------------------- */
826/* The Level one LXT970 is used by many boards */
827
828#define MII_LXT970_MIRROR 16 /* Mirror register */
829#define MII_LXT970_IER 17 /* Interrupt Enable Register */
830#define MII_LXT970_ISR 18 /* Interrupt Status Register */
831#define MII_LXT970_CONFIG 19 /* Configuration Register */
832#define MII_LXT970_CSR 20 /* Chip Status Register */
833
834static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
835{
836 struct fec_enet_private *fep = netdev_priv(dev);
837 volatile uint *s = &(fep->phy_status);
7dd6a2aa 838 uint status;
1da177e4 839
7dd6a2aa 840 status = *s & ~(PHY_STAT_SPMASK);
1da177e4
LT		 841 if (mii_reg & 0x0800) {
842 if (mii_reg & 0x1000)
7dd6a2aa 843 status |= PHY_STAT_100FDX;
1da177e4 844 else
7dd6a2aa 845 status |= PHY_STAT_100HDX;
1da177e4
LT		 846 } else {
847 if (mii_reg & 0x1000)
7dd6a2aa 848 status |= PHY_STAT_10FDX;
1da177e4 849 else
7dd6a2aa 850 status |= PHY_STAT_10HDX;
1da177e4 851 }
7dd6a2aa 852 *s = status;
1da177e4
LT		 853}
854
7dd6a2aa 855static phy_cmd_t const phy_cmd_lxt970_config[] = {
1da177e4
LT		 856 { mk_mii_read(MII_REG_CR), mii_parse_cr },
857 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
858 { mk_mii_end, }
7dd6a2aa
GU		 859 };
860static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
1da177e4
LT		 861 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
862 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
863 { mk_mii_end, }
7dd6a2aa
GU		 864 };
865static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
1da177e4
LT		 866 /* read SR and ISR to acknowledge */
867 { mk_mii_read(MII_REG_SR), mii_parse_sr },
868 { mk_mii_read(MII_LXT970_ISR), NULL },
869
870 /* find out the current status */
871 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
872 { mk_mii_end, }
7dd6a2aa
GU		 873 };
874static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
1da177e4
LT		 875 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
876 { mk_mii_end, }
7dd6a2aa
GU		 877 };
878static phy_info_t const phy_info_lxt970 = {
6aa20a22 879 .id = 0x07810000,
7dd6a2aa
GU		 880 .name = "LXT970",
881 .config = phy_cmd_lxt970_config,
882 .startup = phy_cmd_lxt970_startup,
883 .ack_int = phy_cmd_lxt970_ack_int,
884 .shutdown = phy_cmd_lxt970_shutdown
1da177e4 885};
6aa20a22 886
1da177e4
LT		 887/* ------------------------------------------------------------------------- */
888/* The Level one LXT971 is used on some of my custom boards */
889
890/* register definitions for the 971 */
891
892#define MII_LXT971_PCR 16 /* Port Control Register */
893#define MII_LXT971_SR2 17 /* Status Register 2 */
894#define MII_LXT971_IER 18 /* Interrupt Enable Register */
895#define MII_LXT971_ISR 19 /* Interrupt Status Register */
896#define MII_LXT971_LCR 20 /* LED Control Register */
897#define MII_LXT971_TCR 30 /* Transmit Control Register */
898
6aa20a22 899/*
1da177e4
LT		 900 * I had some nice ideas of running the MDIO faster...
901 * The 971 should support 8MHz and I tried it, but things acted really
902 * weird, so 2.5 MHz ought to be enough for anyone...
903 */
904
905static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
906{
907 struct fec_enet_private *fep = netdev_priv(dev);
908 volatile uint *s = &(fep->phy_status);
7dd6a2aa 909 uint status;
1da177e4 910
7dd6a2aa 911 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1da177e4
LT		 912
913 if (mii_reg & 0x0400) {
914 fep->link = 1;
7dd6a2aa 915 status |= PHY_STAT_LINK;
1da177e4
LT		 916 } else {
917 fep->link = 0;
918 }
919 if (mii_reg & 0x0080)
7dd6a2aa 920 status |= PHY_STAT_ANC;
1da177e4
LT		 921 if (mii_reg & 0x4000) {
922 if (mii_reg & 0x0200)
7dd6a2aa 923 status |= PHY_STAT_100FDX;
1da177e4 924 else
7dd6a2aa 925 status |= PHY_STAT_100HDX;
1da177e4
LT		 926 } else {
927 if (mii_reg & 0x0200)
7dd6a2aa 928 status |= PHY_STAT_10FDX;
1da177e4 929 else
7dd6a2aa 930 status |= PHY_STAT_10HDX;
1da177e4
LT		 931 }
932 if (mii_reg & 0x0008)
7dd6a2aa 933 status |= PHY_STAT_FAULT;
1da177e4 934
7dd6a2aa
GU		 935 *s = status;
936}
6aa20a22 937
7dd6a2aa 938static phy_cmd_t const phy_cmd_lxt971_config[] = {
6aa20a22 939 /* limit to 10MBit because my prototype board
1da177e4
LT		 940 * doesn't work with 100. */
941 { mk_mii_read(MII_REG_CR), mii_parse_cr },
942 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
943 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
944 { mk_mii_end, }
7dd6a2aa
GU		 945 };
946static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
1da177e4
LT		 947 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
948 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
949 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
950 /* Somehow does the 971 tell me that the link is down
951 * the first read after power-up.
952 * read here to get a valid value in ack_int */
6aa20a22 953 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1da177e4 954 { mk_mii_end, }
7dd6a2aa
GU		 955 };
956static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
957 /* acknowledge the int before reading status ! */
958 { mk_mii_read(MII_LXT971_ISR), NULL },
1da177e4
LT		 959 /* find out the current status */
960 { mk_mii_read(MII_REG_SR), mii_parse_sr },
961 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
1da177e4 962 { mk_mii_end, }
7dd6a2aa
GU		 963 };
964static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
1da177e4
LT		 965 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
966 { mk_mii_end, }
7dd6a2aa
GU		 967 };
968static phy_info_t const phy_info_lxt971 = {
6aa20a22 969 .id = 0x0001378e,
7dd6a2aa
GU		 970 .name = "LXT971",
971 .config = phy_cmd_lxt971_config,
972 .startup = phy_cmd_lxt971_startup,
973 .ack_int = phy_cmd_lxt971_ack_int,
974 .shutdown = phy_cmd_lxt971_shutdown
1da177e4
LT		 975};
976
977/* ------------------------------------------------------------------------- */
978/* The Quality Semiconductor QS6612 is used on the RPX CLLF */
979
980/* register definitions */
981
982#define MII_QS6612_MCR 17 /* Mode Control Register */
983#define MII_QS6612_FTR 27 /* Factory Test Register */
984#define MII_QS6612_MCO 28 /* Misc. Control Register */
985#define MII_QS6612_ISR 29 /* Interrupt Source Register */
986#define MII_QS6612_IMR 30 /* Interrupt Mask Register */
987#define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
988
989static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
990{
991 struct fec_enet_private *fep = netdev_priv(dev);
992 volatile uint *s = &(fep->phy_status);
7dd6a2aa 993 uint status;
1da177e4 994
7dd6a2aa 995 status = *s & ~(PHY_STAT_SPMASK);
1da177e4
LT		 996
997 switch((mii_reg >> 2) & 7) {
7dd6a2aa
GU		 998 case 1: status |= PHY_STAT_10HDX; break;
999 case 2: status |= PHY_STAT_100HDX; break;
1000 case 5: status |= PHY_STAT_10FDX; break;
1001 case 6: status |= PHY_STAT_100FDX; break;
1da177e4
LT		 1002}
1003
7dd6a2aa
GU		 1004 *s = status;
1005}
1006
1007static phy_cmd_t const phy_cmd_qs6612_config[] = {
6aa20a22 1008 /* The PHY powers up isolated on the RPX,
1da177e4
LT		 1009 * so send a command to allow operation.
1010 */
1011 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1012
1013 /* parse cr and anar to get some info */
1014 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1015 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1016 { mk_mii_end, }
7dd6a2aa
GU		 1017 };
1018static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
1da177e4
LT		 1019 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1020 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1021 { mk_mii_end, }
7dd6a2aa
GU		 1022 };
1023static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
1da177e4
LT		 1024 /* we need to read ISR, SR and ANER to acknowledge */
1025 { mk_mii_read(MII_QS6612_ISR), NULL },
1026 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1027 { mk_mii_read(MII_REG_ANER), NULL },
1028
1029 /* read pcr to get info */
1030 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1031 { mk_mii_end, }
7dd6a2aa
GU		 1032 };
1033static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
1da177e4
LT		 1034 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1035 { mk_mii_end, }
7dd6a2aa
GU		 1036 };
1037static phy_info_t const phy_info_qs6612 = {
6aa20a22 1038 .id = 0x00181440,
7dd6a2aa
GU		 1039 .name = "QS6612",
1040 .config = phy_cmd_qs6612_config,
1041 .startup = phy_cmd_qs6612_startup,
1042 .ack_int = phy_cmd_qs6612_ack_int,
1043 .shutdown = phy_cmd_qs6612_shutdown
1da177e4
LT		 1044};
1045
1046/* ------------------------------------------------------------------------- */
1047/* AMD AM79C874 phy */
1048
1049/* register definitions for the 874 */
1050
1051#define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1052#define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1053#define MII_AM79C874_DR 18 /* Diagnostic Register */
1054#define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1055#define MII_AM79C874_MCR 21 /* ModeControl Register */
1056#define MII_AM79C874_DC 23 /* Disconnect Counter */
1057#define MII_AM79C874_REC 24 /* Recieve Error Counter */
1058
1059static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1060{
1061 struct fec_enet_private *fep = netdev_priv(dev);
1062 volatile uint *s = &(fep->phy_status);
7dd6a2aa 1063 uint status;
1da177e4 1064
7dd6a2aa 1065 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
1da177e4
LT		 1066
1067 if (mii_reg & 0x0080)
7dd6a2aa 1068 status |= PHY_STAT_ANC;
1da177e4 1069 if (mii_reg & 0x0400)
7dd6a2aa 1070 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
1da177e4 1071 else
7dd6a2aa
GU		 1072 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1073
1074 *s = status;
1da177e4
LT		 1075}
1076
7dd6a2aa 1077static phy_cmd_t const phy_cmd_am79c874_config[] = {
1da177e4
LT		 1078 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1079 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1080 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1081 { mk_mii_end, }
7dd6a2aa
GU		 1082 };
1083static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
1da177e4
LT		 1084 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1085 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
6aa20a22 1086 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1da177e4 1087 { mk_mii_end, }
7dd6a2aa
GU		 1088 };
1089static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
1da177e4
LT		 1090 /* find out the current status */
1091 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1092 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1093 /* we only need to read ISR to acknowledge */
1094 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1095 { mk_mii_end, }
7dd6a2aa
GU		 1096 };
1097static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
1da177e4
LT		 1098 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1099 { mk_mii_end, }
7dd6a2aa
GU		 1100 };
1101static phy_info_t const phy_info_am79c874 = {
1102 .id = 0x00022561,
1103 .name = "AM79C874",
1104 .config = phy_cmd_am79c874_config,
1105 .startup = phy_cmd_am79c874_startup,
1106 .ack_int = phy_cmd_am79c874_ack_int,
1107 .shutdown = phy_cmd_am79c874_shutdown
1da177e4
LT		 1108};
1109
7dd6a2aa 1110
1da177e4
LT		 1111/* ------------------------------------------------------------------------- */
1112/* Kendin KS8721BL phy */
1113
1114/* register definitions for the 8721 */
1115
1116#define MII_KS8721BL_RXERCR 21
1117#define MII_KS8721BL_ICSR 22
1118#define MII_KS8721BL_PHYCR 31
1119
7dd6a2aa 1120static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1da177e4
LT		 1121 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1122 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1123 { mk_mii_end, }
7dd6a2aa
GU		 1124 };
1125static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1da177e4
LT		 1126 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1127 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
6aa20a22 1128 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1da177e4 1129 { mk_mii_end, }
7dd6a2aa
GU		 1130 };
1131static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1da177e4
LT		 1132 /* find out the current status */
1133 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1134 /* we only need to read ISR to acknowledge */
1135 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1136 { mk_mii_end, }
7dd6a2aa
GU		 1137 };
1138static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
1da177e4
LT		 1139 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1140 { mk_mii_end, }
7dd6a2aa
GU		 1141 };
1142static phy_info_t const phy_info_ks8721bl = {
6aa20a22 1143 .id = 0x00022161,
7dd6a2aa
GU		 1144 .name = "KS8721BL",
1145 .config = phy_cmd_ks8721bl_config,
1146 .startup = phy_cmd_ks8721bl_startup,
1147 .ack_int = phy_cmd_ks8721bl_ack_int,
1148 .shutdown = phy_cmd_ks8721bl_shutdown
1da177e4
LT		 1149};
1150
562d2f8c
GU		 1151/* ------------------------------------------------------------------------- */
1152/* register definitions for the DP83848 */
1153
1154#define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1155
1156static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1157{
4cf1653a 1158 struct fec_enet_private *fep = netdev_priv(dev);
562d2f8c
GU		 1159 volatile uint *s = &(fep->phy_status);
1160
1161 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1162
1163 /* Link up */
1164 if (mii_reg & 0x0001) {
1165 fep->link = 1;
1166 *s |= PHY_STAT_LINK;
1167 } else
1168 fep->link = 0;
1169 /* Status of link */
1170 if (mii_reg & 0x0010) /* Autonegotioation complete */
1171 *s |= PHY_STAT_ANC;
1172 if (mii_reg & 0x0002) { /* 10MBps? */
1173 if (mii_reg & 0x0004) /* Full Duplex? */
1174 *s |= PHY_STAT_10FDX;
1175 else
1176 *s |= PHY_STAT_10HDX;
1177 } else { /* 100 Mbps? */
1178 if (mii_reg & 0x0004) /* Full Duplex? */
1179 *s |= PHY_STAT_100FDX;
1180 else
1181 *s |= PHY_STAT_100HDX;
1182 }
1183 if (mii_reg & 0x0008)
1184 *s |= PHY_STAT_FAULT;
1185}
1186
1187static phy_info_t phy_info_dp83848= {
1188 0x020005c9,
1189 "DP83848",
1190
1191 (const phy_cmd_t []) { /* config */
1192 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1193 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1194 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1195 { mk_mii_end, }
1196 },
1197 (const phy_cmd_t []) { /* startup - enable interrupts */
1198 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1199 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1200 { mk_mii_end, }
1201 },
1202 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1203 { mk_mii_end, }
1204 },
1205 (const phy_cmd_t []) { /* shutdown */
1206 { mk_mii_end, }
1207 },
1208};
1209
1da177e4
LT		 1210/* ------------------------------------------------------------------------- */
1211
7dd6a2aa 1212static phy_info_t const * const phy_info[] = {
1da177e4
LT		 1213 &phy_info_lxt970,
1214 &phy_info_lxt971,
1215 &phy_info_qs6612,
1216 &phy_info_am79c874,
1217 &phy_info_ks8721bl,
562d2f8c 1218 &phy_info_dp83848,
1da177e4
LT		 1219 NULL
1220};
1221
1222/* ------------------------------------------------------------------------- */
c1d96156 1223#ifdef HAVE_mii_link_interrupt
1da177e4 1224static irqreturn_t
7d12e780 1225mii_link_interrupt(int irq, void * dev_id);
1da177e4
LT		 1226#endif
1227
1228#if defined(CONFIG_M5272)
1da177e4
LT		 1229/*
1230 * Code specific to Coldfire 5272 setup.
1231 */
1232static void __inline__ fec_request_intrs(struct net_device *dev)
1233{
1234 volatile unsigned long *icrp;
7dd6a2aa
GU		 1235 static const struct idesc {
1236 char *name;
1237 unsigned short irq;
7d12e780 1238 irq_handler_t handler;
7dd6a2aa
GU		 1239 } *idp, id[] = {
1240 { "fec(RX)", 86, fec_enet_interrupt },
1241 { "fec(TX)", 87, fec_enet_interrupt },
1242 { "fec(OTHER)", 88, fec_enet_interrupt },
1243 { "fec(MII)", 66, mii_link_interrupt },
1244 { NULL },
1245 };
1da177e4
LT		 1246
1247 /* Setup interrupt handlers. */
7dd6a2aa 1248 for (idp = id; idp->name; idp++) {
0a504779 1249 if (request_irq(idp->irq, idp->handler, IRQF_DISABLED, idp->name, dev) != 0)
7dd6a2aa
GU		 1250 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1251 }
1da177e4
LT		 1252
1253 /* Unmask interrupt at ColdFire 5272 SIM */
1254 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1255 *icrp = 0x00000ddd;
1256 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
f861d62e 1257 *icrp = 0x0d000000;
1da177e4
LT		 1258}
1259
1260static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1261{
1262 volatile fec_t *fecp;
1263
1264 fecp = fep->hwp;
1265 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1266 fecp->fec_x_cntrl = 0x00;
1267
1268 /*
1269 * Set MII speed to 2.5 MHz
1270 * See 5272 manual section 11.5.8: MSCR
1271 */
1272 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1273 fecp->fec_mii_speed = fep->phy_speed;
1274
1275 fec_restart(dev, 0);
1276}
1277
1278static void __inline__ fec_get_mac(struct net_device *dev)
1279{
1280 struct fec_enet_private *fep = netdev_priv(dev);
1281 volatile fec_t *fecp;
7dd6a2aa 1282 unsigned char *iap, tmpaddr[ETH_ALEN];
1da177e4
LT		 1283
1284 fecp = fep->hwp;
1285
7dd6a2aa 1286 if (FEC_FLASHMAC) {
1da177e4
LT		 1287 /*
1288 * Get MAC address from FLASH.
1289 * If it is all 1's or 0's, use the default.
1290 */
7dd6a2aa 1291 iap = (unsigned char *)FEC_FLASHMAC;
1da177e4
LT		 1292 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1293 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1294 iap = fec_mac_default;
1295 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1296 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1297 iap = fec_mac_default;
1298 } else {
1299 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1300 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1301 iap = &tmpaddr[0];
1302 }
1303
7dd6a2aa 1304 memcpy(dev->dev_addr, iap, ETH_ALEN);
1da177e4
LT		 1305
1306 /* Adjust MAC if using default MAC address */
7dd6a2aa
GU		 1307 if (iap == fec_mac_default)
1308 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1da177e4
LT		 1309}
1310
1311static void __inline__ fec_enable_phy_intr(void)
1312{
1313}
1314
1315static void __inline__ fec_disable_phy_intr(void)
1316{
1317 volatile unsigned long *icrp;
1318 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
f861d62e 1319 *icrp = 0x08000000;
1da177e4
LT		 1320}
1321
1322static void __inline__ fec_phy_ack_intr(void)
1323{
1324 volatile unsigned long *icrp;
1325 /* Acknowledge the interrupt */
1326 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
f861d62e 1327 *icrp = 0x0d000000;
1da177e4
LT		 1328}
1329
1330static void __inline__ fec_localhw_setup(void)
1331{
1332}
1333
1334/*
1335 * Do not need to make region uncached on 5272.
1336 */
1337static void __inline__ fec_uncache(unsigned long addr)
1338{
1339}
1340
1341/* ------------------------------------------------------------------------- */
1342
7dd6a2aa 1343#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
1da177e4
LT		 1344
1345/*
7dd6a2aa
GU		 1346 * Code specific to Coldfire 5230/5231/5232/5234/5235,
1347 * the 5270/5271/5274/5275 and 5280/5282 setups.
1da177e4
LT		 1348 */
1349static void __inline__ fec_request_intrs(struct net_device *dev)
1350{
1351 struct fec_enet_private *fep;
1352 int b;
7dd6a2aa
GU		 1353 static const struct idesc {
1354 char *name;
1355 unsigned short irq;
1356 } *idp, id[] = {
1357 { "fec(TXF)", 23 },
7dd6a2aa 1358 { "fec(RXF)", 27 },
7dd6a2aa 1359 { "fec(MII)", 29 },
7dd6a2aa
GU		 1360 { NULL },
1361 };
1da177e4
LT		 1362
1363 fep = netdev_priv(dev);
1364 b = (fep->index) ? 128 : 64;
1365
1366 /* Setup interrupt handlers. */
7dd6a2aa 1367 for (idp = id; idp->name; idp++) {
0a504779 1368 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name, dev) != 0)
7dd6a2aa
GU		 1369 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1370 }
1da177e4
LT		 1371
1372 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1373 {
1374 volatile unsigned char *icrp;
1375 volatile unsigned long *imrp;
83901fc1 1376 int i, ilip;
1da177e4
LT		 1377
1378 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1379 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1380 MCFINTC_ICR0);
83901fc1
WC		 1381 for (i = 23, ilip = 0x28; (i < 36); i++)
1382 icrp[i] = ilip--;
1da177e4
LT		 1383
1384 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1385 MCFINTC_IMRH);
1386 *imrp &= ~0x0000000f;
1387 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1388 MCFINTC_IMRL);
1389 *imrp &= ~0xff800001;
1390 }
1391
1392#if defined(CONFIG_M528x)
1393 /* Set up gpio outputs for MII lines */
1394 {
7dd6a2aa
GU		 1395 volatile u16 *gpio_paspar;
1396 volatile u8 *gpio_pehlpar;
6aa20a22 1397
7dd6a2aa
GU		 1398 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1399 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
1400 *gpio_paspar |= 0x0f00;
1401 *gpio_pehlpar = 0xc0;
1da177e4
LT		 1402 }
1403#endif
b8a94b3d
MC		 1404
1405#if defined(CONFIG_M527x)
1406 /* Set up gpio outputs for MII lines */
1407 {
1408 volatile u8 *gpio_par_fec;
1409 volatile u16 *gpio_par_feci2c;
1410
1411 gpio_par_feci2c = (volatile u16 *)(MCF_IPSBAR + 0x100082);
1412 /* Set up gpio outputs for FEC0 MII lines */
1413 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100078);
1414
1415 *gpio_par_feci2c |= 0x0f00;
1416 *gpio_par_fec |= 0xc0;
1417
1418#if defined(CONFIG_FEC2)
1419 /* Set up gpio outputs for FEC1 MII lines */
1420 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100079);
1421
1422 *gpio_par_feci2c |= 0x00a0;
1423 *gpio_par_fec |= 0xc0;
1424#endif /* CONFIG_FEC2 */
1425 }
1426#endif /* CONFIG_M527x */
1da177e4
LT		 1427}
1428
1429static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1430{
1431 volatile fec_t *fecp;
1432
1433 fecp = fep->hwp;
1434 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1435 fecp->fec_x_cntrl = 0x00;
1436
1437 /*
1438 * Set MII speed to 2.5 MHz
1439 * See 5282 manual section 17.5.4.7: MSCR
1440 */
1441 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1442 fecp->fec_mii_speed = fep->phy_speed;
1443
1444 fec_restart(dev, 0);
1445}
1446
1447static void __inline__ fec_get_mac(struct net_device *dev)
1448{
1449 struct fec_enet_private *fep = netdev_priv(dev);
1450 volatile fec_t *fecp;
7dd6a2aa 1451 unsigned char *iap, tmpaddr[ETH_ALEN];
1da177e4
LT		 1452
1453 fecp = fep->hwp;
1454
7dd6a2aa 1455 if (FEC_FLASHMAC) {
1da177e4
LT		 1456 /*
1457 * Get MAC address from FLASH.
1458 * If it is all 1's or 0's, use the default.
1459 */
7dd6a2aa 1460 iap = FEC_FLASHMAC;
1da177e4
LT		 1461 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1462 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1463 iap = fec_mac_default;
1464 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1465 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1466 iap = fec_mac_default;
1467 } else {
1468 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1469 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1470 iap = &tmpaddr[0];
1471 }
1472
7dd6a2aa 1473 memcpy(dev->dev_addr, iap, ETH_ALEN);
1da177e4
LT		 1474
1475 /* Adjust MAC if using default MAC address */
7dd6a2aa
GU		 1476 if (iap == fec_mac_default)
1477 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1da177e4
LT		 1478}
1479
1480static void __inline__ fec_enable_phy_intr(void)
1481{
1482}
1483
1484static void __inline__ fec_disable_phy_intr(void)
1485{
1486}
1487
1488static void __inline__ fec_phy_ack_intr(void)
1489{
1490}
1491
1492static void __inline__ fec_localhw_setup(void)
1493{
1494}
1495
1496/*
1497 * Do not need to make region uncached on 5272.
1498 */
1499static void __inline__ fec_uncache(unsigned long addr)
1500{
1501}
1502
1503/* ------------------------------------------------------------------------- */
1504
562d2f8c
GU		 1505#elif defined(CONFIG_M520x)
1506
1507/*
1508 * Code specific to Coldfire 520x
1509 */
1510static void __inline__ fec_request_intrs(struct net_device *dev)
1511{
1512 struct fec_enet_private *fep;
1513 int b;
1514 static const struct idesc {
1515 char *name;
1516 unsigned short irq;
1517 } *idp, id[] = {
1518 { "fec(TXF)", 23 },
562d2f8c 1519 { "fec(RXF)", 27 },
562d2f8c 1520 { "fec(MII)", 29 },
562d2f8c
GU		 1521 { NULL },
1522 };
1523
1524 fep = netdev_priv(dev);
1525 b = 64 + 13;
1526
1527 /* Setup interrupt handlers. */
1528 for (idp = id; idp->name; idp++) {
0a504779 1529 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
562d2f8c
GU		 1530 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1531 }
1532
1533 /* Unmask interrupts at ColdFire interrupt controller */
1534 {
1535 volatile unsigned char *icrp;
1536 volatile unsigned long *imrp;
1537
1538 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
1539 MCFINTC_ICR0);
1540 for (b = 36; (b < 49); b++)
1541 icrp[b] = 0x04;
1542 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
1543 MCFINTC_IMRH);
1544 *imrp &= ~0x0001FFF0;
1545 }
1546 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
1547 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
1548}
1549
1550static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1551{
1552 volatile fec_t *fecp;
1553
1554 fecp = fep->hwp;
1555 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1556 fecp->fec_x_cntrl = 0x00;
1557
1558 /*
1559 * Set MII speed to 2.5 MHz
1560 * See 5282 manual section 17.5.4.7: MSCR
1561 */
1562 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1563 fecp->fec_mii_speed = fep->phy_speed;
1564
1565 fec_restart(dev, 0);
1566}
1567
1568static void __inline__ fec_get_mac(struct net_device *dev)
1569{
1570 struct fec_enet_private *fep = netdev_priv(dev);
1571 volatile fec_t *fecp;
1572 unsigned char *iap, tmpaddr[ETH_ALEN];
1573
1574 fecp = fep->hwp;
1575
1576 if (FEC_FLASHMAC) {
1577 /*
1578 * Get MAC address from FLASH.
1579 * If it is all 1's or 0's, use the default.
1580 */
1581 iap = FEC_FLASHMAC;
1582 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1583 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1584 iap = fec_mac_default;
1585 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1586 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1587 iap = fec_mac_default;
1588 } else {
1589 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1590 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1591 iap = &tmpaddr[0];
1592 }
1593
1594 memcpy(dev->dev_addr, iap, ETH_ALEN);
1595
1596 /* Adjust MAC if using default MAC address */
1597 if (iap == fec_mac_default)
1598 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1599}
1600
1601static void __inline__ fec_enable_phy_intr(void)
1602{
1603}
1604
1605static void __inline__ fec_disable_phy_intr(void)
1606{
1607}
1608
1609static void __inline__ fec_phy_ack_intr(void)
1610{
1611}
1612
1613static void __inline__ fec_localhw_setup(void)
1614{
1615}
1616
1617static void __inline__ fec_uncache(unsigned long addr)
1618{
1619}
1620
1621/* ------------------------------------------------------------------------- */
1622
6b265293
MW		 1623#elif defined(CONFIG_M532x)
1624/*
1625 * Code specific for M532x
1626 */
1627static void __inline__ fec_request_intrs(struct net_device *dev)
1628{
1629 struct fec_enet_private *fep;
1630 int b;
1631 static const struct idesc {
1632 char *name;
1633 unsigned short irq;
1634 } *idp, id[] = {
1635 { "fec(TXF)", 36 },
6b265293 1636 { "fec(RXF)", 40 },
6b265293 1637 { "fec(MII)", 42 },
6b265293
MW		 1638 { NULL },
1639 };
1640
1641 fep = netdev_priv(dev);
1642 b = (fep->index) ? 128 : 64;
1643
1644 /* Setup interrupt handlers. */
1645 for (idp = id; idp->name; idp++) {
0a504779 1646 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
6aa20a22 1647 printk("FEC: Could not allocate %s IRQ(%d)!\n",
6b265293
MW		 1648 idp->name, b+idp->irq);
1649 }
1650
1651 /* Unmask interrupts */
1652 MCF_INTC0_ICR36 = 0x2;
1653 MCF_INTC0_ICR37 = 0x2;
1654 MCF_INTC0_ICR38 = 0x2;
1655 MCF_INTC0_ICR39 = 0x2;
1656 MCF_INTC0_ICR40 = 0x2;
1657 MCF_INTC0_ICR41 = 0x2;
1658 MCF_INTC0_ICR42 = 0x2;
1659 MCF_INTC0_ICR43 = 0x2;
1660 MCF_INTC0_ICR44 = 0x2;
1661 MCF_INTC0_ICR45 = 0x2;
1662 MCF_INTC0_ICR46 = 0x2;
1663 MCF_INTC0_ICR47 = 0x2;
1664 MCF_INTC0_ICR48 = 0x2;
1665
1666 MCF_INTC0_IMRH &= ~(
1667 MCF_INTC_IMRH_INT_MASK36 |
1668 MCF_INTC_IMRH_INT_MASK37 |
1669 MCF_INTC_IMRH_INT_MASK38 |
1670 MCF_INTC_IMRH_INT_MASK39 |
1671 MCF_INTC_IMRH_INT_MASK40 |
1672 MCF_INTC_IMRH_INT_MASK41 |
1673 MCF_INTC_IMRH_INT_MASK42 |
1674 MCF_INTC_IMRH_INT_MASK43 |
1675 MCF_INTC_IMRH_INT_MASK44 |
1676 MCF_INTC_IMRH_INT_MASK45 |
1677 MCF_INTC_IMRH_INT_MASK46 |
1678 MCF_INTC_IMRH_INT_MASK47 |
1679 MCF_INTC_IMRH_INT_MASK48 );
1680
1681 /* Set up gpio outputs for MII lines */
1682 MCF_GPIO_PAR_FECI2C |= (0 |
1683 MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
1684 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
1685 MCF_GPIO_PAR_FEC = (0 |
1686 MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
1687 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
1688}
1689
1690static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1691{
1692 volatile fec_t *fecp;
1693
1694 fecp = fep->hwp;
1695 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1696 fecp->fec_x_cntrl = 0x00;
1697
1698 /*
1699 * Set MII speed to 2.5 MHz
1700 */
1701 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1702 fecp->fec_mii_speed = fep->phy_speed;
1703
1704 fec_restart(dev, 0);
1705}
1706
1707static void __inline__ fec_get_mac(struct net_device *dev)
1708{
1709 struct fec_enet_private *fep = netdev_priv(dev);
1710 volatile fec_t *fecp;
1711 unsigned char *iap, tmpaddr[ETH_ALEN];
1712
1713 fecp = fep->hwp;
1714
1715 if (FEC_FLASHMAC) {
1716 /*
1717 * Get MAC address from FLASH.
1718 * If it is all 1's or 0's, use the default.
1719 */
1720 iap = FEC_FLASHMAC;
1721 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1722 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1723 iap = fec_mac_default;
1724 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1725 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1726 iap = fec_mac_default;
1727 } else {
1728 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1729 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1730 iap = &tmpaddr[0];
1731 }
1732
1733 memcpy(dev->dev_addr, iap, ETH_ALEN);
1734
1735 /* Adjust MAC if using default MAC address */
1736 if (iap == fec_mac_default)
1737 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1738}
1739
1740static void __inline__ fec_enable_phy_intr(void)
1741{
1742}
1743
1744static void __inline__ fec_disable_phy_intr(void)
1745{
1746}
1747
1748static void __inline__ fec_phy_ack_intr(void)
1749{
1750}
1751
1752static void __inline__ fec_localhw_setup(void)
1753{
1754}
1755
1756/*
1757 * Do not need to make region uncached on 532x.
1758 */
1759static void __inline__ fec_uncache(unsigned long addr)
1760{
1761}
1762
1763/* ------------------------------------------------------------------------- */
1764
1765
1da177e4
LT		 1766#else
1767
1768/*
7dd6a2aa 1769 * Code specific to the MPC860T setup.
1da177e4
LT		 1770 */
1771static void __inline__ fec_request_intrs(struct net_device *dev)
1772{
1773 volatile immap_t *immap;
1774
1775 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1776
1777 if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1778 panic("Could not allocate FEC IRQ!");
1da177e4
LT		 1779}
1780
1781static void __inline__ fec_get_mac(struct net_device *dev)
1782{
1da177e4 1783 bd_t *bd;
1da177e4 1784
1da177e4 1785 bd = (bd_t *)__res;
7dd6a2aa 1786 memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN);
1da177e4
LT		 1787}
1788
1789static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1790{
1791 extern uint _get_IMMR(void);
1792 volatile immap_t *immap;
1793 volatile fec_t *fecp;
1794
1795 fecp = fep->hwp;
1796 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1797
1798 /* Configure all of port D for MII.
1799 */
1800 immap->im_ioport.iop_pdpar = 0x1fff;
1801
1802 /* Bits moved from Rev. D onward.
1803 */
1804 if ((_get_IMMR() & 0xffff) < 0x0501)
1805 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1806 else
1807 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
6aa20a22 1808
1da177e4
LT		 1809 /* Set MII speed to 2.5 MHz
1810 */
6aa20a22 1811 fecp->fec_mii_speed = fep->phy_speed =
1da177e4
LT		 1812 ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e;
1813}
1814
1815static void __inline__ fec_enable_phy_intr(void)
1816{
1817 volatile fec_t *fecp;
1818
1819 fecp = fep->hwp;
1820
6aa20a22 1821 /* Enable MII command finished interrupt
1da177e4
LT		 1822 */
1823 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1824}
1825
1826static void __inline__ fec_disable_phy_intr(void)
1827{
1828}
1829
1830static void __inline__ fec_phy_ack_intr(void)
1831{
1832}
1833
1834static void __inline__ fec_localhw_setup(void)
1835{
1836 volatile fec_t *fecp;
1837
1838 fecp = fep->hwp;
1839 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1840 /* Enable big endian and don't care about SDMA FC.
1841 */
1842 fecp->fec_fun_code = 0x78000000;
1843}
1844
1845static void __inline__ fec_uncache(unsigned long addr)
1846{
1847 pte_t *pte;
1848 pte = va_to_pte(mem_addr);
1849 pte_val(*pte) |= _PAGE_NO_CACHE;
1850 flush_tlb_page(init_mm.mmap, mem_addr);
1851}
1852
1853#endif
1854
1855/* ------------------------------------------------------------------------- */
1856
1857static void mii_display_status(struct net_device *dev)
1858{
1859 struct fec_enet_private *fep = netdev_priv(dev);
1860 volatile uint *s = &(fep->phy_status);
1861
1862 if (!fep->link && !fep->old_link) {
1863 /* Link is still down - don't print anything */
1864 return;
1865 }
1866
1867 printk("%s: status: ", dev->name);
1868
1869 if (!fep->link) {
1870 printk("link down");
1871 } else {
1872 printk("link up");
1873
1874 switch(*s & PHY_STAT_SPMASK) {
1875 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1876 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1877 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1878 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1879 default:
1880 printk(", Unknown speed/duplex");
1881 }
1882
1883 if (*s & PHY_STAT_ANC)
1884 printk(", auto-negotiation complete");
1885 }
1886
1887 if (*s & PHY_STAT_FAULT)
1888 printk(", remote fault");
1889
1890 printk(".\n");
1891}
1892
cb84d6e7 1893static void mii_display_config(struct work_struct *work)
1da177e4 1894{
cb84d6e7
GU		 1895 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1896 struct net_device *dev = fep->netdev;
7dd6a2aa 1897 uint status = fep->phy_status;
1da177e4
LT		 1898
1899 /*
1900 ** When we get here, phy_task is already removed from
1901 ** the workqueue. It is thus safe to allow to reuse it.
1902 */
1903 fep->mii_phy_task_queued = 0;
1904 printk("%s: config: auto-negotiation ", dev->name);
1905
7dd6a2aa 1906 if (status & PHY_CONF_ANE)
1da177e4
LT		 1907 printk("on");
1908 else
1909 printk("off");
1910
7dd6a2aa 1911 if (status & PHY_CONF_100FDX)
1da177e4 1912 printk(", 100FDX");
7dd6a2aa 1913 if (status & PHY_CONF_100HDX)
1da177e4 1914 printk(", 100HDX");
7dd6a2aa 1915 if (status & PHY_CONF_10FDX)
1da177e4 1916 printk(", 10FDX");
7dd6a2aa 1917 if (status & PHY_CONF_10HDX)
1da177e4 1918 printk(", 10HDX");
7dd6a2aa 1919 if (!(status & PHY_CONF_SPMASK))
1da177e4
LT		 1920 printk(", No speed/duplex selected?");
1921
7dd6a2aa 1922 if (status & PHY_CONF_LOOP)
1da177e4 1923 printk(", loopback enabled");
6aa20a22 1924
1da177e4
LT		 1925 printk(".\n");
1926
1927 fep->sequence_done = 1;
1928}
1929
cb84d6e7 1930static void mii_relink(struct work_struct *work)
1da177e4 1931{
cb84d6e7
GU		 1932 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1933 struct net_device *dev = fep->netdev;
1da177e4
LT		 1934 int duplex;
1935
1936 /*
1937 ** When we get here, phy_task is already removed from
1938 ** the workqueue. It is thus safe to allow to reuse it.
1939 */
1940 fep->mii_phy_task_queued = 0;
1941 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1942 mii_display_status(dev);
1943 fep->old_link = fep->link;
1944
1945 if (fep->link) {
1946 duplex = 0;
6aa20a22 1947 if (fep->phy_status
1da177e4
LT		 1948 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1949 duplex = 1;
1950 fec_restart(dev, duplex);
f909b1ef 1951 } else
1da177e4
LT		 1952 fec_stop(dev);
1953
1954#if 0
1955 enable_irq(fep->mii_irq);
1956#endif
1957
1958}
1959
1960/* mii_queue_relink is called in interrupt context from mii_link_interrupt */
1961static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1962{
1963 struct fec_enet_private *fep = netdev_priv(dev);
1964
1965 /*
1966 ** We cannot queue phy_task twice in the workqueue. It
1967 ** would cause an endless loop in the workqueue.
1968 ** Fortunately, if the last mii_relink entry has not yet been
1969 ** executed now, it will do the job for the current interrupt,
1970 ** which is just what we want.
1971 */
1972 if (fep->mii_phy_task_queued)
1973 return;
1974
1975 fep->mii_phy_task_queued = 1;
cb84d6e7 1976 INIT_WORK(&fep->phy_task, mii_relink);
1da177e4
LT		 1977 schedule_work(&fep->phy_task);
1978}
1979
7dd6a2aa 1980/* mii_queue_config is called in interrupt context from fec_enet_mii */
1da177e4
LT		 1981static void mii_queue_config(uint mii_reg, struct net_device *dev)
1982{
1983 struct fec_enet_private *fep = netdev_priv(dev);
1984
1985 if (fep->mii_phy_task_queued)
1986 return;
1987
1988 fep->mii_phy_task_queued = 1;
cb84d6e7 1989 INIT_WORK(&fep->phy_task, mii_display_config);
1da177e4
LT		 1990 schedule_work(&fep->phy_task);
1991}
1992
7dd6a2aa
GU		 1993phy_cmd_t const phy_cmd_relink[] = {
1994 { mk_mii_read(MII_REG_CR), mii_queue_relink },
1995 { mk_mii_end, }
1996 };
1997phy_cmd_t const phy_cmd_config[] = {
1998 { mk_mii_read(MII_REG_CR), mii_queue_config },
1999 { mk_mii_end, }
2000 };
1da177e4
LT		 2001
2002/* Read remainder of PHY ID.
2003*/
2004static void
2005mii_discover_phy3(uint mii_reg, struct net_device *dev)
2006{
2007 struct fec_enet_private *fep;
2008 int i;
2009
2010 fep = netdev_priv(dev);
2011 fep->phy_id |= (mii_reg & 0xffff);
2012 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
2013
2014 for(i = 0; phy_info[i]; i++) {
2015 if(phy_info[i]->id == (fep->phy_id >> 4))
2016 break;
2017 }
2018
2019 if (phy_info[i])
2020 printk(" -- %s\n", phy_info[i]->name);
2021 else
2022 printk(" -- unknown PHY!\n");
6aa20a22 2023
1da177e4
LT		 2024 fep->phy = phy_info[i];
2025 fep->phy_id_done = 1;
2026}
2027
2028/* Scan all of the MII PHY addresses looking for someone to respond
2029 * with a valid ID. This usually happens quickly.
2030 */
2031static void
2032mii_discover_phy(uint mii_reg, struct net_device *dev)
2033{
2034 struct fec_enet_private *fep;
2035 volatile fec_t *fecp;
2036 uint phytype;
2037
2038 fep = netdev_priv(dev);
2039 fecp = fep->hwp;
2040
2041 if (fep->phy_addr < 32) {
2042 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
6aa20a22 2043
1da177e4
LT		 2044 /* Got first part of ID, now get remainder.
2045 */
2046 fep->phy_id = phytype << 16;
2047 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
2048 mii_discover_phy3);
f909b1ef 2049 } else {
1da177e4
LT		 2050 fep->phy_addr++;
2051 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
2052 mii_discover_phy);
2053 }
2054 } else {
2055 printk("FEC: No PHY device found.\n");
2056 /* Disable external MII interface */
2057 fecp->fec_mii_speed = fep->phy_speed = 0;
2058 fec_disable_phy_intr();
2059 }
2060}
2061
2062/* This interrupt occurs when the PHY detects a link change.
2063*/
c1d96156 2064#ifdef HAVE_mii_link_interrupt
1da177e4 2065static irqreturn_t
7d12e780 2066mii_link_interrupt(int irq, void * dev_id)
1da177e4
LT		 2067{
2068 struct net_device *dev = dev_id;
2069 struct fec_enet_private *fep = netdev_priv(dev);
2070
2071 fec_phy_ack_intr();
2072
2073#if 0
2074 disable_irq(fep->mii_irq); /* disable now, enable later */
2075#endif
2076
2077 mii_do_cmd(dev, fep->phy->ack_int);
2078 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
2079
2080 return IRQ_HANDLED;
2081}
c1d96156 2082#endif
1da177e4
LT		 2083
2084static int
2085fec_enet_open(struct net_device *dev)
2086{
2087 struct fec_enet_private *fep = netdev_priv(dev);
2088
2089 /* I should reset the ring buffers here, but I don't yet know
2090 * a simple way to do that.
2091 */
2092 fec_set_mac_address(dev);
2093
2094 fep->sequence_done = 0;
2095 fep->link = 0;
2096
2097 if (fep->phy) {
2098 mii_do_cmd(dev, fep->phy->ack_int);
2099 mii_do_cmd(dev, fep->phy->config);
2100 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
2101
6b265293
MW		 2102 /* Poll until the PHY tells us its configuration
2103 * (not link state).
2104 * Request is initiated by mii_do_cmd above, but answer
2105 * comes by interrupt.
2106 * This should take about 25 usec per register at 2.5 MHz,
2107 * and we read approximately 5 registers.
1da177e4
LT		 2108 */
2109 while(!fep->sequence_done)
2110 schedule();
2111
2112 mii_do_cmd(dev, fep->phy->startup);
2113
2114 /* Set the initial link state to true. A lot of hardware
2115 * based on this device does not implement a PHY interrupt,
2116 * so we are never notified of link change.
2117 */
2118 fep->link = 1;
2119 } else {
2120 fep->link = 1; /* lets just try it and see */
2121 /* no phy, go full duplex, it's most likely a hub chip */
2122 fec_restart(dev, 1);
2123 }
2124
2125 netif_start_queue(dev);
2126 fep->opened = 1;
2127 return 0; /* Success */
2128}
2129
2130static int
2131fec_enet_close(struct net_device *dev)
2132{
2133 struct fec_enet_private *fep = netdev_priv(dev);
2134
2135 /* Don't know what to do yet.
2136 */
2137 fep->opened = 0;
2138 netif_stop_queue(dev);
2139 fec_stop(dev);
2140
2141 return 0;
2142}
2143
1da177e4
LT		 2144/* Set or clear the multicast filter for this adaptor.
2145 * Skeleton taken from sunlance driver.
2146 * The CPM Ethernet implementation allows Multicast as well as individual
2147 * MAC address filtering. Some of the drivers check to make sure it is
2148 * a group multicast address, and discard those that are not. I guess I
2149 * will do the same for now, but just remove the test if you want
2150 * individual filtering as well (do the upper net layers want or support
2151 * this kind of feature?).
2152 */
2153
2154#define HASH_BITS 6 /* #bits in hash */
2155#define CRC32_POLY 0xEDB88320
2156
2157static void set_multicast_list(struct net_device *dev)
2158{
2159 struct fec_enet_private *fep;
2160 volatile fec_t *ep;
2161 struct dev_mc_list *dmi;
2162 unsigned int i, j, bit, data, crc;
2163 unsigned char hash;
2164
2165 fep = netdev_priv(dev);
2166 ep = fep->hwp;
2167
2168 if (dev->flags&IFF_PROMISC) {
1da177e4
LT		 2169 ep->fec_r_cntrl |= 0x0008;
2170 } else {
2171
2172 ep->fec_r_cntrl &= ~0x0008;
2173
2174 if (dev->flags & IFF_ALLMULTI) {
2175 /* Catch all multicast addresses, so set the
2176 * filter to all 1's.
2177 */
cc462f7d
GU		 2178 ep->fec_grp_hash_table_high = 0xffffffff;
2179 ep->fec_grp_hash_table_low = 0xffffffff;
1da177e4
LT		 2180 } else {
2181 /* Clear filter and add the addresses in hash register.
2182 */
cc462f7d
GU		 2183 ep->fec_grp_hash_table_high = 0;
2184 ep->fec_grp_hash_table_low = 0;
6aa20a22 2185
1da177e4
LT		 2186 dmi = dev->mc_list;
2187
2188 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
2189 {
2190 /* Only support group multicast for now.
2191 */
2192 if (!(dmi->dmi_addr[0] & 1))
2193 continue;
6aa20a22 2194
1da177e4
LT		 2195 /* calculate crc32 value of mac address
2196 */
2197 crc = 0xffffffff;
2198
2199 for (i = 0; i < dmi->dmi_addrlen; i++)
2200 {
2201 data = dmi->dmi_addr[i];
2202 for (bit = 0; bit < 8; bit++, data >>= 1)
2203 {
2204 crc = (crc >> 1) ^
2205 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2206 }
2207 }
2208
2209 /* only upper 6 bits (HASH_BITS) are used
2210 which point to specific bit in he hash registers
2211 */
2212 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
6aa20a22 2213
1da177e4 2214 if (hash > 31)
cc462f7d 2215 ep->fec_grp_hash_table_high |= 1 << (hash - 32);
1da177e4 2216 else
cc462f7d 2217 ep->fec_grp_hash_table_low |= 1 << hash;
1da177e4
LT		 2218 }
2219 }
2220 }
2221}
2222
2223/* Set a MAC change in hardware.
2224 */
2225static void
2226fec_set_mac_address(struct net_device *dev)
2227{
1da177e4
LT		 2228 volatile fec_t *fecp;
2229
7dd6a2aa 2230 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
1da177e4
LT		 2231
2232 /* Set station address. */
7dd6a2aa
GU		 2233 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
2234 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
2235 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
2236 (dev->dev_addr[4] << 24);
1da177e4
LT		 2237
2238}
2239
2240/* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
2241 */
2242 /*
2243 * XXX: We need to clean up on failure exits here.
2244 */
2245int __init fec_enet_init(struct net_device *dev)
2246{
2247 struct fec_enet_private *fep = netdev_priv(dev);
2248 unsigned long mem_addr;
2249 volatile cbd_t *bdp;
2250 cbd_t *cbd_base;
2251 volatile fec_t *fecp;
2252 int i, j;
2253 static int index = 0;
2254
2255 /* Only allow us to be probed once. */
2256 if (index >= FEC_MAX_PORTS)
2257 return -ENXIO;
2258
562d2f8c
GU		 2259 /* Allocate memory for buffer descriptors.
2260 */
2261 mem_addr = __get_free_page(GFP_KERNEL);
2262 if (mem_addr == 0) {
2263 printk("FEC: allocate descriptor memory failed?\n");
2264 return -ENOMEM;
2265 }
2266
3b2b74ca
SS		 2267 spin_lock_init(&fep->hw_lock);
2268 spin_lock_init(&fep->mii_lock);
2269
1da177e4
LT		 2270 /* Create an Ethernet device instance.
2271 */
2272 fecp = (volatile fec_t *) fec_hw[index];
2273
2274 fep->index = index;
2275 fep->hwp = fecp;
cb84d6e7 2276 fep->netdev = dev;
1da177e4
LT		 2277
2278 /* Whack a reset. We should wait for this.
2279 */
2280 fecp->fec_ecntrl = 1;
2281 udelay(10);
2282
1da177e4
LT		 2283 /* Set the Ethernet address. If using multiple Enets on the 8xx,
2284 * this needs some work to get unique addresses.
2285 *
2286 * This is our default MAC address unless the user changes
2287 * it via eth_mac_addr (our dev->set_mac_addr handler).
2288 */
2289 fec_get_mac(dev);
2290
1da177e4
LT		 2291 cbd_base = (cbd_t *)mem_addr;
2292 /* XXX: missing check for allocation failure */
2293
2294 fec_uncache(mem_addr);
2295
2296 /* Set receive and transmit descriptor base.
2297 */
2298 fep->rx_bd_base = cbd_base;
2299 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
2300
2301 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2302 fep->cur_rx = fep->rx_bd_base;
2303
2304 fep->skb_cur = fep->skb_dirty = 0;
2305
2306 /* Initialize the receive buffer descriptors.
2307 */
2308 bdp = fep->rx_bd_base;
2309 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
2310
2311 /* Allocate a page.
2312 */
2313 mem_addr = __get_free_page(GFP_KERNEL);
2314 /* XXX: missing check for allocation failure */
2315
2316 fec_uncache(mem_addr);
2317
2318 /* Initialize the BD for every fragment in the page.
2319 */
2320 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2321 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2322 bdp->cbd_bufaddr = __pa(mem_addr);
2323 mem_addr += FEC_ENET_RX_FRSIZE;
2324 bdp++;
2325 }
2326 }
2327
2328 /* Set the last buffer to wrap.
2329 */
2330 bdp--;
2331 bdp->cbd_sc |= BD_SC_WRAP;
2332
2333 /* ...and the same for transmmit.
2334 */
2335 bdp = fep->tx_bd_base;
2336 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2337 if (j >= FEC_ENET_TX_FRPPG) {
2338 mem_addr = __get_free_page(GFP_KERNEL);
2339 j = 1;
2340 } else {
2341 mem_addr += FEC_ENET_TX_FRSIZE;
2342 j++;
2343 }
2344 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2345
2346 /* Initialize the BD for every fragment in the page.
2347 */
2348 bdp->cbd_sc = 0;
2349 bdp->cbd_bufaddr = 0;
2350 bdp++;
2351 }
2352
2353 /* Set the last buffer to wrap.
2354 */
2355 bdp--;
2356 bdp->cbd_sc |= BD_SC_WRAP;
2357
2358 /* Set receive and transmit descriptor base.
2359 */
2360 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2361 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2362
2363 /* Install our interrupt handlers. This varies depending on
2364 * the architecture.
2365 */
2366 fec_request_intrs(dev);
2367
cc462f7d
GU		 2368 fecp->fec_grp_hash_table_high = 0;
2369 fecp->fec_grp_hash_table_low = 0;
562d2f8c
GU		 2370 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2371 fecp->fec_ecntrl = 2;
6b265293 2372 fecp->fec_r_des_active = 0;
cc462f7d
GU		 2373#ifndef CONFIG_M5272
2374 fecp->fec_hash_table_high = 0;
2375 fecp->fec_hash_table_low = 0;
2376#endif
562d2f8c 2377
1da177e4
LT		 2378 dev->base_addr = (unsigned long)fecp;
2379
2380 /* The FEC Ethernet specific entries in the device structure. */
2381 dev->open = fec_enet_open;
2382 dev->hard_start_xmit = fec_enet_start_xmit;
2383 dev->tx_timeout = fec_timeout;
2384 dev->watchdog_timeo = TX_TIMEOUT;
2385 dev->stop = fec_enet_close;
1da177e4
LT		 2386 dev->set_multicast_list = set_multicast_list;
2387
2388 for (i=0; i<NMII-1; i++)
2389 mii_cmds[i].mii_next = &mii_cmds[i+1];
2390 mii_free = mii_cmds;
2391
2392 /* setup MII interface */
2393 fec_set_mii(dev, fep);
2394
6b265293
MW		 2395 /* Clear and enable interrupts */
2396 fecp->fec_ievent = 0xffc00000;
398ec922 2397 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII);
6b265293 2398
1da177e4
LT		 2399 /* Queue up command to detect the PHY and initialize the
2400 * remainder of the interface.
2401 */
2402 fep->phy_id_done = 0;
2403 fep->phy_addr = 0;
2404 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2405
2406 index++;
2407 return 0;
2408}
2409
2410/* This function is called to start or restart the FEC during a link
2411 * change. This only happens when switching between half and full
2412 * duplex.
2413 */
2414static void
2415fec_restart(struct net_device *dev, int duplex)
2416{
2417 struct fec_enet_private *fep;
2418 volatile cbd_t *bdp;
2419 volatile fec_t *fecp;
2420 int i;
2421
2422 fep = netdev_priv(dev);
2423 fecp = fep->hwp;
2424
2425 /* Whack a reset. We should wait for this.
2426 */
2427 fecp->fec_ecntrl = 1;
2428 udelay(10);
2429
1da177e4
LT		 2430 /* Clear any outstanding interrupt.
2431 */
7dd6a2aa 2432 fecp->fec_ievent = 0xffc00000;
1da177e4
LT		 2433 fec_enable_phy_intr();
2434
2435 /* Set station address.
2436 */
7dd6a2aa 2437 fec_set_mac_address(dev);
1da177e4
LT		 2438
2439 /* Reset all multicast.
2440 */
cc462f7d
GU		 2441 fecp->fec_grp_hash_table_high = 0;
2442 fecp->fec_grp_hash_table_low = 0;
1da177e4
LT		 2443
2444 /* Set maximum receive buffer size.
2445 */
2446 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2447
2448 fec_localhw_setup();
2449
2450 /* Set receive and transmit descriptor base.
2451 */
2452 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2453 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2454
2455 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2456 fep->cur_rx = fep->rx_bd_base;
2457
2458 /* Reset SKB transmit buffers.
2459 */
2460 fep->skb_cur = fep->skb_dirty = 0;
2461 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2462 if (fep->tx_skbuff[i] != NULL) {
2463 dev_kfree_skb_any(fep->tx_skbuff[i]);
2464 fep->tx_skbuff[i] = NULL;
2465 }
2466 }
2467
2468 /* Initialize the receive buffer descriptors.
2469 */
2470 bdp = fep->rx_bd_base;
2471 for (i=0; i<RX_RING_SIZE; i++) {
2472
2473 /* Initialize the BD for every fragment in the page.
2474 */
2475 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2476 bdp++;
2477 }
2478
2479 /* Set the last buffer to wrap.
2480 */
2481 bdp--;
2482 bdp->cbd_sc |= BD_SC_WRAP;
2483
2484 /* ...and the same for transmmit.
2485 */
2486 bdp = fep->tx_bd_base;
2487 for (i=0; i<TX_RING_SIZE; i++) {
2488
2489 /* Initialize the BD for every fragment in the page.
2490 */
2491 bdp->cbd_sc = 0;
2492 bdp->cbd_bufaddr = 0;
2493 bdp++;
2494 }
2495
2496 /* Set the last buffer to wrap.
2497 */
2498 bdp--;
2499 bdp->cbd_sc |= BD_SC_WRAP;
2500
2501 /* Enable MII mode.
2502 */
2503 if (duplex) {
2504 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2505 fecp->fec_x_cntrl = 0x04; /* FD enable */
f909b1ef 2506 } else {
1da177e4
LT		 2507 /* MII enable|No Rcv on Xmit */
2508 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2509 fecp->fec_x_cntrl = 0x00;
2510 }
2511 fep->full_duplex = duplex;
2512
2513 /* Set MII speed.
2514 */
2515 fecp->fec_mii_speed = fep->phy_speed;
2516
2517 /* And last, enable the transmit and receive processing.
2518 */
2519 fecp->fec_ecntrl = 2;
6b265293
MW		 2520 fecp->fec_r_des_active = 0;
2521
2522 /* Enable interrupts we wish to service.
2523 */
398ec922 2524 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII);
1da177e4
LT		 2525}
2526
2527static void
2528fec_stop(struct net_device *dev)
2529{
2530 volatile fec_t *fecp;
2531 struct fec_enet_private *fep;
2532
2533 fep = netdev_priv(dev);
2534 fecp = fep->hwp;
2535
677177c5
PDM		 2536 /*
2537 ** We cannot expect a graceful transmit stop without link !!!
2538 */
2539 if (fep->link)
2540 {
2541 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
2542 udelay(10);
2543 if (!(fecp->fec_ievent & FEC_ENET_GRA))
2544 printk("fec_stop : Graceful transmit stop did not complete !\n");
2545 }
1da177e4
LT		 2546
2547 /* Whack a reset. We should wait for this.
2548 */
2549 fecp->fec_ecntrl = 1;
2550 udelay(10);
2551
2552 /* Clear outstanding MII command interrupts.
2553 */
2554 fecp->fec_ievent = FEC_ENET_MII;
2555 fec_enable_phy_intr();
2556
2557 fecp->fec_imask = FEC_ENET_MII;
2558 fecp->fec_mii_speed = fep->phy_speed;
2559}
2560
2561static int __init fec_enet_module_init(void)
2562{
2563 struct net_device *dev;
c1d96156 2564 int i, err;
7dd6a2aa
GU		 2565
2566 printk("FEC ENET Version 0.2\n");
1da177e4
LT		 2567
2568 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2569 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2570 if (!dev)
2571 return -ENOMEM;
2572 err = fec_enet_init(dev);
2573 if (err) {
2574 free_netdev(dev);
2575 continue;
2576 }
2577 if (register_netdev(dev) != 0) {
2578 /* XXX: missing cleanup here */
2579 free_netdev(dev);
2580 return -EIO;
2581 }
7dd6a2aa 2582
e174961c 2583 printk("%s: ethernet %pM\n", dev->name, dev->dev_addr);
1da177e4
LT		 2584 }
2585 return 0;
2586}
2587
2588module_init(fec_enet_module_init);
2589
2590MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)