Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b SG |
20 | * |
21 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/spinlock.h> | |
39 | #include <linux/workqueue.h> | |
40 | #include <linux/bitops.h> | |
6f501b17 SH |
41 | #include <linux/io.h> |
42 | #include <linux/irq.h> | |
196719ec | 43 | #include <linux/clk.h> |
ead73183 | 44 | #include <linux/platform_device.h> |
e6b043d5 | 45 | #include <linux/phy.h> |
5eb32bd0 | 46 | #include <linux/fec.h> |
1da177e4 | 47 | |
080853af | 48 | #include <asm/cacheflush.h> |
196719ec | 49 | |
b5680e0b | 50 | #ifndef CONFIG_ARM |
1da177e4 LT |
51 | #include <asm/coldfire.h> |
52 | #include <asm/mcfsim.h> | |
196719ec | 53 | #endif |
6f501b17 | 54 | |
1da177e4 | 55 | #include "fec.h" |
1da177e4 | 56 | |
085e79ed | 57 | #if defined(CONFIG_ARM) |
196719ec SH |
58 | #define FEC_ALIGNMENT 0xf |
59 | #else | |
60 | #define FEC_ALIGNMENT 0x3 | |
61 | #endif | |
62 | ||
b5680e0b SG |
63 | #define DRIVER_NAME "fec" |
64 | ||
65 | /* Controller is ENET-MAC */ | |
66 | #define FEC_QUIRK_ENET_MAC (1 << 0) | |
67 | /* Controller needs driver to swap frame */ | |
68 | #define FEC_QUIRK_SWAP_FRAME (1 << 1) | |
69 | ||
70 | static struct platform_device_id fec_devtype[] = { | |
71 | { | |
72 | .name = DRIVER_NAME, | |
73 | .driver_data = 0, | |
74 | }, { | |
75 | .name = "imx28-fec", | |
76 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, | |
77 | } | |
78 | }; | |
79 | ||
49da97dc SG |
80 | static unsigned char macaddr[ETH_ALEN]; |
81 | module_param_array(macaddr, byte, NULL, 0); | |
82 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 83 | |
49da97dc | 84 | #if defined(CONFIG_M5272) |
1da177e4 LT |
85 | /* |
86 | * Some hardware gets it MAC address out of local flash memory. | |
87 | * if this is non-zero then assume it is the address to get MAC from. | |
88 | */ | |
89 | #if defined(CONFIG_NETtel) | |
90 | #define FEC_FLASHMAC 0xf0006006 | |
91 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
92 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
93 | #elif defined(CONFIG_CANCam) |
94 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
95 | #elif defined (CONFIG_M5272C3) |
96 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
97 | #elif defined(CONFIG_MOD5272) | |
98 | #define FEC_FLASHMAC 0xffc0406b | |
1da177e4 LT |
99 | #else |
100 | #define FEC_FLASHMAC 0 | |
101 | #endif | |
43be6366 | 102 | #endif /* CONFIG_M5272 */ |
ead73183 | 103 | |
1da177e4 LT |
104 | /* The number of Tx and Rx buffers. These are allocated from the page |
105 | * pool. The code may assume these are power of two, so it it best | |
106 | * to keep them that size. | |
107 | * We don't need to allocate pages for the transmitter. We just use | |
108 | * the skbuffer directly. | |
109 | */ | |
110 | #define FEC_ENET_RX_PAGES 8 | |
111 | #define FEC_ENET_RX_FRSIZE 2048 | |
112 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | |
113 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | |
114 | #define FEC_ENET_TX_FRSIZE 2048 | |
115 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) | |
116 | #define TX_RING_SIZE 16 /* Must be power of two */ | |
117 | #define TX_RING_MOD_MASK 15 /* for this to work */ | |
118 | ||
562d2f8c | 119 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) |
6b265293 | 120 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
121 | #endif |
122 | ||
22f6b860 | 123 | /* Interrupt events/masks. */ |
1da177e4 LT |
124 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
125 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
126 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
127 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
128 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
129 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
130 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
131 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
132 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
133 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
134 | ||
4bee1f9a WS |
135 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
136 | ||
1da177e4 LT |
137 | /* The FEC stores dest/src/type, data, and checksum for receive packets. |
138 | */ | |
139 | #define PKT_MAXBUF_SIZE 1518 | |
140 | #define PKT_MINBUF_SIZE 64 | |
141 | #define PKT_MAXBLR_SIZE 1520 | |
142 | ||
143 | ||
144 | /* | |
6b265293 | 145 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
146 | * size bits. Other FEC hardware does not, so we need to take that into |
147 | * account when setting it. | |
148 | */ | |
562d2f8c | 149 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 150 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
151 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
152 | #else | |
153 | #define OPT_FRAME_SIZE 0 | |
154 | #endif | |
155 | ||
156 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and | |
157 | * tx_bd_base always point to the base of the buffer descriptors. The | |
158 | * cur_rx and cur_tx point to the currently available buffer. | |
159 | * The dirty_tx tracks the current buffer that is being sent by the | |
160 | * controller. The cur_tx and dirty_tx are equal under both completely | |
161 | * empty and completely full conditions. The empty/ready indicator in | |
162 | * the buffer descriptor determines the actual condition. | |
163 | */ | |
164 | struct fec_enet_private { | |
165 | /* Hardware registers of the FEC device */ | |
f44d6305 | 166 | void __iomem *hwp; |
1da177e4 | 167 | |
cb84d6e7 GU |
168 | struct net_device *netdev; |
169 | ||
ead73183 SH |
170 | struct clk *clk; |
171 | ||
1da177e4 LT |
172 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
173 | unsigned char *tx_bounce[TX_RING_SIZE]; | |
174 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
f0b3fbea | 175 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; |
1da177e4 LT |
176 | ushort skb_cur; |
177 | ushort skb_dirty; | |
178 | ||
22f6b860 | 179 | /* CPM dual port RAM relative addresses */ |
4661e75b | 180 | dma_addr_t bd_dma; |
22f6b860 | 181 | /* Address of Rx and Tx buffers */ |
2e28532f SH |
182 | struct bufdesc *rx_bd_base; |
183 | struct bufdesc *tx_bd_base; | |
184 | /* The next free ring entry */ | |
185 | struct bufdesc *cur_rx, *cur_tx; | |
22f6b860 | 186 | /* The ring entries to be free()ed */ |
2e28532f SH |
187 | struct bufdesc *dirty_tx; |
188 | ||
1da177e4 | 189 | uint tx_full; |
3b2b74ca SS |
190 | /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ |
191 | spinlock_t hw_lock; | |
1da177e4 | 192 | |
e6b043d5 | 193 | struct platform_device *pdev; |
1da177e4 | 194 | |
e6b043d5 | 195 | int opened; |
1da177e4 | 196 | |
e6b043d5 BW |
197 | /* Phylib and MDIO interface */ |
198 | struct mii_bus *mii_bus; | |
199 | struct phy_device *phy_dev; | |
200 | int mii_timeout; | |
201 | uint phy_speed; | |
5eb32bd0 | 202 | phy_interface_t phy_interface; |
1da177e4 | 203 | int link; |
1da177e4 | 204 | int full_duplex; |
97b72e43 | 205 | struct completion mdio_done; |
1da177e4 LT |
206 | }; |
207 | ||
7d12e780 | 208 | static irqreturn_t fec_enet_interrupt(int irq, void * dev_id); |
1da177e4 LT |
209 | static void fec_enet_tx(struct net_device *dev); |
210 | static void fec_enet_rx(struct net_device *dev); | |
211 | static int fec_enet_close(struct net_device *dev); | |
1da177e4 LT |
212 | static void fec_restart(struct net_device *dev, int duplex); |
213 | static void fec_stop(struct net_device *dev); | |
1da177e4 | 214 | |
e6b043d5 BW |
215 | /* FEC MII MMFR bits definition */ |
216 | #define FEC_MMFR_ST (1 << 30) | |
217 | #define FEC_MMFR_OP_READ (2 << 28) | |
218 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
219 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
220 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
221 | #define FEC_MMFR_TA (2 << 16) | |
222 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 223 | |
97b72e43 | 224 | #define FEC_MII_TIMEOUT 1000 /* us */ |
1da177e4 | 225 | |
22f6b860 SH |
226 | /* Transmitter timeout */ |
227 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 228 | |
b5680e0b SG |
229 | static void *swap_buffer(void *bufaddr, int len) |
230 | { | |
231 | int i; | |
232 | unsigned int *buf = bufaddr; | |
233 | ||
234 | for (i = 0; i < (len + 3) / 4; i++, buf++) | |
235 | *buf = cpu_to_be32(*buf); | |
236 | ||
237 | return bufaddr; | |
238 | } | |
239 | ||
c7621cb3 | 240 | static netdev_tx_t |
1da177e4 LT |
241 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) |
242 | { | |
f44d6305 | 243 | struct fec_enet_private *fep = netdev_priv(dev); |
b5680e0b SG |
244 | const struct platform_device_id *id_entry = |
245 | platform_get_device_id(fep->pdev); | |
2e28532f | 246 | struct bufdesc *bdp; |
9555b31e | 247 | void *bufaddr; |
0e702ab3 | 248 | unsigned short status; |
3b2b74ca | 249 | unsigned long flags; |
1da177e4 | 250 | |
1da177e4 LT |
251 | if (!fep->link) { |
252 | /* Link is down or autonegotiation is in progress. */ | |
5b548140 | 253 | return NETDEV_TX_BUSY; |
1da177e4 LT |
254 | } |
255 | ||
3b2b74ca | 256 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 LT |
257 | /* Fill in a Tx ring entry */ |
258 | bdp = fep->cur_tx; | |
259 | ||
0e702ab3 | 260 | status = bdp->cbd_sc; |
22f6b860 | 261 | |
0e702ab3 | 262 | if (status & BD_ENET_TX_READY) { |
1da177e4 LT |
263 | /* Ooops. All transmit buffers are full. Bail out. |
264 | * This should not happen, since dev->tbusy should be set. | |
265 | */ | |
266 | printk("%s: tx queue full!.\n", dev->name); | |
3b2b74ca | 267 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
5b548140 | 268 | return NETDEV_TX_BUSY; |
1da177e4 | 269 | } |
1da177e4 | 270 | |
22f6b860 | 271 | /* Clear all of the status flags */ |
0e702ab3 | 272 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 273 | |
22f6b860 | 274 | /* Set buffer length and buffer pointer */ |
9555b31e | 275 | bufaddr = skb->data; |
1da177e4 LT |
276 | bdp->cbd_datlen = skb->len; |
277 | ||
278 | /* | |
22f6b860 SH |
279 | * On some FEC implementations data must be aligned on |
280 | * 4-byte boundaries. Use bounce buffers to copy data | |
281 | * and get it aligned. Ugh. | |
1da177e4 | 282 | */ |
9555b31e | 283 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
1da177e4 LT |
284 | unsigned int index; |
285 | index = bdp - fep->tx_bd_base; | |
8a73b0bc | 286 | memcpy(fep->tx_bounce[index], skb->data, skb->len); |
9555b31e | 287 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
288 | } |
289 | ||
b5680e0b SG |
290 | /* |
291 | * Some design made an incorrect assumption on endian mode of | |
292 | * the system that it's running on. As the result, driver has to | |
293 | * swap every frame going to and coming from the controller. | |
294 | */ | |
295 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) | |
296 | swap_buffer(bufaddr, skb->len); | |
297 | ||
22f6b860 | 298 | /* Save skb pointer */ |
1da177e4 LT |
299 | fep->tx_skbuff[fep->skb_cur] = skb; |
300 | ||
09f75cd7 | 301 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 302 | fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; |
6aa20a22 | 303 | |
1da177e4 LT |
304 | /* Push the data cache so the CPM does not get stale memory |
305 | * data. | |
306 | */ | |
9555b31e | 307 | bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr, |
f0b3fbea | 308 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 309 | |
0e702ab3 GU |
310 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
311 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 312 | */ |
0e702ab3 | 313 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 314 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 315 | bdp->cbd_sc = status; |
1da177e4 | 316 | |
1da177e4 | 317 | /* Trigger transmission start */ |
f44d6305 | 318 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); |
1da177e4 | 319 | |
22f6b860 SH |
320 | /* If this was the last BD in the ring, start at the beginning again. */ |
321 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 322 | bdp = fep->tx_bd_base; |
22f6b860 | 323 | else |
1da177e4 | 324 | bdp++; |
1da177e4 LT |
325 | |
326 | if (bdp == fep->dirty_tx) { | |
327 | fep->tx_full = 1; | |
328 | netif_stop_queue(dev); | |
329 | } | |
330 | ||
2e28532f | 331 | fep->cur_tx = bdp; |
1da177e4 | 332 | |
3b2b74ca | 333 | spin_unlock_irqrestore(&fep->hw_lock, flags); |
1da177e4 | 334 | |
6ed10654 | 335 | return NETDEV_TX_OK; |
1da177e4 LT |
336 | } |
337 | ||
338 | static void | |
339 | fec_timeout(struct net_device *dev) | |
340 | { | |
341 | struct fec_enet_private *fep = netdev_priv(dev); | |
342 | ||
09f75cd7 | 343 | dev->stats.tx_errors++; |
1da177e4 | 344 | |
7dd6a2aa | 345 | fec_restart(dev, fep->full_duplex); |
1da177e4 LT |
346 | netif_wake_queue(dev); |
347 | } | |
348 | ||
1da177e4 | 349 | static irqreturn_t |
7d12e780 | 350 | fec_enet_interrupt(int irq, void * dev_id) |
1da177e4 LT |
351 | { |
352 | struct net_device *dev = dev_id; | |
f44d6305 | 353 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 | 354 | uint int_events; |
3b2b74ca | 355 | irqreturn_t ret = IRQ_NONE; |
1da177e4 | 356 | |
3b2b74ca | 357 | do { |
f44d6305 SH |
358 | int_events = readl(fep->hwp + FEC_IEVENT); |
359 | writel(int_events, fep->hwp + FEC_IEVENT); | |
1da177e4 | 360 | |
1da177e4 | 361 | if (int_events & FEC_ENET_RXF) { |
3b2b74ca | 362 | ret = IRQ_HANDLED; |
1da177e4 LT |
363 | fec_enet_rx(dev); |
364 | } | |
365 | ||
366 | /* Transmit OK, or non-fatal error. Update the buffer | |
f44d6305 SH |
367 | * descriptors. FEC handles all errors, we just discover |
368 | * them as part of the transmit process. | |
369 | */ | |
1da177e4 | 370 | if (int_events & FEC_ENET_TXF) { |
3b2b74ca | 371 | ret = IRQ_HANDLED; |
1da177e4 LT |
372 | fec_enet_tx(dev); |
373 | } | |
97b72e43 BS |
374 | |
375 | if (int_events & FEC_ENET_MII) { | |
376 | ret = IRQ_HANDLED; | |
377 | complete(&fep->mdio_done); | |
378 | } | |
3b2b74ca SS |
379 | } while (int_events); |
380 | ||
381 | return ret; | |
1da177e4 LT |
382 | } |
383 | ||
384 | ||
385 | static void | |
386 | fec_enet_tx(struct net_device *dev) | |
387 | { | |
388 | struct fec_enet_private *fep; | |
2e28532f | 389 | struct bufdesc *bdp; |
0e702ab3 | 390 | unsigned short status; |
1da177e4 LT |
391 | struct sk_buff *skb; |
392 | ||
393 | fep = netdev_priv(dev); | |
81538e74 | 394 | spin_lock(&fep->hw_lock); |
1da177e4 LT |
395 | bdp = fep->dirty_tx; |
396 | ||
0e702ab3 | 397 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
f0b3fbea SH |
398 | if (bdp == fep->cur_tx && fep->tx_full == 0) |
399 | break; | |
400 | ||
401 | dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); | |
402 | bdp->cbd_bufaddr = 0; | |
1da177e4 LT |
403 | |
404 | skb = fep->tx_skbuff[fep->skb_dirty]; | |
405 | /* Check for errors. */ | |
0e702ab3 | 406 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
407 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
408 | BD_ENET_TX_CSL)) { | |
09f75cd7 | 409 | dev->stats.tx_errors++; |
0e702ab3 | 410 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
09f75cd7 | 411 | dev->stats.tx_heartbeat_errors++; |
0e702ab3 | 412 | if (status & BD_ENET_TX_LC) /* Late collision */ |
09f75cd7 | 413 | dev->stats.tx_window_errors++; |
0e702ab3 | 414 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
09f75cd7 | 415 | dev->stats.tx_aborted_errors++; |
0e702ab3 | 416 | if (status & BD_ENET_TX_UN) /* Underrun */ |
09f75cd7 | 417 | dev->stats.tx_fifo_errors++; |
0e702ab3 | 418 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
09f75cd7 | 419 | dev->stats.tx_carrier_errors++; |
1da177e4 | 420 | } else { |
09f75cd7 | 421 | dev->stats.tx_packets++; |
1da177e4 LT |
422 | } |
423 | ||
0e702ab3 | 424 | if (status & BD_ENET_TX_READY) |
1da177e4 | 425 | printk("HEY! Enet xmit interrupt and TX_READY.\n"); |
22f6b860 | 426 | |
1da177e4 LT |
427 | /* Deferred means some collisions occurred during transmit, |
428 | * but we eventually sent the packet OK. | |
429 | */ | |
0e702ab3 | 430 | if (status & BD_ENET_TX_DEF) |
09f75cd7 | 431 | dev->stats.collisions++; |
6aa20a22 | 432 | |
22f6b860 | 433 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 LT |
434 | dev_kfree_skb_any(skb); |
435 | fep->tx_skbuff[fep->skb_dirty] = NULL; | |
436 | fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; | |
6aa20a22 | 437 | |
22f6b860 | 438 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 439 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
440 | bdp = fep->tx_bd_base; |
441 | else | |
442 | bdp++; | |
6aa20a22 | 443 | |
22f6b860 | 444 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 LT |
445 | */ |
446 | if (fep->tx_full) { | |
447 | fep->tx_full = 0; | |
448 | if (netif_queue_stopped(dev)) | |
449 | netif_wake_queue(dev); | |
450 | } | |
451 | } | |
2e28532f | 452 | fep->dirty_tx = bdp; |
81538e74 | 453 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
454 | } |
455 | ||
456 | ||
457 | /* During a receive, the cur_rx points to the current incoming buffer. | |
458 | * When we update through the ring, if the next incoming buffer has | |
459 | * not been given to the system, we just set the empty indicator, | |
460 | * effectively tossing the packet. | |
461 | */ | |
462 | static void | |
463 | fec_enet_rx(struct net_device *dev) | |
464 | { | |
f44d6305 | 465 | struct fec_enet_private *fep = netdev_priv(dev); |
b5680e0b SG |
466 | const struct platform_device_id *id_entry = |
467 | platform_get_device_id(fep->pdev); | |
2e28532f | 468 | struct bufdesc *bdp; |
0e702ab3 | 469 | unsigned short status; |
1da177e4 LT |
470 | struct sk_buff *skb; |
471 | ushort pkt_len; | |
472 | __u8 *data; | |
6aa20a22 | 473 | |
0e702ab3 GU |
474 | #ifdef CONFIG_M532x |
475 | flush_cache_all(); | |
6aa20a22 | 476 | #endif |
1da177e4 | 477 | |
81538e74 | 478 | spin_lock(&fep->hw_lock); |
3b2b74ca | 479 | |
1da177e4 LT |
480 | /* First, grab all of the stats for the incoming packet. |
481 | * These get messed up if we get called due to a busy condition. | |
482 | */ | |
483 | bdp = fep->cur_rx; | |
484 | ||
22f6b860 | 485 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 486 | |
22f6b860 SH |
487 | /* Since we have allocated space to hold a complete frame, |
488 | * the last indicator should be set. | |
489 | */ | |
490 | if ((status & BD_ENET_RX_LAST) == 0) | |
491 | printk("FEC ENET: rcv is not +last\n"); | |
1da177e4 | 492 | |
22f6b860 SH |
493 | if (!fep->opened) |
494 | goto rx_processing_done; | |
1da177e4 | 495 | |
22f6b860 SH |
496 | /* Check for errors. */ |
497 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 498 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
22f6b860 SH |
499 | dev->stats.rx_errors++; |
500 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { | |
501 | /* Frame too long or too short. */ | |
502 | dev->stats.rx_length_errors++; | |
503 | } | |
504 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
505 | dev->stats.rx_frame_errors++; | |
506 | if (status & BD_ENET_RX_CR) /* CRC Error */ | |
507 | dev->stats.rx_crc_errors++; | |
508 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ | |
509 | dev->stats.rx_fifo_errors++; | |
1da177e4 | 510 | } |
1da177e4 | 511 | |
22f6b860 SH |
512 | /* Report late collisions as a frame error. |
513 | * On this error, the BD is closed, but we don't know what we | |
514 | * have in the buffer. So, just drop this frame on the floor. | |
515 | */ | |
516 | if (status & BD_ENET_RX_CL) { | |
517 | dev->stats.rx_errors++; | |
518 | dev->stats.rx_frame_errors++; | |
519 | goto rx_processing_done; | |
520 | } | |
1da177e4 | 521 | |
22f6b860 SH |
522 | /* Process the incoming frame. */ |
523 | dev->stats.rx_packets++; | |
524 | pkt_len = bdp->cbd_datlen; | |
525 | dev->stats.rx_bytes += pkt_len; | |
526 | data = (__u8*)__va(bdp->cbd_bufaddr); | |
1da177e4 | 527 | |
f0b3fbea SH |
528 | dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen, |
529 | DMA_FROM_DEVICE); | |
ccdc4f19 | 530 | |
b5680e0b SG |
531 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) |
532 | swap_buffer(data, pkt_len); | |
533 | ||
22f6b860 SH |
534 | /* This does 16 byte alignment, exactly what we need. |
535 | * The packet length includes FCS, but we don't want to | |
536 | * include that when passing upstream as it messes up | |
537 | * bridging applications. | |
538 | */ | |
8549889c | 539 | skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 540 | |
8549889c | 541 | if (unlikely(!skb)) { |
22f6b860 SH |
542 | printk("%s: Memory squeeze, dropping packet.\n", |
543 | dev->name); | |
544 | dev->stats.rx_dropped++; | |
545 | } else { | |
8549889c | 546 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 SH |
547 | skb_put(skb, pkt_len - 4); /* Make room */ |
548 | skb_copy_to_linear_data(skb, data, pkt_len - 4); | |
549 | skb->protocol = eth_type_trans(skb, dev); | |
550 | netif_rx(skb); | |
551 | } | |
f0b3fbea SH |
552 | |
553 | bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen, | |
554 | DMA_FROM_DEVICE); | |
22f6b860 SH |
555 | rx_processing_done: |
556 | /* Clear the status flags for this buffer */ | |
557 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 558 | |
22f6b860 SH |
559 | /* Mark the buffer empty */ |
560 | status |= BD_ENET_RX_EMPTY; | |
561 | bdp->cbd_sc = status; | |
6aa20a22 | 562 | |
22f6b860 SH |
563 | /* Update BD pointer to next entry */ |
564 | if (status & BD_ENET_RX_WRAP) | |
565 | bdp = fep->rx_bd_base; | |
566 | else | |
567 | bdp++; | |
568 | /* Doing this here will keep the FEC running while we process | |
569 | * incoming frames. On a heavily loaded network, we should be | |
570 | * able to keep up at the expense of system resources. | |
571 | */ | |
572 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
573 | } | |
2e28532f | 574 | fep->cur_rx = bdp; |
1da177e4 | 575 | |
81538e74 | 576 | spin_unlock(&fep->hw_lock); |
1da177e4 LT |
577 | } |
578 | ||
e6b043d5 | 579 | /* ------------------------------------------------------------------------- */ |
e6b043d5 | 580 | static void __inline__ fec_get_mac(struct net_device *dev) |
1da177e4 | 581 | { |
e6b043d5 | 582 | struct fec_enet_private *fep = netdev_priv(dev); |
49da97dc | 583 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
e6b043d5 | 584 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 585 | |
49da97dc SG |
586 | /* |
587 | * try to get mac address in following order: | |
588 | * | |
589 | * 1) module parameter via kernel command line in form | |
590 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
591 | */ | |
592 | iap = macaddr; | |
593 | ||
594 | /* | |
595 | * 2) from flash or fuse (via platform data) | |
596 | */ | |
597 | if (!is_valid_ether_addr(iap)) { | |
598 | #ifdef CONFIG_M5272 | |
599 | if (FEC_FLASHMAC) | |
600 | iap = (unsigned char *)FEC_FLASHMAC; | |
601 | #else | |
602 | if (pdata) | |
603 | memcpy(iap, pdata->mac, ETH_ALEN); | |
604 | #endif | |
605 | } | |
606 | ||
607 | /* | |
608 | * 3) FEC mac registers set by bootloader | |
609 | */ | |
610 | if (!is_valid_ether_addr(iap)) { | |
611 | *((unsigned long *) &tmpaddr[0]) = | |
612 | be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); | |
613 | *((unsigned short *) &tmpaddr[4]) = | |
614 | be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 615 | iap = &tmpaddr[0]; |
1da177e4 LT |
616 | } |
617 | ||
e6b043d5 | 618 | memcpy(dev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 619 | |
49da97dc SG |
620 | /* Adjust MAC if using macaddr */ |
621 | if (iap == macaddr) | |
622 | dev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id; | |
1da177e4 LT |
623 | } |
624 | ||
e6b043d5 | 625 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 626 | |
e6b043d5 BW |
627 | /* |
628 | * Phy section | |
629 | */ | |
630 | static void fec_enet_adjust_link(struct net_device *dev) | |
1da177e4 LT |
631 | { |
632 | struct fec_enet_private *fep = netdev_priv(dev); | |
e6b043d5 BW |
633 | struct phy_device *phy_dev = fep->phy_dev; |
634 | unsigned long flags; | |
1da177e4 | 635 | |
e6b043d5 | 636 | int status_change = 0; |
1da177e4 | 637 | |
e6b043d5 | 638 | spin_lock_irqsave(&fep->hw_lock, flags); |
1da177e4 | 639 | |
e6b043d5 BW |
640 | /* Prevent a state halted on mii error */ |
641 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
642 | phy_dev->state = PHY_RESUMING; | |
643 | goto spin_unlock; | |
644 | } | |
1da177e4 | 645 | |
e6b043d5 BW |
646 | /* Duplex link change */ |
647 | if (phy_dev->link) { | |
648 | if (fep->full_duplex != phy_dev->duplex) { | |
649 | fec_restart(dev, phy_dev->duplex); | |
650 | status_change = 1; | |
651 | } | |
652 | } | |
1da177e4 | 653 | |
e6b043d5 BW |
654 | /* Link on or off change */ |
655 | if (phy_dev->link != fep->link) { | |
656 | fep->link = phy_dev->link; | |
657 | if (phy_dev->link) | |
658 | fec_restart(dev, phy_dev->duplex); | |
1da177e4 | 659 | else |
e6b043d5 BW |
660 | fec_stop(dev); |
661 | status_change = 1; | |
1da177e4 | 662 | } |
6aa20a22 | 663 | |
e6b043d5 BW |
664 | spin_unlock: |
665 | spin_unlock_irqrestore(&fep->hw_lock, flags); | |
1da177e4 | 666 | |
e6b043d5 BW |
667 | if (status_change) |
668 | phy_print_status(phy_dev); | |
669 | } | |
1da177e4 | 670 | |
e6b043d5 | 671 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 672 | { |
e6b043d5 | 673 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 674 | unsigned long time_left; |
1da177e4 | 675 | |
e6b043d5 | 676 | fep->mii_timeout = 0; |
97b72e43 | 677 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
678 | |
679 | /* start a read op */ | |
680 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
681 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
682 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
683 | ||
684 | /* wait for end of transfer */ | |
97b72e43 BS |
685 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
686 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
687 | if (time_left == 0) { | |
688 | fep->mii_timeout = 1; | |
689 | printk(KERN_ERR "FEC: MDIO read timeout\n"); | |
690 | return -ETIMEDOUT; | |
1da177e4 | 691 | } |
1da177e4 | 692 | |
e6b043d5 BW |
693 | /* return value */ |
694 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 695 | } |
6aa20a22 | 696 | |
e6b043d5 BW |
697 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
698 | u16 value) | |
1da177e4 | 699 | { |
e6b043d5 | 700 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 701 | unsigned long time_left; |
1da177e4 | 702 | |
e6b043d5 | 703 | fep->mii_timeout = 0; |
97b72e43 | 704 | init_completion(&fep->mdio_done); |
1da177e4 | 705 | |
862f0982 SG |
706 | /* start a write op */ |
707 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
708 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
709 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
710 | fep->hwp + FEC_MII_DATA); | |
711 | ||
712 | /* wait for end of transfer */ | |
97b72e43 BS |
713 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
714 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
715 | if (time_left == 0) { | |
716 | fep->mii_timeout = 1; | |
717 | printk(KERN_ERR "FEC: MDIO write timeout\n"); | |
718 | return -ETIMEDOUT; | |
e6b043d5 | 719 | } |
1da177e4 | 720 | |
e6b043d5 BW |
721 | return 0; |
722 | } | |
1da177e4 | 723 | |
e6b043d5 | 724 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 725 | { |
e6b043d5 | 726 | return 0; |
1da177e4 LT |
727 | } |
728 | ||
e6b043d5 | 729 | static int fec_enet_mii_probe(struct net_device *dev) |
562d2f8c | 730 | { |
4cf1653a | 731 | struct fec_enet_private *fep = netdev_priv(dev); |
e6b043d5 | 732 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
733 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
734 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
735 | int phy_id; | |
b5680e0b | 736 | int dev_id = fep->pdev->id; |
562d2f8c | 737 | |
418bd0d4 BW |
738 | fep->phy_dev = NULL; |
739 | ||
6fcc040f GU |
740 | /* check for attached phy */ |
741 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
742 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
743 | continue; | |
744 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
745 | continue; | |
746 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
747 | continue; | |
b5680e0b SG |
748 | if (dev_id--) |
749 | continue; | |
6fcc040f GU |
750 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
751 | break; | |
e6b043d5 | 752 | } |
1da177e4 | 753 | |
6fcc040f GU |
754 | if (phy_id >= PHY_MAX_ADDR) { |
755 | printk(KERN_INFO "%s: no PHY, assuming direct connection " | |
756 | "to switch\n", dev->name); | |
757 | strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); | |
758 | phy_id = 0; | |
759 | } | |
760 | ||
761 | snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id); | |
762 | phy_dev = phy_connect(dev, phy_name, &fec_enet_adjust_link, 0, | |
763 | PHY_INTERFACE_MODE_MII); | |
764 | if (IS_ERR(phy_dev)) { | |
765 | printk(KERN_ERR "%s: could not attach to PHY\n", dev->name); | |
766 | return PTR_ERR(phy_dev); | |
e6b043d5 | 767 | } |
1da177e4 | 768 | |
e6b043d5 BW |
769 | /* mask with MAC supported features */ |
770 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
771 | phy_dev->advertising = phy_dev->supported; | |
1da177e4 | 772 | |
e6b043d5 BW |
773 | fep->phy_dev = phy_dev; |
774 | fep->link = 0; | |
775 | fep->full_duplex = 0; | |
1da177e4 | 776 | |
418bd0d4 BW |
777 | printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] " |
778 | "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name, | |
779 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), | |
780 | fep->phy_dev->irq); | |
781 | ||
e6b043d5 | 782 | return 0; |
1da177e4 LT |
783 | } |
784 | ||
e6b043d5 | 785 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 786 | { |
b5680e0b | 787 | static struct mii_bus *fec0_mii_bus; |
e6b043d5 | 788 | struct net_device *dev = platform_get_drvdata(pdev); |
562d2f8c | 789 | struct fec_enet_private *fep = netdev_priv(dev); |
b5680e0b SG |
790 | const struct platform_device_id *id_entry = |
791 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 792 | int err = -ENXIO, i; |
6b265293 | 793 | |
b5680e0b SG |
794 | /* |
795 | * The dual fec interfaces are not equivalent with enet-mac. | |
796 | * Here are the differences: | |
797 | * | |
798 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
799 | * - fec0 acts as the 1588 time master while fec1 is slave | |
800 | * - external phys can only be configured by fec0 | |
801 | * | |
802 | * That is to say fec1 can not work independently. It only works | |
803 | * when fec0 is working. The reason behind this design is that the | |
804 | * second interface is added primarily for Switch mode. | |
805 | * | |
806 | * Because of the last point above, both phys are attached on fec0 | |
807 | * mdio interface in board design, and need to be configured by | |
808 | * fec0 mii_bus. | |
809 | */ | |
810 | if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) { | |
811 | /* fec1 uses fec0 mii_bus */ | |
812 | fep->mii_bus = fec0_mii_bus; | |
813 | return 0; | |
814 | } | |
815 | ||
e6b043d5 | 816 | fep->mii_timeout = 0; |
1da177e4 | 817 | |
e6b043d5 BW |
818 | /* |
819 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
820 | */ | |
821 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1; | |
822 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
1da177e4 | 823 | |
e6b043d5 BW |
824 | fep->mii_bus = mdiobus_alloc(); |
825 | if (fep->mii_bus == NULL) { | |
826 | err = -ENOMEM; | |
827 | goto err_out; | |
1da177e4 LT |
828 | } |
829 | ||
e6b043d5 BW |
830 | fep->mii_bus->name = "fec_enet_mii_bus"; |
831 | fep->mii_bus->read = fec_enet_mdio_read; | |
832 | fep->mii_bus->write = fec_enet_mdio_write; | |
833 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
6fcc040f | 834 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id + 1); |
e6b043d5 BW |
835 | fep->mii_bus->priv = fep; |
836 | fep->mii_bus->parent = &pdev->dev; | |
837 | ||
838 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
839 | if (!fep->mii_bus->irq) { | |
840 | err = -ENOMEM; | |
841 | goto err_out_free_mdiobus; | |
1da177e4 LT |
842 | } |
843 | ||
e6b043d5 BW |
844 | for (i = 0; i < PHY_MAX_ADDR; i++) |
845 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 846 | |
e6b043d5 | 847 | platform_set_drvdata(dev, fep->mii_bus); |
1da177e4 | 848 | |
e6b043d5 BW |
849 | if (mdiobus_register(fep->mii_bus)) |
850 | goto err_out_free_mdio_irq; | |
1da177e4 | 851 | |
b5680e0b SG |
852 | /* save fec0 mii_bus */ |
853 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
854 | fec0_mii_bus = fep->mii_bus; | |
855 | ||
e6b043d5 | 856 | return 0; |
1da177e4 | 857 | |
e6b043d5 BW |
858 | err_out_free_mdio_irq: |
859 | kfree(fep->mii_bus->irq); | |
860 | err_out_free_mdiobus: | |
861 | mdiobus_free(fep->mii_bus); | |
862 | err_out: | |
863 | return err; | |
1da177e4 LT |
864 | } |
865 | ||
e6b043d5 | 866 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 867 | { |
e6b043d5 BW |
868 | if (fep->phy_dev) |
869 | phy_disconnect(fep->phy_dev); | |
870 | mdiobus_unregister(fep->mii_bus); | |
871 | kfree(fep->mii_bus->irq); | |
872 | mdiobus_free(fep->mii_bus); | |
1da177e4 LT |
873 | } |
874 | ||
e6b043d5 BW |
875 | static int fec_enet_get_settings(struct net_device *dev, |
876 | struct ethtool_cmd *cmd) | |
1da177e4 LT |
877 | { |
878 | struct fec_enet_private *fep = netdev_priv(dev); | |
e6b043d5 | 879 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 880 | |
e6b043d5 BW |
881 | if (!phydev) |
882 | return -ENODEV; | |
1da177e4 | 883 | |
e6b043d5 | 884 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
885 | } |
886 | ||
e6b043d5 BW |
887 | static int fec_enet_set_settings(struct net_device *dev, |
888 | struct ethtool_cmd *cmd) | |
1da177e4 LT |
889 | { |
890 | struct fec_enet_private *fep = netdev_priv(dev); | |
e6b043d5 | 891 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 892 | |
e6b043d5 BW |
893 | if (!phydev) |
894 | return -ENODEV; | |
1da177e4 | 895 | |
e6b043d5 | 896 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
897 | } |
898 | ||
e6b043d5 BW |
899 | static void fec_enet_get_drvinfo(struct net_device *dev, |
900 | struct ethtool_drvinfo *info) | |
1da177e4 | 901 | { |
e6b043d5 | 902 | struct fec_enet_private *fep = netdev_priv(dev); |
6aa20a22 | 903 | |
e6b043d5 BW |
904 | strcpy(info->driver, fep->pdev->dev.driver->name); |
905 | strcpy(info->version, "Revision: 1.0"); | |
906 | strcpy(info->bus_info, dev_name(&dev->dev)); | |
1da177e4 LT |
907 | } |
908 | ||
e6b043d5 BW |
909 | static struct ethtool_ops fec_enet_ethtool_ops = { |
910 | .get_settings = fec_enet_get_settings, | |
911 | .set_settings = fec_enet_set_settings, | |
912 | .get_drvinfo = fec_enet_get_drvinfo, | |
913 | .get_link = ethtool_op_get_link, | |
914 | }; | |
1da177e4 | 915 | |
e6b043d5 | 916 | static int fec_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
1da177e4 | 917 | { |
1da177e4 | 918 | struct fec_enet_private *fep = netdev_priv(dev); |
e6b043d5 | 919 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 920 | |
e6b043d5 BW |
921 | if (!netif_running(dev)) |
922 | return -EINVAL; | |
1da177e4 | 923 | |
e6b043d5 BW |
924 | if (!phydev) |
925 | return -ENODEV; | |
926 | ||
28b04113 | 927 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
928 | } |
929 | ||
f0b3fbea SH |
930 | static void fec_enet_free_buffers(struct net_device *dev) |
931 | { | |
932 | struct fec_enet_private *fep = netdev_priv(dev); | |
933 | int i; | |
934 | struct sk_buff *skb; | |
935 | struct bufdesc *bdp; | |
936 | ||
937 | bdp = fep->rx_bd_base; | |
938 | for (i = 0; i < RX_RING_SIZE; i++) { | |
939 | skb = fep->rx_skbuff[i]; | |
940 | ||
941 | if (bdp->cbd_bufaddr) | |
942 | dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, | |
943 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); | |
944 | if (skb) | |
945 | dev_kfree_skb(skb); | |
946 | bdp++; | |
947 | } | |
948 | ||
949 | bdp = fep->tx_bd_base; | |
950 | for (i = 0; i < TX_RING_SIZE; i++) | |
951 | kfree(fep->tx_bounce[i]); | |
952 | } | |
953 | ||
954 | static int fec_enet_alloc_buffers(struct net_device *dev) | |
955 | { | |
956 | struct fec_enet_private *fep = netdev_priv(dev); | |
957 | int i; | |
958 | struct sk_buff *skb; | |
959 | struct bufdesc *bdp; | |
960 | ||
961 | bdp = fep->rx_bd_base; | |
962 | for (i = 0; i < RX_RING_SIZE; i++) { | |
963 | skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE); | |
964 | if (!skb) { | |
965 | fec_enet_free_buffers(dev); | |
966 | return -ENOMEM; | |
967 | } | |
968 | fep->rx_skbuff[i] = skb; | |
969 | ||
970 | bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data, | |
971 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); | |
972 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
973 | bdp++; | |
974 | } | |
975 | ||
976 | /* Set the last buffer to wrap. */ | |
977 | bdp--; | |
978 | bdp->cbd_sc |= BD_SC_WRAP; | |
979 | ||
980 | bdp = fep->tx_bd_base; | |
981 | for (i = 0; i < TX_RING_SIZE; i++) { | |
982 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
983 | ||
984 | bdp->cbd_sc = 0; | |
985 | bdp->cbd_bufaddr = 0; | |
986 | bdp++; | |
987 | } | |
988 | ||
989 | /* Set the last buffer to wrap. */ | |
990 | bdp--; | |
991 | bdp->cbd_sc |= BD_SC_WRAP; | |
992 | ||
993 | return 0; | |
994 | } | |
995 | ||
1da177e4 LT |
996 | static int |
997 | fec_enet_open(struct net_device *dev) | |
998 | { | |
999 | struct fec_enet_private *fep = netdev_priv(dev); | |
f0b3fbea | 1000 | int ret; |
1da177e4 LT |
1001 | |
1002 | /* I should reset the ring buffers here, but I don't yet know | |
1003 | * a simple way to do that. | |
1004 | */ | |
1da177e4 | 1005 | |
f0b3fbea SH |
1006 | ret = fec_enet_alloc_buffers(dev); |
1007 | if (ret) | |
1008 | return ret; | |
1009 | ||
418bd0d4 BW |
1010 | /* Probe and connect to PHY when open the interface */ |
1011 | ret = fec_enet_mii_probe(dev); | |
1012 | if (ret) { | |
1013 | fec_enet_free_buffers(dev); | |
1014 | return ret; | |
1015 | } | |
e6b043d5 | 1016 | phy_start(fep->phy_dev); |
1da177e4 LT |
1017 | netif_start_queue(dev); |
1018 | fep->opened = 1; | |
22f6b860 | 1019 | return 0; |
1da177e4 LT |
1020 | } |
1021 | ||
1022 | static int | |
1023 | fec_enet_close(struct net_device *dev) | |
1024 | { | |
1025 | struct fec_enet_private *fep = netdev_priv(dev); | |
1026 | ||
22f6b860 | 1027 | /* Don't know what to do yet. */ |
1da177e4 LT |
1028 | fep->opened = 0; |
1029 | netif_stop_queue(dev); | |
1030 | fec_stop(dev); | |
1031 | ||
418bd0d4 BW |
1032 | if (fep->phy_dev) |
1033 | phy_disconnect(fep->phy_dev); | |
1034 | ||
f0b3fbea SH |
1035 | fec_enet_free_buffers(dev); |
1036 | ||
1da177e4 LT |
1037 | return 0; |
1038 | } | |
1039 | ||
1da177e4 LT |
1040 | /* Set or clear the multicast filter for this adaptor. |
1041 | * Skeleton taken from sunlance driver. | |
1042 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1043 | * MAC address filtering. Some of the drivers check to make sure it is | |
1044 | * a group multicast address, and discard those that are not. I guess I | |
1045 | * will do the same for now, but just remove the test if you want | |
1046 | * individual filtering as well (do the upper net layers want or support | |
1047 | * this kind of feature?). | |
1048 | */ | |
1049 | ||
1050 | #define HASH_BITS 6 /* #bits in hash */ | |
1051 | #define CRC32_POLY 0xEDB88320 | |
1052 | ||
1053 | static void set_multicast_list(struct net_device *dev) | |
1054 | { | |
f44d6305 | 1055 | struct fec_enet_private *fep = netdev_priv(dev); |
22bedad3 | 1056 | struct netdev_hw_addr *ha; |
48e2f183 | 1057 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
1058 | unsigned char hash; |
1059 | ||
22f6b860 | 1060 | if (dev->flags & IFF_PROMISC) { |
f44d6305 SH |
1061 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1062 | tmp |= 0x8; | |
1063 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1064 | return; |
1065 | } | |
1da177e4 | 1066 | |
4e831836 SH |
1067 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1068 | tmp &= ~0x8; | |
1069 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1070 | ||
1071 | if (dev->flags & IFF_ALLMULTI) { | |
1072 | /* Catch all multicast addresses, so set the | |
1073 | * filter to all 1's | |
1074 | */ | |
1075 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1076 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1077 | ||
1078 | return; | |
1079 | } | |
1080 | ||
1081 | /* Clear filter and add the addresses in hash register | |
1082 | */ | |
1083 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1084 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1085 | ||
22bedad3 | 1086 | netdev_for_each_mc_addr(ha, dev) { |
4e831836 | 1087 | /* Only support group multicast for now */ |
22bedad3 | 1088 | if (!(ha->addr[0] & 1)) |
4e831836 SH |
1089 | continue; |
1090 | ||
1091 | /* calculate crc32 value of mac address */ | |
1092 | crc = 0xffffffff; | |
1093 | ||
22bedad3 JP |
1094 | for (i = 0; i < dev->addr_len; i++) { |
1095 | data = ha->addr[i]; | |
4e831836 SH |
1096 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1097 | crc = (crc >> 1) ^ | |
1098 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1099 | } |
1100 | } | |
4e831836 SH |
1101 | |
1102 | /* only upper 6 bits (HASH_BITS) are used | |
1103 | * which point to specific bit in he hash registers | |
1104 | */ | |
1105 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1106 | ||
1107 | if (hash > 31) { | |
1108 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1109 | tmp |= 1 << (hash - 32); | |
1110 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1111 | } else { | |
1112 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1113 | tmp |= 1 << hash; | |
1114 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1115 | } | |
1da177e4 LT |
1116 | } |
1117 | } | |
1118 | ||
22f6b860 | 1119 | /* Set a MAC change in hardware. */ |
009fda83 SH |
1120 | static int |
1121 | fec_set_mac_address(struct net_device *dev, void *p) | |
1da177e4 | 1122 | { |
f44d6305 | 1123 | struct fec_enet_private *fep = netdev_priv(dev); |
009fda83 SH |
1124 | struct sockaddr *addr = p; |
1125 | ||
1126 | if (!is_valid_ether_addr(addr->sa_data)) | |
1127 | return -EADDRNOTAVAIL; | |
1128 | ||
1129 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
1da177e4 | 1130 | |
f44d6305 SH |
1131 | writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) | |
1132 | (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24), | |
1133 | fep->hwp + FEC_ADDR_LOW); | |
1134 | writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24), | |
7cff0943 | 1135 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1136 | return 0; |
1da177e4 LT |
1137 | } |
1138 | ||
009fda83 SH |
1139 | static const struct net_device_ops fec_netdev_ops = { |
1140 | .ndo_open = fec_enet_open, | |
1141 | .ndo_stop = fec_enet_close, | |
1142 | .ndo_start_xmit = fec_enet_start_xmit, | |
1143 | .ndo_set_multicast_list = set_multicast_list, | |
635ecaa7 | 1144 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1145 | .ndo_validate_addr = eth_validate_addr, |
1146 | .ndo_tx_timeout = fec_timeout, | |
1147 | .ndo_set_mac_address = fec_set_mac_address, | |
e6b043d5 | 1148 | .ndo_do_ioctl = fec_enet_ioctl, |
009fda83 SH |
1149 | }; |
1150 | ||
1da177e4 LT |
1151 | /* |
1152 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 1153 | * |
1da177e4 | 1154 | */ |
8649a230 | 1155 | static int fec_enet_init(struct net_device *dev) |
1da177e4 LT |
1156 | { |
1157 | struct fec_enet_private *fep = netdev_priv(dev); | |
f0b3fbea | 1158 | struct bufdesc *cbd_base; |
633e7533 | 1159 | struct bufdesc *bdp; |
f0b3fbea | 1160 | int i; |
1da177e4 | 1161 | |
8d4dd5cf SH |
1162 | /* Allocate memory for buffer descriptors. */ |
1163 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
1164 | GFP_KERNEL); | |
1165 | if (!cbd_base) { | |
562d2f8c GU |
1166 | printk("FEC: allocate descriptor memory failed?\n"); |
1167 | return -ENOMEM; | |
1168 | } | |
1169 | ||
3b2b74ca | 1170 | spin_lock_init(&fep->hw_lock); |
3b2b74ca | 1171 | |
cb84d6e7 | 1172 | fep->netdev = dev; |
1da177e4 | 1173 | |
49da97dc | 1174 | /* Get the Ethernet address */ |
1da177e4 LT |
1175 | fec_get_mac(dev); |
1176 | ||
8d4dd5cf | 1177 | /* Set receive and transmit descriptor base. */ |
1da177e4 LT |
1178 | fep->rx_bd_base = cbd_base; |
1179 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1180 | ||
22f6b860 | 1181 | /* The FEC Ethernet specific entries in the device structure */ |
1da177e4 | 1182 | dev->watchdog_timeo = TX_TIMEOUT; |
009fda83 | 1183 | dev->netdev_ops = &fec_netdev_ops; |
e6b043d5 | 1184 | dev->ethtool_ops = &fec_enet_ethtool_ops; |
633e7533 RH |
1185 | |
1186 | /* Initialize the receive buffer descriptors. */ | |
1187 | bdp = fep->rx_bd_base; | |
1188 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1189 | ||
1190 | /* Initialize the BD for every fragment in the page. */ | |
1191 | bdp->cbd_sc = 0; | |
1192 | bdp++; | |
1193 | } | |
1194 | ||
1195 | /* Set the last buffer to wrap */ | |
1196 | bdp--; | |
1197 | bdp->cbd_sc |= BD_SC_WRAP; | |
1198 | ||
1199 | /* ...and the same for transmit */ | |
1200 | bdp = fep->tx_bd_base; | |
1201 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1202 | ||
1203 | /* Initialize the BD for every fragment in the page. */ | |
1204 | bdp->cbd_sc = 0; | |
1205 | bdp->cbd_bufaddr = 0; | |
1206 | bdp++; | |
1207 | } | |
1208 | ||
1209 | /* Set the last buffer to wrap */ | |
1210 | bdp--; | |
1211 | bdp->cbd_sc |= BD_SC_WRAP; | |
1212 | ||
ead73183 | 1213 | fec_restart(dev, 0); |
1da177e4 | 1214 | |
1da177e4 LT |
1215 | return 0; |
1216 | } | |
1217 | ||
1218 | /* This function is called to start or restart the FEC during a link | |
1219 | * change. This only happens when switching between half and full | |
1220 | * duplex. | |
1221 | */ | |
1222 | static void | |
1223 | fec_restart(struct net_device *dev, int duplex) | |
1224 | { | |
f44d6305 | 1225 | struct fec_enet_private *fep = netdev_priv(dev); |
b5680e0b SG |
1226 | const struct platform_device_id *id_entry = |
1227 | platform_get_device_id(fep->pdev); | |
1da177e4 | 1228 | int i; |
b5680e0b | 1229 | u32 val, temp_mac[2]; |
1da177e4 | 1230 | |
f44d6305 SH |
1231 | /* Whack a reset. We should wait for this. */ |
1232 | writel(1, fep->hwp + FEC_ECNTRL); | |
1da177e4 LT |
1233 | udelay(10); |
1234 | ||
b5680e0b SG |
1235 | /* |
1236 | * enet-mac reset will reset mac address registers too, | |
1237 | * so need to reconfigure it. | |
1238 | */ | |
1239 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
1240 | memcpy(&temp_mac, dev->dev_addr, ETH_ALEN); | |
1241 | writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); | |
1242 | writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); | |
1243 | } | |
1244 | ||
f44d6305 SH |
1245 | /* Clear any outstanding interrupt. */ |
1246 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 1247 | |
f44d6305 SH |
1248 | /* Reset all multicast. */ |
1249 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1250 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
4f1ceb4b SH |
1251 | #ifndef CONFIG_M5272 |
1252 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
1253 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
1254 | #endif | |
1da177e4 | 1255 | |
f44d6305 SH |
1256 | /* Set maximum receive buffer size. */ |
1257 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 1258 | |
f44d6305 SH |
1259 | /* Set receive and transmit descriptor base. */ |
1260 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
2e28532f | 1261 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, |
f44d6305 | 1262 | fep->hwp + FEC_X_DES_START); |
1da177e4 LT |
1263 | |
1264 | fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; | |
1265 | fep->cur_rx = fep->rx_bd_base; | |
1266 | ||
f44d6305 | 1267 | /* Reset SKB transmit buffers. */ |
1da177e4 | 1268 | fep->skb_cur = fep->skb_dirty = 0; |
22f6b860 SH |
1269 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { |
1270 | if (fep->tx_skbuff[i]) { | |
1da177e4 LT |
1271 | dev_kfree_skb_any(fep->tx_skbuff[i]); |
1272 | fep->tx_skbuff[i] = NULL; | |
1273 | } | |
1274 | } | |
1275 | ||
22f6b860 | 1276 | /* Enable MII mode */ |
1da177e4 | 1277 | if (duplex) { |
f44d6305 SH |
1278 | /* MII enable / FD enable */ |
1279 | writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL); | |
1280 | writel(0x04, fep->hwp + FEC_X_CNTRL); | |
f909b1ef | 1281 | } else { |
f44d6305 SH |
1282 | /* MII enable / No Rcv on Xmit */ |
1283 | writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL); | |
1284 | writel(0x0, fep->hwp + FEC_X_CNTRL); | |
1da177e4 LT |
1285 | } |
1286 | fep->full_duplex = duplex; | |
1287 | ||
22f6b860 | 1288 | /* Set MII speed */ |
f44d6305 | 1289 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1290 | |
b5680e0b SG |
1291 | /* |
1292 | * The phy interface and speed need to get configured | |
1293 | * differently on enet-mac. | |
1294 | */ | |
1295 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
1296 | val = readl(fep->hwp + FEC_R_CNTRL); | |
5eb32bd0 | 1297 | |
b5680e0b SG |
1298 | /* MII or RMII */ |
1299 | if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
1300 | val |= (1 << 8); | |
1301 | else | |
1302 | val &= ~(1 << 8); | |
5eb32bd0 | 1303 | |
b5680e0b SG |
1304 | /* 10M or 100M */ |
1305 | if (fep->phy_dev && fep->phy_dev->speed == SPEED_100) | |
1306 | val &= ~(1 << 9); | |
1307 | else | |
1308 | val |= (1 << 9); | |
1309 | ||
1310 | writel(val, fep->hwp + FEC_R_CNTRL); | |
1311 | } else { | |
1312 | #ifdef FEC_MIIGSK_ENR | |
1313 | if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) { | |
1314 | /* disable the gasket and wait */ | |
1315 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
1316 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
1317 | udelay(1); | |
1318 | ||
1319 | /* | |
1320 | * configure the gasket: | |
1321 | * RMII, 50 MHz, no loopback, no echo | |
1322 | */ | |
1323 | writel(1, fep->hwp + FEC_MIIGSK_CFGR); | |
1324 | ||
1325 | /* re-enable the gasket */ | |
1326 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
1327 | } | |
5eb32bd0 | 1328 | #endif |
b5680e0b | 1329 | } |
5eb32bd0 | 1330 | |
22f6b860 | 1331 | /* And last, enable the transmit and receive processing */ |
f44d6305 SH |
1332 | writel(2, fep->hwp + FEC_ECNTRL); |
1333 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
6b265293 | 1334 | |
22f6b860 | 1335 | /* Enable interrupts we wish to service */ |
4bee1f9a | 1336 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); |
1da177e4 LT |
1337 | } |
1338 | ||
1339 | static void | |
1340 | fec_stop(struct net_device *dev) | |
1341 | { | |
f44d6305 | 1342 | struct fec_enet_private *fep = netdev_priv(dev); |
1da177e4 | 1343 | |
22f6b860 | 1344 | /* We cannot expect a graceful transmit stop without link !!! */ |
f44d6305 SH |
1345 | if (fep->link) { |
1346 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
677177c5 | 1347 | udelay(10); |
f44d6305 | 1348 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) |
677177c5 | 1349 | printk("fec_stop : Graceful transmit stop did not complete !\n"); |
f44d6305 | 1350 | } |
1da177e4 | 1351 | |
f44d6305 SH |
1352 | /* Whack a reset. We should wait for this. */ |
1353 | writel(1, fep->hwp + FEC_ECNTRL); | |
1da177e4 | 1354 | udelay(10); |
f44d6305 | 1355 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
4bee1f9a | 1356 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); |
1da177e4 LT |
1357 | } |
1358 | ||
ead73183 SH |
1359 | static int __devinit |
1360 | fec_probe(struct platform_device *pdev) | |
1361 | { | |
1362 | struct fec_enet_private *fep; | |
5eb32bd0 | 1363 | struct fec_platform_data *pdata; |
ead73183 SH |
1364 | struct net_device *ndev; |
1365 | int i, irq, ret = 0; | |
1366 | struct resource *r; | |
1367 | ||
1368 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1369 | if (!r) | |
1370 | return -ENXIO; | |
1371 | ||
1372 | r = request_mem_region(r->start, resource_size(r), pdev->name); | |
1373 | if (!r) | |
1374 | return -EBUSY; | |
1375 | ||
1376 | /* Init network device */ | |
1377 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
28e2188e UKK |
1378 | if (!ndev) { |
1379 | ret = -ENOMEM; | |
1380 | goto failed_alloc_etherdev; | |
1381 | } | |
ead73183 SH |
1382 | |
1383 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1384 | ||
1385 | /* setup board info structure */ | |
1386 | fep = netdev_priv(ndev); | |
ead73183 | 1387 | |
24e531b4 | 1388 | fep->hwp = ioremap(r->start, resource_size(r)); |
e6b043d5 | 1389 | fep->pdev = pdev; |
ead73183 | 1390 | |
24e531b4 | 1391 | if (!fep->hwp) { |
ead73183 SH |
1392 | ret = -ENOMEM; |
1393 | goto failed_ioremap; | |
1394 | } | |
1395 | ||
1396 | platform_set_drvdata(pdev, ndev); | |
1397 | ||
5eb32bd0 BS |
1398 | pdata = pdev->dev.platform_data; |
1399 | if (pdata) | |
1400 | fep->phy_interface = pdata->phy; | |
1401 | ||
ead73183 SH |
1402 | /* This device has up to three irqs on some platforms */ |
1403 | for (i = 0; i < 3; i++) { | |
1404 | irq = platform_get_irq(pdev, i); | |
1405 | if (i && irq < 0) | |
1406 | break; | |
1407 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); | |
1408 | if (ret) { | |
b2b09ad6 | 1409 | while (--i >= 0) { |
ead73183 SH |
1410 | irq = platform_get_irq(pdev, i); |
1411 | free_irq(irq, ndev); | |
ead73183 SH |
1412 | } |
1413 | goto failed_irq; | |
1414 | } | |
1415 | } | |
1416 | ||
1417 | fep->clk = clk_get(&pdev->dev, "fec_clk"); | |
1418 | if (IS_ERR(fep->clk)) { | |
1419 | ret = PTR_ERR(fep->clk); | |
1420 | goto failed_clk; | |
1421 | } | |
1422 | clk_enable(fep->clk); | |
1423 | ||
8649a230 | 1424 | ret = fec_enet_init(ndev); |
ead73183 SH |
1425 | if (ret) |
1426 | goto failed_init; | |
1427 | ||
e6b043d5 BW |
1428 | ret = fec_enet_mii_init(pdev); |
1429 | if (ret) | |
1430 | goto failed_mii_init; | |
1431 | ||
03c698c9 OS |
1432 | /* Carrier starts down, phylib will bring it up */ |
1433 | netif_carrier_off(ndev); | |
1434 | ||
ead73183 SH |
1435 | ret = register_netdev(ndev); |
1436 | if (ret) | |
1437 | goto failed_register; | |
1438 | ||
1439 | return 0; | |
1440 | ||
1441 | failed_register: | |
e6b043d5 BW |
1442 | fec_enet_mii_remove(fep); |
1443 | failed_mii_init: | |
ead73183 SH |
1444 | failed_init: |
1445 | clk_disable(fep->clk); | |
1446 | clk_put(fep->clk); | |
1447 | failed_clk: | |
1448 | for (i = 0; i < 3; i++) { | |
1449 | irq = platform_get_irq(pdev, i); | |
1450 | if (irq > 0) | |
1451 | free_irq(irq, ndev); | |
1452 | } | |
1453 | failed_irq: | |
24e531b4 | 1454 | iounmap(fep->hwp); |
ead73183 SH |
1455 | failed_ioremap: |
1456 | free_netdev(ndev); | |
28e2188e UKK |
1457 | failed_alloc_etherdev: |
1458 | release_mem_region(r->start, resource_size(r)); | |
ead73183 SH |
1459 | |
1460 | return ret; | |
1461 | } | |
1462 | ||
1463 | static int __devexit | |
1464 | fec_drv_remove(struct platform_device *pdev) | |
1465 | { | |
1466 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1467 | struct fec_enet_private *fep = netdev_priv(ndev); | |
28e2188e | 1468 | struct resource *r; |
ead73183 SH |
1469 | |
1470 | platform_set_drvdata(pdev, NULL); | |
1471 | ||
1472 | fec_stop(ndev); | |
e6b043d5 | 1473 | fec_enet_mii_remove(fep); |
ead73183 SH |
1474 | clk_disable(fep->clk); |
1475 | clk_put(fep->clk); | |
24e531b4 | 1476 | iounmap(fep->hwp); |
ead73183 SH |
1477 | unregister_netdev(ndev); |
1478 | free_netdev(ndev); | |
28e2188e UKK |
1479 | |
1480 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1481 | BUG_ON(!r); | |
1482 | release_mem_region(r->start, resource_size(r)); | |
1483 | ||
ead73183 SH |
1484 | return 0; |
1485 | } | |
1486 | ||
59d4289b | 1487 | #ifdef CONFIG_PM |
ead73183 | 1488 | static int |
87cad5c3 | 1489 | fec_suspend(struct device *dev) |
ead73183 | 1490 | { |
87cad5c3 | 1491 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1492 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1493 | |
04e5216d UKK |
1494 | if (netif_running(ndev)) { |
1495 | fec_stop(ndev); | |
1496 | netif_device_detach(ndev); | |
ead73183 | 1497 | } |
04e5216d UKK |
1498 | clk_disable(fep->clk); |
1499 | ||
ead73183 SH |
1500 | return 0; |
1501 | } | |
1502 | ||
1503 | static int | |
87cad5c3 | 1504 | fec_resume(struct device *dev) |
ead73183 | 1505 | { |
87cad5c3 | 1506 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 1507 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 1508 | |
04e5216d UKK |
1509 | clk_enable(fep->clk); |
1510 | if (netif_running(ndev)) { | |
1511 | fec_restart(ndev, fep->full_duplex); | |
1512 | netif_device_attach(ndev); | |
ead73183 | 1513 | } |
04e5216d | 1514 | |
ead73183 SH |
1515 | return 0; |
1516 | } | |
1517 | ||
59d4289b DK |
1518 | static const struct dev_pm_ops fec_pm_ops = { |
1519 | .suspend = fec_suspend, | |
1520 | .resume = fec_resume, | |
1521 | .freeze = fec_suspend, | |
1522 | .thaw = fec_resume, | |
1523 | .poweroff = fec_suspend, | |
1524 | .restore = fec_resume, | |
1525 | }; | |
87cad5c3 | 1526 | #endif |
59d4289b | 1527 | |
ead73183 SH |
1528 | static struct platform_driver fec_driver = { |
1529 | .driver = { | |
b5680e0b | 1530 | .name = DRIVER_NAME, |
87cad5c3 EB |
1531 | .owner = THIS_MODULE, |
1532 | #ifdef CONFIG_PM | |
1533 | .pm = &fec_pm_ops, | |
1534 | #endif | |
ead73183 | 1535 | }, |
b5680e0b | 1536 | .id_table = fec_devtype, |
87cad5c3 EB |
1537 | .probe = fec_probe, |
1538 | .remove = __devexit_p(fec_drv_remove), | |
ead73183 SH |
1539 | }; |
1540 | ||
1541 | static int __init | |
1542 | fec_enet_module_init(void) | |
1543 | { | |
1544 | printk(KERN_INFO "FEC Ethernet Driver\n"); | |
1545 | ||
1546 | return platform_driver_register(&fec_driver); | |
1547 | } | |
1548 | ||
1549 | static void __exit | |
1550 | fec_enet_cleanup(void) | |
1551 | { | |
1552 | platform_driver_unregister(&fec_driver); | |
1553 | } | |
1554 | ||
1555 | module_exit(fec_enet_cleanup); | |
1da177e4 LT |
1556 | module_init(fec_enet_module_init); |
1557 | ||
1558 | MODULE_LICENSE("GPL"); |