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natsemi: update to net_device_ops
[linux-2.6-block.git] / drivers / net / fealnx.c
CommitLineData
1da177e4
LT		 1/*
2 Written 1998-2000 by Donald Becker.
3
4 This software may be used and distributed according to the terms of
5 the GNU General Public License (GPL), incorporated herein by reference.
6 Drivers based on or derived from this code fall under the GPL and must
7 retain the authorship, copyright and license notice. This file is not
8 a complete program and may only be used when the entire operating
9 system is licensed under the GPL.
10
11 The author may be reached as becker@scyld.com, or C/O
12 Scyld Computing Corporation
13 410 Severn Ave., Suite 210
14 Annapolis MD 21403
15
16 Support information and updates available at
17 http://www.scyld.com/network/pci-skeleton.html
18
19 Linux kernel updates:
20
21 Version 2.51, Nov 17, 2001 (jgarzik):
22 - Add ethtool support
23 - Replace some MII-related magic numbers with constants
24
25*/
26
27#define DRV_NAME "fealnx"
d5b20697
AG		 28#define DRV_VERSION "2.52"
29#define DRV_RELDATE "Sep-11-2006"
1da177e4
LT		 30
31static int debug; /* 1-> print debug message */
32static int max_interrupt_work = 20;
33
34/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
35static int multicast_filter_limit = 32;
36
37/* Set the copy breakpoint for the copy-only-tiny-frames scheme. */
38/* Setting to > 1518 effectively disables this feature. */
39static int rx_copybreak;
40
41/* Used to pass the media type, etc. */
42/* Both 'options[]' and 'full_duplex[]' should exist for driver */
43/* interoperability. */
44/* The media type is usually passed in 'options[]'. */
45#define MAX_UNITS 8 /* More are supported, limit only on options */
46static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
47static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
48
49/* Operational parameters that are set at compile time. */
50/* Keep the ring sizes a power of two for compile efficiency. */
51/* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */
52/* Making the Tx ring too large decreases the effectiveness of channel */
53/* bonding and packet priority. */
54/* There are no ill effects from too-large receive rings. */
55// 88-12-9 modify,
56// #define TX_RING_SIZE 16
57// #define RX_RING_SIZE 32
58#define TX_RING_SIZE 6
59#define RX_RING_SIZE 12
60#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc)
61#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc)
62
63/* Operational parameters that usually are not changed. */
64/* Time in jiffies before concluding the transmitter is hung. */
65#define TX_TIMEOUT (2*HZ)
66
67#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
68
69
70/* Include files, designed to support most kernel versions 2.0.0 and later. */
71#include <linux/module.h>
72#include <linux/kernel.h>
73#include <linux/string.h>
74#include <linux/timer.h>
75#include <linux/errno.h>
76#include <linux/ioport.h>
77#include <linux/slab.h>
78#include <linux/interrupt.h>
79#include <linux/pci.h>
80#include <linux/netdevice.h>
81#include <linux/etherdevice.h>
82#include <linux/skbuff.h>
83#include <linux/init.h>
84#include <linux/mii.h>
85#include <linux/ethtool.h>
86#include <linux/crc32.h>
87#include <linux/delay.h>
88#include <linux/bitops.h>
89
90#include <asm/processor.h> /* Processor type for cache alignment. */
91#include <asm/io.h>
92#include <asm/uaccess.h>
28cd4289 93#include <asm/byteorder.h>
1da177e4
LT		 94
95/* These identify the driver base version and may not be removed. */
90d5aed2 96static char version[] =
1da177e4
LT		 97KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
98
99
100/* This driver was written to use PCI memory space, however some x86 systems
101 work only with I/O space accesses. */
102#ifndef __alpha__
103#define USE_IO_OPS
104#endif
105
106/* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
107/* This is only in the support-all-kernels source code. */
108
109#define RUN_AT(x) (jiffies + (x))
110
111MODULE_AUTHOR("Myson or whoever");
112MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver");
113MODULE_LICENSE("GPL");
114module_param(max_interrupt_work, int, 0);
1da177e4
LT		 115module_param(debug, int, 0);
116module_param(rx_copybreak, int, 0);
117module_param(multicast_filter_limit, int, 0);
118module_param_array(options, int, NULL, 0);
119module_param_array(full_duplex, int, NULL, 0);
120MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt");
121MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)");
122MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames");
123MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses");
124MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
125MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
126
46009c8b
JG		 127enum {
128 MIN_REGION_SIZE = 136,
129};
1da177e4 130
1da177e4
LT		 131/* A chip capabilities table, matching the entries in pci_tbl[] above. */
132enum chip_capability_flags {
133 HAS_MII_XCVR,
134 HAS_CHIP_XCVR,
135};
136
137/* 89/6/13 add, */
138/* for different PHY */
139enum phy_type_flags {
140 MysonPHY = 1,
141 AhdocPHY = 2,
142 SeeqPHY = 3,
143 MarvellPHY = 4,
144 Myson981 = 5,
145 LevelOnePHY = 6,
146 OtherPHY = 10,
147};
148
149struct chip_info {
150 char *chip_name;
1da177e4
LT		 151 int flags;
152};
153
46009c8b 154static const struct chip_info skel_netdrv_tbl[] __devinitdata = {
c3d8e682
JG		 155 { "100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
156 { "100/10M Ethernet PCI Adapter", HAS_CHIP_XCVR },
157 { "1000/100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
1da177e4
LT		 158};
159
160/* Offsets to the Command and Status Registers. */
161enum fealnx_offsets {
162 PAR0 = 0x0, /* physical address 0-3 */
163 PAR1 = 0x04, /* physical address 4-5 */
164 MAR0 = 0x08, /* multicast address 0-3 */
165 MAR1 = 0x0C, /* multicast address 4-7 */
166 FAR0 = 0x10, /* flow-control address 0-3 */
167 FAR1 = 0x14, /* flow-control address 4-5 */
168 TCRRCR = 0x18, /* receive & transmit configuration */
169 BCR = 0x1C, /* bus command */
170 TXPDR = 0x20, /* transmit polling demand */
171 RXPDR = 0x24, /* receive polling demand */
172 RXCWP = 0x28, /* receive current word pointer */
173 TXLBA = 0x2C, /* transmit list base address */
174 RXLBA = 0x30, /* receive list base address */
175 ISR = 0x34, /* interrupt status */
176 IMR = 0x38, /* interrupt mask */
177 FTH = 0x3C, /* flow control high/low threshold */
178 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */
179 TALLY = 0x44, /* tally counters for crc and mpa */
180 TSR = 0x48, /* tally counter for transmit status */
181 BMCRSR = 0x4c, /* basic mode control and status */
182 PHYIDENTIFIER = 0x50, /* phy identifier */
183 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link
184 partner ability */
185 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */
186 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */
187};
188
189/* Bits in the interrupt status/enable registers. */
190/* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
191enum intr_status_bits {
192 RFCON = 0x00020000, /* receive flow control xon packet */
193 RFCOFF = 0x00010000, /* receive flow control xoff packet */
194 LSCStatus = 0x00008000, /* link status change */
195 ANCStatus = 0x00004000, /* autonegotiation completed */
196 FBE = 0x00002000, /* fatal bus error */
197 FBEMask = 0x00001800, /* mask bit12-11 */
198 ParityErr = 0x00000000, /* parity error */
199 TargetErr = 0x00001000, /* target abort */
200 MasterErr = 0x00000800, /* master error */
201 TUNF = 0x00000400, /* transmit underflow */
202 ROVF = 0x00000200, /* receive overflow */
203 ETI = 0x00000100, /* transmit early int */
204 ERI = 0x00000080, /* receive early int */
205 CNTOVF = 0x00000040, /* counter overflow */
206 RBU = 0x00000020, /* receive buffer unavailable */
207 TBU = 0x00000010, /* transmit buffer unavilable */
208 TI = 0x00000008, /* transmit interrupt */
209 RI = 0x00000004, /* receive interrupt */
210 RxErr = 0x00000002, /* receive error */
211};
212
213/* Bits in the NetworkConfig register, W for writing, R for reading */
214/* FIXME: some names are invented by me. Marked with (name?) */
215/* If you have docs and know bit names, please fix 'em */
216enum rx_mode_bits {
217 CR_W_ENH = 0x02000000, /* enhanced mode (name?) */
218 CR_W_FD = 0x00100000, /* full duplex */
219 CR_W_PS10 = 0x00080000, /* 10 mbit */
220 CR_W_TXEN = 0x00040000, /* tx enable (name?) */
221 CR_W_PS1000 = 0x00010000, /* 1000 mbit */
222 /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */
223 CR_W_RXMODEMASK = 0x000000e0,
224 CR_W_PROM = 0x00000080, /* promiscuous mode */
225 CR_W_AB = 0x00000040, /* accept broadcast */
226 CR_W_AM = 0x00000020, /* accept mutlicast */
227 CR_W_ARP = 0x00000008, /* receive runt pkt */
228 CR_W_ALP = 0x00000004, /* receive long pkt */
229 CR_W_SEP = 0x00000002, /* receive error pkt */
230 CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */
231
232 CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */
233 CR_R_FD = 0x00100000, /* full duplex detected */
234 CR_R_PS10 = 0x00080000, /* 10 mbit detected */
235 CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */
236};
237
238/* The Tulip Rx and Tx buffer descriptors. */
239struct fealnx_desc {
240 s32 status;
241 s32 control;
242 u32 buffer;
243 u32 next_desc;
244 struct fealnx_desc *next_desc_logical;
245 struct sk_buff *skbuff;
246 u32 reserved1;
247 u32 reserved2;
248};
249
250/* Bits in network_desc.status */
251enum rx_desc_status_bits {
252 RXOWN = 0x80000000, /* own bit */
253 FLNGMASK = 0x0fff0000, /* frame length */
254 FLNGShift = 16,
255 MARSTATUS = 0x00004000, /* multicast address received */
256 BARSTATUS = 0x00002000, /* broadcast address received */
257 PHYSTATUS = 0x00001000, /* physical address received */
258 RXFSD = 0x00000800, /* first descriptor */
259 RXLSD = 0x00000400, /* last descriptor */
260 ErrorSummary = 0x80, /* error summary */
261 RUNT = 0x40, /* runt packet received */
262 LONG = 0x20, /* long packet received */
263 FAE = 0x10, /* frame align error */
264 CRC = 0x08, /* crc error */
265 RXER = 0x04, /* receive error */
266};
267
268enum rx_desc_control_bits {
269 RXIC = 0x00800000, /* interrupt control */
270 RBSShift = 0,
271};
272
273enum tx_desc_status_bits {
274 TXOWN = 0x80000000, /* own bit */
275 JABTO = 0x00004000, /* jabber timeout */
276 CSL = 0x00002000, /* carrier sense lost */
277 LC = 0x00001000, /* late collision */
278 EC = 0x00000800, /* excessive collision */
279 UDF = 0x00000400, /* fifo underflow */
280 DFR = 0x00000200, /* deferred */
281 HF = 0x00000100, /* heartbeat fail */
282 NCRMask = 0x000000ff, /* collision retry count */
283 NCRShift = 0,
284};
285
286enum tx_desc_control_bits {
287 TXIC = 0x80000000, /* interrupt control */
288 ETIControl = 0x40000000, /* early transmit interrupt */
289 TXLD = 0x20000000, /* last descriptor */
290 TXFD = 0x10000000, /* first descriptor */
291 CRCEnable = 0x08000000, /* crc control */
292 PADEnable = 0x04000000, /* padding control */
293 RetryTxLC = 0x02000000, /* retry late collision */
294 PKTSMask = 0x3ff800, /* packet size bit21-11 */
295 PKTSShift = 11,
296 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */
297 TBSShift = 0,
298};
299
300/* BootROM/EEPROM/MII Management Register */
301#define MASK_MIIR_MII_READ 0x00000000
302#define MASK_MIIR_MII_WRITE 0x00000008
303#define MASK_MIIR_MII_MDO 0x00000004
304#define MASK_MIIR_MII_MDI 0x00000002
305#define MASK_MIIR_MII_MDC 0x00000001
306
307/* ST+OP+PHYAD+REGAD+TA */
308#define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
309#define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
310
311/* ------------------------------------------------------------------------- */
312/* Constants for Myson PHY */
313/* ------------------------------------------------------------------------- */
314#define MysonPHYID 0xd0000302
315/* 89-7-27 add, (begin) */
316#define MysonPHYID0 0x0302
317#define StatusRegister 18
318#define SPEED100 0x0400 // bit10
319#define FULLMODE 0x0800 // bit11
320/* 89-7-27 add, (end) */
321
322/* ------------------------------------------------------------------------- */
323/* Constants for Seeq 80225 PHY */
324/* ------------------------------------------------------------------------- */
325#define SeeqPHYID0 0x0016
326
327#define MIIRegister18 18
328#define SPD_DET_100 0x80
329#define DPLX_DET_FULL 0x40
330
331/* ------------------------------------------------------------------------- */
332/* Constants for Ahdoc 101 PHY */
333/* ------------------------------------------------------------------------- */
334#define AhdocPHYID0 0x0022
335
336#define DiagnosticReg 18
337#define DPLX_FULL 0x0800
338#define Speed_100 0x0400
339
340/* 89/6/13 add, */
341/* -------------------------------------------------------------------------- */
342/* Constants */
343/* -------------------------------------------------------------------------- */
344#define MarvellPHYID0 0x0141
345#define LevelOnePHYID0 0x0013
346
347#define MII1000BaseTControlReg 9
348#define MII1000BaseTStatusReg 10
349#define SpecificReg 17
350
351/* for 1000BaseT Control Register */
352#define PHYAbletoPerform1000FullDuplex 0x0200
353#define PHYAbletoPerform1000HalfDuplex 0x0100
354#define PHY1000AbilityMask 0x300
355
356// for phy specific status register, marvell phy.
357#define SpeedMask 0x0c000
358#define Speed_1000M 0x08000
359#define Speed_100M 0x4000
360#define Speed_10M 0
361#define Full_Duplex 0x2000
362
363// 89/12/29 add, for phy specific status register, levelone phy, (begin)
364#define LXT1000_100M 0x08000
365#define LXT1000_1000M 0x0c000
366#define LXT1000_Full 0x200
367// 89/12/29 add, for phy specific status register, levelone phy, (end)
368
369/* for 3-in-1 case, BMCRSR register */
370#define LinkIsUp2 0x00040000
371
372/* for PHY */
373#define LinkIsUp 0x0004
374
375
376struct netdev_private {
377 /* Descriptor rings first for alignment. */
378 struct fealnx_desc *rx_ring;
379 struct fealnx_desc *tx_ring;
380
381 dma_addr_t rx_ring_dma;
382 dma_addr_t tx_ring_dma;
383
384 spinlock_t lock;
385
386 struct net_device_stats stats;
387
388 /* Media monitoring timer. */
389 struct timer_list timer;
390
391 /* Reset timer */
392 struct timer_list reset_timer;
393 int reset_timer_armed;
394 unsigned long crvalue_sv;
395 unsigned long imrvalue_sv;
396
397 /* Frequently used values: keep some adjacent for cache effect. */
398 int flags;
399 struct pci_dev *pci_dev;
400 unsigned long crvalue;
401 unsigned long bcrvalue;
402 unsigned long imrvalue;
403 struct fealnx_desc *cur_rx;
404 struct fealnx_desc *lack_rxbuf;
405 int really_rx_count;
406 struct fealnx_desc *cur_tx;
407 struct fealnx_desc *cur_tx_copy;
408 int really_tx_count;
409 int free_tx_count;
410 unsigned int rx_buf_sz; /* Based on MTU+slack. */
411
412 /* These values are keep track of the transceiver/media in use. */
413 unsigned int linkok;
414 unsigned int line_speed;
415 unsigned int duplexmode;
416 unsigned int default_port:4; /* Last dev->if_port value. */
417 unsigned int PHYType;
418
419 /* MII transceiver section. */
420 int mii_cnt; /* MII device addresses. */
421 unsigned char phys[2]; /* MII device addresses. */
422 struct mii_if_info mii;
423 void __iomem *mem;
424};
425
426
427static int mdio_read(struct net_device *dev, int phy_id, int location);
428static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
429static int netdev_open(struct net_device *dev);
430static void getlinktype(struct net_device *dev);
431static void getlinkstatus(struct net_device *dev);
432static void netdev_timer(unsigned long data);
433static void reset_timer(unsigned long data);
ed4cb133 434static void fealnx_tx_timeout(struct net_device *dev);
1da177e4
LT		 435static void init_ring(struct net_device *dev);
436static int start_tx(struct sk_buff *skb, struct net_device *dev);
7d12e780 437static irqreturn_t intr_handler(int irq, void *dev_instance);
1da177e4
LT		 438static int netdev_rx(struct net_device *dev);
439static void set_rx_mode(struct net_device *dev);
440static void __set_rx_mode(struct net_device *dev);
441static struct net_device_stats *get_stats(struct net_device *dev);
442static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
7282d491 443static const struct ethtool_ops netdev_ethtool_ops;
1da177e4
LT		 444static int netdev_close(struct net_device *dev);
445static void reset_rx_descriptors(struct net_device *dev);
446static void reset_tx_descriptors(struct net_device *dev);
447
448static void stop_nic_rx(void __iomem *ioaddr, long crvalue)
449{
450 int delay = 0x1000;
451 iowrite32(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
452 while (--delay) {
453 if ( (ioread32(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
454 break;
455 }
456}
457
458
459static void stop_nic_rxtx(void __iomem *ioaddr, long crvalue)
460{
461 int delay = 0x1000;
462 iowrite32(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
463 while (--delay) {
464 if ( (ioread32(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
465 == (CR_R_RXSTOP+CR_R_TXSTOP) )
466 break;
467 }
468}
469
470
471static int __devinit fealnx_init_one(struct pci_dev *pdev,
472 const struct pci_device_id *ent)
473{
474 struct netdev_private *np;
475 int i, option, err, irq;
476 static int card_idx = -1;
477 char boardname[12];
478 void __iomem *ioaddr;
479 unsigned long len;
480 unsigned int chip_id = ent->driver_data;
481 struct net_device *dev;
482 void *ring_space;
483 dma_addr_t ring_dma;
484#ifdef USE_IO_OPS
485 int bar = 0;
486#else
487 int bar = 1;
488#endif
6aa20a22 489
1da177e4
LT		 490/* when built into the kernel, we only print version if device is found */
491#ifndef MODULE
492 static int printed_version;
493 if (!printed_version++)
494 printk(version);
495#endif
6aa20a22 496
1da177e4
LT		 497 card_idx++;
498 sprintf(boardname, "fealnx%d", card_idx);
6aa20a22 499
1da177e4
LT		 500 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
501
502 i = pci_enable_device(pdev);
503 if (i) return i;
504 pci_set_master(pdev);
6aa20a22 505
1da177e4
LT		 506 len = pci_resource_len(pdev, bar);
507 if (len < MIN_REGION_SIZE) {
9b91cf9d 508 dev_err(&pdev->dev,
46009c8b 509 "region size %ld too small, aborting\n", len);
1da177e4
LT		 510 return -ENODEV;
511 }
512
513 i = pci_request_regions(pdev, boardname);
46009c8b
JG		 514 if (i)
515 return i;
6aa20a22 516
1da177e4
LT		 517 irq = pdev->irq;
518
519 ioaddr = pci_iomap(pdev, bar, len);
520 if (!ioaddr) {
521 err = -ENOMEM;
522 goto err_out_res;
523 }
524
525 dev = alloc_etherdev(sizeof(struct netdev_private));
526 if (!dev) {
527 err = -ENOMEM;
528 goto err_out_unmap;
529 }
1da177e4
LT		 530 SET_NETDEV_DEV(dev, &pdev->dev);
531
532 /* read ethernet id */
533 for (i = 0; i < 6; ++i)
534 dev->dev_addr[i] = ioread8(ioaddr + PAR0 + i);
535
536 /* Reset the chip to erase previous misconfiguration. */
537 iowrite32(0x00000001, ioaddr + BCR);
538
539 dev->base_addr = (unsigned long)ioaddr;
540 dev->irq = irq;
541
542 /* Make certain the descriptor lists are aligned. */
543 np = netdev_priv(dev);
544 np->mem = ioaddr;
545 spin_lock_init(&np->lock);
546 np->pci_dev = pdev;
547 np->flags = skel_netdrv_tbl[chip_id].flags;
548 pci_set_drvdata(pdev, dev);
549 np->mii.dev = dev;
550 np->mii.mdio_read = mdio_read;
551 np->mii.mdio_write = mdio_write;
552 np->mii.phy_id_mask = 0x1f;
553 np->mii.reg_num_mask = 0x1f;
554
555 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
556 if (!ring_space) {
557 err = -ENOMEM;
558 goto err_out_free_dev;
559 }
560 np->rx_ring = (struct fealnx_desc *)ring_space;
561 np->rx_ring_dma = ring_dma;
562
563 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
564 if (!ring_space) {
565 err = -ENOMEM;
566 goto err_out_free_rx;
567 }
568 np->tx_ring = (struct fealnx_desc *)ring_space;
569 np->tx_ring_dma = ring_dma;
570
571 /* find the connected MII xcvrs */
572 if (np->flags == HAS_MII_XCVR) {
573 int phy, phy_idx = 0;
574
575 for (phy = 1; phy < 32 && phy_idx < 4; phy++) {
576 int mii_status = mdio_read(dev, phy, 1);
577
578 if (mii_status != 0xffff && mii_status != 0x0000) {
579 np->phys[phy_idx++] = phy;
9b91cf9d 580 dev_info(&pdev->dev,
2e8a538d
JG		 581 "MII PHY found at address %d, status "
582 "0x%4.4x.\n", phy, mii_status);
1da177e4
LT		 583 /* get phy type */
584 {
585 unsigned int data;
586
587 data = mdio_read(dev, np->phys[0], 2);
588 if (data == SeeqPHYID0)
589 np->PHYType = SeeqPHY;
590 else if (data == AhdocPHYID0)
591 np->PHYType = AhdocPHY;
592 else if (data == MarvellPHYID0)
593 np->PHYType = MarvellPHY;
594 else if (data == MysonPHYID0)
595 np->PHYType = Myson981;
596 else if (data == LevelOnePHYID0)
597 np->PHYType = LevelOnePHY;
598 else
599 np->PHYType = OtherPHY;
600 }
601 }
602 }
603
604 np->mii_cnt = phy_idx;
2e8a538d 605 if (phy_idx == 0)
9b91cf9d 606 dev_warn(&pdev->dev,
2e8a538d
JG		 607 "MII PHY not found -- this device may "
608 "not operate correctly.\n");
1da177e4
LT		 609 } else {
610 np->phys[0] = 32;
611/* 89/6/23 add, (begin) */
612 /* get phy type */
613 if (ioread32(ioaddr + PHYIDENTIFIER) == MysonPHYID)
614 np->PHYType = MysonPHY;
615 else
616 np->PHYType = OtherPHY;
617 }
618 np->mii.phy_id = np->phys[0];
619
620 if (dev->mem_start)
621 option = dev->mem_start;
622
623 /* The lower four bits are the media type. */
624 if (option > 0) {
625 if (option & 0x200)
626 np->mii.full_duplex = 1;
627 np->default_port = option & 15;
628 }
629
630 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
631 np->mii.full_duplex = full_duplex[card_idx];
632
633 if (np->mii.full_duplex) {
9b91cf9d 634 dev_info(&pdev->dev, "Media type forced to Full Duplex.\n");
1da177e4
LT		 635/* 89/6/13 add, (begin) */
636// if (np->PHYType==MarvellPHY)
637 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
638 unsigned int data;
639
640 data = mdio_read(dev, np->phys[0], 9);
641 data = (data & 0xfcff) | 0x0200;
642 mdio_write(dev, np->phys[0], 9, data);
643 }
644/* 89/6/13 add, (end) */
645 if (np->flags == HAS_MII_XCVR)
646 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
647 else
648 iowrite32(ADVERTISE_FULL, ioaddr + ANARANLPAR);
649 np->mii.force_media = 1;
650 }
651
652 /* The chip-specific entries in the device structure. */
653 dev->open = &netdev_open;
654 dev->hard_start_xmit = &start_tx;
655 dev->stop = &netdev_close;
656 dev->get_stats = &get_stats;
657 dev->set_multicast_list = &set_rx_mode;
658 dev->do_ioctl = &mii_ioctl;
659 dev->ethtool_ops = &netdev_ethtool_ops;
ed4cb133 660 dev->tx_timeout = &fealnx_tx_timeout;
1da177e4 661 dev->watchdog_timeo = TX_TIMEOUT;
6aa20a22 662
1da177e4
LT		 663 err = register_netdev(dev);
664 if (err)
665 goto err_out_free_tx;
666
e174961c 667 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
0795af57 668 dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr,
e174961c 669 dev->dev_addr, irq);
1da177e4
LT		 670
671 return 0;
672
673err_out_free_tx:
674 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
675err_out_free_rx:
676 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
677err_out_free_dev:
678 free_netdev(dev);
679err_out_unmap:
680 pci_iounmap(pdev, ioaddr);
681err_out_res:
682 pci_release_regions(pdev);
683 return err;
684}
685
686
687static void __devexit fealnx_remove_one(struct pci_dev *pdev)
688{
689 struct net_device *dev = pci_get_drvdata(pdev);
690
691 if (dev) {
692 struct netdev_private *np = netdev_priv(dev);
693
694 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
695 np->tx_ring_dma);
696 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
697 np->rx_ring_dma);
698 unregister_netdev(dev);
699 pci_iounmap(pdev, np->mem);
700 free_netdev(dev);
701 pci_release_regions(pdev);
702 pci_set_drvdata(pdev, NULL);
703 } else
704 printk(KERN_ERR "fealnx: remove for unknown device\n");
705}
706
707
708static ulong m80x_send_cmd_to_phy(void __iomem *miiport, int opcode, int phyad, int regad)
709{
710 ulong miir;
711 int i;
712 unsigned int mask, data;
713
714 /* enable MII output */
715 miir = (ulong) ioread32(miiport);
716 miir &= 0xfffffff0;
717
718 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
719
720 /* send 32 1's preamble */
721 for (i = 0; i < 32; i++) {
722 /* low MDC; MDO is already high (miir) */
723 miir &= ~MASK_MIIR_MII_MDC;
724 iowrite32(miir, miiport);
725
726 /* high MDC */
727 miir |= MASK_MIIR_MII_MDC;
728 iowrite32(miir, miiport);
729 }
730
731 /* calculate ST+OP+PHYAD+REGAD+TA */
732 data = opcode | (phyad << 7) | (regad << 2);
733
734 /* sent out */
735 mask = 0x8000;
736 while (mask) {
737 /* low MDC, prepare MDO */
738 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
739 if (mask & data)
740 miir |= MASK_MIIR_MII_MDO;
741
742 iowrite32(miir, miiport);
743 /* high MDC */
744 miir |= MASK_MIIR_MII_MDC;
745 iowrite32(miir, miiport);
746 udelay(30);
747
748 /* next */
749 mask >>= 1;
750 if (mask == 0x2 && opcode == OP_READ)
751 miir &= ~MASK_MIIR_MII_WRITE;
752 }
753 return miir;
754}
755
756
757static int mdio_read(struct net_device *dev, int phyad, int regad)
758{
759 struct netdev_private *np = netdev_priv(dev);
760 void __iomem *miiport = np->mem + MANAGEMENT;
761 ulong miir;
762 unsigned int mask, data;
763
764 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad);
765
766 /* read data */
767 mask = 0x8000;
768 data = 0;
769 while (mask) {
770 /* low MDC */
771 miir &= ~MASK_MIIR_MII_MDC;
772 iowrite32(miir, miiport);
773
774 /* read MDI */
775 miir = ioread32(miiport);
776 if (miir & MASK_MIIR_MII_MDI)
777 data |= mask;
778
779 /* high MDC, and wait */
780 miir |= MASK_MIIR_MII_MDC;
781 iowrite32(miir, miiport);
782 udelay(30);
783
784 /* next */
785 mask >>= 1;
786 }
787
788 /* low MDC */
789 miir &= ~MASK_MIIR_MII_MDC;
790 iowrite32(miir, miiport);
791
792 return data & 0xffff;
793}
794
795
796static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
797{
798 struct netdev_private *np = netdev_priv(dev);
799 void __iomem *miiport = np->mem + MANAGEMENT;
800 ulong miir;
801 unsigned int mask;
802
803 miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad);
804
805 /* write data */
806 mask = 0x8000;
807 while (mask) {
808 /* low MDC, prepare MDO */
809 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
810 if (mask & data)
811 miir |= MASK_MIIR_MII_MDO;
812 iowrite32(miir, miiport);
813
814 /* high MDC */
815 miir |= MASK_MIIR_MII_MDC;
816 iowrite32(miir, miiport);
817
818 /* next */
819 mask >>= 1;
820 }
821
822 /* low MDC */
823 miir &= ~MASK_MIIR_MII_MDC;
824 iowrite32(miir, miiport);
825}
826
827
828static int netdev_open(struct net_device *dev)
829{
830 struct netdev_private *np = netdev_priv(dev);
831 void __iomem *ioaddr = np->mem;
832 int i;
833
834 iowrite32(0x00000001, ioaddr + BCR); /* Reset */
835
1fb9df5d 836 if (request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev))
1da177e4
LT		 837 return -EAGAIN;
838
839 for (i = 0; i < 3; i++)
840 iowrite16(((unsigned short*)dev->dev_addr)[i],
841 ioaddr + PAR0 + i*2);
842
843 init_ring(dev);
844
845 iowrite32(np->rx_ring_dma, ioaddr + RXLBA);
846 iowrite32(np->tx_ring_dma, ioaddr + TXLBA);
847
848 /* Initialize other registers. */
849 /* Configure the PCI bus bursts and FIFO thresholds.
850 486: Set 8 longword burst.
851 586: no burst limit.
852 Burst length 5:3
853 0 0 0 1
854 0 0 1 4
855 0 1 0 8
856 0 1 1 16
857 1 0 0 32
858 1 0 1 64
859 1 1 0 128
860 1 1 1 256
861 Wait the specified 50 PCI cycles after a reset by initializing
862 Tx and Rx queues and the address filter list.
863 FIXME (Ueimor): optimistic for alpha + posted writes ? */
28cd4289 864
1da177e4 865 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
28cd4289
JG		 866#ifdef __BIG_ENDIAN
867 np->bcrvalue |= 0x04; /* big-endian */
1da177e4 868#endif
28cd4289
JG		 869
870#if defined(__i386__) && !defined(MODULE)
871 if (boot_cpu_data.x86 <= 4)
872 np->crvalue = 0xa00;
873 else
1da177e4 874#endif
28cd4289
JG		 875 np->crvalue = 0xe00; /* rx 128 burst length */
876
877
1da177e4
LT		 878// 89/12/29 add,
879// 90/1/16 modify,
880// np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
881 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
882 if (np->pci_dev->device == 0x891) {
883 np->bcrvalue |= 0x200; /* set PROG bit */
884 np->crvalue |= CR_W_ENH; /* set enhanced bit */
885 np->imrvalue |= ETI;
886 }
887 iowrite32(np->bcrvalue, ioaddr + BCR);
888
889 if (dev->if_port == 0)
890 dev->if_port = np->default_port;
891
892 iowrite32(0, ioaddr + RXPDR);
893// 89/9/1 modify,
894// np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
895 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
896 np->mii.full_duplex = np->mii.force_media;
897 getlinkstatus(dev);
898 if (np->linkok)
899 getlinktype(dev);
900 __set_rx_mode(dev);
901
902 netif_start_queue(dev);
903
904 /* Clear and Enable interrupts by setting the interrupt mask. */
905 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
906 iowrite32(np->imrvalue, ioaddr + IMR);
907
908 if (debug)
909 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
910
911 /* Set the timer to check for link beat. */
912 init_timer(&np->timer);
913 np->timer.expires = RUN_AT(3 * HZ);
914 np->timer.data = (unsigned long) dev;
915 np->timer.function = &netdev_timer;
916
917 /* timer handler */
918 add_timer(&np->timer);
919
920 init_timer(&np->reset_timer);
921 np->reset_timer.data = (unsigned long) dev;
922 np->reset_timer.function = &reset_timer;
923 np->reset_timer_armed = 0;
924
925 return 0;
926}
927
928
929static void getlinkstatus(struct net_device *dev)
930/* function: Routine will read MII Status Register to get link status. */
931/* input : dev... pointer to the adapter block. */
932/* output : none. */
933{
934 struct netdev_private *np = netdev_priv(dev);
935 unsigned int i, DelayTime = 0x1000;
936
937 np->linkok = 0;
938
939 if (np->PHYType == MysonPHY) {
940 for (i = 0; i < DelayTime; ++i) {
941 if (ioread32(np->mem + BMCRSR) & LinkIsUp2) {
942 np->linkok = 1;
943 return;
944 }
945 udelay(100);
946 }
947 } else {
948 for (i = 0; i < DelayTime; ++i) {
949 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
950 np->linkok = 1;
951 return;
952 }
953 udelay(100);
954 }
955 }
956}
957
958
959static void getlinktype(struct net_device *dev)
960{
961 struct netdev_private *np = netdev_priv(dev);
962
963 if (np->PHYType == MysonPHY) { /* 3-in-1 case */
964 if (ioread32(np->mem + TCRRCR) & CR_R_FD)
965 np->duplexmode = 2; /* full duplex */
966 else
967 np->duplexmode = 1; /* half duplex */
968 if (ioread32(np->mem + TCRRCR) & CR_R_PS10)
969 np->line_speed = 1; /* 10M */
970 else
971 np->line_speed = 2; /* 100M */
972 } else {
973 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */
974 unsigned int data;
975
976 data = mdio_read(dev, np->phys[0], MIIRegister18);
977 if (data & SPD_DET_100)
978 np->line_speed = 2; /* 100M */
979 else
980 np->line_speed = 1; /* 10M */
981 if (data & DPLX_DET_FULL)
982 np->duplexmode = 2; /* full duplex mode */
983 else
984 np->duplexmode = 1; /* half duplex mode */
985 } else if (np->PHYType == AhdocPHY) {
986 unsigned int data;
987
988 data = mdio_read(dev, np->phys[0], DiagnosticReg);
989 if (data & Speed_100)
990 np->line_speed = 2; /* 100M */
991 else
992 np->line_speed = 1; /* 10M */
993 if (data & DPLX_FULL)
994 np->duplexmode = 2; /* full duplex mode */
995 else
996 np->duplexmode = 1; /* half duplex mode */
997 }
998/* 89/6/13 add, (begin) */
999 else if (np->PHYType == MarvellPHY) {
1000 unsigned int data;
1001
1002 data = mdio_read(dev, np->phys[0], SpecificReg);
1003 if (data & Full_Duplex)
1004 np->duplexmode = 2; /* full duplex mode */
1005 else
1006 np->duplexmode = 1; /* half duplex mode */
1007 data &= SpeedMask;
1008 if (data == Speed_1000M)
1009 np->line_speed = 3; /* 1000M */
1010 else if (data == Speed_100M)
1011 np->line_speed = 2; /* 100M */
1012 else
1013 np->line_speed = 1; /* 10M */
1014 }
1015/* 89/6/13 add, (end) */
1016/* 89/7/27 add, (begin) */
1017 else if (np->PHYType == Myson981) {
1018 unsigned int data;
1019
1020 data = mdio_read(dev, np->phys[0], StatusRegister);
1021
1022 if (data & SPEED100)
1023 np->line_speed = 2;
1024 else
1025 np->line_speed = 1;
1026
1027 if (data & FULLMODE)
1028 np->duplexmode = 2;
1029 else
1030 np->duplexmode = 1;
1031 }
1032/* 89/7/27 add, (end) */
1033/* 89/12/29 add */
1034 else if (np->PHYType == LevelOnePHY) {
1035 unsigned int data;
1036
1037 data = mdio_read(dev, np->phys[0], SpecificReg);
1038 if (data & LXT1000_Full)
1039 np->duplexmode = 2; /* full duplex mode */
1040 else
1041 np->duplexmode = 1; /* half duplex mode */
1042 data &= SpeedMask;
1043 if (data == LXT1000_1000M)
1044 np->line_speed = 3; /* 1000M */
1045 else if (data == LXT1000_100M)
1046 np->line_speed = 2; /* 100M */
1047 else
1048 np->line_speed = 1; /* 10M */
1049 }
1050 np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000);
1051 if (np->line_speed == 1)
1052 np->crvalue |= CR_W_PS10;
1053 else if (np->line_speed == 3)
1054 np->crvalue |= CR_W_PS1000;
1055 if (np->duplexmode == 2)
1056 np->crvalue |= CR_W_FD;
1057 }
1058}
1059
1060
1061/* Take lock before calling this */
1062static void allocate_rx_buffers(struct net_device *dev)
1063{
1064 struct netdev_private *np = netdev_priv(dev);
1065
1066 /* allocate skb for rx buffers */
1067 while (np->really_rx_count != RX_RING_SIZE) {
1068 struct sk_buff *skb;
1069
1070 skb = dev_alloc_skb(np->rx_buf_sz);
1071 if (skb == NULL)
1072 break; /* Better luck next round. */
1073
1074 while (np->lack_rxbuf->skbuff)
1075 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1076
1077 skb->dev = dev; /* Mark as being used by this device. */
1078 np->lack_rxbuf->skbuff = skb;
689be439 1079 np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->data,
1da177e4
LT		 1080 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1081 np->lack_rxbuf->status = RXOWN;
1082 ++np->really_rx_count;
1083 }
1084}
1085
1086
1087static void netdev_timer(unsigned long data)
1088{
1089 struct net_device *dev = (struct net_device *) data;
1090 struct netdev_private *np = netdev_priv(dev);
1091 void __iomem *ioaddr = np->mem;
1092 int old_crvalue = np->crvalue;
1093 unsigned int old_linkok = np->linkok;
1094 unsigned long flags;
1095
1096 if (debug)
1097 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
1098 "config %8.8x.\n", dev->name, ioread32(ioaddr + ISR),
1099 ioread32(ioaddr + TCRRCR));
1100
1101 spin_lock_irqsave(&np->lock, flags);
1102
1103 if (np->flags == HAS_MII_XCVR) {
1104 getlinkstatus(dev);
1105 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */
1106 getlinktype(dev);
1107 if (np->crvalue != old_crvalue) {
1108 stop_nic_rxtx(ioaddr, np->crvalue);
1109 iowrite32(np->crvalue, ioaddr + TCRRCR);
1110 }
1111 }
1112 }
1113
1114 allocate_rx_buffers(dev);
1115
1116 spin_unlock_irqrestore(&np->lock, flags);
1117
1118 np->timer.expires = RUN_AT(10 * HZ);
1119 add_timer(&np->timer);
1120}
1121
1122
1123/* Take lock before calling */
1124/* Reset chip and disable rx, tx and interrupts */
1125static void reset_and_disable_rxtx(struct net_device *dev)
1126{
1127 struct netdev_private *np = netdev_priv(dev);
1128 void __iomem *ioaddr = np->mem;
1129 int delay=51;
1130
1131 /* Reset the chip's Tx and Rx processes. */
1132 stop_nic_rxtx(ioaddr, 0);
1133
1134 /* Disable interrupts by clearing the interrupt mask. */
1135 iowrite32(0, ioaddr + IMR);
1136
1137 /* Reset the chip to erase previous misconfiguration. */
1138 iowrite32(0x00000001, ioaddr + BCR);
1139
6aa20a22 1140 /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
1da177e4
LT		 1141 We surely wait too long (address+data phase). Who cares? */
1142 while (--delay) {
1143 ioread32(ioaddr + BCR);
1144 rmb();
1145 }
1146}
1147
1148
1149/* Take lock before calling */
1150/* Restore chip after reset */
1151static void enable_rxtx(struct net_device *dev)
1152{
1153 struct netdev_private *np = netdev_priv(dev);
1154 void __iomem *ioaddr = np->mem;
1155
1156 reset_rx_descriptors(dev);
1157
1158 iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
1159 ioaddr + TXLBA);
1160 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1161 ioaddr + RXLBA);
1162
1163 iowrite32(np->bcrvalue, ioaddr + BCR);
1164
1165 iowrite32(0, ioaddr + RXPDR);
1166 __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
1167
1168 /* Clear and Enable interrupts by setting the interrupt mask. */
1169 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
1170 iowrite32(np->imrvalue, ioaddr + IMR);
1171
1172 iowrite32(0, ioaddr + TXPDR);
1173}
1174
1175
1176static void reset_timer(unsigned long data)
1177{
1178 struct net_device *dev = (struct net_device *) data;
1179 struct netdev_private *np = netdev_priv(dev);
1180 unsigned long flags;
1181
1182 printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name);
1183
1184 spin_lock_irqsave(&np->lock, flags);
1185 np->crvalue = np->crvalue_sv;
1186 np->imrvalue = np->imrvalue_sv;
1187
1188 reset_and_disable_rxtx(dev);
1189 /* works for me without this:
1190 reset_tx_descriptors(dev); */
1191 enable_rxtx(dev);
1192 netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */
6aa20a22 1193
1da177e4
LT		 1194 np->reset_timer_armed = 0;
1195
1196 spin_unlock_irqrestore(&np->lock, flags);
1197}
1198
1199
ed4cb133 1200static void fealnx_tx_timeout(struct net_device *dev)
1da177e4
LT		 1201{
1202 struct netdev_private *np = netdev_priv(dev);
1203 void __iomem *ioaddr = np->mem;
1204 unsigned long flags;
1205 int i;
1206
1207 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
1208 " resetting...\n", dev->name, ioread32(ioaddr + ISR));
1209
1210 {
1211 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
1212 for (i = 0; i < RX_RING_SIZE; i++)
1213 printk(" %8.8x", (unsigned int) np->rx_ring[i].status);
1214 printk("\n" KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1215 for (i = 0; i < TX_RING_SIZE; i++)
1216 printk(" %4.4x", np->tx_ring[i].status);
1217 printk("\n");
1218 }
6aa20a22 1219
1da177e4
LT		 1220 spin_lock_irqsave(&np->lock, flags);
1221
1222 reset_and_disable_rxtx(dev);
1223 reset_tx_descriptors(dev);
1224 enable_rxtx(dev);
1225
1226 spin_unlock_irqrestore(&np->lock, flags);
1227
1228 dev->trans_start = jiffies;
1229 np->stats.tx_errors++;
1230 netif_wake_queue(dev); /* or .._start_.. ?? */
1231}
1232
1233
1234/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1235static void init_ring(struct net_device *dev)
1236{
1237 struct netdev_private *np = netdev_priv(dev);
1238 int i;
1239
1240 /* initialize rx variables */
1241 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1242 np->cur_rx = &np->rx_ring[0];
1243 np->lack_rxbuf = np->rx_ring;
1244 np->really_rx_count = 0;
1245
1246 /* initial rx descriptors. */
1247 for (i = 0; i < RX_RING_SIZE; i++) {
1248 np->rx_ring[i].status = 0;
1249 np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1250 np->rx_ring[i].next_desc = np->rx_ring_dma +
1251 (i + 1)*sizeof(struct fealnx_desc);
1252 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1253 np->rx_ring[i].skbuff = NULL;
1254 }
1255
1256 /* for the last rx descriptor */
1257 np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1258 np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1259
1260 /* allocate skb for rx buffers */
1261 for (i = 0; i < RX_RING_SIZE; i++) {
1262 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1263
1264 if (skb == NULL) {
1265 np->lack_rxbuf = &np->rx_ring[i];
1266 break;
1267 }
1268
1269 ++np->really_rx_count;
1270 np->rx_ring[i].skbuff = skb;
1271 skb->dev = dev; /* Mark as being used by this device. */
689be439 1272 np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->data,
1da177e4
LT		 1273 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1274 np->rx_ring[i].status = RXOWN;
1275 np->rx_ring[i].control |= RXIC;
1276 }
1277
1278 /* initialize tx variables */
1279 np->cur_tx = &np->tx_ring[0];
1280 np->cur_tx_copy = &np->tx_ring[0];
1281 np->really_tx_count = 0;
1282 np->free_tx_count = TX_RING_SIZE;
1283
1284 for (i = 0; i < TX_RING_SIZE; i++) {
1285 np->tx_ring[i].status = 0;
1286 /* do we need np->tx_ring[i].control = XXX; ?? */
1287 np->tx_ring[i].next_desc = np->tx_ring_dma +
1288 (i + 1)*sizeof(struct fealnx_desc);
1289 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1290 np->tx_ring[i].skbuff = NULL;
1291 }
1292
1293 /* for the last tx descriptor */
1294 np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1295 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1296}
1297
1298
1299static int start_tx(struct sk_buff *skb, struct net_device *dev)
1300{
1301 struct netdev_private *np = netdev_priv(dev);
1302 unsigned long flags;
1303
1304 spin_lock_irqsave(&np->lock, flags);
1305
1306 np->cur_tx_copy->skbuff = skb;
1307
1308#define one_buffer
1309#define BPT 1022
1310#if defined(one_buffer)
1311 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1312 skb->len, PCI_DMA_TODEVICE);
1313 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1314 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1315 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1316// 89/12/29 add,
1317 if (np->pci_dev->device == 0x891)
1318 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1319 np->cur_tx_copy->status = TXOWN;
1320 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1321 --np->free_tx_count;
1322#elif defined(two_buffer)
1323 if (skb->len > BPT) {
1324 struct fealnx_desc *next;
1325
1326 /* for the first descriptor */
1327 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1328 BPT, PCI_DMA_TODEVICE);
1329 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1330 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1331 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */
1332
1333 /* for the last descriptor */
1334 next = np->cur_tx_copy->next_desc_logical;
1335 next->skbuff = skb;
1336 next->control = TXIC | TXLD | CRCEnable | PADEnable;
1337 next->control |= (skb->len << PKTSShift); /* pkt size */
1338 next->control |= ((skb->len - BPT) << TBSShift); /* buf size */
1339// 89/12/29 add,
1340 if (np->pci_dev->device == 0x891)
1341 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1342 next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT,
1343 skb->len - BPT, PCI_DMA_TODEVICE);
1344
1345 next->status = TXOWN;
1346 np->cur_tx_copy->status = TXOWN;
1347
1348 np->cur_tx_copy = next->next_desc_logical;
1349 np->free_tx_count -= 2;
1350 } else {
1351 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1352 skb->len, PCI_DMA_TODEVICE);
1353 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1354 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1355 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1356// 89/12/29 add,
1357 if (np->pci_dev->device == 0x891)
1358 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1359 np->cur_tx_copy->status = TXOWN;
1360 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1361 --np->free_tx_count;
1362 }
1363#endif
1364
1365 if (np->free_tx_count < 2)
1366 netif_stop_queue(dev);
1367 ++np->really_tx_count;
1368 iowrite32(0, np->mem + TXPDR);
1369 dev->trans_start = jiffies;
1370
1371 spin_unlock_irqrestore(&np->lock, flags);
1372 return 0;
1373}
1374
1375
1376/* Take lock before calling */
1377/* Chip probably hosed tx ring. Clean up. */
1378static void reset_tx_descriptors(struct net_device *dev)
1379{
1380 struct netdev_private *np = netdev_priv(dev);
1381 struct fealnx_desc *cur;
1382 int i;
1383
1384 /* initialize tx variables */
1385 np->cur_tx = &np->tx_ring[0];
1386 np->cur_tx_copy = &np->tx_ring[0];
1387 np->really_tx_count = 0;
1388 np->free_tx_count = TX_RING_SIZE;
1389
1390 for (i = 0; i < TX_RING_SIZE; i++) {
1391 cur = &np->tx_ring[i];
1392 if (cur->skbuff) {
1393 pci_unmap_single(np->pci_dev, cur->buffer,
1394 cur->skbuff->len, PCI_DMA_TODEVICE);
400de2c0 1395 dev_kfree_skb_any(cur->skbuff);
1da177e4
LT		 1396 cur->skbuff = NULL;
1397 }
1398 cur->status = 0;
1399 cur->control = 0; /* needed? */
1400 /* probably not needed. We do it for purely paranoid reasons */
1401 cur->next_desc = np->tx_ring_dma +
1402 (i + 1)*sizeof(struct fealnx_desc);
1403 cur->next_desc_logical = &np->tx_ring[i + 1];
1404 }
1405 /* for the last tx descriptor */
1406 np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma;
1407 np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0];
1408}
1409
1410
1411/* Take lock and stop rx before calling this */
1412static void reset_rx_descriptors(struct net_device *dev)
1413{
1414 struct netdev_private *np = netdev_priv(dev);
1415 struct fealnx_desc *cur = np->cur_rx;
1416 int i;
1417
1418 allocate_rx_buffers(dev);
1419
1420 for (i = 0; i < RX_RING_SIZE; i++) {
1421 if (cur->skbuff)
1422 cur->status = RXOWN;
1423 cur = cur->next_desc_logical;
1424 }
1425
1426 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1427 np->mem + RXLBA);
1428}
1429
1430
1431/* The interrupt handler does all of the Rx thread work and cleans up
1432 after the Tx thread. */
7d12e780 1433static irqreturn_t intr_handler(int irq, void *dev_instance)
1da177e4
LT		 1434{
1435 struct net_device *dev = (struct net_device *) dev_instance;
1436 struct netdev_private *np = netdev_priv(dev);
1437 void __iomem *ioaddr = np->mem;
1438 long boguscnt = max_interrupt_work;
1439 unsigned int num_tx = 0;
1440 int handled = 0;
1441
1442 spin_lock(&np->lock);
1443
1444 iowrite32(0, ioaddr + IMR);
1445
1446 do {
1447 u32 intr_status = ioread32(ioaddr + ISR);
1448
1449 /* Acknowledge all of the current interrupt sources ASAP. */
1450 iowrite32(intr_status, ioaddr + ISR);
1451
1452 if (debug)
1453 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
1454 intr_status);
1455
1456 if (!(intr_status & np->imrvalue))
1457 break;
1458
1459 handled = 1;
1460
1461// 90/1/16 delete,
1462//
1463// if (intr_status & FBE)
1464// { /* fatal error */
1465// stop_nic_tx(ioaddr, 0);
1466// stop_nic_rx(ioaddr, 0);
1467// break;
1468// };
1469
1470 if (intr_status & TUNF)
1471 iowrite32(0, ioaddr + TXPDR);
1472
1473 if (intr_status & CNTOVF) {
1474 /* missed pkts */
1475 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1476
1477 /* crc error */
1478 np->stats.rx_crc_errors +=
1479 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1480 }
1481
1482 if (intr_status & (RI | RBU)) {
1483 if (intr_status & RI)
1484 netdev_rx(dev);
1485 else {
1486 stop_nic_rx(ioaddr, np->crvalue);
1487 reset_rx_descriptors(dev);
1488 iowrite32(np->crvalue, ioaddr + TCRRCR);
6aa20a22 1489 }
1da177e4
LT		 1490 }
1491
1492 while (np->really_tx_count) {
1493 long tx_status = np->cur_tx->status;
1494 long tx_control = np->cur_tx->control;
1495
1496 if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */
1497 struct fealnx_desc *next;
1498
1499 next = np->cur_tx->next_desc_logical;
1500 tx_status = next->status;
1501 tx_control = next->control;
1502 }
1503
1504 if (tx_status & TXOWN)
1505 break;
1506
1507 if (!(np->crvalue & CR_W_ENH)) {
1508 if (tx_status & (CSL | LC | EC | UDF | HF)) {
1509 np->stats.tx_errors++;
1510 if (tx_status & EC)
1511 np->stats.tx_aborted_errors++;
1512 if (tx_status & CSL)
1513 np->stats.tx_carrier_errors++;
1514 if (tx_status & LC)
1515 np->stats.tx_window_errors++;
1516 if (tx_status & UDF)
1517 np->stats.tx_fifo_errors++;
1518 if ((tx_status & HF) && np->mii.full_duplex == 0)
1519 np->stats.tx_heartbeat_errors++;
1520
1521 } else {
1522 np->stats.tx_bytes +=
1523 ((tx_control & PKTSMask) >> PKTSShift);
1524
1525 np->stats.collisions +=
1526 ((tx_status & NCRMask) >> NCRShift);
1527 np->stats.tx_packets++;
1528 }
1529 } else {
1530 np->stats.tx_bytes +=
1531 ((tx_control & PKTSMask) >> PKTSShift);
1532 np->stats.tx_packets++;
1533 }
1534
1535 /* Free the original skb. */
1536 pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1537 np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1538 dev_kfree_skb_irq(np->cur_tx->skbuff);
1539 np->cur_tx->skbuff = NULL;
1540 --np->really_tx_count;
1541 if (np->cur_tx->control & TXLD) {
1542 np->cur_tx = np->cur_tx->next_desc_logical;
1543 ++np->free_tx_count;
1544 } else {
1545 np->cur_tx = np->cur_tx->next_desc_logical;
1546 np->cur_tx = np->cur_tx->next_desc_logical;
1547 np->free_tx_count += 2;
1548 }
1549 num_tx++;
1550 } /* end of for loop */
6aa20a22 1551
1da177e4
LT		 1552 if (num_tx && np->free_tx_count >= 2)
1553 netif_wake_queue(dev);
1554
1555 /* read transmit status for enhanced mode only */
1556 if (np->crvalue & CR_W_ENH) {
1557 long data;
1558
1559 data = ioread32(ioaddr + TSR);
1560 np->stats.tx_errors += (data & 0xff000000) >> 24;
1561 np->stats.tx_aborted_errors += (data & 0xff000000) >> 24;
1562 np->stats.tx_window_errors += (data & 0x00ff0000) >> 16;
1563 np->stats.collisions += (data & 0x0000ffff);
1564 }
1565
1566 if (--boguscnt < 0) {
1567 printk(KERN_WARNING "%s: Too much work at interrupt, "
1568 "status=0x%4.4x.\n", dev->name, intr_status);
1569 if (!np->reset_timer_armed) {
1570 np->reset_timer_armed = 1;
1571 np->reset_timer.expires = RUN_AT(HZ/2);
1572 add_timer(&np->reset_timer);
1573 stop_nic_rxtx(ioaddr, 0);
1574 netif_stop_queue(dev);
1575 /* or netif_tx_disable(dev); ?? */
1576 /* Prevent other paths from enabling tx,rx,intrs */
1577 np->crvalue_sv = np->crvalue;
1578 np->imrvalue_sv = np->imrvalue;
1579 np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */
1580 np->imrvalue = 0;
1581 }
1582
1583 break;
1584 }
1585 } while (1);
1586
1587 /* read the tally counters */
1588 /* missed pkts */
1589 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1590
1591 /* crc error */
1592 np->stats.rx_crc_errors += (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1593
1594 if (debug)
1595 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1596 dev->name, ioread32(ioaddr + ISR));
1597
1598 iowrite32(np->imrvalue, ioaddr + IMR);
1599
1600 spin_unlock(&np->lock);
1601
1602 return IRQ_RETVAL(handled);
1603}
1604
1605
1606/* This routine is logically part of the interrupt handler, but separated
1607 for clarity and better register allocation. */
1608static int netdev_rx(struct net_device *dev)
1609{
1610 struct netdev_private *np = netdev_priv(dev);
1611 void __iomem *ioaddr = np->mem;
1612
1613 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1614 while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
1615 s32 rx_status = np->cur_rx->status;
1616
1617 if (np->really_rx_count == 0)
1618 break;
1619
1620 if (debug)
1621 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status);
1622
1623 if ((!((rx_status & RXFSD) && (rx_status & RXLSD)))
1624 || (rx_status & ErrorSummary)) {
1625 if (rx_status & ErrorSummary) { /* there was a fatal error */
1626 if (debug)
1627 printk(KERN_DEBUG
1628 "%s: Receive error, Rx status %8.8x.\n",
1629 dev->name, rx_status);
1630
1631 np->stats.rx_errors++; /* end of a packet. */
1632 if (rx_status & (LONG | RUNT))
1633 np->stats.rx_length_errors++;
1634 if (rx_status & RXER)
1635 np->stats.rx_frame_errors++;
1636 if (rx_status & CRC)
1637 np->stats.rx_crc_errors++;
1638 } else {
1639 int need_to_reset = 0;
1640 int desno = 0;
1641
1642 if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */
1643 struct fealnx_desc *cur;
1644
1645 /* check this packet is received completely? */
1646 cur = np->cur_rx;
1647 while (desno <= np->really_rx_count) {
1648 ++desno;
1649 if ((!(cur->status & RXOWN))
1650 && (cur->status & RXLSD))
1651 break;
1652 /* goto next rx descriptor */
1653 cur = cur->next_desc_logical;
1654 }
1655 if (desno > np->really_rx_count)
1656 need_to_reset = 1;
1657 } else /* RXLSD did not find, something error */
1658 need_to_reset = 1;
1659
1660 if (need_to_reset == 0) {
1661 int i;
1662
1663 np->stats.rx_length_errors++;
1664
1665 /* free all rx descriptors related this long pkt */
1666 for (i = 0; i < desno; ++i) {
1667 if (!np->cur_rx->skbuff) {
1668 printk(KERN_DEBUG
1669 "%s: I'm scared\n", dev->name);
1670 break;
1671 }
1672 np->cur_rx->status = RXOWN;
1673 np->cur_rx = np->cur_rx->next_desc_logical;
1674 }
1675 continue;
1676 } else { /* rx error, need to reset this chip */
1677 stop_nic_rx(ioaddr, np->crvalue);
1678 reset_rx_descriptors(dev);
1679 iowrite32(np->crvalue, ioaddr + TCRRCR);
1680 }
1681 break; /* exit the while loop */
1682 }
1683 } else { /* this received pkt is ok */
1684
1685 struct sk_buff *skb;
1686 /* Omit the four octet CRC from the length. */
1687 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4;
1688
1689#ifndef final_version
1690 if (debug)
1691 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1692 " status %x.\n", pkt_len, rx_status);
1693#endif
1694
1695 /* Check if the packet is long enough to accept without copying
1696 to a minimally-sized skbuff. */
1697 if (pkt_len < rx_copybreak &&
1698 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 1699 skb_reserve(skb, 2); /* 16 byte align the IP header */
1700 pci_dma_sync_single_for_cpu(np->pci_dev,
1701 np->cur_rx->buffer,
1702 np->rx_buf_sz,
1703 PCI_DMA_FROMDEVICE);
1704 /* Call copy + cksum if available. */
1705
1706#if ! defined(__alpha__)
8c7b7faa
DM		 1707 skb_copy_to_linear_data(skb,
1708 np->cur_rx->skbuff->data, pkt_len);
1da177e4
LT		 1709 skb_put(skb, pkt_len);
1710#else
1711 memcpy(skb_put(skb, pkt_len),
689be439 1712 np->cur_rx->skbuff->data, pkt_len);
1da177e4
LT		 1713#endif
1714 pci_dma_sync_single_for_device(np->pci_dev,
1715 np->cur_rx->buffer,
1716 np->rx_buf_sz,
1717 PCI_DMA_FROMDEVICE);
1718 } else {
1719 pci_unmap_single(np->pci_dev,
1720 np->cur_rx->buffer,
1721 np->rx_buf_sz,
1722 PCI_DMA_FROMDEVICE);
1723 skb_put(skb = np->cur_rx->skbuff, pkt_len);
1724 np->cur_rx->skbuff = NULL;
1725 --np->really_rx_count;
1726 }
1727 skb->protocol = eth_type_trans(skb, dev);
1728 netif_rx(skb);
1da177e4
LT		 1729 np->stats.rx_packets++;
1730 np->stats.rx_bytes += pkt_len;
1731 }
1732
1733 np->cur_rx = np->cur_rx->next_desc_logical;
1734 } /* end of while loop */
1735
1736 /* allocate skb for rx buffers */
1737 allocate_rx_buffers(dev);
1738
1739 return 0;
1740}
1741
1742
1743static struct net_device_stats *get_stats(struct net_device *dev)
1744{
1745 struct netdev_private *np = netdev_priv(dev);
1746 void __iomem *ioaddr = np->mem;
1747
1748 /* The chip only need report frame silently dropped. */
1749 if (netif_running(dev)) {
1750 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1751 np->stats.rx_crc_errors += (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1752 }
1753
1754 return &np->stats;
1755}
1756
1757
1758/* for dev->set_multicast_list */
1759static void set_rx_mode(struct net_device *dev)
1760{
1761 spinlock_t *lp = &((struct netdev_private *)netdev_priv(dev))->lock;
1762 unsigned long flags;
1763 spin_lock_irqsave(lp, flags);
1764 __set_rx_mode(dev);
1765 spin_unlock_irqrestore(lp, flags);
1766}
1767
1768
1769/* Take lock before calling */
1770static void __set_rx_mode(struct net_device *dev)
1771{
1772 struct netdev_private *np = netdev_priv(dev);
1773 void __iomem *ioaddr = np->mem;
1774 u32 mc_filter[2]; /* Multicast hash filter */
1775 u32 rx_mode;
1776
1777 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4
LT		 1778 memset(mc_filter, 0xff, sizeof(mc_filter));
1779 rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM;
1780 } else if ((dev->mc_count > multicast_filter_limit)
1781 || (dev->flags & IFF_ALLMULTI)) {
1782 /* Too many to match, or accept all multicasts. */
1783 memset(mc_filter, 0xff, sizeof(mc_filter));
1784 rx_mode = CR_W_AB | CR_W_AM;
1785 } else {
1786 struct dev_mc_list *mclist;
1787 int i;
1788
1789 memset(mc_filter, 0, sizeof(mc_filter));
1790 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1791 i++, mclist = mclist->next) {
1792 unsigned int bit;
1793 bit = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26) ^ 0x3F;
1794 mc_filter[bit >> 5] |= (1 << bit);
1795 }
1796 rx_mode = CR_W_AB | CR_W_AM;
1797 }
1798
1799 stop_nic_rxtx(ioaddr, np->crvalue);
1800
1801 iowrite32(mc_filter[0], ioaddr + MAR0);
1802 iowrite32(mc_filter[1], ioaddr + MAR1);
1803 np->crvalue &= ~CR_W_RXMODEMASK;
1804 np->crvalue |= rx_mode;
1805 iowrite32(np->crvalue, ioaddr + TCRRCR);
1806}
1807
1808static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1809{
1810 struct netdev_private *np = netdev_priv(dev);
1811
1812 strcpy(info->driver, DRV_NAME);
1813 strcpy(info->version, DRV_VERSION);
1814 strcpy(info->bus_info, pci_name(np->pci_dev));
1815}
1816
1817static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1818{
1819 struct netdev_private *np = netdev_priv(dev);
1820 int rc;
1821
1822 spin_lock_irq(&np->lock);
1823 rc = mii_ethtool_gset(&np->mii, cmd);
1824 spin_unlock_irq(&np->lock);
1825
1826 return rc;
1827}
1828
1829static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1830{
1831 struct netdev_private *np = netdev_priv(dev);
1832 int rc;
1833
1834 spin_lock_irq(&np->lock);
1835 rc = mii_ethtool_sset(&np->mii, cmd);
1836 spin_unlock_irq(&np->lock);
1837
1838 return rc;
1839}
1840
1841static int netdev_nway_reset(struct net_device *dev)
1842{
1843 struct netdev_private *np = netdev_priv(dev);
1844 return mii_nway_restart(&np->mii);
1845}
1846
1847static u32 netdev_get_link(struct net_device *dev)
1848{
1849 struct netdev_private *np = netdev_priv(dev);
1850 return mii_link_ok(&np->mii);
1851}
1852
1853static u32 netdev_get_msglevel(struct net_device *dev)
1854{
1855 return debug;
1856}
1857
1858static void netdev_set_msglevel(struct net_device *dev, u32 value)
1859{
1860 debug = value;
1861}
1862
7282d491 1863static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 1864 .get_drvinfo = netdev_get_drvinfo,
1865 .get_settings = netdev_get_settings,
1866 .set_settings = netdev_set_settings,
1867 .nway_reset = netdev_nway_reset,
1868 .get_link = netdev_get_link,
1869 .get_msglevel = netdev_get_msglevel,
1870 .set_msglevel = netdev_set_msglevel,
1da177e4
LT		 1871};
1872
1873static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1874{
1875 struct netdev_private *np = netdev_priv(dev);
1876 int rc;
1877
1878 if (!netif_running(dev))
1879 return -EINVAL;
1880
1881 spin_lock_irq(&np->lock);
1882 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
1883 spin_unlock_irq(&np->lock);
1884
1885 return rc;
1886}
1887
1888
1889static int netdev_close(struct net_device *dev)
1890{
1891 struct netdev_private *np = netdev_priv(dev);
1892 void __iomem *ioaddr = np->mem;
1893 int i;
1894
1895 netif_stop_queue(dev);
1896
1897 /* Disable interrupts by clearing the interrupt mask. */
1898 iowrite32(0x0000, ioaddr + IMR);
1899
1900 /* Stop the chip's Tx and Rx processes. */
1901 stop_nic_rxtx(ioaddr, 0);
1902
1903 del_timer_sync(&np->timer);
1904 del_timer_sync(&np->reset_timer);
1905
1906 free_irq(dev->irq, dev);
1907
1908 /* Free all the skbuffs in the Rx queue. */
1909 for (i = 0; i < RX_RING_SIZE; i++) {
1910 struct sk_buff *skb = np->rx_ring[i].skbuff;
1911
1912 np->rx_ring[i].status = 0;
1913 if (skb) {
1914 pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1915 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1916 dev_kfree_skb(skb);
1917 np->rx_ring[i].skbuff = NULL;
1918 }
1919 }
1920
1921 for (i = 0; i < TX_RING_SIZE; i++) {
1922 struct sk_buff *skb = np->tx_ring[i].skbuff;
1923
1924 if (skb) {
1925 pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1926 skb->len, PCI_DMA_TODEVICE);
1927 dev_kfree_skb(skb);
1928 np->tx_ring[i].skbuff = NULL;
1929 }
1930 }
1931
1932 return 0;
1933}
1934
1935static struct pci_device_id fealnx_pci_tbl[] = {
1936 {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1937 {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1938 {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1939 {} /* terminate list */
1940};
1941MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl);
1942
1943
1944static struct pci_driver fealnx_driver = {
1945 .name = "fealnx",
1946 .id_table = fealnx_pci_tbl,
1947 .probe = fealnx_init_one,
1948 .remove = __devexit_p(fealnx_remove_one),
1949};
1950
1951static int __init fealnx_init(void)
1952{
1953/* when a module, this is printed whether or not devices are found in probe */
1954#ifdef MODULE
1955 printk(version);
1956#endif
1957
29917620 1958 return pci_register_driver(&fealnx_driver);
1da177e4
LT		 1959}
1960
1961static void __exit fealnx_exit(void)
1962{
1963 pci_unregister_driver(&fealnx_driver);
1964}
1965
1966module_init(fealnx_init);
1967module_exit(fealnx_exit);
Linux 6.x block layer and io_uring tree(s)