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ethoc: align received packet to make IP header at word boundary
[linux-2.6-block.git] / drivers / net / ethoc.c
CommitLineData
a1702857
TR		 1/*
2 * linux/drivers/net/ethoc.c
3 *
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
12 */
13
14#include <linux/etherdevice.h>
15#include <linux/crc32.h>
16#include <linux/io.h>
17#include <linux/mii.h>
18#include <linux/phy.h>
19#include <linux/platform_device.h>
20#include <net/ethoc.h>
21
22/* register offsets */
23#define MODER 0x00
24#define INT_SOURCE 0x04
25#define INT_MASK 0x08
26#define IPGT 0x0c
27#define IPGR1 0x10
28#define IPGR2 0x14
29#define PACKETLEN 0x18
30#define COLLCONF 0x1c
31#define TX_BD_NUM 0x20
32#define CTRLMODER 0x24
33#define MIIMODER 0x28
34#define MIICOMMAND 0x2c
35#define MIIADDRESS 0x30
36#define MIITX_DATA 0x34
37#define MIIRX_DATA 0x38
38#define MIISTATUS 0x3c
39#define MAC_ADDR0 0x40
40#define MAC_ADDR1 0x44
41#define ETH_HASH0 0x48
42#define ETH_HASH1 0x4c
43#define ETH_TXCTRL 0x50
44
45/* mode register */
46#define MODER_RXEN (1 << 0) /* receive enable */
47#define MODER_TXEN (1 << 1) /* transmit enable */
48#define MODER_NOPRE (1 << 2) /* no preamble */
49#define MODER_BRO (1 << 3) /* broadcast address */
50#define MODER_IAM (1 << 4) /* individual address mode */
51#define MODER_PRO (1 << 5) /* promiscuous mode */
52#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
53#define MODER_LOOP (1 << 7) /* loopback */
54#define MODER_NBO (1 << 8) /* no back-off */
55#define MODER_EDE (1 << 9) /* excess defer enable */
56#define MODER_FULLD (1 << 10) /* full duplex */
57#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
58#define MODER_DCRC (1 << 12) /* delayed CRC enable */
59#define MODER_CRC (1 << 13) /* CRC enable */
60#define MODER_HUGE (1 << 14) /* huge packets enable */
61#define MODER_PAD (1 << 15) /* padding enabled */
62#define MODER_RSM (1 << 16) /* receive small packets */
63
64/* interrupt source and mask registers */
65#define INT_MASK_TXF (1 << 0) /* transmit frame */
66#define INT_MASK_TXE (1 << 1) /* transmit error */
67#define INT_MASK_RXF (1 << 2) /* receive frame */
68#define INT_MASK_RXE (1 << 3) /* receive error */
69#define INT_MASK_BUSY (1 << 4)
70#define INT_MASK_TXC (1 << 5) /* transmit control frame */
71#define INT_MASK_RXC (1 << 6) /* receive control frame */
72
73#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
74#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
75
76#define INT_MASK_ALL ( \
77 INT_MASK_TXF | INT_MASK_TXE | \
78 INT_MASK_RXF | INT_MASK_RXE | \
79 INT_MASK_TXC | INT_MASK_RXC | \
80 INT_MASK_BUSY \
81 )
82
83/* packet length register */
84#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
85#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
86#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
87 PACKETLEN_MAX(max))
88
89/* transmit buffer number register */
90#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
91
92/* control module mode register */
93#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
94#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
95#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
96
97/* MII mode register */
98#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
99#define MIIMODER_NOPRE (1 << 8) /* no preamble */
100
101/* MII command register */
102#define MIICOMMAND_SCAN (1 << 0) /* scan status */
103#define MIICOMMAND_READ (1 << 1) /* read status */
104#define MIICOMMAND_WRITE (1 << 2) /* write control data */
105
106/* MII address register */
107#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
108#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
109#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
110 MIIADDRESS_RGAD(reg))
111
112/* MII transmit data register */
113#define MIITX_DATA_VAL(x) ((x) & 0xffff)
114
115/* MII receive data register */
116#define MIIRX_DATA_VAL(x) ((x) & 0xffff)
117
118/* MII status register */
119#define MIISTATUS_LINKFAIL (1 << 0)
120#define MIISTATUS_BUSY (1 << 1)
121#define MIISTATUS_INVALID (1 << 2)
122
123/* TX buffer descriptor */
124#define TX_BD_CS (1 << 0) /* carrier sense lost */
125#define TX_BD_DF (1 << 1) /* defer indication */
126#define TX_BD_LC (1 << 2) /* late collision */
127#define TX_BD_RL (1 << 3) /* retransmission limit */
128#define TX_BD_RETRY_MASK (0x00f0)
129#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
130#define TX_BD_UR (1 << 8) /* transmitter underrun */
131#define TX_BD_CRC (1 << 11) /* TX CRC enable */
132#define TX_BD_PAD (1 << 12) /* pad enable for short packets */
133#define TX_BD_WRAP (1 << 13)
134#define TX_BD_IRQ (1 << 14) /* interrupt request enable */
135#define TX_BD_READY (1 << 15) /* TX buffer ready */
136#define TX_BD_LEN(x) (((x) & 0xffff) << 16)
137#define TX_BD_LEN_MASK (0xffff << 16)
138
139#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
140 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
141
142/* RX buffer descriptor */
143#define RX_BD_LC (1 << 0) /* late collision */
144#define RX_BD_CRC (1 << 1) /* RX CRC error */
145#define RX_BD_SF (1 << 2) /* short frame */
146#define RX_BD_TL (1 << 3) /* too long */
147#define RX_BD_DN (1 << 4) /* dribble nibble */
148#define RX_BD_IS (1 << 5) /* invalid symbol */
149#define RX_BD_OR (1 << 6) /* receiver overrun */
150#define RX_BD_MISS (1 << 7)
151#define RX_BD_CF (1 << 8) /* control frame */
152#define RX_BD_WRAP (1 << 13)
153#define RX_BD_IRQ (1 << 14) /* interrupt request enable */
154#define RX_BD_EMPTY (1 << 15)
155#define RX_BD_LEN(x) (((x) & 0xffff) << 16)
156
157#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
158 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
159
160#define ETHOC_BUFSIZ 1536
161#define ETHOC_ZLEN 64
162#define ETHOC_BD_BASE 0x400
163#define ETHOC_TIMEOUT (HZ / 2)
164#define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
165
166/**
167 * struct ethoc - driver-private device structure
168 * @iobase: pointer to I/O memory region
169 * @membase: pointer to buffer memory region
170 * @num_tx: number of send buffers
171 * @cur_tx: last send buffer written
172 * @dty_tx: last buffer actually sent
173 * @num_rx: number of receive buffers
174 * @cur_rx: current receive buffer
175 * @netdev: pointer to network device structure
176 * @napi: NAPI structure
177 * @stats: network device statistics
178 * @msg_enable: device state flags
179 * @rx_lock: receive lock
180 * @lock: device lock
181 * @phy: attached PHY
182 * @mdio: MDIO bus for PHY access
183 * @phy_id: address of attached PHY
184 */
185struct ethoc {
186 void __iomem *iobase;
187 void __iomem *membase;
188
189 unsigned int num_tx;
190 unsigned int cur_tx;
191 unsigned int dty_tx;
192
193 unsigned int num_rx;
194 unsigned int cur_rx;
195
196 struct net_device *netdev;
197 struct napi_struct napi;
198 struct net_device_stats stats;
199 u32 msg_enable;
200
201 spinlock_t rx_lock;
202 spinlock_t lock;
203
204 struct phy_device *phy;
205 struct mii_bus *mdio;
206 s8 phy_id;
207};
208
209/**
210 * struct ethoc_bd - buffer descriptor
211 * @stat: buffer statistics
212 * @addr: physical memory address
213 */
214struct ethoc_bd {
215 u32 stat;
216 u32 addr;
217};
218
219static u32 ethoc_read(struct ethoc *dev, loff_t offset)
220{
221 return ioread32(dev->iobase + offset);
222}
223
224static void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
225{
226 iowrite32(data, dev->iobase + offset);
227}
228
229static void ethoc_read_bd(struct ethoc *dev, int index, struct ethoc_bd *bd)
230{
231 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
232 bd->stat = ethoc_read(dev, offset + 0);
233 bd->addr = ethoc_read(dev, offset + 4);
234}
235
236static void ethoc_write_bd(struct ethoc *dev, int index,
237 const struct ethoc_bd *bd)
238{
239 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
240 ethoc_write(dev, offset + 0, bd->stat);
241 ethoc_write(dev, offset + 4, bd->addr);
242}
243
244static void ethoc_enable_irq(struct ethoc *dev, u32 mask)
245{
246 u32 imask = ethoc_read(dev, INT_MASK);
247 imask |= mask;
248 ethoc_write(dev, INT_MASK, imask);
249}
250
251static void ethoc_disable_irq(struct ethoc *dev, u32 mask)
252{
253 u32 imask = ethoc_read(dev, INT_MASK);
254 imask &= ~mask;
255 ethoc_write(dev, INT_MASK, imask);
256}
257
258static void ethoc_ack_irq(struct ethoc *dev, u32 mask)
259{
260 ethoc_write(dev, INT_SOURCE, mask);
261}
262
263static void ethoc_enable_rx_and_tx(struct ethoc *dev)
264{
265 u32 mode = ethoc_read(dev, MODER);
266 mode |= MODER_RXEN | MODER_TXEN;
267 ethoc_write(dev, MODER, mode);
268}
269
270static void ethoc_disable_rx_and_tx(struct ethoc *dev)
271{
272 u32 mode = ethoc_read(dev, MODER);
273 mode &= ~(MODER_RXEN | MODER_TXEN);
274 ethoc_write(dev, MODER, mode);
275}
276
277static int ethoc_init_ring(struct ethoc *dev)
278{
279 struct ethoc_bd bd;
280 int i;
281
282 dev->cur_tx = 0;
283 dev->dty_tx = 0;
284 dev->cur_rx = 0;
285
286 /* setup transmission buffers */
3ee19a85 287 bd.addr = virt_to_phys(dev->membase);
a1702857
TR		 288 bd.stat = TX_BD_IRQ | TX_BD_CRC;
289
290 for (i = 0; i < dev->num_tx; i++) {
291 if (i == dev->num_tx - 1)
292 bd.stat |= TX_BD_WRAP;
293
294 ethoc_write_bd(dev, i, &bd);
295 bd.addr += ETHOC_BUFSIZ;
296 }
297
a1702857
TR		 298 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
299
300 for (i = 0; i < dev->num_rx; i++) {
301 if (i == dev->num_rx - 1)
302 bd.stat |= RX_BD_WRAP;
303
304 ethoc_write_bd(dev, dev->num_tx + i, &bd);
305 bd.addr += ETHOC_BUFSIZ;
306 }
307
308 return 0;
309}
310
311static int ethoc_reset(struct ethoc *dev)
312{
313 u32 mode;
314
315 /* TODO: reset controller? */
316
317 ethoc_disable_rx_and_tx(dev);
318
319 /* TODO: setup registers */
320
321 /* enable FCS generation and automatic padding */
322 mode = ethoc_read(dev, MODER);
323 mode |= MODER_CRC | MODER_PAD;
324 ethoc_write(dev, MODER, mode);
325
326 /* set full-duplex mode */
327 mode = ethoc_read(dev, MODER);
328 mode |= MODER_FULLD;
329 ethoc_write(dev, MODER, mode);
330 ethoc_write(dev, IPGT, 0x15);
331
332 ethoc_ack_irq(dev, INT_MASK_ALL);
333 ethoc_enable_irq(dev, INT_MASK_ALL);
334 ethoc_enable_rx_and_tx(dev);
335 return 0;
336}
337
338static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
339 struct ethoc_bd *bd)
340{
341 struct net_device *netdev = dev->netdev;
342 unsigned int ret = 0;
343
344 if (bd->stat & RX_BD_TL) {
345 dev_err(&netdev->dev, "RX: frame too long\n");
346 dev->stats.rx_length_errors++;
347 ret++;
348 }
349
350 if (bd->stat & RX_BD_SF) {
351 dev_err(&netdev->dev, "RX: frame too short\n");
352 dev->stats.rx_length_errors++;
353 ret++;
354 }
355
356 if (bd->stat & RX_BD_DN) {
357 dev_err(&netdev->dev, "RX: dribble nibble\n");
358 dev->stats.rx_frame_errors++;
359 }
360
361 if (bd->stat & RX_BD_CRC) {
362 dev_err(&netdev->dev, "RX: wrong CRC\n");
363 dev->stats.rx_crc_errors++;
364 ret++;
365 }
366
367 if (bd->stat & RX_BD_OR) {
368 dev_err(&netdev->dev, "RX: overrun\n");
369 dev->stats.rx_over_errors++;
370 ret++;
371 }
372
373 if (bd->stat & RX_BD_MISS)
374 dev->stats.rx_missed_errors++;
375
376 if (bd->stat & RX_BD_LC) {
377 dev_err(&netdev->dev, "RX: late collision\n");
378 dev->stats.collisions++;
379 ret++;
380 }
381
382 return ret;
383}
384
385static int ethoc_rx(struct net_device *dev, int limit)
386{
387 struct ethoc *priv = netdev_priv(dev);
388 int count;
389
390 for (count = 0; count < limit; ++count) {
391 unsigned int entry;
392 struct ethoc_bd bd;
393
394 entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
395 ethoc_read_bd(priv, entry, &bd);
396 if (bd.stat & RX_BD_EMPTY)
397 break;
398
399 if (ethoc_update_rx_stats(priv, &bd) == 0) {
400 int size = bd.stat >> 16;
401 struct sk_buff *skb = netdev_alloc_skb(dev, size);
050f91dc
TC		 402
403 size -= 4; /* strip the CRC */
404 skb_reserve(skb, 2); /* align TCP/IP header */
405
a1702857 406 if (likely(skb)) {
3ee19a85 407 void *src = phys_to_virt(bd.addr);
a1702857
TR		 408 memcpy_fromio(skb_put(skb, size), src, size);
409 skb->protocol = eth_type_trans(skb, dev);
a1702857
TR		 410 priv->stats.rx_packets++;
411 priv->stats.rx_bytes += size;
412 netif_receive_skb(skb);
413 } else {
414 if (net_ratelimit())
415 dev_warn(&dev->dev, "low on memory - "
416 "packet dropped\n");
417
418 priv->stats.rx_dropped++;
419 break;
420 }
421 }
422
423 /* clear the buffer descriptor so it can be reused */
424 bd.stat &= ~RX_BD_STATS;
425 bd.stat |= RX_BD_EMPTY;
426 ethoc_write_bd(priv, entry, &bd);
427 priv->cur_rx++;
428 }
429
430 return count;
431}
432
433static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
434{
435 struct net_device *netdev = dev->netdev;
436
437 if (bd->stat & TX_BD_LC) {
438 dev_err(&netdev->dev, "TX: late collision\n");
439 dev->stats.tx_window_errors++;
440 }
441
442 if (bd->stat & TX_BD_RL) {
443 dev_err(&netdev->dev, "TX: retransmit limit\n");
444 dev->stats.tx_aborted_errors++;
445 }
446
447 if (bd->stat & TX_BD_UR) {
448 dev_err(&netdev->dev, "TX: underrun\n");
449 dev->stats.tx_fifo_errors++;
450 }
451
452 if (bd->stat & TX_BD_CS) {
453 dev_err(&netdev->dev, "TX: carrier sense lost\n");
454 dev->stats.tx_carrier_errors++;
455 }
456
457 if (bd->stat & TX_BD_STATS)
458 dev->stats.tx_errors++;
459
460 dev->stats.collisions += (bd->stat >> 4) & 0xf;
461 dev->stats.tx_bytes += bd->stat >> 16;
462 dev->stats.tx_packets++;
463 return 0;
464}
465
466static void ethoc_tx(struct net_device *dev)
467{
468 struct ethoc *priv = netdev_priv(dev);
469
470 spin_lock(&priv->lock);
471
472 while (priv->dty_tx != priv->cur_tx) {
473 unsigned int entry = priv->dty_tx % priv->num_tx;
474 struct ethoc_bd bd;
475
476 ethoc_read_bd(priv, entry, &bd);
477 if (bd.stat & TX_BD_READY)
478 break;
479
480 entry = (++priv->dty_tx) % priv->num_tx;
481 (void)ethoc_update_tx_stats(priv, &bd);
482 }
483
484 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
485 netif_wake_queue(dev);
486
487 ethoc_ack_irq(priv, INT_MASK_TX);
488 spin_unlock(&priv->lock);
489}
490
491static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
492{
493 struct net_device *dev = (struct net_device *)dev_id;
494 struct ethoc *priv = netdev_priv(dev);
495 u32 pending;
496
497 ethoc_disable_irq(priv, INT_MASK_ALL);
498 pending = ethoc_read(priv, INT_SOURCE);
499 if (unlikely(pending == 0)) {
500 ethoc_enable_irq(priv, INT_MASK_ALL);
501 return IRQ_NONE;
502 }
503
504 ethoc_ack_irq(priv, INT_MASK_ALL);
505
506 if (pending & INT_MASK_BUSY) {
507 dev_err(&dev->dev, "packet dropped\n");
508 priv->stats.rx_dropped++;
509 }
510
511 if (pending & INT_MASK_RX) {
512 if (napi_schedule_prep(&priv->napi))
513 __napi_schedule(&priv->napi);
514 } else {
515 ethoc_enable_irq(priv, INT_MASK_RX);
516 }
517
518 if (pending & INT_MASK_TX)
519 ethoc_tx(dev);
520
521 ethoc_enable_irq(priv, INT_MASK_ALL & ~INT_MASK_RX);
522 return IRQ_HANDLED;
523}
524
525static int ethoc_get_mac_address(struct net_device *dev, void *addr)
526{
527 struct ethoc *priv = netdev_priv(dev);
528 u8 *mac = (u8 *)addr;
529 u32 reg;
530
531 reg = ethoc_read(priv, MAC_ADDR0);
532 mac[2] = (reg >> 24) & 0xff;
533 mac[3] = (reg >> 16) & 0xff;
534 mac[4] = (reg >> 8) & 0xff;
535 mac[5] = (reg >> 0) & 0xff;
536
537 reg = ethoc_read(priv, MAC_ADDR1);
538 mac[0] = (reg >> 8) & 0xff;
539 mac[1] = (reg >> 0) & 0xff;
540
541 return 0;
542}
543
544static int ethoc_poll(struct napi_struct *napi, int budget)
545{
546 struct ethoc *priv = container_of(napi, struct ethoc, napi);
547 int work_done = 0;
548
549 work_done = ethoc_rx(priv->netdev, budget);
550 if (work_done < budget) {
551 ethoc_enable_irq(priv, INT_MASK_RX);
552 napi_complete(napi);
553 }
554
555 return work_done;
556}
557
558static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
559{
560 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
561 struct ethoc *priv = bus->priv;
562
563 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
564 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
565
566 while (time_before(jiffies, timeout)) {
567 u32 status = ethoc_read(priv, MIISTATUS);
568 if (!(status & MIISTATUS_BUSY)) {
569 u32 data = ethoc_read(priv, MIIRX_DATA);
570 /* reset MII command register */
571 ethoc_write(priv, MIICOMMAND, 0);
572 return data;
573 }
574
575 schedule();
576 }
577
578 return -EBUSY;
579}
580
581static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
582{
583 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
584 struct ethoc *priv = bus->priv;
585
586 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
587 ethoc_write(priv, MIITX_DATA, val);
588 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
589
590 while (time_before(jiffies, timeout)) {
591 u32 stat = ethoc_read(priv, MIISTATUS);
592 if (!(stat & MIISTATUS_BUSY))
593 return 0;
594
595 schedule();
596 }
597
598 return -EBUSY;
599}
600
601static int ethoc_mdio_reset(struct mii_bus *bus)
602{
603 return 0;
604}
605
606static void ethoc_mdio_poll(struct net_device *dev)
607{
608}
609
610static int ethoc_mdio_probe(struct net_device *dev)
611{
612 struct ethoc *priv = netdev_priv(dev);
613 struct phy_device *phy;
614 int i;
615
616 for (i = 0; i < PHY_MAX_ADDR; i++) {
617 phy = priv->mdio->phy_map[i];
618 if (phy) {
619 if (priv->phy_id != -1) {
620 /* attach to specified PHY */
621 if (priv->phy_id == phy->addr)
622 break;
623 } else {
624 /* autoselect PHY if none was specified */
625 if (phy->addr != 0)
626 break;
627 }
628 }
629 }
630
631 if (!phy) {
632 dev_err(&dev->dev, "no PHY found\n");
633 return -ENXIO;
634 }
635
636 phy = phy_connect(dev, dev_name(&phy->dev), &ethoc_mdio_poll, 0,
637 PHY_INTERFACE_MODE_GMII);
638 if (IS_ERR(phy)) {
639 dev_err(&dev->dev, "could not attach to PHY\n");
640 return PTR_ERR(phy);
641 }
642
643 priv->phy = phy;
644 return 0;
645}
646
647static int ethoc_open(struct net_device *dev)
648{
649 struct ethoc *priv = netdev_priv(dev);
650 unsigned int min_tx = 2;
651 unsigned int num_bd;
652 int ret;
653
654 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
655 dev->name, dev);
656 if (ret)
657 return ret;
658
659 /* calculate the number of TX/RX buffers */
660 num_bd = (dev->mem_end - dev->mem_start + 1) / ETHOC_BUFSIZ;
639b62a5 661 priv->num_tx = max(min_tx, num_bd / 4);
a1702857
TR		 662 priv->num_rx = num_bd - priv->num_tx;
663 ethoc_write(priv, TX_BD_NUM, priv->num_tx);
664
665 ethoc_init_ring(priv);
666 ethoc_reset(priv);
667
668 if (netif_queue_stopped(dev)) {
669 dev_dbg(&dev->dev, " resuming queue\n");
670 netif_wake_queue(dev);
671 } else {
672 dev_dbg(&dev->dev, " starting queue\n");
673 netif_start_queue(dev);
674 }
675
676 phy_start(priv->phy);
677 napi_enable(&priv->napi);
678
679 if (netif_msg_ifup(priv)) {
680 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
681 dev->base_addr, dev->mem_start, dev->mem_end);
682 }
683
684 return 0;
685}
686
687static int ethoc_stop(struct net_device *dev)
688{
689 struct ethoc *priv = netdev_priv(dev);
690
691 napi_disable(&priv->napi);
692
693 if (priv->phy)
694 phy_stop(priv->phy);
695
696 ethoc_disable_rx_and_tx(priv);
697 free_irq(dev->irq, dev);
698
699 if (!netif_queue_stopped(dev))
700 netif_stop_queue(dev);
701
702 return 0;
703}
704
705static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
706{
707 struct ethoc *priv = netdev_priv(dev);
708 struct mii_ioctl_data *mdio = if_mii(ifr);
709 struct phy_device *phy = NULL;
710
711 if (!netif_running(dev))
712 return -EINVAL;
713
714 if (cmd != SIOCGMIIPHY) {
715 if (mdio->phy_id >= PHY_MAX_ADDR)
716 return -ERANGE;
717
718 phy = priv->mdio->phy_map[mdio->phy_id];
719 if (!phy)
720 return -ENODEV;
721 } else {
722 phy = priv->phy;
723 }
724
725 return phy_mii_ioctl(phy, mdio, cmd);
726}
727
728static int ethoc_config(struct net_device *dev, struct ifmap *map)
729{
730 return -ENOSYS;
731}
732
733static int ethoc_set_mac_address(struct net_device *dev, void *addr)
734{
735 struct ethoc *priv = netdev_priv(dev);
736 u8 *mac = (u8 *)addr;
737
738 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
739 (mac[4] << 8) | (mac[5] << 0));
740 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
741
742 return 0;
743}
744
745static void ethoc_set_multicast_list(struct net_device *dev)
746{
747 struct ethoc *priv = netdev_priv(dev);
748 u32 mode = ethoc_read(priv, MODER);
749 struct dev_mc_list *mc = NULL;
750 u32 hash[2] = { 0, 0 };
751
752 /* set loopback mode if requested */
753 if (dev->flags & IFF_LOOPBACK)
754 mode |= MODER_LOOP;
755 else
756 mode &= ~MODER_LOOP;
757
758 /* receive broadcast frames if requested */
759 if (dev->flags & IFF_BROADCAST)
760 mode &= ~MODER_BRO;
761 else
762 mode |= MODER_BRO;
763
764 /* enable promiscuous mode if requested */
765 if (dev->flags & IFF_PROMISC)
766 mode |= MODER_PRO;
767 else
768 mode &= ~MODER_PRO;
769
770 ethoc_write(priv, MODER, mode);
771
772 /* receive multicast frames */
773 if (dev->flags & IFF_ALLMULTI) {
774 hash[0] = 0xffffffff;
775 hash[1] = 0xffffffff;
776 } else {
777 for (mc = dev->mc_list; mc; mc = mc->next) {
778 u32 crc = ether_crc(mc->dmi_addrlen, mc->dmi_addr);
779 int bit = (crc >> 26) & 0x3f;
780 hash[bit >> 5] |= 1 << (bit & 0x1f);
781 }
782 }
783
784 ethoc_write(priv, ETH_HASH0, hash[0]);
785 ethoc_write(priv, ETH_HASH1, hash[1]);
786}
787
788static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
789{
790 return -ENOSYS;
791}
792
793static void ethoc_tx_timeout(struct net_device *dev)
794{
795 struct ethoc *priv = netdev_priv(dev);
796 u32 pending = ethoc_read(priv, INT_SOURCE);
797 if (likely(pending))
798 ethoc_interrupt(dev->irq, dev);
799}
800
801static struct net_device_stats *ethoc_stats(struct net_device *dev)
802{
803 struct ethoc *priv = netdev_priv(dev);
804 return &priv->stats;
805}
806
61357325 807static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
a1702857
TR		 808{
809 struct ethoc *priv = netdev_priv(dev);
810 struct ethoc_bd bd;
811 unsigned int entry;
812 void *dest;
813
814 if (unlikely(skb->len > ETHOC_BUFSIZ)) {
815 priv->stats.tx_errors++;
3790c8cd 816 goto out;
a1702857
TR		 817 }
818
819 entry = priv->cur_tx % priv->num_tx;
820 spin_lock_irq(&priv->lock);
821 priv->cur_tx++;
822
823 ethoc_read_bd(priv, entry, &bd);
824 if (unlikely(skb->len < ETHOC_ZLEN))
825 bd.stat |= TX_BD_PAD;
826 else
827 bd.stat &= ~TX_BD_PAD;
828
3ee19a85 829 dest = phys_to_virt(bd.addr);
a1702857
TR		 830 memcpy_toio(dest, skb->data, skb->len);
831
832 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
833 bd.stat |= TX_BD_LEN(skb->len);
834 ethoc_write_bd(priv, entry, &bd);
835
836 bd.stat |= TX_BD_READY;
837 ethoc_write_bd(priv, entry, &bd);
838
839 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
840 dev_dbg(&dev->dev, "stopping queue\n");
841 netif_stop_queue(dev);
842 }
843
844 dev->trans_start = jiffies;
a1702857 845 spin_unlock_irq(&priv->lock);
3790c8cd
PM		 846out:
847 dev_kfree_skb(skb);
a1702857
TR		 848 return NETDEV_TX_OK;
849}
850
851static const struct net_device_ops ethoc_netdev_ops = {
852 .ndo_open = ethoc_open,
853 .ndo_stop = ethoc_stop,
854 .ndo_do_ioctl = ethoc_ioctl,
855 .ndo_set_config = ethoc_config,
856 .ndo_set_mac_address = ethoc_set_mac_address,
857 .ndo_set_multicast_list = ethoc_set_multicast_list,
858 .ndo_change_mtu = ethoc_change_mtu,
859 .ndo_tx_timeout = ethoc_tx_timeout,
860 .ndo_get_stats = ethoc_stats,
861 .ndo_start_xmit = ethoc_start_xmit,
862};
863
864/**
865 * ethoc_probe() - initialize OpenCores ethernet MAC
866 * pdev: platform device
867 */
868static int ethoc_probe(struct platform_device *pdev)
869{
870 struct net_device *netdev = NULL;
871 struct resource *res = NULL;
872 struct resource *mmio = NULL;
873 struct resource *mem = NULL;
874 struct ethoc *priv = NULL;
875 unsigned int phy;
876 int ret = 0;
877
878 /* allocate networking device */
879 netdev = alloc_etherdev(sizeof(struct ethoc));
880 if (!netdev) {
881 dev_err(&pdev->dev, "cannot allocate network device\n");
882 ret = -ENOMEM;
883 goto out;
884 }
885
886 SET_NETDEV_DEV(netdev, &pdev->dev);
887 platform_set_drvdata(pdev, netdev);
888
889 /* obtain I/O memory space */
890 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
891 if (!res) {
892 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
893 ret = -ENXIO;
894 goto free;
895 }
896
897 mmio = devm_request_mem_region(&pdev->dev, res->start,
898 res->end - res->start + 1, res->name);
463889e2 899 if (!mmio) {
a1702857
TR		 900 dev_err(&pdev->dev, "cannot request I/O memory space\n");
901 ret = -ENXIO;
902 goto free;
903 }
904
905 netdev->base_addr = mmio->start;
906
907 /* obtain buffer memory space */
908 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
909 if (!res) {
910 dev_err(&pdev->dev, "cannot obtain memory space\n");
911 ret = -ENXIO;
912 goto free;
913 }
914
915 mem = devm_request_mem_region(&pdev->dev, res->start,
916 res->end - res->start + 1, res->name);
917 if (!mem) {
918 dev_err(&pdev->dev, "cannot request memory space\n");
919 ret = -ENXIO;
920 goto free;
921 }
922
923 netdev->mem_start = mem->start;
924 netdev->mem_end = mem->end;
925
926 /* obtain device IRQ number */
927 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
928 if (!res) {
929 dev_err(&pdev->dev, "cannot obtain IRQ\n");
930 ret = -ENXIO;
931 goto free;
932 }
933
934 netdev->irq = res->start;
935
936 /* setup driver-private data */
937 priv = netdev_priv(netdev);
938 priv->netdev = netdev;
939
940 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
941 mmio->end - mmio->start + 1);
942 if (!priv->iobase) {
943 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
944 ret = -ENXIO;
945 goto error;
946 }
947
948 priv->membase = devm_ioremap_nocache(&pdev->dev, netdev->mem_start,
949 mem->end - mem->start + 1);
950 if (!priv->membase) {
951 dev_err(&pdev->dev, "cannot remap memory space\n");
952 ret = -ENXIO;
953 goto error;
954 }
955
956 /* Allow the platform setup code to pass in a MAC address. */
957 if (pdev->dev.platform_data) {
958 struct ethoc_platform_data *pdata =
959 (struct ethoc_platform_data *)pdev->dev.platform_data;
960 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
961 priv->phy_id = pdata->phy_id;
962 }
963
964 /* Check that the given MAC address is valid. If it isn't, read the
965 * current MAC from the controller. */
966 if (!is_valid_ether_addr(netdev->dev_addr))
967 ethoc_get_mac_address(netdev, netdev->dev_addr);
968
969 /* Check the MAC again for validity, if it still isn't choose and
970 * program a random one. */
971 if (!is_valid_ether_addr(netdev->dev_addr))
972 random_ether_addr(netdev->dev_addr);
973
974 ethoc_set_mac_address(netdev, netdev->dev_addr);
975
976 /* register MII bus */
977 priv->mdio = mdiobus_alloc();
978 if (!priv->mdio) {
979 ret = -ENOMEM;
980 goto free;
981 }
982
983 priv->mdio->name = "ethoc-mdio";
984 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
985 priv->mdio->name, pdev->id);
986 priv->mdio->read = ethoc_mdio_read;
987 priv->mdio->write = ethoc_mdio_write;
988 priv->mdio->reset = ethoc_mdio_reset;
989 priv->mdio->priv = priv;
990
991 priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
992 if (!priv->mdio->irq) {
993 ret = -ENOMEM;
994 goto free_mdio;
995 }
996
997 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
998 priv->mdio->irq[phy] = PHY_POLL;
999
1000 ret = mdiobus_register(priv->mdio);
1001 if (ret) {
1002 dev_err(&netdev->dev, "failed to register MDIO bus\n");
1003 goto free_mdio;
1004 }
1005
1006 ret = ethoc_mdio_probe(netdev);
1007 if (ret) {
1008 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1009 goto error;
1010 }
1011
1012 ether_setup(netdev);
1013
1014 /* setup the net_device structure */
1015 netdev->netdev_ops = &ethoc_netdev_ops;
1016 netdev->watchdog_timeo = ETHOC_TIMEOUT;
1017 netdev->features |= 0;
1018
1019 /* setup NAPI */
1020 memset(&priv->napi, 0, sizeof(priv->napi));
1021 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1022
1023 spin_lock_init(&priv->rx_lock);
1024 spin_lock_init(&priv->lock);
1025
1026 ret = register_netdev(netdev);
1027 if (ret < 0) {
1028 dev_err(&netdev->dev, "failed to register interface\n");
1029 goto error;
1030 }
1031
1032 goto out;
1033
1034error:
1035 mdiobus_unregister(priv->mdio);
1036free_mdio:
1037 kfree(priv->mdio->irq);
1038 mdiobus_free(priv->mdio);
1039free:
1040 free_netdev(netdev);
1041out:
1042 return ret;
1043}
1044
1045/**
1046 * ethoc_remove() - shutdown OpenCores ethernet MAC
1047 * @pdev: platform device
1048 */
1049static int ethoc_remove(struct platform_device *pdev)
1050{
1051 struct net_device *netdev = platform_get_drvdata(pdev);
1052 struct ethoc *priv = netdev_priv(netdev);
1053
1054 platform_set_drvdata(pdev, NULL);
1055
1056 if (netdev) {
1057 phy_disconnect(priv->phy);
1058 priv->phy = NULL;
1059
1060 if (priv->mdio) {
1061 mdiobus_unregister(priv->mdio);
1062 kfree(priv->mdio->irq);
1063 mdiobus_free(priv->mdio);
1064 }
1065
1066 unregister_netdev(netdev);
1067 free_netdev(netdev);
1068 }
1069
1070 return 0;
1071}
1072
1073#ifdef CONFIG_PM
1074static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1075{
1076 return -ENOSYS;
1077}
1078
1079static int ethoc_resume(struct platform_device *pdev)
1080{
1081 return -ENOSYS;
1082}
1083#else
1084# define ethoc_suspend NULL
1085# define ethoc_resume NULL
1086#endif
1087
1088static struct platform_driver ethoc_driver = {
1089 .probe = ethoc_probe,
1090 .remove = ethoc_remove,
1091 .suspend = ethoc_suspend,
1092 .resume = ethoc_resume,
1093 .driver = {
1094 .name = "ethoc",
1095 },
1096};
1097
1098static int __init ethoc_init(void)
1099{
1100 return platform_driver_register(&ethoc_driver);
1101}
1102
1103static void __exit ethoc_exit(void)
1104{
1105 platform_driver_unregister(&ethoc_driver);
1106}
1107
1108module_init(ethoc_init);
1109module_exit(ethoc_exit);
1110
1111MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1112MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1113MODULE_LICENSE("GPL v2");
1114
Linux 6.x block layer and io_uring tree(s)