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tile_net: Implement the SIOCGHWTSTAMP ioctl
[linux-2.6-block.git] / drivers / net / ethernet / xscale / ixp4xx_eth.c
CommitLineData
dac2f83f
KH		 1/*
2 * Intel IXP4xx Ethernet driver for Linux
3 *
4 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 * Ethernet port config (0x00 is not present on IXP42X):
11 *
12 * logical port 0x00 0x10 0x20
13 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
14 * physical PortId 2 0 1
15 * TX queue 23 24 25
16 * RX-free queue 26 27 28
17 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
18 *
19 *
20 * Queue entries:
21 * bits 0 -> 1 - NPE ID (RX and TX-done)
22 * bits 0 -> 2 - priority (TX, per 802.1D)
23 * bits 3 -> 4 - port ID (user-set?)
24 * bits 5 -> 31 - physical descriptor address
25 */
26
27#include <linux/delay.h>
28#include <linux/dma-mapping.h>
29#include <linux/dmapool.h>
30#include <linux/etherdevice.h>
31#include <linux/io.h>
32#include <linux/kernel.h>
32bd93e8 33#include <linux/net_tstamp.h>
2098c18d 34#include <linux/phy.h>
dac2f83f 35#include <linux/platform_device.h>
32bd93e8 36#include <linux/ptp_classify.h>
5a0e3ad6 37#include <linux/slab.h>
9d9779e7 38#include <linux/module.h>
32bd93e8 39#include <mach/ixp46x_ts.h>
a09e64fb
RK		 40#include <mach/npe.h>
41#include <mach/qmgr.h>
dac2f83f 42
dac2f83f
KH		 43#define DEBUG_DESC 0
44#define DEBUG_RX 0
45#define DEBUG_TX 0
46#define DEBUG_PKT_BYTES 0
47#define DEBUG_MDIO 0
48#define DEBUG_CLOSE 0
49
50#define DRV_NAME "ixp4xx_eth"
51
52#define MAX_NPES 3
53
54#define RX_DESCS 64 /* also length of all RX queues */
55#define TX_DESCS 16 /* also length of all TX queues */
56#define TXDONE_QUEUE_LEN 64 /* dwords */
57
58#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
59#define REGS_SIZE 0x1000
60#define MAX_MRU 1536 /* 0x600 */
61#define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
62
63#define NAPI_WEIGHT 16
64#define MDIO_INTERVAL (3 * HZ)
65#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
dac2f83f
KH		 66#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
67
68#define NPE_ID(port_id) ((port_id) >> 4)
69#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
70#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
71#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
72#define TXDONE_QUEUE 31
73
32bd93e8
RC		 74#define PTP_SLAVE_MODE 1
75#define PTP_MASTER_MODE 2
76#define PORT2CHANNEL(p) NPE_ID(p->id)
77
dac2f83f
KH		 78/* TX Control Registers */
79#define TX_CNTRL0_TX_EN 0x01
80#define TX_CNTRL0_HALFDUPLEX 0x02
81#define TX_CNTRL0_RETRY 0x04
82#define TX_CNTRL0_PAD_EN 0x08
83#define TX_CNTRL0_APPEND_FCS 0x10
84#define TX_CNTRL0_2DEFER 0x20
85#define TX_CNTRL0_RMII 0x40 /* reduced MII */
86#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
87
88/* RX Control Registers */
89#define RX_CNTRL0_RX_EN 0x01
90#define RX_CNTRL0_PADSTRIP_EN 0x02
91#define RX_CNTRL0_SEND_FCS 0x04
92#define RX_CNTRL0_PAUSE_EN 0x08
93#define RX_CNTRL0_LOOP_EN 0x10
94#define RX_CNTRL0_ADDR_FLTR_EN 0x20
95#define RX_CNTRL0_RX_RUNT_EN 0x40
96#define RX_CNTRL0_BCAST_DIS 0x80
97#define RX_CNTRL1_DEFER_EN 0x01
98
99/* Core Control Register */
100#define CORE_RESET 0x01
101#define CORE_RX_FIFO_FLUSH 0x02
102#define CORE_TX_FIFO_FLUSH 0x04
103#define CORE_SEND_JAM 0x08
104#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
105
106#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
107 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
108 TX_CNTRL0_2DEFER)
109#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
110#define DEFAULT_CORE_CNTRL CORE_MDC_EN
111
112
113/* NPE message codes */
114#define NPE_GETSTATUS 0x00
115#define NPE_EDB_SETPORTADDRESS 0x01
116#define NPE_EDB_GETMACADDRESSDATABASE 0x02
117#define NPE_EDB_SETMACADDRESSSDATABASE 0x03
118#define NPE_GETSTATS 0x04
119#define NPE_RESETSTATS 0x05
120#define NPE_SETMAXFRAMELENGTHS 0x06
121#define NPE_VLAN_SETRXTAGMODE 0x07
122#define NPE_VLAN_SETDEFAULTRXVID 0x08
123#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
124#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
125#define NPE_VLAN_SETRXQOSENTRY 0x0B
126#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
127#define NPE_STP_SETBLOCKINGSTATE 0x0D
128#define NPE_FW_SETFIREWALLMODE 0x0E
129#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
130#define NPE_PC_SETAPMACTABLE 0x11
131#define NPE_SETLOOPBACK_MODE 0x12
132#define NPE_PC_SETBSSIDTABLE 0x13
133#define NPE_ADDRESS_FILTER_CONFIG 0x14
134#define NPE_APPENDFCSCONFIG 0x15
135#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
136#define NPE_MAC_RECOVERY_START 0x17
137
138
139#ifdef __ARMEB__
140typedef struct sk_buff buffer_t;
141#define free_buffer dev_kfree_skb
142#define free_buffer_irq dev_kfree_skb_irq
143#else
144typedef void buffer_t;
145#define free_buffer kfree
146#define free_buffer_irq kfree
147#endif
148
149struct eth_regs {
150 u32 tx_control[2], __res1[2]; /* 000 */
151 u32 rx_control[2], __res2[2]; /* 010 */
152 u32 random_seed, __res3[3]; /* 020 */
153 u32 partial_empty_threshold, __res4; /* 030 */
154 u32 partial_full_threshold, __res5; /* 038 */
155 u32 tx_start_bytes, __res6[3]; /* 040 */
156 u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
157 u32 tx_2part_deferral[2], __res8[2]; /* 060 */
158 u32 slot_time, __res9[3]; /* 070 */
159 u32 mdio_command[4]; /* 080 */
160 u32 mdio_status[4]; /* 090 */
161 u32 mcast_mask[6], __res10[2]; /* 0A0 */
162 u32 mcast_addr[6], __res11[2]; /* 0C0 */
163 u32 int_clock_threshold, __res12[3]; /* 0E0 */
164 u32 hw_addr[6], __res13[61]; /* 0F0 */
165 u32 core_control; /* 1FC */
166};
167
168struct port {
169 struct resource *mem_res;
170 struct eth_regs __iomem *regs;
171 struct npe *npe;
172 struct net_device *netdev;
173 struct napi_struct napi;
2098c18d 174 struct phy_device *phydev;
dac2f83f
KH		 175 struct eth_plat_info *plat;
176 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
177 struct desc *desc_tab; /* coherent */
178 u32 desc_tab_phys;
179 int id; /* logical port ID */
2098c18d 180 int speed, duplex;
490b7722 181 u8 firmware[4];
32bd93e8
RC		 182 int hwts_tx_en;
183 int hwts_rx_en;
dac2f83f
KH		 184};
185
186/* NPE message structure */
187struct msg {
188#ifdef __ARMEB__
189 u8 cmd, eth_id, byte2, byte3;
190 u8 byte4, byte5, byte6, byte7;
191#else
192 u8 byte3, byte2, eth_id, cmd;
193 u8 byte7, byte6, byte5, byte4;
194#endif
195};
196
197/* Ethernet packet descriptor */
198struct desc {
199 u32 next; /* pointer to next buffer, unused */
200
201#ifdef __ARMEB__
202 u16 buf_len; /* buffer length */
203 u16 pkt_len; /* packet length */
204 u32 data; /* pointer to data buffer in RAM */
205 u8 dest_id;
206 u8 src_id;
207 u16 flags;
208 u8 qos;
209 u8 padlen;
210 u16 vlan_tci;
211#else
212 u16 pkt_len; /* packet length */
213 u16 buf_len; /* buffer length */
214 u32 data; /* pointer to data buffer in RAM */
215 u16 flags;
216 u8 src_id;
217 u8 dest_id;
218 u16 vlan_tci;
219 u8 padlen;
220 u8 qos;
221#endif
222
223#ifdef __ARMEB__
224 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
225 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
226 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
227#else
228 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
229 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
230 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
231#endif
232};
233
234
235#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
236 (n) * sizeof(struct desc))
237#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
238
239#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
240 ((n) + RX_DESCS) * sizeof(struct desc))
241#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
242
243#ifndef __ARMEB__
244static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
245{
246 int i;
247 for (i = 0; i < cnt; i++)
248 dest[i] = swab32(src[i]);
249}
250#endif
251
252static spinlock_t mdio_lock;
253static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
0409cb0d 254static struct mii_bus *mdio_bus;
dac2f83f
KH		 255static int ports_open;
256static struct port *npe_port_tab[MAX_NPES];
257static struct dma_pool *dma_pool;
258
32bd93e8
RC		 259static struct sock_filter ptp_filter[] = {
260 PTP_FILTER
261};
262
263static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
264{
265 u8 *data = skb->data;
266 unsigned int offset;
267 u16 *hi, *id;
268 u32 lo;
269
270 if (sk_run_filter(skb, ptp_filter) != PTP_CLASS_V1_IPV4)
271 return 0;
272
273 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
274
275 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
276 return 0;
277
278 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
279 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
280
281 memcpy(&lo, &hi[1], sizeof(lo));
282
283 return (uid_hi == ntohs(*hi) &&
284 uid_lo == ntohl(lo) &&
285 seqid == ntohs(*id));
286}
287
288static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb)
289{
290 struct skb_shared_hwtstamps *shhwtstamps;
291 struct ixp46x_ts_regs *regs;
292 u64 ns;
293 u32 ch, hi, lo, val;
294 u16 uid, seq;
295
296 if (!port->hwts_rx_en)
297 return;
298
299 ch = PORT2CHANNEL(port);
300
301 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
302
303 val = __raw_readl(&regs->channel[ch].ch_event);
304
305 if (!(val & RX_SNAPSHOT_LOCKED))
306 return;
307
308 lo = __raw_readl(&regs->channel[ch].src_uuid_lo);
309 hi = __raw_readl(&regs->channel[ch].src_uuid_hi);
310
311 uid = hi & 0xffff;
312 seq = (hi >> 16) & 0xffff;
313
314 if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
315 goto out;
316
317 lo = __raw_readl(&regs->channel[ch].rx_snap_lo);
318 hi = __raw_readl(&regs->channel[ch].rx_snap_hi);
319 ns = ((u64) hi) << 32;
320 ns |= lo;
321 ns <<= TICKS_NS_SHIFT;
322
323 shhwtstamps = skb_hwtstamps(skb);
324 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
325 shhwtstamps->hwtstamp = ns_to_ktime(ns);
326out:
327 __raw_writel(RX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);
328}
329
330static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb)
331{
332 struct skb_shared_hwtstamps shhwtstamps;
333 struct ixp46x_ts_regs *regs;
334 struct skb_shared_info *shtx;
335 u64 ns;
336 u32 ch, cnt, hi, lo, val;
337
338 shtx = skb_shinfo(skb);
339 if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en))
340 shtx->tx_flags |= SKBTX_IN_PROGRESS;
341 else
342 return;
343
344 ch = PORT2CHANNEL(port);
345
346 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
347
348 /*
349 * This really stinks, but we have to poll for the Tx time stamp.
350 * Usually, the time stamp is ready after 4 to 6 microseconds.
351 */
352 for (cnt = 0; cnt < 100; cnt++) {
353 val = __raw_readl(&regs->channel[ch].ch_event);
354 if (val & TX_SNAPSHOT_LOCKED)
355 break;
356 udelay(1);
357 }
358 if (!(val & TX_SNAPSHOT_LOCKED)) {
359 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
360 return;
361 }
362
363 lo = __raw_readl(&regs->channel[ch].tx_snap_lo);
364 hi = __raw_readl(&regs->channel[ch].tx_snap_hi);
365 ns = ((u64) hi) << 32;
366 ns |= lo;
367 ns <<= TICKS_NS_SHIFT;
368
369 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
370 shhwtstamps.hwtstamp = ns_to_ktime(ns);
371 skb_tstamp_tx(skb, &shhwtstamps);
372
373 __raw_writel(TX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);
374}
375
376static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
377{
378 struct hwtstamp_config cfg;
379 struct ixp46x_ts_regs *regs;
380 struct port *port = netdev_priv(netdev);
381 int ch;
382
383 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
384 return -EFAULT;
385
386 if (cfg.flags) /* reserved for future extensions */
387 return -EINVAL;
388
389 ch = PORT2CHANNEL(port);
390 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
391
a5be8cd3 392 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
32bd93e8 393 return -ERANGE;
32bd93e8
RC		 394
395 switch (cfg.rx_filter) {
396 case HWTSTAMP_FILTER_NONE:
397 port->hwts_rx_en = 0;
398 break;
399 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
400 port->hwts_rx_en = PTP_SLAVE_MODE;
401 __raw_writel(0, &regs->channel[ch].ch_control);
402 break;
403 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
404 port->hwts_rx_en = PTP_MASTER_MODE;
405 __raw_writel(MASTER_MODE, &regs->channel[ch].ch_control);
406 break;
407 default:
408 return -ERANGE;
409 }
410
a5be8cd3
BH		 411 port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
412
32bd93e8
RC		 413 /* Clear out any old time stamps. */
414 __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
415 &regs->channel[ch].ch_event);
416
417 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
418}
dac2f83f 419
2098c18d
KH		 420static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
421 int write, u16 cmd)
dac2f83f
KH		 422{
423 int cycles = 0;
424
425 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
2098c18d
KH		 426 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
427 return -1;
dac2f83f
KH		 428 }
429
430 if (write) {
431 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
432 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
433 }
434 __raw_writel(((phy_id << 5) | location) & 0xFF,
435 &mdio_regs->mdio_command[2]);
436 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
437 &mdio_regs->mdio_command[3]);
438
439 while ((cycles < MAX_MDIO_RETRIES) &&
440 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
441 udelay(1);
442 cycles++;
443 }
444
445 if (cycles == MAX_MDIO_RETRIES) {
2098c18d
KH		 446 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
447 phy_id);
448 return -1;
dac2f83f
KH		 449 }
450
451#if DEBUG_MDIO
2098c18d
KH		 452 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
453 phy_id, write ? "write" : "read", cycles);
dac2f83f
KH		 454#endif
455
456 if (write)
457 return 0;
458
459 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
2098c18d
KH		 460#if DEBUG_MDIO
461 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
462 phy_id);
463#endif
464 return 0xFFFF; /* don't return error */
dac2f83f
KH		 465 }
466
467 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
2098c18d 468 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
dac2f83f
KH		 469}
470
2098c18d 471static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
dac2f83f
KH		 472{
473 unsigned long flags;
2098c18d 474 int ret;
dac2f83f
KH		 475
476 spin_lock_irqsave(&mdio_lock, flags);
2098c18d 477 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
dac2f83f 478 spin_unlock_irqrestore(&mdio_lock, flags);
2098c18d
KH		 479#if DEBUG_MDIO
480 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
481 phy_id, location, ret);
482#endif
483 return ret;
dac2f83f
KH		 484}
485
2098c18d
KH		 486static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
487 u16 val)
dac2f83f
KH		 488{
489 unsigned long flags;
2098c18d 490 int ret;
dac2f83f
KH		 491
492 spin_lock_irqsave(&mdio_lock, flags);
2098c18d 493 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
dac2f83f 494 spin_unlock_irqrestore(&mdio_lock, flags);
2098c18d 495#if DEBUG_MDIO
8ae45a53 496 printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n",
2098c18d
KH		 497 bus->name, phy_id, location, val, ret);
498#endif
499 return ret;
dac2f83f
KH		 500}
501
2098c18d 502static int ixp4xx_mdio_register(void)
dac2f83f 503{
2098c18d 504 int err;
dac2f83f 505
2098c18d
KH		 506 if (!(mdio_bus = mdiobus_alloc()))
507 return -ENOMEM;
dac2f83f 508
5ca328d2
KH		 509 if (cpu_is_ixp43x()) {
510 /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
511 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH))
3ba8c792 512 return -ENODEV;
5ca328d2
KH		 513 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
514 } else {
515 /* All MII PHY accesses use NPE-B Ethernet registers */
516 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
3ba8c792 517 return -ENODEV;
5ca328d2
KH		 518 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
519 }
dac2f83f 520
5ca328d2
KH		 521 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
522 spin_lock_init(&mdio_lock);
2098c18d
KH		 523 mdio_bus->name = "IXP4xx MII Bus";
524 mdio_bus->read = &ixp4xx_mdio_read;
525 mdio_bus->write = &ixp4xx_mdio_write;
0869b3a4 526 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0");
dac2f83f 527
2098c18d
KH		 528 if ((err = mdiobus_register(mdio_bus)))
529 mdiobus_free(mdio_bus);
530 return err;
dac2f83f
KH		 531}
532
2098c18d 533static void ixp4xx_mdio_remove(void)
dac2f83f 534{
2098c18d
KH		 535 mdiobus_unregister(mdio_bus);
536 mdiobus_free(mdio_bus);
dac2f83f
KH		 537}
538
539
2098c18d 540static void ixp4xx_adjust_link(struct net_device *dev)
dac2f83f 541{
2098c18d
KH		 542 struct port *port = netdev_priv(dev);
543 struct phy_device *phydev = port->phydev;
544
545 if (!phydev->link) {
546 if (port->speed) {
547 port->speed = 0;
dac2f83f 548 printk(KERN_INFO "%s: link down\n", dev->name);
dac2f83f 549 }
2098c18d 550 return;
dac2f83f 551 }
dac2f83f 552
2098c18d
KH		 553 if (port->speed == phydev->speed && port->duplex == phydev->duplex)
554 return;
dac2f83f 555
2098c18d
KH		 556 port->speed = phydev->speed;
557 port->duplex = phydev->duplex;
dac2f83f 558
2098c18d
KH		 559 if (port->duplex)
560 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
561 &port->regs->tx_control[0]);
562 else
563 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
564 &port->regs->tx_control[0]);
dac2f83f 565
2098c18d
KH		 566 printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
567 dev->name, port->speed, port->duplex ? "full" : "half");
dac2f83f
KH		 568}
569
570
571static inline void debug_pkt(struct net_device *dev, const char *func,
572 u8 *data, int len)
573{
574#if DEBUG_PKT_BYTES
575 int i;
576
577 printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
578 for (i = 0; i < len; i++) {
579 if (i >= DEBUG_PKT_BYTES)
580 break;
581 printk("%s%02X",
582 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
583 data[i]);
584 }
585 printk("\n");
586#endif
587}
588
589
590static inline void debug_desc(u32 phys, struct desc *desc)
591{
592#if DEBUG_DESC
593 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
594 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
595 phys, desc->next, desc->buf_len, desc->pkt_len,
596 desc->data, desc->dest_id, desc->src_id, desc->flags,
597 desc->qos, desc->padlen, desc->vlan_tci,
598 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
599 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
600 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
601 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
602#endif
603}
604
dac2f83f
KH		 605static inline int queue_get_desc(unsigned int queue, struct port *port,
606 int is_tx)
607{
608 u32 phys, tab_phys, n_desc;
609 struct desc *tab;
610
e6da96ac 611 if (!(phys = qmgr_get_entry(queue)))
dac2f83f
KH		 612 return -1;
613
614 phys &= ~0x1F; /* mask out non-address bits */
615 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
616 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
617 n_desc = (phys - tab_phys) / sizeof(struct desc);
618 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
619 debug_desc(phys, &tab[n_desc]);
620 BUG_ON(tab[n_desc].next);
621 return n_desc;
622}
623
624static inline void queue_put_desc(unsigned int queue, u32 phys,
625 struct desc *desc)
626{
dac2f83f
KH		 627 debug_desc(phys, desc);
628 BUG_ON(phys & 0x1F);
629 qmgr_put_entry(queue, phys);
6a68afe3
KH		 630 /* Don't check for queue overflow here, we've allocated sufficient
631 length and queues >= 32 don't support this check anyway. */
dac2f83f
KH		 632}
633
634
635static inline void dma_unmap_tx(struct port *port, struct desc *desc)
636{
637#ifdef __ARMEB__
638 dma_unmap_single(&port->netdev->dev, desc->data,
639 desc->buf_len, DMA_TO_DEVICE);
640#else
641 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
642 ALIGN((desc->data & 3) + desc->buf_len, 4),
643 DMA_TO_DEVICE);
644#endif
645}
646
647
648static void eth_rx_irq(void *pdev)
649{
650 struct net_device *dev = pdev;
651 struct port *port = netdev_priv(dev);
652
653#if DEBUG_RX
654 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
655#endif
656 qmgr_disable_irq(port->plat->rxq);
288379f0 657 napi_schedule(&port->napi);
dac2f83f
KH		 658}
659
660static int eth_poll(struct napi_struct *napi, int budget)
661{
662 struct port *port = container_of(napi, struct port, napi);
663 struct net_device *dev = port->netdev;
664 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
665 int received = 0;
666
667#if DEBUG_RX
668 printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
669#endif
670
671 while (received < budget) {
672 struct sk_buff *skb;
673 struct desc *desc;
674 int n;
675#ifdef __ARMEB__
676 struct sk_buff *temp;
677 u32 phys;
678#endif
679
680 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
dac2f83f 681#if DEBUG_RX
288379f0 682 printk(KERN_DEBUG "%s: eth_poll napi_complete\n",
dac2f83f
KH		 683 dev->name);
684#endif
288379f0 685 napi_complete(napi);
dac2f83f 686 qmgr_enable_irq(rxq);
9733bb8e
KH		 687 if (!qmgr_stat_below_low_watermark(rxq) &&
688 napi_reschedule(napi)) { /* not empty again */
dac2f83f
KH		 689#if DEBUG_RX
690 printk(KERN_DEBUG "%s: eth_poll"
288379f0 691 " napi_reschedule successed\n",
dac2f83f
KH		 692 dev->name);
693#endif
694 qmgr_disable_irq(rxq);
695 continue;
696 }
697#if DEBUG_RX
698 printk(KERN_DEBUG "%s: eth_poll all done\n",
699 dev->name);
700#endif
9076689a 701 return received; /* all work done */
dac2f83f
KH		 702 }
703
704 desc = rx_desc_ptr(port, n);
705
706#ifdef __ARMEB__
707 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
708 phys = dma_map_single(&dev->dev, skb->data,
709 RX_BUFF_SIZE, DMA_FROM_DEVICE);
7144decb 710 if (dma_mapping_error(&dev->dev, phys)) {
dac2f83f
KH		 711 dev_kfree_skb(skb);
712 skb = NULL;
713 }
714 }
715#else
716 skb = netdev_alloc_skb(dev,
717 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
718#endif
719
720 if (!skb) {
b4c7d3b0 721 dev->stats.rx_dropped++;
dac2f83f
KH		 722 /* put the desc back on RX-ready queue */
723 desc->buf_len = MAX_MRU;
724 desc->pkt_len = 0;
725 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
726 continue;
727 }
728
729 /* process received frame */
730#ifdef __ARMEB__
731 temp = skb;
732 skb = port->rx_buff_tab[n];
733 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
734 RX_BUFF_SIZE, DMA_FROM_DEVICE);
735#else
5d23a1d2
FT		 736 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN,
737 RX_BUFF_SIZE, DMA_FROM_DEVICE);
dac2f83f
KH		 738 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
739 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
740#endif
741 skb_reserve(skb, NET_IP_ALIGN);
742 skb_put(skb, desc->pkt_len);
743
744 debug_pkt(dev, "eth_poll", skb->data, skb->len);
745
32bd93e8 746 ixp_rx_timestamp(port, skb);
dac2f83f 747 skb->protocol = eth_type_trans(skb, dev);
b4c7d3b0
KH		 748 dev->stats.rx_packets++;
749 dev->stats.rx_bytes += skb->len;
dac2f83f
KH		 750 netif_receive_skb(skb);
751
752 /* put the new buffer on RX-free queue */
753#ifdef __ARMEB__
754 port->rx_buff_tab[n] = temp;
755 desc->data = phys + NET_IP_ALIGN;
756#endif
757 desc->buf_len = MAX_MRU;
758 desc->pkt_len = 0;
759 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
760 received++;
761 }
762
763#if DEBUG_RX
764 printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
765#endif
766 return received; /* not all work done */
767}
768
769
770static void eth_txdone_irq(void *unused)
771{
772 u32 phys;
773
774#if DEBUG_TX
775 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
776#endif
e6da96ac 777 while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {
dac2f83f
KH		 778 u32 npe_id, n_desc;
779 struct port *port;
780 struct desc *desc;
781 int start;
782
783 npe_id = phys & 3;
784 BUG_ON(npe_id >= MAX_NPES);
785 port = npe_port_tab[npe_id];
786 BUG_ON(!port);
787 phys &= ~0x1F; /* mask out non-address bits */
788 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
789 BUG_ON(n_desc >= TX_DESCS);
790 desc = tx_desc_ptr(port, n_desc);
791 debug_desc(phys, desc);
792
793 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
b4c7d3b0
KH		 794 port->netdev->stats.tx_packets++;
795 port->netdev->stats.tx_bytes += desc->pkt_len;
dac2f83f
KH		 796
797 dma_unmap_tx(port, desc);
798#if DEBUG_TX
799 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
800 port->netdev->name, port->tx_buff_tab[n_desc]);
801#endif
802 free_buffer_irq(port->tx_buff_tab[n_desc]);
803 port->tx_buff_tab[n_desc] = NULL;
804 }
805
9733bb8e 806 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
dac2f83f 807 queue_put_desc(port->plat->txreadyq, phys, desc);
9733bb8e 808 if (start) { /* TX-ready queue was empty */
dac2f83f
KH		 809#if DEBUG_TX
810 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
811 port->netdev->name);
812#endif
813 netif_wake_queue(port->netdev);
814 }
815 }
816}
817
818static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
819{
820 struct port *port = netdev_priv(dev);
821 unsigned int txreadyq = port->plat->txreadyq;
822 int len, offset, bytes, n;
823 void *mem;
824 u32 phys;
825 struct desc *desc;
826
827#if DEBUG_TX
828 printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
829#endif
830
831 if (unlikely(skb->len > MAX_MRU)) {
832 dev_kfree_skb(skb);
b4c7d3b0 833 dev->stats.tx_errors++;
dac2f83f
KH		 834 return NETDEV_TX_OK;
835 }
836
837 debug_pkt(dev, "eth_xmit", skb->data, skb->len);
838
839 len = skb->len;
840#ifdef __ARMEB__
841 offset = 0; /* no need to keep alignment */
842 bytes = len;
843 mem = skb->data;
844#else
845 offset = (int)skb->data & 3; /* keep 32-bit alignment */
846 bytes = ALIGN(offset + len, 4);
847 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
848 dev_kfree_skb(skb);
b4c7d3b0 849 dev->stats.tx_dropped++;
dac2f83f
KH		 850 return NETDEV_TX_OK;
851 }
852 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
dac2f83f
KH		 853#endif
854
855 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
7144decb 856 if (dma_mapping_error(&dev->dev, phys)) {
dac2f83f 857 dev_kfree_skb(skb);
32bd93e8 858#ifndef __ARMEB__
dac2f83f
KH		 859 kfree(mem);
860#endif
b4c7d3b0 861 dev->stats.tx_dropped++;
dac2f83f
KH		 862 return NETDEV_TX_OK;
863 }
864
865 n = queue_get_desc(txreadyq, port, 1);
866 BUG_ON(n < 0);
867 desc = tx_desc_ptr(port, n);
868
869#ifdef __ARMEB__
870 port->tx_buff_tab[n] = skb;
871#else
872 port->tx_buff_tab[n] = mem;
873#endif
874 desc->data = phys + offset;
875 desc->buf_len = desc->pkt_len = len;
876
877 /* NPE firmware pads short frames with zeros internally */
878 wmb();
879 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
dac2f83f 880
9733bb8e 881 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
dac2f83f
KH		 882#if DEBUG_TX
883 printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
884#endif
885 netif_stop_queue(dev);
886 /* we could miss TX ready interrupt */
6a68afe3 887 /* really empty in fact */
9733bb8e 888 if (!qmgr_stat_below_low_watermark(txreadyq)) {
dac2f83f
KH		 889#if DEBUG_TX
890 printk(KERN_DEBUG "%s: eth_xmit ready again\n",
891 dev->name);
892#endif
893 netif_wake_queue(dev);
894 }
895 }
896
897#if DEBUG_TX
898 printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
899#endif
32bd93e8
RC		 900
901 ixp_tx_timestamp(port, skb);
902 skb_tx_timestamp(skb);
903
904#ifndef __ARMEB__
905 dev_kfree_skb(skb);
906#endif
dac2f83f
KH		 907 return NETDEV_TX_OK;
908}
909
910
dac2f83f
KH		 911static void eth_set_mcast_list(struct net_device *dev)
912{
913 struct port *port = netdev_priv(dev);
22bedad3 914 struct netdev_hw_addr *ha;
dac2f83f 915 u8 diffs[ETH_ALEN], *addr;
3b9a7728 916 int i;
95e3bb7a
RC		 917 static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
918
919 if (dev->flags & IFF_ALLMULTI) {
920 for (i = 0; i < ETH_ALEN; i++) {
921 __raw_writel(allmulti[i], &port->regs->mcast_addr[i]);
922 __raw_writel(allmulti[i], &port->regs->mcast_mask[i]);
923 }
924 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
925 &port->regs->rx_control[0]);
926 return;
927 }
dac2f83f 928
3b9a7728 929 if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) {
dac2f83f
KH		 930 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
931 &port->regs->rx_control[0]);
932 return;
933 }
934
935 memset(diffs, 0, ETH_ALEN);
dac2f83f 936
3b9a7728 937 addr = NULL;
22bedad3 938 netdev_for_each_mc_addr(ha, dev) {
3b9a7728 939 if (!addr)
22bedad3 940 addr = ha->addr; /* first MAC address */
dac2f83f 941 for (i = 0; i < ETH_ALEN; i++)
22bedad3 942 diffs[i] |= addr[i] ^ ha->addr[i];
3b9a7728 943 }
dac2f83f
KH		 944
945 for (i = 0; i < ETH_ALEN; i++) {
946 __raw_writel(addr[i], &port->regs->mcast_addr[i]);
947 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
948 }
949
950 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
951 &port->regs->rx_control[0]);
952}
953
954
955static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
956{
957 struct port *port = netdev_priv(dev);
dac2f83f
KH		 958
959 if (!netif_running(dev))
960 return -EINVAL;
28b04113 961
32bd93e8
RC		 962 if (cpu_is_ixp46x() && cmd == SIOCSHWTSTAMP)
963 return hwtstamp_ioctl(dev, req, cmd);
964
28b04113 965 return phy_mii_ioctl(port->phydev, req, cmd);
dac2f83f
KH		 966}
967
490b7722
KH		 968/* ethtool support */
969
970static void ixp4xx_get_drvinfo(struct net_device *dev,
971 struct ethtool_drvinfo *info)
972{
973 struct port *port = netdev_priv(dev);
7826d43f
JP		 974
975 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
490b7722
KH		 976 snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",
977 port->firmware[0], port->firmware[1],
978 port->firmware[2], port->firmware[3]);
7826d43f 979 strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
dac2f83f
KH		 980}
981
490b7722
KH		 982static int ixp4xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
983{
984 struct port *port = netdev_priv(dev);
985 return phy_ethtool_gset(port->phydev, cmd);
986}
987
988static int ixp4xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
989{
990 struct port *port = netdev_priv(dev);
991 return phy_ethtool_sset(port->phydev, cmd);
992}
993
994static int ixp4xx_nway_reset(struct net_device *dev)
995{
996 struct port *port = netdev_priv(dev);
997 return phy_start_aneg(port->phydev);
998}
999
509a7c25 1000int ixp46x_phc_index = -1;
8b82f7c3 1001EXPORT_SYMBOL_GPL(ixp46x_phc_index);
509a7c25
RC		 1002
1003static int ixp4xx_get_ts_info(struct net_device *dev,
1004 struct ethtool_ts_info *info)
1005{
1006 if (!cpu_is_ixp46x()) {
1007 info->so_timestamping =
1008 SOF_TIMESTAMPING_TX_SOFTWARE |
1009 SOF_TIMESTAMPING_RX_SOFTWARE |
1010 SOF_TIMESTAMPING_SOFTWARE;
1011 info->phc_index = -1;
1012 return 0;
1013 }
1014 info->so_timestamping =
1015 SOF_TIMESTAMPING_TX_HARDWARE |
1016 SOF_TIMESTAMPING_RX_HARDWARE |
1017 SOF_TIMESTAMPING_RAW_HARDWARE;
1018 info->phc_index = ixp46x_phc_index;
1019 info->tx_types =
1020 (1 << HWTSTAMP_TX_OFF) |
1021 (1 << HWTSTAMP_TX_ON);
1022 info->rx_filters =
1023 (1 << HWTSTAMP_FILTER_NONE) |
1024 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1025 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ);
1026 return 0;
1027}
1028
0fc0b732 1029static const struct ethtool_ops ixp4xx_ethtool_ops = {
490b7722
KH		 1030 .get_drvinfo = ixp4xx_get_drvinfo,
1031 .get_settings = ixp4xx_get_settings,
1032 .set_settings = ixp4xx_set_settings,
1033 .nway_reset = ixp4xx_nway_reset,
1034 .get_link = ethtool_op_get_link,
509a7c25 1035 .get_ts_info = ixp4xx_get_ts_info,
490b7722
KH		 1036};
1037
dac2f83f
KH		 1038
1039static int request_queues(struct port *port)
1040{
1041 int err;
1042
e6da96ac 1043 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,
2e418400 1044 "%s:RX-free", port->netdev->name);
dac2f83f
KH		 1045 if (err)
1046 return err;
1047
e6da96ac 1048 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,
2e418400 1049 "%s:RX", port->netdev->name);
dac2f83f
KH		 1050 if (err)
1051 goto rel_rxfree;
1052
e6da96ac 1053 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,
2e418400 1054 "%s:TX", port->netdev->name);
dac2f83f
KH		 1055 if (err)
1056 goto rel_rx;
1057
e6da96ac 1058 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
2e418400 1059 "%s:TX-ready", port->netdev->name);
dac2f83f
KH		 1060 if (err)
1061 goto rel_tx;
1062
1063 /* TX-done queue handles skbs sent out by the NPEs */
1064 if (!ports_open) {
e6da96ac 1065 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
2e418400 1066 "%s:TX-done", DRV_NAME);
dac2f83f
KH		 1067 if (err)
1068 goto rel_txready;
1069 }
1070 return 0;
1071
1072rel_txready:
1073 qmgr_release_queue(port->plat->txreadyq);
1074rel_tx:
1075 qmgr_release_queue(TX_QUEUE(port->id));
1076rel_rx:
1077 qmgr_release_queue(port->plat->rxq);
1078rel_rxfree:
1079 qmgr_release_queue(RXFREE_QUEUE(port->id));
1080 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1081 port->netdev->name);
1082 return err;
1083}
1084
1085static void release_queues(struct port *port)
1086{
1087 qmgr_release_queue(RXFREE_QUEUE(port->id));
1088 qmgr_release_queue(port->plat->rxq);
1089 qmgr_release_queue(TX_QUEUE(port->id));
1090 qmgr_release_queue(port->plat->txreadyq);
1091
1092 if (!ports_open)
1093 qmgr_release_queue(TXDONE_QUEUE);
1094}
1095
1096static int init_queues(struct port *port)
1097{
1098 int i;
1099
1a490117
XW		 1100 if (!ports_open) {
1101 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
1102 POOL_ALLOC_SIZE, 32, 0);
1103 if (!dma_pool)
dac2f83f 1104 return -ENOMEM;
1a490117 1105 }
dac2f83f
KH		 1106
1107 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
1108 &port->desc_tab_phys)))
1109 return -ENOMEM;
1110 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
1111 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
1112 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
1113
1114 /* Setup RX buffers */
1115 for (i = 0; i < RX_DESCS; i++) {
1116 struct desc *desc = rx_desc_ptr(port, i);
1117 buffer_t *buff; /* skb or kmalloc()ated memory */
1118 void *data;
1119#ifdef __ARMEB__
1120 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
1121 return -ENOMEM;
1122 data = buff->data;
1123#else
1124 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
1125 return -ENOMEM;
1126 data = buff;
1127#endif
1128 desc->buf_len = MAX_MRU;
1129 desc->data = dma_map_single(&port->netdev->dev, data,
1130 RX_BUFF_SIZE, DMA_FROM_DEVICE);
7144decb 1131 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
dac2f83f
KH		 1132 free_buffer(buff);
1133 return -EIO;
1134 }
1135 desc->data += NET_IP_ALIGN;
1136 port->rx_buff_tab[i] = buff;
1137 }
1138
1139 return 0;
1140}
1141
1142static void destroy_queues(struct port *port)
1143{
1144 int i;
1145
1146 if (port->desc_tab) {
1147 for (i = 0; i < RX_DESCS; i++) {
1148 struct desc *desc = rx_desc_ptr(port, i);
1149 buffer_t *buff = port->rx_buff_tab[i];
1150 if (buff) {
1151 dma_unmap_single(&port->netdev->dev,
1152 desc->data - NET_IP_ALIGN,
1153 RX_BUFF_SIZE, DMA_FROM_DEVICE);
1154 free_buffer(buff);
1155 }
1156 }
1157 for (i = 0; i < TX_DESCS; i++) {
1158 struct desc *desc = tx_desc_ptr(port, i);
1159 buffer_t *buff = port->tx_buff_tab[i];
1160 if (buff) {
1161 dma_unmap_tx(port, desc);
1162 free_buffer(buff);
1163 }
1164 }
1165 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1166 port->desc_tab = NULL;
1167 }
1168
1169 if (!ports_open && dma_pool) {
1170 dma_pool_destroy(dma_pool);
1171 dma_pool = NULL;
1172 }
1173}
1174
1175static int eth_open(struct net_device *dev)
1176{
1177 struct port *port = netdev_priv(dev);
1178 struct npe *npe = port->npe;
1179 struct msg msg;
1180 int i, err;
1181
1182 if (!npe_running(npe)) {
1183 err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
1184 if (err)
1185 return err;
1186
1187 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
1188 printk(KERN_ERR "%s: %s not responding\n", dev->name,
1189 npe_name(npe));
1190 return -EIO;
1191 }
490b7722
KH		 1192 port->firmware[0] = msg.byte4;
1193 port->firmware[1] = msg.byte5;
1194 port->firmware[2] = msg.byte6;
1195 port->firmware[3] = msg.byte7;
dac2f83f
KH		 1196 }
1197
dac2f83f
KH		 1198 memset(&msg, 0, sizeof(msg));
1199 msg.cmd = NPE_VLAN_SETRXQOSENTRY;
1200 msg.eth_id = port->id;
1201 msg.byte5 = port->plat->rxq | 0x80;
1202 msg.byte7 = port->plat->rxq << 4;
1203 for (i = 0; i < 8; i++) {
1204 msg.byte3 = i;
1205 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
1206 return -EIO;
1207 }
1208
1209 msg.cmd = NPE_EDB_SETPORTADDRESS;
1210 msg.eth_id = PHYSICAL_ID(port->id);
1211 msg.byte2 = dev->dev_addr[0];
1212 msg.byte3 = dev->dev_addr[1];
1213 msg.byte4 = dev->dev_addr[2];
1214 msg.byte5 = dev->dev_addr[3];
1215 msg.byte6 = dev->dev_addr[4];
1216 msg.byte7 = dev->dev_addr[5];
1217 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1218 return -EIO;
1219
1220 memset(&msg, 0, sizeof(msg));
1221 msg.cmd = NPE_FW_SETFIREWALLMODE;
1222 msg.eth_id = port->id;
1223 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1224 return -EIO;
1225
1226 if ((err = request_queues(port)) != 0)
1227 return err;
1228
1229 if ((err = init_queues(port)) != 0) {
1230 destroy_queues(port);
1231 release_queues(port);
1232 return err;
1233 }
1234
2098c18d
KH		 1235 port->speed = 0; /* force "link up" message */
1236 phy_start(port->phydev);
1237
dac2f83f
KH		 1238 for (i = 0; i < ETH_ALEN; i++)
1239 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1240 __raw_writel(0x08, &port->regs->random_seed);
1241 __raw_writel(0x12, &port->regs->partial_empty_threshold);
1242 __raw_writel(0x30, &port->regs->partial_full_threshold);
1243 __raw_writel(0x08, &port->regs->tx_start_bytes);
1244 __raw_writel(0x15, &port->regs->tx_deferral);
1245 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1246 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1247 __raw_writel(0x80, &port->regs->slot_time);
1248 __raw_writel(0x01, &port->regs->int_clock_threshold);
1249
1250 /* Populate queues with buffers, no failure after this point */
1251 for (i = 0; i < TX_DESCS; i++)
1252 queue_put_desc(port->plat->txreadyq,
1253 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1254
1255 for (i = 0; i < RX_DESCS; i++)
1256 queue_put_desc(RXFREE_QUEUE(port->id),
1257 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1258
1259 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1260 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1261 __raw_writel(0, &port->regs->rx_control[1]);
1262 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1263
1264 napi_enable(&port->napi);
dac2f83f
KH		 1265 eth_set_mcast_list(dev);
1266 netif_start_queue(dev);
dac2f83f
KH		 1267
1268 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1269 eth_rx_irq, dev);
1270 if (!ports_open) {
1271 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1272 eth_txdone_irq, NULL);
1273 qmgr_enable_irq(TXDONE_QUEUE);
1274 }
1275 ports_open++;
1276 /* we may already have RX data, enables IRQ */
288379f0 1277 napi_schedule(&port->napi);
dac2f83f
KH		 1278 return 0;
1279}
1280
1281static int eth_close(struct net_device *dev)
1282{
1283 struct port *port = netdev_priv(dev);
1284 struct msg msg;
1285 int buffs = RX_DESCS; /* allocated RX buffers */
1286 int i;
1287
1288 ports_open--;
1289 qmgr_disable_irq(port->plat->rxq);
1290 napi_disable(&port->napi);
1291 netif_stop_queue(dev);
1292
1293 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1294 buffs--;
1295
1296 memset(&msg, 0, sizeof(msg));
1297 msg.cmd = NPE_SETLOOPBACK_MODE;
1298 msg.eth_id = port->id;
1299 msg.byte3 = 1;
1300 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1301 printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1302
1303 i = 0;
1304 do { /* drain RX buffers */
1305 while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1306 buffs--;
1307 if (!buffs)
1308 break;
1309 if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1310 /* we have to inject some packet */
1311 struct desc *desc;
1312 u32 phys;
1313 int n = queue_get_desc(port->plat->txreadyq, port, 1);
1314 BUG_ON(n < 0);
1315 desc = tx_desc_ptr(port, n);
1316 phys = tx_desc_phys(port, n);
1317 desc->buf_len = desc->pkt_len = 1;
1318 wmb();
1319 queue_put_desc(TX_QUEUE(port->id), phys, desc);
1320 }
1321 udelay(1);
1322 } while (++i < MAX_CLOSE_WAIT);
1323
1324 if (buffs)
1325 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1326 " left in NPE\n", dev->name, buffs);
1327#if DEBUG_CLOSE
1328 if (!buffs)
1329 printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1330#endif
1331
1332 buffs = TX_DESCS;
1333 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1334 buffs--; /* cancel TX */
1335
1336 i = 0;
1337 do {
1338 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1339 buffs--;
1340 if (!buffs)
1341 break;
1342 } while (++i < MAX_CLOSE_WAIT);
1343
1344 if (buffs)
1345 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1346 "left in NPE\n", dev->name, buffs);
1347#if DEBUG_CLOSE
1348 if (!buffs)
1349 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1350#endif
1351
1352 msg.byte3 = 0;
1353 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1354 printk(KERN_CRIT "%s: unable to disable loopback\n",
1355 dev->name);
1356
2098c18d 1357 phy_stop(port->phydev);
dac2f83f
KH		 1358
1359 if (!ports_open)
1360 qmgr_disable_irq(TXDONE_QUEUE);
dac2f83f
KH		 1361 destroy_queues(port);
1362 release_queues(port);
1363 return 0;
1364}
1365
59f8500e
KH		 1366static const struct net_device_ops ixp4xx_netdev_ops = {
1367 .ndo_open = eth_open,
1368 .ndo_stop = eth_close,
1369 .ndo_start_xmit = eth_xmit,
afc4b13d 1370 .ndo_set_rx_mode = eth_set_mcast_list,
59f8500e 1371 .ndo_do_ioctl = eth_ioctl,
635ecaa7 1372 .ndo_change_mtu = eth_change_mtu,
240c102d
BH		 1373 .ndo_set_mac_address = eth_mac_addr,
1374 .ndo_validate_addr = eth_validate_addr,
59f8500e
KH		 1375};
1376
9871b639 1377static int eth_init_one(struct platform_device *pdev)
dac2f83f
KH		 1378{
1379 struct port *port;
1380 struct net_device *dev;
387d40ac 1381 struct eth_plat_info *plat = dev_get_platdata(&pdev->dev);
dac2f83f 1382 u32 regs_phys;
0e53c7f9 1383 char phy_id[MII_BUS_ID_SIZE + 3];
dac2f83f
KH		 1384 int err;
1385
32bd93e8
RC		 1386 if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
1387 pr_err("ixp4xx_eth: bad ptp filter\n");
1388 return -EINVAL;
1389 }
1390
dac2f83f
KH		 1391 if (!(dev = alloc_etherdev(sizeof(struct port))))
1392 return -ENOMEM;
1393
1394 SET_NETDEV_DEV(dev, &pdev->dev);
1395 port = netdev_priv(dev);
1396 port->netdev = dev;
1397 port->id = pdev->id;
1398
1399 switch (port->id) {
1400 case IXP4XX_ETH_NPEA:
1401 port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1402 regs_phys = IXP4XX_EthA_BASE_PHYS;
1403 break;
1404 case IXP4XX_ETH_NPEB:
1405 port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1406 regs_phys = IXP4XX_EthB_BASE_PHYS;
1407 break;
1408 case IXP4XX_ETH_NPEC:
1409 port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1410 regs_phys = IXP4XX_EthC_BASE_PHYS;
1411 break;
1412 default:
3ba8c792 1413 err = -ENODEV;
dac2f83f
KH		 1414 goto err_free;
1415 }
1416
59f8500e 1417 dev->netdev_ops = &ixp4xx_netdev_ops;
490b7722 1418 dev->ethtool_ops = &ixp4xx_ethtool_ops;
dac2f83f
KH		 1419 dev->tx_queue_len = 100;
1420
1421 netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
1422
1423 if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1424 err = -EIO;
1425 goto err_free;
1426 }
1427
dac2f83f
KH		 1428 port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1429 if (!port->mem_res) {
1430 err = -EBUSY;
7aa6a478 1431 goto err_npe_rel;
dac2f83f
KH		 1432 }
1433
1434 port->plat = plat;
1435 npe_port_tab[NPE_ID(port->id)] = port;
1436 memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1437
1438 platform_set_drvdata(pdev, dev);
1439
1440 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1441 &port->regs->core_control);
1442 udelay(50);
1443 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1444 udelay(50);
1445
7465ac3c
FF		 1446 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
1447 mdio_bus->id, plat->phy);
f9a8f83b 1448 port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link,
2098c18d 1449 PHY_INTERFACE_MODE_MII);
0c661001
AL		 1450 if (IS_ERR(port->phydev)) {
1451 err = PTR_ERR(port->phydev);
7aa6a478 1452 goto err_free_mem;
0c661001 1453 }
2098c18d
KH		 1454
1455 port->phydev->irq = PHY_POLL;
dac2f83f 1456
7aa6a478
KH		 1457 if ((err = register_netdev(dev)))
1458 goto err_phy_dis;
1459
dac2f83f
KH		 1460 printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1461 npe_name(port->npe));
1462
dac2f83f
KH		 1463 return 0;
1464
7aa6a478
KH		 1465err_phy_dis:
1466 phy_disconnect(port->phydev);
1467err_free_mem:
1468 npe_port_tab[NPE_ID(port->id)] = NULL;
7aa6a478 1469 release_resource(port->mem_res);
dac2f83f
KH		 1470err_npe_rel:
1471 npe_release(port->npe);
1472err_free:
1473 free_netdev(dev);
1474 return err;
1475}
1476
9871b639 1477static int eth_remove_one(struct platform_device *pdev)
dac2f83f
KH		 1478{
1479 struct net_device *dev = platform_get_drvdata(pdev);
1480 struct port *port = netdev_priv(dev);
1481
1482 unregister_netdev(dev);
7aa6a478 1483 phy_disconnect(port->phydev);
dac2f83f 1484 npe_port_tab[NPE_ID(port->id)] = NULL;
dac2f83f
KH		 1485 npe_release(port->npe);
1486 release_resource(port->mem_res);
1487 free_netdev(dev);
1488 return 0;
1489}
1490
3c36a837 1491static struct platform_driver ixp4xx_eth_driver = {
dac2f83f
KH		 1492 .driver.name = DRV_NAME,
1493 .probe = eth_init_one,
1494 .remove = eth_remove_one,
1495};
1496
1497static int __init eth_init_module(void)
1498{
2098c18d 1499 int err;
2098c18d
KH		 1500 if ((err = ixp4xx_mdio_register()))
1501 return err;
3c36a837 1502 return platform_driver_register(&ixp4xx_eth_driver);
dac2f83f
KH		 1503}
1504
1505static void __exit eth_cleanup_module(void)
1506{
3c36a837 1507 platform_driver_unregister(&ixp4xx_eth_driver);
2098c18d 1508 ixp4xx_mdio_remove();
dac2f83f
KH		 1509}
1510
1511MODULE_AUTHOR("Krzysztof Halasa");
1512MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1513MODULE_LICENSE("GPL v2");
1514MODULE_ALIAS("platform:ixp4xx_eth");
1515module_init(eth_init_module);
1516module_exit(eth_cleanup_module);
Linux 6.x block layer and io_uring tree(s)