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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
8a3b7a25 | 2 | /* |
3 | * Xilinx Axi Ethernet device driver | |
4 | * | |
5 | * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi | |
6 | * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net> | |
7 | * Copyright (c) 2008-2009 Secret Lab Technologies Ltd. | |
59a54f30 MS |
8 | * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu> |
9 | * Copyright (c) 2010 - 2011 PetaLogix | |
10 | * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved. | |
8a3b7a25 | 11 | * |
12 | * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6 | |
13 | * and Spartan6. | |
14 | * | |
15 | * TODO: | |
16 | * - Add Axi Fifo support. | |
17 | * - Factor out Axi DMA code into separate driver. | |
18 | * - Test and fix basic multicast filtering. | |
19 | * - Add support for extended multicast filtering. | |
20 | * - Test basic VLAN support. | |
21 | * - Add support for extended VLAN support. | |
22 | */ | |
23 | ||
09a0354c | 24 | #include <linux/clk.h> |
8a3b7a25 | 25 | #include <linux/delay.h> |
26 | #include <linux/etherdevice.h> | |
8a3b7a25 | 27 | #include <linux/module.h> |
28 | #include <linux/netdevice.h> | |
29 | #include <linux/of_mdio.h> | |
da90e380 | 30 | #include <linux/of_net.h> |
8a3b7a25 | 31 | #include <linux/of_platform.h> |
9d5e8ec6 | 32 | #include <linux/of_irq.h> |
8a3b7a25 | 33 | #include <linux/of_address.h> |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/spinlock.h> | |
36 | #include <linux/phy.h> | |
37 | #include <linux/mii.h> | |
38 | #include <linux/ethtool.h> | |
39 | ||
40 | #include "xilinx_axienet.h" | |
41 | ||
8b09ca82 RH |
42 | /* Descriptors defines for Tx and Rx DMA */ |
43 | #define TX_BD_NUM_DEFAULT 64 | |
44 | #define RX_BD_NUM_DEFAULT 1024 | |
45 | #define TX_BD_NUM_MAX 4096 | |
46 | #define RX_BD_NUM_MAX 4096 | |
8a3b7a25 | 47 | |
48 | /* Must be shorter than length of ethtool_drvinfo.driver field to fit */ | |
49 | #define DRIVER_NAME "xaxienet" | |
50 | #define DRIVER_DESCRIPTION "Xilinx Axi Ethernet driver" | |
51 | #define DRIVER_VERSION "1.00a" | |
52 | ||
867d03bc | 53 | #define AXIENET_REGS_N 40 |
8a3b7a25 | 54 | |
55 | /* Match table for of_platform binding */ | |
74847f23 | 56 | static const struct of_device_id axienet_of_match[] = { |
8a3b7a25 | 57 | { .compatible = "xlnx,axi-ethernet-1.00.a", }, |
58 | { .compatible = "xlnx,axi-ethernet-1.01.a", }, | |
59 | { .compatible = "xlnx,axi-ethernet-2.01.a", }, | |
60 | {}, | |
61 | }; | |
62 | ||
63 | MODULE_DEVICE_TABLE(of, axienet_of_match); | |
64 | ||
65 | /* Option table for setting up Axi Ethernet hardware options */ | |
66 | static struct axienet_option axienet_options[] = { | |
67 | /* Turn on jumbo packet support for both Rx and Tx */ | |
68 | { | |
69 | .opt = XAE_OPTION_JUMBO, | |
70 | .reg = XAE_TC_OFFSET, | |
71 | .m_or = XAE_TC_JUM_MASK, | |
72 | }, { | |
73 | .opt = XAE_OPTION_JUMBO, | |
74 | .reg = XAE_RCW1_OFFSET, | |
75 | .m_or = XAE_RCW1_JUM_MASK, | |
76 | }, { /* Turn on VLAN packet support for both Rx and Tx */ | |
77 | .opt = XAE_OPTION_VLAN, | |
78 | .reg = XAE_TC_OFFSET, | |
79 | .m_or = XAE_TC_VLAN_MASK, | |
80 | }, { | |
81 | .opt = XAE_OPTION_VLAN, | |
82 | .reg = XAE_RCW1_OFFSET, | |
83 | .m_or = XAE_RCW1_VLAN_MASK, | |
84 | }, { /* Turn on FCS stripping on receive packets */ | |
85 | .opt = XAE_OPTION_FCS_STRIP, | |
86 | .reg = XAE_RCW1_OFFSET, | |
87 | .m_or = XAE_RCW1_FCS_MASK, | |
88 | }, { /* Turn on FCS insertion on transmit packets */ | |
89 | .opt = XAE_OPTION_FCS_INSERT, | |
90 | .reg = XAE_TC_OFFSET, | |
91 | .m_or = XAE_TC_FCS_MASK, | |
92 | }, { /* Turn off length/type field checking on receive packets */ | |
93 | .opt = XAE_OPTION_LENTYPE_ERR, | |
94 | .reg = XAE_RCW1_OFFSET, | |
95 | .m_or = XAE_RCW1_LT_DIS_MASK, | |
96 | }, { /* Turn on Rx flow control */ | |
97 | .opt = XAE_OPTION_FLOW_CONTROL, | |
98 | .reg = XAE_FCC_OFFSET, | |
99 | .m_or = XAE_FCC_FCRX_MASK, | |
100 | }, { /* Turn on Tx flow control */ | |
101 | .opt = XAE_OPTION_FLOW_CONTROL, | |
102 | .reg = XAE_FCC_OFFSET, | |
103 | .m_or = XAE_FCC_FCTX_MASK, | |
104 | }, { /* Turn on promiscuous frame filtering */ | |
105 | .opt = XAE_OPTION_PROMISC, | |
106 | .reg = XAE_FMI_OFFSET, | |
107 | .m_or = XAE_FMI_PM_MASK, | |
108 | }, { /* Enable transmitter */ | |
109 | .opt = XAE_OPTION_TXEN, | |
110 | .reg = XAE_TC_OFFSET, | |
111 | .m_or = XAE_TC_TX_MASK, | |
112 | }, { /* Enable receiver */ | |
113 | .opt = XAE_OPTION_RXEN, | |
114 | .reg = XAE_RCW1_OFFSET, | |
115 | .m_or = XAE_RCW1_RX_MASK, | |
116 | }, | |
117 | {} | |
118 | }; | |
119 | ||
120 | /** | |
121 | * axienet_dma_in32 - Memory mapped Axi DMA register read | |
122 | * @lp: Pointer to axienet local structure | |
123 | * @reg: Address offset from the base address of the Axi DMA core | |
124 | * | |
b0d081c5 | 125 | * Return: The contents of the Axi DMA register |
8a3b7a25 | 126 | * |
127 | * This function returns the contents of the corresponding Axi DMA register. | |
128 | */ | |
129 | static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg) | |
130 | { | |
d85f5f3e | 131 | return ioread32(lp->dma_regs + reg); |
8a3b7a25 | 132 | } |
133 | ||
134 | /** | |
135 | * axienet_dma_out32 - Memory mapped Axi DMA register write. | |
136 | * @lp: Pointer to axienet local structure | |
137 | * @reg: Address offset from the base address of the Axi DMA core | |
138 | * @value: Value to be written into the Axi DMA register | |
139 | * | |
140 | * This function writes the desired value into the corresponding Axi DMA | |
141 | * register. | |
142 | */ | |
143 | static inline void axienet_dma_out32(struct axienet_local *lp, | |
144 | off_t reg, u32 value) | |
145 | { | |
d85f5f3e | 146 | iowrite32(value, lp->dma_regs + reg); |
8a3b7a25 | 147 | } |
148 | ||
149 | /** | |
150 | * axienet_dma_bd_release - Release buffer descriptor rings | |
151 | * @ndev: Pointer to the net_device structure | |
152 | * | |
153 | * This function is used to release the descriptors allocated in | |
154 | * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet | |
155 | * driver stop api is called. | |
156 | */ | |
157 | static void axienet_dma_bd_release(struct net_device *ndev) | |
158 | { | |
159 | int i; | |
160 | struct axienet_local *lp = netdev_priv(ndev); | |
161 | ||
8b09ca82 | 162 | for (i = 0; i < lp->rx_bd_num; i++) { |
8a3b7a25 | 163 | dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys, |
164 | lp->max_frm_size, DMA_FROM_DEVICE); | |
23e6b2dc | 165 | dev_kfree_skb(lp->rx_bd_v[i].skb); |
8a3b7a25 | 166 | } |
167 | ||
168 | if (lp->rx_bd_v) { | |
169 | dma_free_coherent(ndev->dev.parent, | |
8b09ca82 | 170 | sizeof(*lp->rx_bd_v) * lp->rx_bd_num, |
8a3b7a25 | 171 | lp->rx_bd_v, |
172 | lp->rx_bd_p); | |
173 | } | |
174 | if (lp->tx_bd_v) { | |
175 | dma_free_coherent(ndev->dev.parent, | |
8b09ca82 | 176 | sizeof(*lp->tx_bd_v) * lp->tx_bd_num, |
8a3b7a25 | 177 | lp->tx_bd_v, |
178 | lp->tx_bd_p); | |
179 | } | |
180 | } | |
181 | ||
182 | /** | |
183 | * axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA | |
184 | * @ndev: Pointer to the net_device structure | |
185 | * | |
b0d081c5 | 186 | * Return: 0, on success -ENOMEM, on failure |
8a3b7a25 | 187 | * |
188 | * This function is called to initialize the Rx and Tx DMA descriptor | |
189 | * rings. This initializes the descriptors with required default values | |
190 | * and is called when Axi Ethernet driver reset is called. | |
191 | */ | |
192 | static int axienet_dma_bd_init(struct net_device *ndev) | |
193 | { | |
194 | u32 cr; | |
195 | int i; | |
196 | struct sk_buff *skb; | |
197 | struct axienet_local *lp = netdev_priv(ndev); | |
198 | ||
199 | /* Reset the indexes which are used for accessing the BDs */ | |
200 | lp->tx_bd_ci = 0; | |
201 | lp->tx_bd_tail = 0; | |
202 | lp->rx_bd_ci = 0; | |
203 | ||
850a7503 | 204 | /* Allocate the Tx and Rx buffer descriptors. */ |
750afb08 | 205 | lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent, |
8b09ca82 | 206 | sizeof(*lp->tx_bd_v) * lp->tx_bd_num, |
750afb08 | 207 | &lp->tx_bd_p, GFP_KERNEL); |
d0320f75 | 208 | if (!lp->tx_bd_v) |
8a3b7a25 | 209 | goto out; |
8a3b7a25 | 210 | |
750afb08 | 211 | lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent, |
8b09ca82 | 212 | sizeof(*lp->rx_bd_v) * lp->rx_bd_num, |
750afb08 | 213 | &lp->rx_bd_p, GFP_KERNEL); |
d0320f75 | 214 | if (!lp->rx_bd_v) |
8a3b7a25 | 215 | goto out; |
8a3b7a25 | 216 | |
8b09ca82 | 217 | for (i = 0; i < lp->tx_bd_num; i++) { |
8a3b7a25 | 218 | lp->tx_bd_v[i].next = lp->tx_bd_p + |
219 | sizeof(*lp->tx_bd_v) * | |
8b09ca82 | 220 | ((i + 1) % lp->tx_bd_num); |
8a3b7a25 | 221 | } |
222 | ||
8b09ca82 | 223 | for (i = 0; i < lp->rx_bd_num; i++) { |
8a3b7a25 | 224 | lp->rx_bd_v[i].next = lp->rx_bd_p + |
225 | sizeof(*lp->rx_bd_v) * | |
8b09ca82 | 226 | ((i + 1) % lp->rx_bd_num); |
8a3b7a25 | 227 | |
228 | skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size); | |
720a43ef | 229 | if (!skb) |
8a3b7a25 | 230 | goto out; |
8a3b7a25 | 231 | |
23e6b2dc | 232 | lp->rx_bd_v[i].skb = skb; |
8a3b7a25 | 233 | lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent, |
234 | skb->data, | |
235 | lp->max_frm_size, | |
236 | DMA_FROM_DEVICE); | |
237 | lp->rx_bd_v[i].cntrl = lp->max_frm_size; | |
238 | } | |
239 | ||
240 | /* Start updating the Rx channel control register */ | |
241 | cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); | |
242 | /* Update the interrupt coalesce count */ | |
243 | cr = ((cr & ~XAXIDMA_COALESCE_MASK) | | |
244 | ((lp->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT)); | |
245 | /* Update the delay timer count */ | |
246 | cr = ((cr & ~XAXIDMA_DELAY_MASK) | | |
247 | (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT)); | |
248 | /* Enable coalesce, delay timer and error interrupts */ | |
249 | cr |= XAXIDMA_IRQ_ALL_MASK; | |
250 | /* Write to the Rx channel control register */ | |
251 | axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); | |
252 | ||
253 | /* Start updating the Tx channel control register */ | |
254 | cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); | |
255 | /* Update the interrupt coalesce count */ | |
256 | cr = (((cr & ~XAXIDMA_COALESCE_MASK)) | | |
257 | ((lp->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT)); | |
258 | /* Update the delay timer count */ | |
259 | cr = (((cr & ~XAXIDMA_DELAY_MASK)) | | |
260 | (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT)); | |
261 | /* Enable coalesce, delay timer and error interrupts */ | |
262 | cr |= XAXIDMA_IRQ_ALL_MASK; | |
263 | /* Write to the Tx channel control register */ | |
264 | axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); | |
265 | ||
266 | /* Populate the tail pointer and bring the Rx Axi DMA engine out of | |
850a7503 MS |
267 | * halted state. This will make the Rx side ready for reception. |
268 | */ | |
8a3b7a25 | 269 | axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p); |
270 | cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); | |
271 | axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, | |
272 | cr | XAXIDMA_CR_RUNSTOP_MASK); | |
273 | axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p + | |
8b09ca82 | 274 | (sizeof(*lp->rx_bd_v) * (lp->rx_bd_num - 1))); |
8a3b7a25 | 275 | |
276 | /* Write to the RS (Run-stop) bit in the Tx channel control register. | |
277 | * Tx channel is now ready to run. But only after we write to the | |
850a7503 MS |
278 | * tail pointer register that the Tx channel will start transmitting. |
279 | */ | |
8a3b7a25 | 280 | axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p); |
281 | cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); | |
282 | axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, | |
283 | cr | XAXIDMA_CR_RUNSTOP_MASK); | |
284 | ||
285 | return 0; | |
286 | out: | |
287 | axienet_dma_bd_release(ndev); | |
288 | return -ENOMEM; | |
289 | } | |
290 | ||
291 | /** | |
292 | * axienet_set_mac_address - Write the MAC address | |
293 | * @ndev: Pointer to the net_device structure | |
294 | * @address: 6 byte Address to be written as MAC address | |
295 | * | |
296 | * This function is called to initialize the MAC address of the Axi Ethernet | |
297 | * core. It writes to the UAW0 and UAW1 registers of the core. | |
298 | */ | |
da90e380 TK |
299 | static void axienet_set_mac_address(struct net_device *ndev, |
300 | const void *address) | |
8a3b7a25 | 301 | { |
302 | struct axienet_local *lp = netdev_priv(ndev); | |
303 | ||
304 | if (address) | |
305 | memcpy(ndev->dev_addr, address, ETH_ALEN); | |
306 | if (!is_valid_ether_addr(ndev->dev_addr)) | |
452349c3 | 307 | eth_hw_addr_random(ndev); |
8a3b7a25 | 308 | |
309 | /* Set up unicast MAC address filter set its mac address */ | |
310 | axienet_iow(lp, XAE_UAW0_OFFSET, | |
311 | (ndev->dev_addr[0]) | | |
312 | (ndev->dev_addr[1] << 8) | | |
313 | (ndev->dev_addr[2] << 16) | | |
314 | (ndev->dev_addr[3] << 24)); | |
315 | axienet_iow(lp, XAE_UAW1_OFFSET, | |
316 | (((axienet_ior(lp, XAE_UAW1_OFFSET)) & | |
317 | ~XAE_UAW1_UNICASTADDR_MASK) | | |
318 | (ndev->dev_addr[4] | | |
319 | (ndev->dev_addr[5] << 8)))); | |
320 | } | |
321 | ||
322 | /** | |
323 | * netdev_set_mac_address - Write the MAC address (from outside the driver) | |
324 | * @ndev: Pointer to the net_device structure | |
325 | * @p: 6 byte Address to be written as MAC address | |
326 | * | |
b0d081c5 | 327 | * Return: 0 for all conditions. Presently, there is no failure case. |
8a3b7a25 | 328 | * |
329 | * This function is called to initialize the MAC address of the Axi Ethernet | |
330 | * core. It calls the core specific axienet_set_mac_address. This is the | |
331 | * function that goes into net_device_ops structure entry ndo_set_mac_address. | |
332 | */ | |
333 | static int netdev_set_mac_address(struct net_device *ndev, void *p) | |
334 | { | |
335 | struct sockaddr *addr = p; | |
336 | axienet_set_mac_address(ndev, addr->sa_data); | |
337 | return 0; | |
338 | } | |
339 | ||
340 | /** | |
341 | * axienet_set_multicast_list - Prepare the multicast table | |
342 | * @ndev: Pointer to the net_device structure | |
343 | * | |
344 | * This function is called to initialize the multicast table during | |
345 | * initialization. The Axi Ethernet basic multicast support has a four-entry | |
346 | * multicast table which is initialized here. Additionally this function | |
347 | * goes into the net_device_ops structure entry ndo_set_multicast_list. This | |
348 | * means whenever the multicast table entries need to be updated this | |
349 | * function gets called. | |
350 | */ | |
351 | static void axienet_set_multicast_list(struct net_device *ndev) | |
352 | { | |
353 | int i; | |
354 | u32 reg, af0reg, af1reg; | |
355 | struct axienet_local *lp = netdev_priv(ndev); | |
356 | ||
357 | if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) || | |
358 | netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) { | |
359 | /* We must make the kernel realize we had to move into | |
360 | * promiscuous mode. If it was a promiscuous mode request | |
850a7503 MS |
361 | * the flag is already set. If not we set it. |
362 | */ | |
8a3b7a25 | 363 | ndev->flags |= IFF_PROMISC; |
364 | reg = axienet_ior(lp, XAE_FMI_OFFSET); | |
365 | reg |= XAE_FMI_PM_MASK; | |
366 | axienet_iow(lp, XAE_FMI_OFFSET, reg); | |
367 | dev_info(&ndev->dev, "Promiscuous mode enabled.\n"); | |
368 | } else if (!netdev_mc_empty(ndev)) { | |
369 | struct netdev_hw_addr *ha; | |
370 | ||
371 | i = 0; | |
372 | netdev_for_each_mc_addr(ha, ndev) { | |
373 | if (i >= XAE_MULTICAST_CAM_TABLE_NUM) | |
374 | break; | |
375 | ||
376 | af0reg = (ha->addr[0]); | |
377 | af0reg |= (ha->addr[1] << 8); | |
378 | af0reg |= (ha->addr[2] << 16); | |
379 | af0reg |= (ha->addr[3] << 24); | |
380 | ||
381 | af1reg = (ha->addr[4]); | |
382 | af1reg |= (ha->addr[5] << 8); | |
383 | ||
384 | reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00; | |
385 | reg |= i; | |
386 | ||
387 | axienet_iow(lp, XAE_FMI_OFFSET, reg); | |
388 | axienet_iow(lp, XAE_AF0_OFFSET, af0reg); | |
389 | axienet_iow(lp, XAE_AF1_OFFSET, af1reg); | |
390 | i++; | |
391 | } | |
392 | } else { | |
393 | reg = axienet_ior(lp, XAE_FMI_OFFSET); | |
394 | reg &= ~XAE_FMI_PM_MASK; | |
395 | ||
396 | axienet_iow(lp, XAE_FMI_OFFSET, reg); | |
397 | ||
398 | for (i = 0; i < XAE_MULTICAST_CAM_TABLE_NUM; i++) { | |
399 | reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00; | |
400 | reg |= i; | |
401 | ||
402 | axienet_iow(lp, XAE_FMI_OFFSET, reg); | |
403 | axienet_iow(lp, XAE_AF0_OFFSET, 0); | |
404 | axienet_iow(lp, XAE_AF1_OFFSET, 0); | |
405 | } | |
406 | ||
407 | dev_info(&ndev->dev, "Promiscuous mode disabled.\n"); | |
408 | } | |
409 | } | |
410 | ||
411 | /** | |
412 | * axienet_setoptions - Set an Axi Ethernet option | |
413 | * @ndev: Pointer to the net_device structure | |
414 | * @options: Option to be enabled/disabled | |
415 | * | |
416 | * The Axi Ethernet core has multiple features which can be selectively turned | |
417 | * on or off. The typical options could be jumbo frame option, basic VLAN | |
418 | * option, promiscuous mode option etc. This function is used to set or clear | |
419 | * these options in the Axi Ethernet hardware. This is done through | |
420 | * axienet_option structure . | |
421 | */ | |
422 | static void axienet_setoptions(struct net_device *ndev, u32 options) | |
423 | { | |
424 | int reg; | |
425 | struct axienet_local *lp = netdev_priv(ndev); | |
426 | struct axienet_option *tp = &axienet_options[0]; | |
427 | ||
428 | while (tp->opt) { | |
429 | reg = ((axienet_ior(lp, tp->reg)) & ~(tp->m_or)); | |
430 | if (options & tp->opt) | |
431 | reg |= tp->m_or; | |
432 | axienet_iow(lp, tp->reg, reg); | |
433 | tp++; | |
434 | } | |
435 | ||
436 | lp->options |= options; | |
437 | } | |
438 | ||
489d4d77 | 439 | static void __axienet_device_reset(struct axienet_local *lp) |
8a3b7a25 | 440 | { |
441 | u32 timeout; | |
442 | /* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset | |
443 | * process of Axi DMA takes a while to complete as all pending | |
444 | * commands/transfers will be flushed or completed during this | |
850a7503 | 445 | * reset process. |
489d4d77 RH |
446 | * Note that even though both TX and RX have their own reset register, |
447 | * they both reset the entire DMA core, so only one needs to be used. | |
850a7503 | 448 | */ |
489d4d77 | 449 | axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, XAXIDMA_CR_RESET_MASK); |
8a3b7a25 | 450 | timeout = DELAY_OF_ONE_MILLISEC; |
489d4d77 RH |
451 | while (axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET) & |
452 | XAXIDMA_CR_RESET_MASK) { | |
8a3b7a25 | 453 | udelay(1); |
454 | if (--timeout == 0) { | |
c81a97b5 ST |
455 | netdev_err(lp->ndev, "%s: DMA reset timeout!\n", |
456 | __func__); | |
8a3b7a25 | 457 | break; |
458 | } | |
459 | } | |
460 | } | |
461 | ||
462 | /** | |
463 | * axienet_device_reset - Reset and initialize the Axi Ethernet hardware. | |
464 | * @ndev: Pointer to the net_device structure | |
465 | * | |
466 | * This function is called to reset and initialize the Axi Ethernet core. This | |
467 | * is typically called during initialization. It does a reset of the Axi DMA | |
468 | * Rx/Tx channels and initializes the Axi DMA BDs. Since Axi DMA reset lines | |
469 | * areconnected to Axi Ethernet reset lines, this in turn resets the Axi | |
470 | * Ethernet core. No separate hardware reset is done for the Axi Ethernet | |
471 | * core. | |
472 | */ | |
473 | static void axienet_device_reset(struct net_device *ndev) | |
474 | { | |
475 | u32 axienet_status; | |
476 | struct axienet_local *lp = netdev_priv(ndev); | |
477 | ||
489d4d77 | 478 | __axienet_device_reset(lp); |
8a3b7a25 | 479 | |
480 | lp->max_frm_size = XAE_MAX_VLAN_FRAME_SIZE; | |
f080a8c3 | 481 | lp->options |= XAE_OPTION_VLAN; |
8a3b7a25 | 482 | lp->options &= (~XAE_OPTION_JUMBO); |
483 | ||
484 | if ((ndev->mtu > XAE_MTU) && | |
f080a8c3 ST |
485 | (ndev->mtu <= XAE_JUMBO_MTU)) { |
486 | lp->max_frm_size = ndev->mtu + VLAN_ETH_HLEN + | |
487 | XAE_TRL_SIZE; | |
488 | ||
489 | if (lp->max_frm_size <= lp->rxmem) | |
490 | lp->options |= XAE_OPTION_JUMBO; | |
8a3b7a25 | 491 | } |
492 | ||
493 | if (axienet_dma_bd_init(ndev)) { | |
c81a97b5 ST |
494 | netdev_err(ndev, "%s: descriptor allocation failed\n", |
495 | __func__); | |
8a3b7a25 | 496 | } |
497 | ||
498 | axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET); | |
499 | axienet_status &= ~XAE_RCW1_RX_MASK; | |
500 | axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status); | |
501 | ||
502 | axienet_status = axienet_ior(lp, XAE_IP_OFFSET); | |
503 | if (axienet_status & XAE_INT_RXRJECT_MASK) | |
504 | axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK); | |
522856ce RH |
505 | axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ? |
506 | XAE_INT_RECV_ERROR_MASK : 0); | |
8a3b7a25 | 507 | |
508 | axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK); | |
509 | ||
510 | /* Sync default options with HW but leave receiver and | |
850a7503 MS |
511 | * transmitter disabled. |
512 | */ | |
8a3b7a25 | 513 | axienet_setoptions(ndev, lp->options & |
514 | ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); | |
515 | axienet_set_mac_address(ndev, NULL); | |
516 | axienet_set_multicast_list(ndev); | |
517 | axienet_setoptions(ndev, lp->options); | |
518 | ||
860e9538 | 519 | netif_trans_update(ndev); |
8a3b7a25 | 520 | } |
521 | ||
522 | /** | |
523 | * axienet_adjust_link - Adjust the PHY link speed/duplex. | |
524 | * @ndev: Pointer to the net_device structure | |
525 | * | |
526 | * This function is called to change the speed and duplex setting after | |
527 | * auto negotiation is done by the PHY. This is the function that gets | |
528 | * registered with the PHY interface through the "of_phy_connect" call. | |
529 | */ | |
530 | static void axienet_adjust_link(struct net_device *ndev) | |
531 | { | |
532 | u32 emmc_reg; | |
533 | u32 link_state; | |
534 | u32 setspeed = 1; | |
535 | struct axienet_local *lp = netdev_priv(ndev); | |
b1b7dcff | 536 | struct phy_device *phy = ndev->phydev; |
8a3b7a25 | 537 | |
538 | link_state = phy->speed | (phy->duplex << 1) | phy->link; | |
539 | if (lp->last_link != link_state) { | |
540 | if ((phy->speed == SPEED_10) || (phy->speed == SPEED_100)) { | |
ee06b172 | 541 | if (lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) |
8a3b7a25 | 542 | setspeed = 0; |
543 | } else { | |
544 | if ((phy->speed == SPEED_1000) && | |
ee06b172 | 545 | (lp->phy_mode == PHY_INTERFACE_MODE_MII)) |
8a3b7a25 | 546 | setspeed = 0; |
547 | } | |
548 | ||
549 | if (setspeed == 1) { | |
550 | emmc_reg = axienet_ior(lp, XAE_EMMC_OFFSET); | |
551 | emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK; | |
552 | ||
553 | switch (phy->speed) { | |
554 | case SPEED_1000: | |
555 | emmc_reg |= XAE_EMMC_LINKSPD_1000; | |
556 | break; | |
557 | case SPEED_100: | |
558 | emmc_reg |= XAE_EMMC_LINKSPD_100; | |
559 | break; | |
560 | case SPEED_10: | |
561 | emmc_reg |= XAE_EMMC_LINKSPD_10; | |
562 | break; | |
563 | default: | |
564 | dev_err(&ndev->dev, "Speed other than 10, 100 " | |
565 | "or 1Gbps is not supported\n"); | |
566 | break; | |
567 | } | |
568 | ||
569 | axienet_iow(lp, XAE_EMMC_OFFSET, emmc_reg); | |
570 | lp->last_link = link_state; | |
571 | phy_print_status(phy); | |
572 | } else { | |
c81a97b5 ST |
573 | netdev_err(ndev, |
574 | "Error setting Axi Ethernet mac speed\n"); | |
8a3b7a25 | 575 | } |
576 | } | |
577 | } | |
578 | ||
579 | /** | |
580 | * axienet_start_xmit_done - Invoked once a transmit is completed by the | |
581 | * Axi DMA Tx channel. | |
582 | * @ndev: Pointer to the net_device structure | |
583 | * | |
584 | * This function is invoked from the Axi DMA Tx isr to notify the completion | |
585 | * of transmit operation. It clears fields in the corresponding Tx BDs and | |
586 | * unmaps the corresponding buffer so that CPU can regain ownership of the | |
587 | * buffer. It finally invokes "netif_wake_queue" to restart transmission if | |
588 | * required. | |
589 | */ | |
590 | static void axienet_start_xmit_done(struct net_device *ndev) | |
591 | { | |
592 | u32 size = 0; | |
593 | u32 packets = 0; | |
594 | struct axienet_local *lp = netdev_priv(ndev); | |
595 | struct axidma_bd *cur_p; | |
596 | unsigned int status = 0; | |
597 | ||
598 | cur_p = &lp->tx_bd_v[lp->tx_bd_ci]; | |
599 | status = cur_p->status; | |
600 | while (status & XAXIDMA_BD_STS_COMPLETE_MASK) { | |
601 | dma_unmap_single(ndev->dev.parent, cur_p->phys, | |
602 | (cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK), | |
603 | DMA_TO_DEVICE); | |
23e6b2dc RH |
604 | if (cur_p->skb) |
605 | dev_consume_skb_irq(cur_p->skb); | |
8a3b7a25 | 606 | /*cur_p->phys = 0;*/ |
607 | cur_p->app0 = 0; | |
608 | cur_p->app1 = 0; | |
609 | cur_p->app2 = 0; | |
610 | cur_p->app4 = 0; | |
611 | cur_p->status = 0; | |
23e6b2dc | 612 | cur_p->skb = NULL; |
8a3b7a25 | 613 | |
614 | size += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK; | |
615 | packets++; | |
616 | ||
8b09ca82 RH |
617 | if (++lp->tx_bd_ci >= lp->tx_bd_num) |
618 | lp->tx_bd_ci = 0; | |
8a3b7a25 | 619 | cur_p = &lp->tx_bd_v[lp->tx_bd_ci]; |
620 | status = cur_p->status; | |
621 | } | |
622 | ||
623 | ndev->stats.tx_packets += packets; | |
624 | ndev->stats.tx_bytes += size; | |
7de44285 RH |
625 | |
626 | /* Matches barrier in axienet_start_xmit */ | |
627 | smp_mb(); | |
628 | ||
8a3b7a25 | 629 | netif_wake_queue(ndev); |
630 | } | |
631 | ||
632 | /** | |
633 | * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy | |
634 | * @lp: Pointer to the axienet_local structure | |
635 | * @num_frag: The number of BDs to check for | |
636 | * | |
b0d081c5 | 637 | * Return: 0, on success |
8a3b7a25 | 638 | * NETDEV_TX_BUSY, if any of the descriptors are not free |
639 | * | |
640 | * This function is invoked before BDs are allocated and transmission starts. | |
641 | * This function returns 0 if a BD or group of BDs can be allocated for | |
642 | * transmission. If the BD or any of the BDs are not free the function | |
643 | * returns a busy status. This is invoked from axienet_start_xmit. | |
644 | */ | |
645 | static inline int axienet_check_tx_bd_space(struct axienet_local *lp, | |
646 | int num_frag) | |
647 | { | |
648 | struct axidma_bd *cur_p; | |
8b09ca82 | 649 | cur_p = &lp->tx_bd_v[(lp->tx_bd_tail + num_frag) % lp->tx_bd_num]; |
8a3b7a25 | 650 | if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK) |
651 | return NETDEV_TX_BUSY; | |
652 | return 0; | |
653 | } | |
654 | ||
655 | /** | |
656 | * axienet_start_xmit - Starts the transmission. | |
657 | * @skb: sk_buff pointer that contains data to be Txed. | |
658 | * @ndev: Pointer to net_device structure. | |
659 | * | |
b0d081c5 | 660 | * Return: NETDEV_TX_OK, on success |
8a3b7a25 | 661 | * NETDEV_TX_BUSY, if any of the descriptors are not free |
662 | * | |
663 | * This function is invoked from upper layers to initiate transmission. The | |
664 | * function uses the next available free BDs and populates their fields to | |
665 | * start the transmission. Additionally if checksum offloading is supported, | |
666 | * it populates AXI Stream Control fields with appropriate values. | |
667 | */ | |
81255af8 Y |
668 | static netdev_tx_t |
669 | axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |
8a3b7a25 | 670 | { |
671 | u32 ii; | |
672 | u32 num_frag; | |
673 | u32 csum_start_off; | |
674 | u32 csum_index_off; | |
675 | skb_frag_t *frag; | |
676 | dma_addr_t tail_p; | |
677 | struct axienet_local *lp = netdev_priv(ndev); | |
678 | struct axidma_bd *cur_p; | |
679 | ||
680 | num_frag = skb_shinfo(skb)->nr_frags; | |
681 | cur_p = &lp->tx_bd_v[lp->tx_bd_tail]; | |
682 | ||
683 | if (axienet_check_tx_bd_space(lp, num_frag)) { | |
7de44285 RH |
684 | if (netif_queue_stopped(ndev)) |
685 | return NETDEV_TX_BUSY; | |
686 | ||
687 | netif_stop_queue(ndev); | |
688 | ||
689 | /* Matches barrier in axienet_start_xmit_done */ | |
690 | smp_mb(); | |
691 | ||
692 | /* Space might have just been freed - check again */ | |
693 | if (axienet_check_tx_bd_space(lp, num_frag)) | |
694 | return NETDEV_TX_BUSY; | |
695 | ||
696 | netif_wake_queue(ndev); | |
8a3b7a25 | 697 | } |
698 | ||
699 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
700 | if (lp->features & XAE_FEATURE_FULL_TX_CSUM) { | |
701 | /* Tx Full Checksum Offload Enabled */ | |
702 | cur_p->app0 |= 2; | |
703 | } else if (lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) { | |
704 | csum_start_off = skb_transport_offset(skb); | |
705 | csum_index_off = csum_start_off + skb->csum_offset; | |
706 | /* Tx Partial Checksum Offload Enabled */ | |
707 | cur_p->app0 |= 1; | |
708 | cur_p->app1 = (csum_start_off << 16) | csum_index_off; | |
709 | } | |
710 | } else if (skb->ip_summed == CHECKSUM_UNNECESSARY) { | |
711 | cur_p->app0 |= 2; /* Tx Full Checksum Offload Enabled */ | |
712 | } | |
713 | ||
714 | cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK; | |
715 | cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, | |
716 | skb_headlen(skb), DMA_TO_DEVICE); | |
717 | ||
718 | for (ii = 0; ii < num_frag; ii++) { | |
8b09ca82 RH |
719 | if (++lp->tx_bd_tail >= lp->tx_bd_num) |
720 | lp->tx_bd_tail = 0; | |
8a3b7a25 | 721 | cur_p = &lp->tx_bd_v[lp->tx_bd_tail]; |
722 | frag = &skb_shinfo(skb)->frags[ii]; | |
723 | cur_p->phys = dma_map_single(ndev->dev.parent, | |
724 | skb_frag_address(frag), | |
725 | skb_frag_size(frag), | |
726 | DMA_TO_DEVICE); | |
727 | cur_p->cntrl = skb_frag_size(frag); | |
728 | } | |
729 | ||
730 | cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK; | |
23e6b2dc | 731 | cur_p->skb = skb; |
8a3b7a25 | 732 | |
733 | tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail; | |
734 | /* Start the transfer */ | |
735 | axienet_dma_out32(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p); | |
8b09ca82 RH |
736 | if (++lp->tx_bd_tail >= lp->tx_bd_num) |
737 | lp->tx_bd_tail = 0; | |
8a3b7a25 | 738 | |
739 | return NETDEV_TX_OK; | |
740 | } | |
741 | ||
742 | /** | |
743 | * axienet_recv - Is called from Axi DMA Rx Isr to complete the received | |
744 | * BD processing. | |
745 | * @ndev: Pointer to net_device structure. | |
746 | * | |
747 | * This function is invoked from the Axi DMA Rx isr to process the Rx BDs. It | |
748 | * does minimal processing and invokes "netif_rx" to complete further | |
749 | * processing. | |
750 | */ | |
751 | static void axienet_recv(struct net_device *ndev) | |
752 | { | |
753 | u32 length; | |
754 | u32 csumstatus; | |
755 | u32 size = 0; | |
756 | u32 packets = 0; | |
38e96b35 | 757 | dma_addr_t tail_p = 0; |
8a3b7a25 | 758 | struct axienet_local *lp = netdev_priv(ndev); |
759 | struct sk_buff *skb, *new_skb; | |
760 | struct axidma_bd *cur_p; | |
761 | ||
8a3b7a25 | 762 | cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; |
763 | ||
764 | while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK)) { | |
38e96b35 | 765 | tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci; |
8a3b7a25 | 766 | |
767 | dma_unmap_single(ndev->dev.parent, cur_p->phys, | |
768 | lp->max_frm_size, | |
769 | DMA_FROM_DEVICE); | |
770 | ||
23e6b2dc RH |
771 | skb = cur_p->skb; |
772 | cur_p->skb = NULL; | |
773 | length = cur_p->app4 & 0x0000FFFF; | |
774 | ||
8a3b7a25 | 775 | skb_put(skb, length); |
776 | skb->protocol = eth_type_trans(skb, ndev); | |
777 | /*skb_checksum_none_assert(skb);*/ | |
778 | skb->ip_summed = CHECKSUM_NONE; | |
779 | ||
780 | /* if we're doing Rx csum offload, set it up */ | |
781 | if (lp->features & XAE_FEATURE_FULL_RX_CSUM) { | |
782 | csumstatus = (cur_p->app2 & | |
783 | XAE_FULL_CSUM_STATUS_MASK) >> 3; | |
784 | if ((csumstatus == XAE_IP_TCP_CSUM_VALIDATED) || | |
785 | (csumstatus == XAE_IP_UDP_CSUM_VALIDATED)) { | |
786 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
787 | } | |
788 | } else if ((lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) != 0 && | |
ceffc4ac | 789 | skb->protocol == htons(ETH_P_IP) && |
8a3b7a25 | 790 | skb->len > 64) { |
791 | skb->csum = be32_to_cpu(cur_p->app3 & 0xFFFF); | |
792 | skb->ip_summed = CHECKSUM_COMPLETE; | |
793 | } | |
794 | ||
795 | netif_rx(skb); | |
796 | ||
797 | size += length; | |
798 | packets++; | |
799 | ||
800 | new_skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size); | |
720a43ef | 801 | if (!new_skb) |
8a3b7a25 | 802 | return; |
720a43ef | 803 | |
8a3b7a25 | 804 | cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data, |
805 | lp->max_frm_size, | |
806 | DMA_FROM_DEVICE); | |
807 | cur_p->cntrl = lp->max_frm_size; | |
808 | cur_p->status = 0; | |
23e6b2dc | 809 | cur_p->skb = new_skb; |
8a3b7a25 | 810 | |
8b09ca82 RH |
811 | if (++lp->rx_bd_ci >= lp->rx_bd_num) |
812 | lp->rx_bd_ci = 0; | |
8a3b7a25 | 813 | cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; |
814 | } | |
815 | ||
816 | ndev->stats.rx_packets += packets; | |
817 | ndev->stats.rx_bytes += size; | |
818 | ||
38e96b35 PC |
819 | if (tail_p) |
820 | axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p); | |
8a3b7a25 | 821 | } |
822 | ||
823 | /** | |
824 | * axienet_tx_irq - Tx Done Isr. | |
825 | * @irq: irq number | |
826 | * @_ndev: net_device pointer | |
827 | * | |
9cbc1b68 | 828 | * Return: IRQ_HANDLED if device generated a TX interrupt, IRQ_NONE otherwise. |
8a3b7a25 | 829 | * |
830 | * This is the Axi DMA Tx done Isr. It invokes "axienet_start_xmit_done" | |
831 | * to complete the BD processing. | |
832 | */ | |
833 | static irqreturn_t axienet_tx_irq(int irq, void *_ndev) | |
834 | { | |
835 | u32 cr; | |
836 | unsigned int status; | |
837 | struct net_device *ndev = _ndev; | |
838 | struct axienet_local *lp = netdev_priv(ndev); | |
839 | ||
840 | status = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET); | |
841 | if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) { | |
80c775ac | 842 | axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status); |
8a3b7a25 | 843 | axienet_start_xmit_done(lp->ndev); |
844 | goto out; | |
845 | } | |
846 | if (!(status & XAXIDMA_IRQ_ALL_MASK)) | |
9cbc1b68 | 847 | return IRQ_NONE; |
8a3b7a25 | 848 | if (status & XAXIDMA_IRQ_ERROR_MASK) { |
849 | dev_err(&ndev->dev, "DMA Tx error 0x%x\n", status); | |
850 | dev_err(&ndev->dev, "Current BD is at: 0x%x\n", | |
851 | (lp->tx_bd_v[lp->tx_bd_ci]).phys); | |
852 | ||
853 | cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); | |
854 | /* Disable coalesce, delay timer and error interrupts */ | |
855 | cr &= (~XAXIDMA_IRQ_ALL_MASK); | |
856 | /* Write to the Tx channel control register */ | |
857 | axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); | |
858 | ||
859 | cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); | |
860 | /* Disable coalesce, delay timer and error interrupts */ | |
861 | cr &= (~XAXIDMA_IRQ_ALL_MASK); | |
862 | /* Write to the Rx channel control register */ | |
863 | axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); | |
864 | ||
865 | tasklet_schedule(&lp->dma_err_tasklet); | |
80c775ac | 866 | axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status); |
8a3b7a25 | 867 | } |
868 | out: | |
8a3b7a25 | 869 | return IRQ_HANDLED; |
870 | } | |
871 | ||
872 | /** | |
873 | * axienet_rx_irq - Rx Isr. | |
874 | * @irq: irq number | |
875 | * @_ndev: net_device pointer | |
876 | * | |
9cbc1b68 | 877 | * Return: IRQ_HANDLED if device generated a RX interrupt, IRQ_NONE otherwise. |
8a3b7a25 | 878 | * |
879 | * This is the Axi DMA Rx Isr. It invokes "axienet_recv" to complete the BD | |
880 | * processing. | |
881 | */ | |
882 | static irqreturn_t axienet_rx_irq(int irq, void *_ndev) | |
883 | { | |
884 | u32 cr; | |
885 | unsigned int status; | |
886 | struct net_device *ndev = _ndev; | |
887 | struct axienet_local *lp = netdev_priv(ndev); | |
888 | ||
889 | status = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET); | |
890 | if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) { | |
80c775ac | 891 | axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status); |
8a3b7a25 | 892 | axienet_recv(lp->ndev); |
893 | goto out; | |
894 | } | |
895 | if (!(status & XAXIDMA_IRQ_ALL_MASK)) | |
9cbc1b68 | 896 | return IRQ_NONE; |
8a3b7a25 | 897 | if (status & XAXIDMA_IRQ_ERROR_MASK) { |
898 | dev_err(&ndev->dev, "DMA Rx error 0x%x\n", status); | |
899 | dev_err(&ndev->dev, "Current BD is at: 0x%x\n", | |
900 | (lp->rx_bd_v[lp->rx_bd_ci]).phys); | |
901 | ||
902 | cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); | |
903 | /* Disable coalesce, delay timer and error interrupts */ | |
904 | cr &= (~XAXIDMA_IRQ_ALL_MASK); | |
905 | /* Finally write to the Tx channel control register */ | |
906 | axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); | |
907 | ||
908 | cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); | |
909 | /* Disable coalesce, delay timer and error interrupts */ | |
910 | cr &= (~XAXIDMA_IRQ_ALL_MASK); | |
911 | /* write to the Rx channel control register */ | |
912 | axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); | |
913 | ||
914 | tasklet_schedule(&lp->dma_err_tasklet); | |
80c775ac | 915 | axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status); |
8a3b7a25 | 916 | } |
917 | out: | |
8a3b7a25 | 918 | return IRQ_HANDLED; |
919 | } | |
920 | ||
522856ce RH |
921 | /** |
922 | * axienet_eth_irq - Ethernet core Isr. | |
923 | * @irq: irq number | |
924 | * @_ndev: net_device pointer | |
925 | * | |
926 | * Return: IRQ_HANDLED if device generated a core interrupt, IRQ_NONE otherwise. | |
927 | * | |
928 | * Handle miscellaneous conditions indicated by Ethernet core IRQ. | |
929 | */ | |
930 | static irqreturn_t axienet_eth_irq(int irq, void *_ndev) | |
931 | { | |
932 | struct net_device *ndev = _ndev; | |
933 | struct axienet_local *lp = netdev_priv(ndev); | |
934 | unsigned int pending; | |
935 | ||
936 | pending = axienet_ior(lp, XAE_IP_OFFSET); | |
937 | if (!pending) | |
938 | return IRQ_NONE; | |
939 | ||
940 | if (pending & XAE_INT_RXFIFOOVR_MASK) | |
941 | ndev->stats.rx_missed_errors++; | |
942 | ||
943 | if (pending & XAE_INT_RXRJECT_MASK) | |
944 | ndev->stats.rx_frame_errors++; | |
945 | ||
946 | axienet_iow(lp, XAE_IS_OFFSET, pending); | |
947 | return IRQ_HANDLED; | |
948 | } | |
949 | ||
aecb55be JM |
950 | static void axienet_dma_err_handler(unsigned long data); |
951 | ||
8a3b7a25 | 952 | /** |
953 | * axienet_open - Driver open routine. | |
954 | * @ndev: Pointer to net_device structure | |
955 | * | |
b0d081c5 | 956 | * Return: 0, on success. |
8a3b7a25 | 957 | * non-zero error value on failure |
958 | * | |
959 | * This is the driver open routine. It calls phy_start to start the PHY device. | |
960 | * It also allocates interrupt service routines, enables the interrupt lines | |
961 | * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer | |
962 | * descriptors are initialized. | |
963 | */ | |
964 | static int axienet_open(struct net_device *ndev) | |
965 | { | |
7789e9ed | 966 | int ret; |
8a3b7a25 | 967 | struct axienet_local *lp = netdev_priv(ndev); |
b1b7dcff | 968 | struct phy_device *phydev = NULL; |
8a3b7a25 | 969 | |
970 | dev_dbg(&ndev->dev, "axienet_open()\n"); | |
971 | ||
8a3b7a25 | 972 | /* Disable the MDIO interface till Axi Ethernet Reset is completed. |
973 | * When we do an Axi Ethernet reset, it resets the complete core | |
7789e9ed RH |
974 | * including the MDIO. MDIO must be disabled before resetting |
975 | * and re-enabled afterwards. | |
976 | * Hold MDIO bus lock to avoid MDIO accesses during the reset. | |
850a7503 | 977 | */ |
7789e9ed RH |
978 | mutex_lock(&lp->mii_bus->mdio_lock); |
979 | axienet_mdio_disable(lp); | |
8a3b7a25 | 980 | axienet_device_reset(ndev); |
7789e9ed RH |
981 | ret = axienet_mdio_enable(lp); |
982 | mutex_unlock(&lp->mii_bus->mdio_lock); | |
8a3b7a25 | 983 | if (ret < 0) |
984 | return ret; | |
985 | ||
986 | if (lp->phy_node) { | |
ee06b172 A |
987 | phydev = of_phy_connect(lp->ndev, lp->phy_node, |
988 | axienet_adjust_link, 0, lp->phy_mode); | |
d1d372e8 | 989 | |
b1b7dcff | 990 | if (!phydev) |
8a3b7a25 | 991 | dev_err(lp->dev, "of_phy_connect() failed\n"); |
d7cc3163 | 992 | else |
b1b7dcff | 993 | phy_start(phydev); |
8a3b7a25 | 994 | } |
995 | ||
71c6c837 XF |
996 | /* Enable tasklets for Axi DMA error handling */ |
997 | tasklet_init(&lp->dma_err_tasklet, axienet_dma_err_handler, | |
998 | (unsigned long) lp); | |
999 | ||
8a3b7a25 | 1000 | /* Enable interrupts for Axi DMA Tx */ |
9cbc1b68 RH |
1001 | ret = request_irq(lp->tx_irq, axienet_tx_irq, IRQF_SHARED, |
1002 | ndev->name, ndev); | |
8a3b7a25 | 1003 | if (ret) |
1004 | goto err_tx_irq; | |
1005 | /* Enable interrupts for Axi DMA Rx */ | |
9cbc1b68 RH |
1006 | ret = request_irq(lp->rx_irq, axienet_rx_irq, IRQF_SHARED, |
1007 | ndev->name, ndev); | |
8a3b7a25 | 1008 | if (ret) |
1009 | goto err_rx_irq; | |
522856ce RH |
1010 | /* Enable interrupts for Axi Ethernet core (if defined) */ |
1011 | if (lp->eth_irq > 0) { | |
1012 | ret = request_irq(lp->eth_irq, axienet_eth_irq, IRQF_SHARED, | |
1013 | ndev->name, ndev); | |
1014 | if (ret) | |
1015 | goto err_eth_irq; | |
1016 | } | |
71c6c837 | 1017 | |
8a3b7a25 | 1018 | return 0; |
1019 | ||
522856ce RH |
1020 | err_eth_irq: |
1021 | free_irq(lp->rx_irq, ndev); | |
8a3b7a25 | 1022 | err_rx_irq: |
1023 | free_irq(lp->tx_irq, ndev); | |
1024 | err_tx_irq: | |
b1b7dcff PR |
1025 | if (phydev) |
1026 | phy_disconnect(phydev); | |
71c6c837 | 1027 | tasklet_kill(&lp->dma_err_tasklet); |
8a3b7a25 | 1028 | dev_err(lp->dev, "request_irq() failed\n"); |
1029 | return ret; | |
1030 | } | |
1031 | ||
1032 | /** | |
1033 | * axienet_stop - Driver stop routine. | |
1034 | * @ndev: Pointer to net_device structure | |
1035 | * | |
b0d081c5 | 1036 | * Return: 0, on success. |
8a3b7a25 | 1037 | * |
1038 | * This is the driver stop routine. It calls phy_disconnect to stop the PHY | |
1039 | * device. It also removes the interrupt handlers and disables the interrupts. | |
1040 | * The Axi DMA Tx/Rx BDs are released. | |
1041 | */ | |
1042 | static int axienet_stop(struct net_device *ndev) | |
1043 | { | |
489d4d77 RH |
1044 | u32 cr, sr; |
1045 | int count; | |
8a3b7a25 | 1046 | struct axienet_local *lp = netdev_priv(ndev); |
1047 | ||
1048 | dev_dbg(&ndev->dev, "axienet_close()\n"); | |
1049 | ||
8a3b7a25 | 1050 | axienet_setoptions(ndev, lp->options & |
1051 | ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); | |
1052 | ||
489d4d77 RH |
1053 | cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); |
1054 | cr &= ~(XAXIDMA_CR_RUNSTOP_MASK | XAXIDMA_IRQ_ALL_MASK); | |
1055 | axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); | |
1056 | ||
1057 | cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); | |
1058 | cr &= ~(XAXIDMA_CR_RUNSTOP_MASK | XAXIDMA_IRQ_ALL_MASK); | |
1059 | axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); | |
1060 | ||
1061 | axienet_iow(lp, XAE_IE_OFFSET, 0); | |
1062 | ||
1063 | /* Give DMAs a chance to halt gracefully */ | |
1064 | sr = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET); | |
1065 | for (count = 0; !(sr & XAXIDMA_SR_HALT_MASK) && count < 5; ++count) { | |
1066 | msleep(20); | |
1067 | sr = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET); | |
1068 | } | |
1069 | ||
1070 | sr = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET); | |
1071 | for (count = 0; !(sr & XAXIDMA_SR_HALT_MASK) && count < 5; ++count) { | |
1072 | msleep(20); | |
1073 | sr = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET); | |
1074 | } | |
1075 | ||
1076 | /* Do a reset to ensure DMA is really stopped */ | |
1077 | mutex_lock(&lp->mii_bus->mdio_lock); | |
1078 | axienet_mdio_disable(lp); | |
1079 | __axienet_device_reset(lp); | |
1080 | axienet_mdio_enable(lp); | |
1081 | mutex_unlock(&lp->mii_bus->mdio_lock); | |
1082 | ||
175c0dff | 1083 | tasklet_kill(&lp->dma_err_tasklet); |
8a3b7a25 | 1084 | |
522856ce RH |
1085 | if (lp->eth_irq > 0) |
1086 | free_irq(lp->eth_irq, ndev); | |
8a3b7a25 | 1087 | free_irq(lp->tx_irq, ndev); |
1088 | free_irq(lp->rx_irq, ndev); | |
1089 | ||
b1b7dcff PR |
1090 | if (ndev->phydev) |
1091 | phy_disconnect(ndev->phydev); | |
8a3b7a25 | 1092 | |
1093 | axienet_dma_bd_release(ndev); | |
1094 | return 0; | |
1095 | } | |
1096 | ||
1097 | /** | |
1098 | * axienet_change_mtu - Driver change mtu routine. | |
1099 | * @ndev: Pointer to net_device structure | |
1100 | * @new_mtu: New mtu value to be applied | |
1101 | * | |
b0d081c5 | 1102 | * Return: Always returns 0 (success). |
8a3b7a25 | 1103 | * |
1104 | * This is the change mtu driver routine. It checks if the Axi Ethernet | |
1105 | * hardware supports jumbo frames before changing the mtu. This can be | |
1106 | * called only when the device is not up. | |
1107 | */ | |
1108 | static int axienet_change_mtu(struct net_device *ndev, int new_mtu) | |
1109 | { | |
1110 | struct axienet_local *lp = netdev_priv(ndev); | |
1111 | ||
1112 | if (netif_running(ndev)) | |
1113 | return -EBUSY; | |
f080a8c3 ST |
1114 | |
1115 | if ((new_mtu + VLAN_ETH_HLEN + | |
1116 | XAE_TRL_SIZE) > lp->rxmem) | |
1117 | return -EINVAL; | |
1118 | ||
f080a8c3 | 1119 | ndev->mtu = new_mtu; |
8a3b7a25 | 1120 | |
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1125 | /** | |
1126 | * axienet_poll_controller - Axi Ethernet poll mechanism. | |
1127 | * @ndev: Pointer to net_device structure | |
1128 | * | |
1129 | * This implements Rx/Tx ISR poll mechanisms. The interrupts are disabled prior | |
1130 | * to polling the ISRs and are enabled back after the polling is done. | |
1131 | */ | |
1132 | static void axienet_poll_controller(struct net_device *ndev) | |
1133 | { | |
1134 | struct axienet_local *lp = netdev_priv(ndev); | |
1135 | disable_irq(lp->tx_irq); | |
1136 | disable_irq(lp->rx_irq); | |
1137 | axienet_rx_irq(lp->tx_irq, ndev); | |
1138 | axienet_tx_irq(lp->rx_irq, ndev); | |
1139 | enable_irq(lp->tx_irq); | |
1140 | enable_irq(lp->rx_irq); | |
1141 | } | |
1142 | #endif | |
1143 | ||
1144 | static const struct net_device_ops axienet_netdev_ops = { | |
1145 | .ndo_open = axienet_open, | |
1146 | .ndo_stop = axienet_stop, | |
1147 | .ndo_start_xmit = axienet_start_xmit, | |
1148 | .ndo_change_mtu = axienet_change_mtu, | |
1149 | .ndo_set_mac_address = netdev_set_mac_address, | |
1150 | .ndo_validate_addr = eth_validate_addr, | |
1151 | .ndo_set_rx_mode = axienet_set_multicast_list, | |
1152 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1153 | .ndo_poll_controller = axienet_poll_controller, | |
1154 | #endif | |
1155 | }; | |
1156 | ||
8a3b7a25 | 1157 | /** |
1158 | * axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information. | |
1159 | * @ndev: Pointer to net_device structure | |
1160 | * @ed: Pointer to ethtool_drvinfo structure | |
1161 | * | |
1162 | * This implements ethtool command for getting the driver information. | |
1163 | * Issue "ethtool -i ethX" under linux prompt to execute this function. | |
1164 | */ | |
1165 | static void axienet_ethtools_get_drvinfo(struct net_device *ndev, | |
1166 | struct ethtool_drvinfo *ed) | |
1167 | { | |
7826d43f JP |
1168 | strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver)); |
1169 | strlcpy(ed->version, DRIVER_VERSION, sizeof(ed->version)); | |
8a3b7a25 | 1170 | } |
1171 | ||
1172 | /** | |
1173 | * axienet_ethtools_get_regs_len - Get the total regs length present in the | |
1174 | * AxiEthernet core. | |
1175 | * @ndev: Pointer to net_device structure | |
1176 | * | |
1177 | * This implements ethtool command for getting the total register length | |
1178 | * information. | |
b0d081c5 MS |
1179 | * |
1180 | * Return: the total regs length | |
8a3b7a25 | 1181 | */ |
1182 | static int axienet_ethtools_get_regs_len(struct net_device *ndev) | |
1183 | { | |
1184 | return sizeof(u32) * AXIENET_REGS_N; | |
1185 | } | |
1186 | ||
1187 | /** | |
1188 | * axienet_ethtools_get_regs - Dump the contents of all registers present | |
1189 | * in AxiEthernet core. | |
1190 | * @ndev: Pointer to net_device structure | |
1191 | * @regs: Pointer to ethtool_regs structure | |
1192 | * @ret: Void pointer used to return the contents of the registers. | |
1193 | * | |
1194 | * This implements ethtool command for getting the Axi Ethernet register dump. | |
1195 | * Issue "ethtool -d ethX" to execute this function. | |
1196 | */ | |
1197 | static void axienet_ethtools_get_regs(struct net_device *ndev, | |
1198 | struct ethtool_regs *regs, void *ret) | |
1199 | { | |
1200 | u32 *data = (u32 *) ret; | |
1201 | size_t len = sizeof(u32) * AXIENET_REGS_N; | |
1202 | struct axienet_local *lp = netdev_priv(ndev); | |
1203 | ||
1204 | regs->version = 0; | |
1205 | regs->len = len; | |
1206 | ||
1207 | memset(data, 0, len); | |
1208 | data[0] = axienet_ior(lp, XAE_RAF_OFFSET); | |
1209 | data[1] = axienet_ior(lp, XAE_TPF_OFFSET); | |
1210 | data[2] = axienet_ior(lp, XAE_IFGP_OFFSET); | |
1211 | data[3] = axienet_ior(lp, XAE_IS_OFFSET); | |
1212 | data[4] = axienet_ior(lp, XAE_IP_OFFSET); | |
1213 | data[5] = axienet_ior(lp, XAE_IE_OFFSET); | |
1214 | data[6] = axienet_ior(lp, XAE_TTAG_OFFSET); | |
1215 | data[7] = axienet_ior(lp, XAE_RTAG_OFFSET); | |
1216 | data[8] = axienet_ior(lp, XAE_UAWL_OFFSET); | |
1217 | data[9] = axienet_ior(lp, XAE_UAWU_OFFSET); | |
1218 | data[10] = axienet_ior(lp, XAE_TPID0_OFFSET); | |
1219 | data[11] = axienet_ior(lp, XAE_TPID1_OFFSET); | |
1220 | data[12] = axienet_ior(lp, XAE_PPST_OFFSET); | |
1221 | data[13] = axienet_ior(lp, XAE_RCW0_OFFSET); | |
1222 | data[14] = axienet_ior(lp, XAE_RCW1_OFFSET); | |
1223 | data[15] = axienet_ior(lp, XAE_TC_OFFSET); | |
1224 | data[16] = axienet_ior(lp, XAE_FCC_OFFSET); | |
1225 | data[17] = axienet_ior(lp, XAE_EMMC_OFFSET); | |
1226 | data[18] = axienet_ior(lp, XAE_PHYC_OFFSET); | |
1227 | data[19] = axienet_ior(lp, XAE_MDIO_MC_OFFSET); | |
1228 | data[20] = axienet_ior(lp, XAE_MDIO_MCR_OFFSET); | |
1229 | data[21] = axienet_ior(lp, XAE_MDIO_MWD_OFFSET); | |
1230 | data[22] = axienet_ior(lp, XAE_MDIO_MRD_OFFSET); | |
1231 | data[23] = axienet_ior(lp, XAE_MDIO_MIS_OFFSET); | |
1232 | data[24] = axienet_ior(lp, XAE_MDIO_MIP_OFFSET); | |
1233 | data[25] = axienet_ior(lp, XAE_MDIO_MIE_OFFSET); | |
1234 | data[26] = axienet_ior(lp, XAE_MDIO_MIC_OFFSET); | |
1235 | data[27] = axienet_ior(lp, XAE_UAW0_OFFSET); | |
1236 | data[28] = axienet_ior(lp, XAE_UAW1_OFFSET); | |
1237 | data[29] = axienet_ior(lp, XAE_FMI_OFFSET); | |
1238 | data[30] = axienet_ior(lp, XAE_AF0_OFFSET); | |
1239 | data[31] = axienet_ior(lp, XAE_AF1_OFFSET); | |
867d03bc RH |
1240 | data[32] = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); |
1241 | data[33] = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET); | |
1242 | data[34] = axienet_dma_in32(lp, XAXIDMA_TX_CDESC_OFFSET); | |
1243 | data[35] = axienet_dma_in32(lp, XAXIDMA_TX_TDESC_OFFSET); | |
1244 | data[36] = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); | |
1245 | data[37] = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET); | |
1246 | data[38] = axienet_dma_in32(lp, XAXIDMA_RX_CDESC_OFFSET); | |
1247 | data[39] = axienet_dma_in32(lp, XAXIDMA_RX_TDESC_OFFSET); | |
8a3b7a25 | 1248 | } |
1249 | ||
8b09ca82 RH |
1250 | static void axienet_ethtools_get_ringparam(struct net_device *ndev, |
1251 | struct ethtool_ringparam *ering) | |
1252 | { | |
1253 | struct axienet_local *lp = netdev_priv(ndev); | |
1254 | ||
1255 | ering->rx_max_pending = RX_BD_NUM_MAX; | |
1256 | ering->rx_mini_max_pending = 0; | |
1257 | ering->rx_jumbo_max_pending = 0; | |
1258 | ering->tx_max_pending = TX_BD_NUM_MAX; | |
1259 | ering->rx_pending = lp->rx_bd_num; | |
1260 | ering->rx_mini_pending = 0; | |
1261 | ering->rx_jumbo_pending = 0; | |
1262 | ering->tx_pending = lp->tx_bd_num; | |
1263 | } | |
1264 | ||
1265 | static int axienet_ethtools_set_ringparam(struct net_device *ndev, | |
1266 | struct ethtool_ringparam *ering) | |
1267 | { | |
1268 | struct axienet_local *lp = netdev_priv(ndev); | |
1269 | ||
1270 | if (ering->rx_pending > RX_BD_NUM_MAX || | |
1271 | ering->rx_mini_pending || | |
1272 | ering->rx_jumbo_pending || | |
1273 | ering->rx_pending > TX_BD_NUM_MAX) | |
1274 | return -EINVAL; | |
1275 | ||
1276 | if (netif_running(ndev)) | |
1277 | return -EBUSY; | |
1278 | ||
1279 | lp->rx_bd_num = ering->rx_pending; | |
1280 | lp->tx_bd_num = ering->tx_pending; | |
1281 | return 0; | |
1282 | } | |
1283 | ||
8a3b7a25 | 1284 | /** |
1285 | * axienet_ethtools_get_pauseparam - Get the pause parameter setting for | |
1286 | * Tx and Rx paths. | |
1287 | * @ndev: Pointer to net_device structure | |
1288 | * @epauseparm: Pointer to ethtool_pauseparam structure. | |
1289 | * | |
1290 | * This implements ethtool command for getting axi ethernet pause frame | |
1291 | * setting. Issue "ethtool -a ethX" to execute this function. | |
1292 | */ | |
1293 | static void | |
1294 | axienet_ethtools_get_pauseparam(struct net_device *ndev, | |
1295 | struct ethtool_pauseparam *epauseparm) | |
1296 | { | |
1297 | u32 regval; | |
1298 | struct axienet_local *lp = netdev_priv(ndev); | |
1299 | epauseparm->autoneg = 0; | |
1300 | regval = axienet_ior(lp, XAE_FCC_OFFSET); | |
1301 | epauseparm->tx_pause = regval & XAE_FCC_FCTX_MASK; | |
1302 | epauseparm->rx_pause = regval & XAE_FCC_FCRX_MASK; | |
1303 | } | |
1304 | ||
1305 | /** | |
1306 | * axienet_ethtools_set_pauseparam - Set device pause parameter(flow control) | |
1307 | * settings. | |
1308 | * @ndev: Pointer to net_device structure | |
b0d081c5 | 1309 | * @epauseparm:Pointer to ethtool_pauseparam structure |
8a3b7a25 | 1310 | * |
1311 | * This implements ethtool command for enabling flow control on Rx and Tx | |
1312 | * paths. Issue "ethtool -A ethX tx on|off" under linux prompt to execute this | |
1313 | * function. | |
b0d081c5 MS |
1314 | * |
1315 | * Return: 0 on success, -EFAULT if device is running | |
8a3b7a25 | 1316 | */ |
1317 | static int | |
1318 | axienet_ethtools_set_pauseparam(struct net_device *ndev, | |
1319 | struct ethtool_pauseparam *epauseparm) | |
1320 | { | |
1321 | u32 regval = 0; | |
1322 | struct axienet_local *lp = netdev_priv(ndev); | |
1323 | ||
1324 | if (netif_running(ndev)) { | |
c81a97b5 ST |
1325 | netdev_err(ndev, |
1326 | "Please stop netif before applying configuration\n"); | |
8a3b7a25 | 1327 | return -EFAULT; |
1328 | } | |
1329 | ||
1330 | regval = axienet_ior(lp, XAE_FCC_OFFSET); | |
1331 | if (epauseparm->tx_pause) | |
1332 | regval |= XAE_FCC_FCTX_MASK; | |
1333 | else | |
1334 | regval &= ~XAE_FCC_FCTX_MASK; | |
1335 | if (epauseparm->rx_pause) | |
1336 | regval |= XAE_FCC_FCRX_MASK; | |
1337 | else | |
1338 | regval &= ~XAE_FCC_FCRX_MASK; | |
1339 | axienet_iow(lp, XAE_FCC_OFFSET, regval); | |
1340 | ||
1341 | return 0; | |
1342 | } | |
1343 | ||
1344 | /** | |
1345 | * axienet_ethtools_get_coalesce - Get DMA interrupt coalescing count. | |
1346 | * @ndev: Pointer to net_device structure | |
1347 | * @ecoalesce: Pointer to ethtool_coalesce structure | |
1348 | * | |
1349 | * This implements ethtool command for getting the DMA interrupt coalescing | |
1350 | * count on Tx and Rx paths. Issue "ethtool -c ethX" under linux prompt to | |
1351 | * execute this function. | |
b0d081c5 MS |
1352 | * |
1353 | * Return: 0 always | |
8a3b7a25 | 1354 | */ |
1355 | static int axienet_ethtools_get_coalesce(struct net_device *ndev, | |
1356 | struct ethtool_coalesce *ecoalesce) | |
1357 | { | |
1358 | u32 regval = 0; | |
1359 | struct axienet_local *lp = netdev_priv(ndev); | |
1360 | regval = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); | |
1361 | ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK) | |
1362 | >> XAXIDMA_COALESCE_SHIFT; | |
1363 | regval = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); | |
1364 | ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK) | |
1365 | >> XAXIDMA_COALESCE_SHIFT; | |
1366 | return 0; | |
1367 | } | |
1368 | ||
1369 | /** | |
1370 | * axienet_ethtools_set_coalesce - Set DMA interrupt coalescing count. | |
1371 | * @ndev: Pointer to net_device structure | |
1372 | * @ecoalesce: Pointer to ethtool_coalesce structure | |
1373 | * | |
1374 | * This implements ethtool command for setting the DMA interrupt coalescing | |
1375 | * count on Tx and Rx paths. Issue "ethtool -C ethX rx-frames 5" under linux | |
1376 | * prompt to execute this function. | |
b0d081c5 MS |
1377 | * |
1378 | * Return: 0, on success, Non-zero error value on failure. | |
8a3b7a25 | 1379 | */ |
1380 | static int axienet_ethtools_set_coalesce(struct net_device *ndev, | |
1381 | struct ethtool_coalesce *ecoalesce) | |
1382 | { | |
1383 | struct axienet_local *lp = netdev_priv(ndev); | |
1384 | ||
1385 | if (netif_running(ndev)) { | |
c81a97b5 ST |
1386 | netdev_err(ndev, |
1387 | "Please stop netif before applying configuration\n"); | |
8a3b7a25 | 1388 | return -EFAULT; |
1389 | } | |
1390 | ||
1391 | if ((ecoalesce->rx_coalesce_usecs) || | |
1392 | (ecoalesce->rx_coalesce_usecs_irq) || | |
1393 | (ecoalesce->rx_max_coalesced_frames_irq) || | |
1394 | (ecoalesce->tx_coalesce_usecs) || | |
1395 | (ecoalesce->tx_coalesce_usecs_irq) || | |
1396 | (ecoalesce->tx_max_coalesced_frames_irq) || | |
1397 | (ecoalesce->stats_block_coalesce_usecs) || | |
1398 | (ecoalesce->use_adaptive_rx_coalesce) || | |
1399 | (ecoalesce->use_adaptive_tx_coalesce) || | |
1400 | (ecoalesce->pkt_rate_low) || | |
1401 | (ecoalesce->rx_coalesce_usecs_low) || | |
1402 | (ecoalesce->rx_max_coalesced_frames_low) || | |
1403 | (ecoalesce->tx_coalesce_usecs_low) || | |
1404 | (ecoalesce->tx_max_coalesced_frames_low) || | |
1405 | (ecoalesce->pkt_rate_high) || | |
1406 | (ecoalesce->rx_coalesce_usecs_high) || | |
1407 | (ecoalesce->rx_max_coalesced_frames_high) || | |
1408 | (ecoalesce->tx_coalesce_usecs_high) || | |
1409 | (ecoalesce->tx_max_coalesced_frames_high) || | |
1410 | (ecoalesce->rate_sample_interval)) | |
1411 | return -EOPNOTSUPP; | |
1412 | if (ecoalesce->rx_max_coalesced_frames) | |
1413 | lp->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames; | |
1414 | if (ecoalesce->tx_max_coalesced_frames) | |
1415 | lp->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames; | |
1416 | ||
1417 | return 0; | |
1418 | } | |
1419 | ||
c7735f1b | 1420 | static const struct ethtool_ops axienet_ethtool_ops = { |
8a3b7a25 | 1421 | .get_drvinfo = axienet_ethtools_get_drvinfo, |
1422 | .get_regs_len = axienet_ethtools_get_regs_len, | |
1423 | .get_regs = axienet_ethtools_get_regs, | |
1424 | .get_link = ethtool_op_get_link, | |
8b09ca82 RH |
1425 | .get_ringparam = axienet_ethtools_get_ringparam, |
1426 | .set_ringparam = axienet_ethtools_set_ringparam, | |
8a3b7a25 | 1427 | .get_pauseparam = axienet_ethtools_get_pauseparam, |
1428 | .set_pauseparam = axienet_ethtools_set_pauseparam, | |
1429 | .get_coalesce = axienet_ethtools_get_coalesce, | |
1430 | .set_coalesce = axienet_ethtools_set_coalesce, | |
6e384840 PR |
1431 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
1432 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
8a3b7a25 | 1433 | }; |
1434 | ||
1435 | /** | |
1436 | * axienet_dma_err_handler - Tasklet handler for Axi DMA Error | |
1437 | * @data: Data passed | |
1438 | * | |
1439 | * Resets the Axi DMA and Axi Ethernet devices, and reconfigures the | |
1440 | * Tx/Rx BDs. | |
1441 | */ | |
1442 | static void axienet_dma_err_handler(unsigned long data) | |
1443 | { | |
1444 | u32 axienet_status; | |
1445 | u32 cr, i; | |
8a3b7a25 | 1446 | struct axienet_local *lp = (struct axienet_local *) data; |
1447 | struct net_device *ndev = lp->ndev; | |
1448 | struct axidma_bd *cur_p; | |
1449 | ||
1450 | axienet_setoptions(ndev, lp->options & | |
1451 | ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); | |
8a3b7a25 | 1452 | /* Disable the MDIO interface till Axi Ethernet Reset is completed. |
1453 | * When we do an Axi Ethernet reset, it resets the complete core | |
7789e9ed RH |
1454 | * including the MDIO. MDIO must be disabled before resetting |
1455 | * and re-enabled afterwards. | |
1456 | * Hold MDIO bus lock to avoid MDIO accesses during the reset. | |
850a7503 | 1457 | */ |
7789e9ed RH |
1458 | mutex_lock(&lp->mii_bus->mdio_lock); |
1459 | axienet_mdio_disable(lp); | |
489d4d77 | 1460 | __axienet_device_reset(lp); |
7789e9ed RH |
1461 | axienet_mdio_enable(lp); |
1462 | mutex_unlock(&lp->mii_bus->mdio_lock); | |
8a3b7a25 | 1463 | |
8b09ca82 | 1464 | for (i = 0; i < lp->tx_bd_num; i++) { |
8a3b7a25 | 1465 | cur_p = &lp->tx_bd_v[i]; |
1466 | if (cur_p->phys) | |
1467 | dma_unmap_single(ndev->dev.parent, cur_p->phys, | |
1468 | (cur_p->cntrl & | |
1469 | XAXIDMA_BD_CTRL_LENGTH_MASK), | |
1470 | DMA_TO_DEVICE); | |
23e6b2dc RH |
1471 | if (cur_p->skb) |
1472 | dev_kfree_skb_irq(cur_p->skb); | |
8a3b7a25 | 1473 | cur_p->phys = 0; |
1474 | cur_p->cntrl = 0; | |
1475 | cur_p->status = 0; | |
1476 | cur_p->app0 = 0; | |
1477 | cur_p->app1 = 0; | |
1478 | cur_p->app2 = 0; | |
1479 | cur_p->app3 = 0; | |
1480 | cur_p->app4 = 0; | |
23e6b2dc | 1481 | cur_p->skb = NULL; |
8a3b7a25 | 1482 | } |
1483 | ||
8b09ca82 | 1484 | for (i = 0; i < lp->rx_bd_num; i++) { |
8a3b7a25 | 1485 | cur_p = &lp->rx_bd_v[i]; |
1486 | cur_p->status = 0; | |
1487 | cur_p->app0 = 0; | |
1488 | cur_p->app1 = 0; | |
1489 | cur_p->app2 = 0; | |
1490 | cur_p->app3 = 0; | |
1491 | cur_p->app4 = 0; | |
1492 | } | |
1493 | ||
1494 | lp->tx_bd_ci = 0; | |
1495 | lp->tx_bd_tail = 0; | |
1496 | lp->rx_bd_ci = 0; | |
1497 | ||
1498 | /* Start updating the Rx channel control register */ | |
1499 | cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); | |
1500 | /* Update the interrupt coalesce count */ | |
1501 | cr = ((cr & ~XAXIDMA_COALESCE_MASK) | | |
1502 | (XAXIDMA_DFT_RX_THRESHOLD << XAXIDMA_COALESCE_SHIFT)); | |
1503 | /* Update the delay timer count */ | |
1504 | cr = ((cr & ~XAXIDMA_DELAY_MASK) | | |
1505 | (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT)); | |
1506 | /* Enable coalesce, delay timer and error interrupts */ | |
1507 | cr |= XAXIDMA_IRQ_ALL_MASK; | |
1508 | /* Finally write to the Rx channel control register */ | |
1509 | axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); | |
1510 | ||
1511 | /* Start updating the Tx channel control register */ | |
1512 | cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); | |
1513 | /* Update the interrupt coalesce count */ | |
1514 | cr = (((cr & ~XAXIDMA_COALESCE_MASK)) | | |
1515 | (XAXIDMA_DFT_TX_THRESHOLD << XAXIDMA_COALESCE_SHIFT)); | |
1516 | /* Update the delay timer count */ | |
1517 | cr = (((cr & ~XAXIDMA_DELAY_MASK)) | | |
1518 | (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT)); | |
1519 | /* Enable coalesce, delay timer and error interrupts */ | |
1520 | cr |= XAXIDMA_IRQ_ALL_MASK; | |
1521 | /* Finally write to the Tx channel control register */ | |
1522 | axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); | |
1523 | ||
1524 | /* Populate the tail pointer and bring the Rx Axi DMA engine out of | |
850a7503 MS |
1525 | * halted state. This will make the Rx side ready for reception. |
1526 | */ | |
8a3b7a25 | 1527 | axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p); |
1528 | cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); | |
1529 | axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, | |
1530 | cr | XAXIDMA_CR_RUNSTOP_MASK); | |
1531 | axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p + | |
8b09ca82 | 1532 | (sizeof(*lp->rx_bd_v) * (lp->rx_bd_num - 1))); |
8a3b7a25 | 1533 | |
1534 | /* Write to the RS (Run-stop) bit in the Tx channel control register. | |
1535 | * Tx channel is now ready to run. But only after we write to the | |
850a7503 MS |
1536 | * tail pointer register that the Tx channel will start transmitting |
1537 | */ | |
8a3b7a25 | 1538 | axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p); |
1539 | cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); | |
1540 | axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, | |
1541 | cr | XAXIDMA_CR_RUNSTOP_MASK); | |
1542 | ||
1543 | axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET); | |
1544 | axienet_status &= ~XAE_RCW1_RX_MASK; | |
1545 | axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status); | |
1546 | ||
1547 | axienet_status = axienet_ior(lp, XAE_IP_OFFSET); | |
1548 | if (axienet_status & XAE_INT_RXRJECT_MASK) | |
1549 | axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK); | |
522856ce RH |
1550 | axienet_iow(lp, XAE_IE_OFFSET, lp->eth_irq > 0 ? |
1551 | XAE_INT_RECV_ERROR_MASK : 0); | |
8a3b7a25 | 1552 | axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK); |
1553 | ||
1554 | /* Sync default options with HW but leave receiver and | |
850a7503 MS |
1555 | * transmitter disabled. |
1556 | */ | |
8a3b7a25 | 1557 | axienet_setoptions(ndev, lp->options & |
1558 | ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); | |
1559 | axienet_set_mac_address(ndev, NULL); | |
1560 | axienet_set_multicast_list(ndev); | |
1561 | axienet_setoptions(ndev, lp->options); | |
1562 | } | |
1563 | ||
1564 | /** | |
2be58620 | 1565 | * axienet_probe - Axi Ethernet probe function. |
95219aa5 | 1566 | * @pdev: Pointer to platform device structure. |
8a3b7a25 | 1567 | * |
b0d081c5 | 1568 | * Return: 0, on success |
8a3b7a25 | 1569 | * Non-zero error value on failure. |
1570 | * | |
1571 | * This is the probe routine for Axi Ethernet driver. This is called before | |
1572 | * any other driver routines are invoked. It allocates and sets up the Ethernet | |
1573 | * device. Parses through device tree and populates fields of | |
1574 | * axienet_local. It registers the Ethernet device. | |
1575 | */ | |
2be58620 | 1576 | static int axienet_probe(struct platform_device *pdev) |
8a3b7a25 | 1577 | { |
8495659b | 1578 | int ret; |
8a3b7a25 | 1579 | struct device_node *np; |
1580 | struct axienet_local *lp; | |
1581 | struct net_device *ndev; | |
da90e380 | 1582 | const void *mac_addr; |
46aa27df | 1583 | struct resource *ethres, dmares; |
8495659b | 1584 | u32 value; |
8a3b7a25 | 1585 | |
1586 | ndev = alloc_etherdev(sizeof(*lp)); | |
41de8d4c | 1587 | if (!ndev) |
8a3b7a25 | 1588 | return -ENOMEM; |
8a3b7a25 | 1589 | |
95219aa5 | 1590 | platform_set_drvdata(pdev, ndev); |
8a3b7a25 | 1591 | |
95219aa5 | 1592 | SET_NETDEV_DEV(ndev, &pdev->dev); |
8a3b7a25 | 1593 | ndev->flags &= ~IFF_MULTICAST; /* clear multicast */ |
28e24c62 | 1594 | ndev->features = NETIF_F_SG; |
8a3b7a25 | 1595 | ndev->netdev_ops = &axienet_netdev_ops; |
1596 | ndev->ethtool_ops = &axienet_ethtool_ops; | |
1597 | ||
d894be57 JW |
1598 | /* MTU range: 64 - 9000 */ |
1599 | ndev->min_mtu = 64; | |
1600 | ndev->max_mtu = XAE_JUMBO_MTU; | |
1601 | ||
8a3b7a25 | 1602 | lp = netdev_priv(ndev); |
1603 | lp->ndev = ndev; | |
95219aa5 | 1604 | lp->dev = &pdev->dev; |
8a3b7a25 | 1605 | lp->options = XAE_OPTION_DEFAULTS; |
8b09ca82 RH |
1606 | lp->rx_bd_num = RX_BD_NUM_DEFAULT; |
1607 | lp->tx_bd_num = TX_BD_NUM_DEFAULT; | |
8a3b7a25 | 1608 | /* Map device registers */ |
46aa27df | 1609 | ethres = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
88a972d7 | 1610 | lp->regs_start = ethres->start; |
46aa27df | 1611 | lp->regs = devm_ioremap_resource(&pdev->dev, ethres); |
fcc028c1 | 1612 | if (IS_ERR(lp->regs)) { |
95219aa5 | 1613 | dev_err(&pdev->dev, "could not map Axi Ethernet regs.\n"); |
fcc028c1 | 1614 | ret = PTR_ERR(lp->regs); |
46aa27df | 1615 | goto free_netdev; |
8a3b7a25 | 1616 | } |
46aa27df | 1617 | |
8a3b7a25 | 1618 | /* Setup checksum offload, but default to off if not specified */ |
1619 | lp->features = 0; | |
1620 | ||
8495659b ST |
1621 | ret = of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value); |
1622 | if (!ret) { | |
1623 | switch (value) { | |
8a3b7a25 | 1624 | case 1: |
1625 | lp->csum_offload_on_tx_path = | |
1626 | XAE_FEATURE_PARTIAL_TX_CSUM; | |
1627 | lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM; | |
1628 | /* Can checksum TCP/UDP over IPv4. */ | |
1629 | ndev->features |= NETIF_F_IP_CSUM; | |
1630 | break; | |
1631 | case 2: | |
1632 | lp->csum_offload_on_tx_path = | |
1633 | XAE_FEATURE_FULL_TX_CSUM; | |
1634 | lp->features |= XAE_FEATURE_FULL_TX_CSUM; | |
1635 | /* Can checksum TCP/UDP over IPv4. */ | |
1636 | ndev->features |= NETIF_F_IP_CSUM; | |
1637 | break; | |
1638 | default: | |
1639 | lp->csum_offload_on_tx_path = XAE_NO_CSUM_OFFLOAD; | |
1640 | } | |
1641 | } | |
8495659b ST |
1642 | ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxcsum", &value); |
1643 | if (!ret) { | |
1644 | switch (value) { | |
8a3b7a25 | 1645 | case 1: |
1646 | lp->csum_offload_on_rx_path = | |
1647 | XAE_FEATURE_PARTIAL_RX_CSUM; | |
1648 | lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM; | |
1649 | break; | |
1650 | case 2: | |
1651 | lp->csum_offload_on_rx_path = | |
1652 | XAE_FEATURE_FULL_RX_CSUM; | |
1653 | lp->features |= XAE_FEATURE_FULL_RX_CSUM; | |
1654 | break; | |
1655 | default: | |
1656 | lp->csum_offload_on_rx_path = XAE_NO_CSUM_OFFLOAD; | |
1657 | } | |
1658 | } | |
1659 | /* For supporting jumbo frames, the Axi Ethernet hardware must have | |
f080a8c3 ST |
1660 | * a larger Rx/Tx Memory. Typically, the size must be large so that |
1661 | * we can enable jumbo option and start supporting jumbo frames. | |
1662 | * Here we check for memory allocated for Rx/Tx in the hardware from | |
1663 | * the device-tree and accordingly set flags. | |
1664 | */ | |
8495659b | 1665 | of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem); |
ee06b172 A |
1666 | |
1667 | /* Start with the proprietary, and broken phy_type */ | |
1668 | ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value); | |
1669 | if (!ret) { | |
1670 | netdev_warn(ndev, "Please upgrade your device tree binary blob to use phy-mode"); | |
1671 | switch (value) { | |
1672 | case XAE_PHY_TYPE_MII: | |
1673 | lp->phy_mode = PHY_INTERFACE_MODE_MII; | |
1674 | break; | |
1675 | case XAE_PHY_TYPE_GMII: | |
1676 | lp->phy_mode = PHY_INTERFACE_MODE_GMII; | |
1677 | break; | |
1678 | case XAE_PHY_TYPE_RGMII_2_0: | |
1679 | lp->phy_mode = PHY_INTERFACE_MODE_RGMII_ID; | |
1680 | break; | |
1681 | case XAE_PHY_TYPE_SGMII: | |
1682 | lp->phy_mode = PHY_INTERFACE_MODE_SGMII; | |
1683 | break; | |
1684 | case XAE_PHY_TYPE_1000BASE_X: | |
1685 | lp->phy_mode = PHY_INTERFACE_MODE_1000BASEX; | |
1686 | break; | |
1687 | default: | |
1688 | ret = -EINVAL; | |
1689 | goto free_netdev; | |
1690 | } | |
1691 | } else { | |
1692 | lp->phy_mode = of_get_phy_mode(pdev->dev.of_node); | |
1693 | if (lp->phy_mode < 0) { | |
1694 | ret = -EINVAL; | |
1695 | goto free_netdev; | |
1696 | } | |
1697 | } | |
8a3b7a25 | 1698 | |
1699 | /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ | |
95219aa5 | 1700 | np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0); |
3ad7b147 | 1701 | if (!np) { |
95219aa5 | 1702 | dev_err(&pdev->dev, "could not find DMA node\n"); |
3ad7b147 | 1703 | ret = -ENODEV; |
46aa27df | 1704 | goto free_netdev; |
8a3b7a25 | 1705 | } |
46aa27df ST |
1706 | ret = of_address_to_resource(np, 0, &dmares); |
1707 | if (ret) { | |
1708 | dev_err(&pdev->dev, "unable to get DMA resource\n"); | |
fa3a419d | 1709 | of_node_put(np); |
46aa27df ST |
1710 | goto free_netdev; |
1711 | } | |
1712 | lp->dma_regs = devm_ioremap_resource(&pdev->dev, &dmares); | |
fcc028c1 | 1713 | if (IS_ERR(lp->dma_regs)) { |
46aa27df | 1714 | dev_err(&pdev->dev, "could not map DMA regs\n"); |
fcc028c1 | 1715 | ret = PTR_ERR(lp->dma_regs); |
fa3a419d | 1716 | of_node_put(np); |
46aa27df | 1717 | goto free_netdev; |
8a3b7a25 | 1718 | } |
1719 | lp->rx_irq = irq_of_parse_and_map(np, 1); | |
1720 | lp->tx_irq = irq_of_parse_and_map(np, 0); | |
522856ce | 1721 | lp->eth_irq = irq_of_parse_and_map(np, 2); |
8a3b7a25 | 1722 | of_node_put(np); |
cb59c87d | 1723 | if ((lp->rx_irq <= 0) || (lp->tx_irq <= 0)) { |
95219aa5 | 1724 | dev_err(&pdev->dev, "could not determine irqs\n"); |
8a3b7a25 | 1725 | ret = -ENOMEM; |
46aa27df | 1726 | goto free_netdev; |
8a3b7a25 | 1727 | } |
1728 | ||
522856ce RH |
1729 | /* Check for Ethernet core IRQ (optional) */ |
1730 | if (lp->eth_irq <= 0) | |
1731 | dev_info(&pdev->dev, "Ethernet core IRQ not defined\n"); | |
1732 | ||
8a3b7a25 | 1733 | /* Retrieve the MAC address */ |
da90e380 | 1734 | mac_addr = of_get_mac_address(pdev->dev.of_node); |
a51645f7 | 1735 | if (IS_ERR(mac_addr)) { |
95219aa5 | 1736 | dev_err(&pdev->dev, "could not find MAC address\n"); |
46aa27df | 1737 | goto free_netdev; |
8a3b7a25 | 1738 | } |
da90e380 | 1739 | axienet_set_mac_address(ndev, mac_addr); |
8a3b7a25 | 1740 | |
1741 | lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD; | |
1742 | lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD; | |
1743 | ||
95219aa5 | 1744 | lp->phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); |
46aa27df | 1745 | if (lp->phy_node) { |
09a0354c RH |
1746 | lp->clk = devm_clk_get(&pdev->dev, NULL); |
1747 | if (IS_ERR(lp->clk)) { | |
1748 | dev_warn(&pdev->dev, "Failed to get clock: %ld\n", | |
1749 | PTR_ERR(lp->clk)); | |
1750 | lp->clk = NULL; | |
1751 | } else { | |
1752 | ret = clk_prepare_enable(lp->clk); | |
1753 | if (ret) { | |
1754 | dev_err(&pdev->dev, "Unable to enable clock: %d\n", | |
1755 | ret); | |
1756 | goto free_netdev; | |
1757 | } | |
1758 | } | |
1759 | ||
1760 | ret = axienet_mdio_setup(lp); | |
46aa27df | 1761 | if (ret) |
09a0354c RH |
1762 | dev_warn(&pdev->dev, |
1763 | "error registering MDIO bus: %d\n", ret); | |
46aa27df | 1764 | } |
8a3b7a25 | 1765 | |
1766 | ret = register_netdev(lp->ndev); | |
1767 | if (ret) { | |
1768 | dev_err(lp->dev, "register_netdev() error (%i)\n", ret); | |
46aa27df | 1769 | goto free_netdev; |
8a3b7a25 | 1770 | } |
1771 | ||
8a3b7a25 | 1772 | return 0; |
1773 | ||
46aa27df | 1774 | free_netdev: |
8a3b7a25 | 1775 | free_netdev(ndev); |
46aa27df | 1776 | |
8a3b7a25 | 1777 | return ret; |
1778 | } | |
1779 | ||
2be58620 | 1780 | static int axienet_remove(struct platform_device *pdev) |
8a3b7a25 | 1781 | { |
95219aa5 | 1782 | struct net_device *ndev = platform_get_drvdata(pdev); |
8a3b7a25 | 1783 | struct axienet_local *lp = netdev_priv(ndev); |
1784 | ||
8a3b7a25 | 1785 | unregister_netdev(ndev); |
e7a3d116 | 1786 | axienet_mdio_teardown(lp); |
8a3b7a25 | 1787 | |
09a0354c RH |
1788 | if (lp->clk) |
1789 | clk_disable_unprepare(lp->clk); | |
1790 | ||
6f3a59ac | 1791 | of_node_put(lp->phy_node); |
8a3b7a25 | 1792 | lp->phy_node = NULL; |
1793 | ||
8a3b7a25 | 1794 | free_netdev(ndev); |
1795 | ||
1796 | return 0; | |
1797 | } | |
1798 | ||
2be58620 ST |
1799 | static struct platform_driver axienet_driver = { |
1800 | .probe = axienet_probe, | |
1801 | .remove = axienet_remove, | |
8a3b7a25 | 1802 | .driver = { |
8a3b7a25 | 1803 | .name = "xilinx_axienet", |
1804 | .of_match_table = axienet_of_match, | |
1805 | }, | |
1806 | }; | |
1807 | ||
2be58620 | 1808 | module_platform_driver(axienet_driver); |
8a3b7a25 | 1809 | |
1810 | MODULE_DESCRIPTION("Xilinx Axi Ethernet driver"); | |
1811 | MODULE_AUTHOR("Xilinx"); | |
1812 | MODULE_LICENSE("GPL"); |