[linux-2.6-block.git] / drivers / net / ethernet / ti / davinci_mdio.c

/*
 * DaVinci MDIO Module driver
 *
 * Copyright (C) 2010 Texas Instruments.
 *
 * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
 *
 * Copyright (C) 2009 Texas Instruments.
 *
 * ---------------------------------------------------------------------------
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 * ---------------------------------------------------------------------------
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/phy.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/davinci_emac.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_mdio.h>
#include <linux/pinctrl/consumer.h>

/*
 * This timeout definition is a worst-case ultra defensive measure against
 * unexpected controller lock ups.  Ideally, we should never ever hit this
 * scenario in practice.
 */
#define MDIO_TIMEOUT		100 /* msecs */

#define PHY_REG_MASK		0x1f
#define PHY_ID_MASK		0x1f

#define DEF_OUT_FREQ		2200000		/* 2.2 MHz */

struct davinci_mdio_of_param {
	int autosuspend_delay_ms;
};

struct davinci_mdio_regs {
	u32	version;
	u32	control;
#define CONTROL_IDLE		BIT(31)
#define CONTROL_ENABLE		BIT(30)
#define CONTROL_MAX_DIV		(0xffff)

	u32	alive;
	u32	link;
	u32	linkintraw;
	u32	linkintmasked;
	u32	__reserved_0[2];
	u32	userintraw;
	u32	userintmasked;
	u32	userintmaskset;
	u32	userintmaskclr;
	u32	__reserved_1[20];

	struct {
		u32	access;
#define USERACCESS_GO		BIT(31)
#define USERACCESS_WRITE	BIT(30)
#define USERACCESS_ACK		BIT(29)
#define USERACCESS_READ		(0)
#define USERACCESS_DATA		(0xffff)

		u32	physel;
	}	user[0];
};

static const struct mdio_platform_data default_pdata = {
	.bus_freq = DEF_OUT_FREQ,
};

struct davinci_mdio_data {
	struct mdio_platform_data pdata;
	struct davinci_mdio_regs __iomem *regs;
	struct clk	*clk;
	struct device	*dev;
	struct mii_bus	*bus;
	bool            active_in_suspend;
	unsigned long	access_time; /* jiffies */
	/* Indicates that driver shouldn't modify phy_mask in case
	 * if MDIO bus is registered from DT.
	 */
	bool		skip_scan;
	u32		clk_div;
};

static void davinci_mdio_init_clk(struct davinci_mdio_data *data)
{
	u32 mdio_in, div, mdio_out_khz, access_time;

	mdio_in = clk_get_rate(data->clk);
	div = (mdio_in / data->pdata.bus_freq) - 1;
	if (div > CONTROL_MAX_DIV)
		div = CONTROL_MAX_DIV;

	data->clk_div = div;
	/*
	 * One mdio transaction consists of:
	 *	32 bits of preamble
	 *	32 bits of transferred data
	 *	24 bits of bus yield (not needed unless shared?)
	 */
	mdio_out_khz = mdio_in / (1000 * (div + 1));
	access_time  = (88 * 1000) / mdio_out_khz;

	/*
	 * In the worst case, we could be kicking off a user-access immediately
	 * after the mdio bus scan state-machine triggered its own read.  If
	 * so, our request could get deferred by one access cycle.  We
	 * defensively allow for 4 access cycles.
	 */
	data->access_time = usecs_to_jiffies(access_time * 4);
	if (!data->access_time)
		data->access_time = 1;
}

static void davinci_mdio_enable(struct davinci_mdio_data *data)
{
	/* set enable and clock divider */
	__raw_writel(data->clk_div | CONTROL_ENABLE, &data->regs->control);
}

static int davinci_mdio_reset(struct mii_bus *bus)
{
	struct davinci_mdio_data *data = bus->priv;
	u32 phy_mask, ver;
	int ret;

	ret = pm_runtime_get_sync(data->dev);
	if (ret < 0) {
		pm_runtime_put_noidle(data->dev);
		return ret;
	}

	/* wait for scan logic to settle */
	msleep(PHY_MAX_ADDR * data->access_time);

	/* dump hardware version info */
	ver = __raw_readl(&data->regs->version);
	dev_info(data->dev, "davinci mdio revision %d.%d\n",
		 (ver >> 8) & 0xff, ver & 0xff);

	if (data->skip_scan)
		goto done;

	/* get phy mask from the alive register */
	phy_mask = __raw_readl(&data->regs->alive);
	if (phy_mask) {
		/* restrict mdio bus to live phys only */
		dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
		phy_mask = ~phy_mask;
	} else {
		/* desperately scan all phys */
		dev_warn(data->dev, "no live phy, scanning all\n");
		phy_mask = 0;
	}
	data->bus->phy_mask = phy_mask;

done:
	pm_runtime_mark_last_busy(data->dev);
	pm_runtime_put_autosuspend(data->dev);

	return 0;
}

/* wait until hardware is ready for another user access */
static inline int wait_for_user_access(struct davinci_mdio_data *data)
{
	struct davinci_mdio_regs __iomem *regs = data->regs;
	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
	u32 reg;

	while (time_after(timeout, jiffies)) {
		reg = __raw_readl(&regs->user[0].access);
		if ((reg & USERACCESS_GO) == 0)
			return 0;

		reg = __raw_readl(&regs->control);
		if ((reg & CONTROL_IDLE) == 0)
			continue;

		/*
		 * An emac soft_reset may have clobbered the mdio controller's
		 * state machine.  We need to reset and retry the current
		 * operation
		 */
		dev_warn(data->dev, "resetting idled controller\n");
		davinci_mdio_enable(data);
		return -EAGAIN;
	}

	reg = __raw_readl(&regs->user[0].access);
	if ((reg & USERACCESS_GO) == 0)
		return 0;

	dev_err(data->dev, "timed out waiting for user access\n");
	return -ETIMEDOUT;
}

/* wait until hardware state machine is idle */
static inline int wait_for_idle(struct davinci_mdio_data *data)
{
	struct davinci_mdio_regs __iomem *regs = data->regs;
	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);

	while (time_after(timeout, jiffies)) {
		if (__raw_readl(&regs->control) & CONTROL_IDLE)
			return 0;
	}
	dev_err(data->dev, "timed out waiting for idle\n");
	return -ETIMEDOUT;
}

static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
{
	struct davinci_mdio_data *data = bus->priv;
	u32 reg;
	int ret;

	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
		return -EINVAL;

	ret = pm_runtime_get_sync(data->dev);
	if (ret < 0) {
		pm_runtime_put_noidle(data->dev);
		return ret;
	}

	reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
	       (phy_id << 16));

	while (1) {
		ret = wait_for_user_access(data);
		if (ret == -EAGAIN)
			continue;
		if (ret < 0)
			break;

		__raw_writel(reg, &data->regs->user[0].access);

		ret = wait_for_user_access(data);
		if (ret == -EAGAIN)
			continue;
		if (ret < 0)
			break;

		reg = __raw_readl(&data->regs->user[0].access);
		ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
		break;
	}

	pm_runtime_mark_last_busy(data->dev);
	pm_runtime_put_autosuspend(data->dev);
	return ret;
}

static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
			      int phy_reg, u16 phy_data)
{
	struct davinci_mdio_data *data = bus->priv;
	u32 reg;
	int ret;

	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
		return -EINVAL;

	ret = pm_runtime_get_sync(data->dev);
	if (ret < 0) {
		pm_runtime_put_noidle(data->dev);
		return ret;
	}

	reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
		   (phy_id << 16) | (phy_data & USERACCESS_DATA));

	while (1) {
		ret = wait_for_user_access(data);
		if (ret == -EAGAIN)
			continue;
		if (ret < 0)
			break;

		__raw_writel(reg, &data->regs->user[0].access);

		ret = wait_for_user_access(data);
		if (ret == -EAGAIN)
			continue;
		break;
	}

	pm_runtime_mark_last_busy(data->dev);
	pm_runtime_put_autosuspend(data->dev);

	return ret;
}

#if IS_ENABLED(CONFIG_OF)
static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
			 struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	u32 prop;

	if (!node)
		return -EINVAL;

	if (of_property_read_u32(node, "bus_freq", &prop)) {
		dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n");
		return -EINVAL;
	}
	data->bus_freq = prop;

	return 0;
}
#endif

#if IS_ENABLED(CONFIG_OF)
static const struct davinci_mdio_of_param of_cpsw_mdio_data = {
	.autosuspend_delay_ms = 100,
};

static const struct of_device_id davinci_mdio_of_mtable[] = {
	{ .compatible = "ti,davinci_mdio", },
	{ .compatible = "ti,cpsw-mdio", .data = &of_cpsw_mdio_data},
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
#endif

static int davinci_mdio_probe(struct platform_device *pdev)
{
	struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct device *dev = &pdev->dev;
	struct davinci_mdio_data *data;
	struct resource *res;
	struct phy_device *phy;
	int ret, addr;
	int autosuspend_delay_ms = -1;

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->bus = devm_mdiobus_alloc(dev);
	if (!data->bus) {
		dev_err(dev, "failed to alloc mii bus\n");
		return -ENOMEM;
	}

	if (dev->of_node) {
		const struct of_device_id	*of_id;

		ret = davinci_mdio_probe_dt(&data->pdata, pdev);
		if (ret)
			return ret;
		snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);

		of_id = of_match_device(davinci_mdio_of_mtable, &pdev->dev);
		if (of_id) {
			const struct davinci_mdio_of_param *of_mdio_data;

			of_mdio_data = of_id->data;
			if (of_mdio_data)
				autosuspend_delay_ms =
					of_mdio_data->autosuspend_delay_ms;
		}
	} else {
		data->pdata = pdata ? (*pdata) : default_pdata;
		snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
			 pdev->name, pdev->id);
	}

	data->bus->name		= dev_name(dev);
	data->bus->read		= davinci_mdio_read,
	data->bus->write	= davinci_mdio_write,
	data->bus->reset	= davinci_mdio_reset,
	data->bus->parent	= dev;
	data->bus->priv		= data;

	data->clk = devm_clk_get(dev, "fck");
	if (IS_ERR(data->clk)) {
		dev_err(dev, "failed to get device clock\n");
		return PTR_ERR(data->clk);
	}

	dev_set_drvdata(dev, data);
	data->dev = dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	data->regs = devm_ioremap_resource(dev, res);
	if (IS_ERR(data->regs))
		return PTR_ERR(data->regs);

	davinci_mdio_init_clk(data);

	pm_runtime_set_autosuspend_delay(&pdev->dev, autosuspend_delay_ms);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_enable(&pdev->dev);

	/* register the mii bus
	 * Create PHYs from DT only in case if PHY child nodes are explicitly
	 * defined to support backward compatibility with DTs which assume that
	 * Davinci MDIO will always scan the bus for PHYs detection.
	 */
	if (dev->of_node && of_get_child_count(dev->of_node)) {
		data->skip_scan = true;
		ret = of_mdiobus_register(data->bus, dev->of_node);
	} else {
		ret = mdiobus_register(data->bus);
	}
	if (ret)
		goto bail_out;

	/* scan and dump the bus */
	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
		phy = mdiobus_get_phy(data->bus, addr);
		if (phy) {
			dev_info(dev, "phy[%d]: device %s, driver %s\n",
				 phy->mdio.addr, phydev_name(phy),
				 phy->drv ? phy->drv->name : "unknown");
		}
	}

	return 0;

bail_out:
	pm_runtime_dont_use_autosuspend(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	return ret;
}

static int davinci_mdio_remove(struct platform_device *pdev)
{
	struct davinci_mdio_data *data = platform_get_drvdata(pdev);

	if (data->bus)
		mdiobus_unregister(data->bus);

	pm_runtime_dont_use_autosuspend(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

#ifdef CONFIG_PM
static int davinci_mdio_runtime_suspend(struct device *dev)
{
	struct davinci_mdio_data *data = dev_get_drvdata(dev);
	u32 ctrl;

	/* shutdown the scan state machine */
	ctrl = __raw_readl(&data->regs->control);
	ctrl &= ~CONTROL_ENABLE;
	__raw_writel(ctrl, &data->regs->control);
	wait_for_idle(data);

	return 0;
}

static int davinci_mdio_runtime_resume(struct device *dev)
{
	struct davinci_mdio_data *data = dev_get_drvdata(dev);

	davinci_mdio_enable(data);
	return 0;
}
#endif

#ifdef CONFIG_PM_SLEEP
static int davinci_mdio_suspend(struct device *dev)
{
	struct davinci_mdio_data *data = dev_get_drvdata(dev);
	int ret = 0;

	data->active_in_suspend = !pm_runtime_status_suspended(dev);
	if (data->active_in_suspend)
		ret = pm_runtime_force_suspend(dev);
	if (ret < 0)
		return ret;

	/* Select sleep pin state */
	pinctrl_pm_select_sleep_state(dev);

	return 0;
}

static int davinci_mdio_resume(struct device *dev)
{
	struct davinci_mdio_data *data = dev_get_drvdata(dev);

	/* Select default pin state */
	pinctrl_pm_select_default_state(dev);

	if (data->active_in_suspend)
		pm_runtime_force_resume(dev);

	return 0;
}
#endif

static const struct dev_pm_ops davinci_mdio_pm_ops = {
	SET_RUNTIME_PM_OPS(davinci_mdio_runtime_suspend,
			   davinci_mdio_runtime_resume, NULL)
	SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume)
};

static struct platform_driver davinci_mdio_driver = {
	.driver = {
		.name	 = "davinci_mdio",
		.pm	 = &davinci_mdio_pm_ops,
		.of_match_table = of_match_ptr(davinci_mdio_of_mtable),
	},
	.probe = davinci_mdio_probe,
	.remove = davinci_mdio_remove,
};

static int __init davinci_mdio_init(void)
{
	return platform_driver_register(&davinci_mdio_driver);
}
device_initcall(davinci_mdio_init);

static void __exit davinci_mdio_exit(void)
{
	platform_driver_unregister(&davinci_mdio_driver);
}
module_exit(davinci_mdio_exit);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("DaVinci MDIO driver");
Commit	Line	Data
f20136eb CC	1	/*
	2	* DaVinci MDIO Module driver
	3	*
	4	* Copyright (C) 2010 Texas Instruments.
	5	*
	6	* Shamelessly ripped out of davinci_emac.c, original copyrights follow:
	7	*
	8	* Copyright (C) 2009 Texas Instruments.
	9	*
	10	* ---------------------------------------------------------------------------
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2 of the License, or
	15	* (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	25	* ---------------------------------------------------------------------------
	26	*/
	27	#include <linux/module.h>
	28	#include <linux/kernel.h>
	29	#include <linux/platform_device.h>
	30	#include <linux/delay.h>
	31	#include <linux/sched.h>
	32	#include <linux/slab.h>
	33	#include <linux/phy.h>
	34	#include <linux/clk.h>
	35	#include <linux/err.h>
	36	#include <linux/io.h>
8e476d9d	37	#include <linux/pm_runtime.h>
f20136eb	38	#include <linux/davinci_emac.h>
ec03e6a8 M	39	#include <linux/of.h>
ec03e6a8 M	40	#include <linux/of_device.h>
0a0ea068	41	#include <linux/of_mdio.h>
5c0e3580	42	#include <linux/pinctrl/consumer.h>
f20136eb CC	43
	44	/*
	45	* This timeout definition is a worst-case ultra defensive measure against
	46	* unexpected controller lock ups. Ideally, we should never ever hit this
	47	* scenario in practice.
	48	*/
	49	#define MDIO_TIMEOUT 100 /* msecs */
	50
	51	#define PHY_REG_MASK 0x1f
	52	#define PHY_ID_MASK 0x1f
	53
	54	#define DEF_OUT_FREQ 2200000 /* 2.2 MHz */
	55
9eae9c7d GS	56	struct davinci_mdio_of_param {
	57	int autosuspend_delay_ms;
	58	};
	59
f20136eb CC	60	struct davinci_mdio_regs {
	61	u32 version;
	62	u32 control;
	63	#define CONTROL_IDLE BIT(31)
	64	#define CONTROL_ENABLE BIT(30)
7c3a95a1	65	#define CONTROL_MAX_DIV (0xffff)
f20136eb CC	66
	67	u32 alive;
	68	u32 link;
	69	u32 linkintraw;
	70	u32 linkintmasked;
	71	u32 __reserved_0[2];
	72	u32 userintraw;
	73	u32 userintmasked;
	74	u32 userintmaskset;
	75	u32 userintmaskclr;
	76	u32 __reserved_1[20];
	77
	78	struct {
	79	u32 access;
	80	#define USERACCESS_GO BIT(31)
	81	#define USERACCESS_WRITE BIT(30)
	82	#define USERACCESS_ACK BIT(29)
	83	#define USERACCESS_READ (0)
	84	#define USERACCESS_DATA (0xffff)
	85
	86	u32 physel;
	87	} user[0];
	88	};
	89
9b05f462	90	static const struct mdio_platform_data default_pdata = {
f20136eb CC	91	.bus_freq = DEF_OUT_FREQ,
	92	};
	93
	94	struct davinci_mdio_data {
	95	struct mdio_platform_data pdata;
	96	struct davinci_mdio_regs __iomem *regs;
f20136eb CC	97	struct clk *clk;
	98	struct device *dev;
	99	struct mii_bus *bus;
8ea63bba	100	bool active_in_suspend;
f20136eb	101	unsigned long access_time; /* jiffies */
0a0ea068 GS	102	/* Indicates that driver shouldn't modify phy_mask in case
	103	* if MDIO bus is registered from DT.
	104	*/
	105	bool skip_scan;
28f0ccb9	106	u32 clk_div;
f20136eb CC	107	};
f20136eb CC	108
28f0ccb9	109	static void davinci_mdio_init_clk(struct davinci_mdio_data *data)
f20136eb CC	110	{
	111	u32 mdio_in, div, mdio_out_khz, access_time;
	112
	113	mdio_in = clk_get_rate(data->clk);
	114	div = (mdio_in / data->pdata.bus_freq) - 1;
	115	if (div > CONTROL_MAX_DIV)
	116	div = CONTROL_MAX_DIV;
	117
28f0ccb9	118	data->clk_div = div;
f20136eb CC	119	/*
	120	* One mdio transaction consists of:
	121	* 32 bits of preamble
	122	* 32 bits of transferred data
	123	* 24 bits of bus yield (not needed unless shared?)
	124	*/
	125	mdio_out_khz = mdio_in / (1000 * (div + 1));
	126	access_time = (88 * 1000) / mdio_out_khz;
	127
	128	/*
	129	* In the worst case, we could be kicking off a user-access immediately
	130	* after the mdio bus scan state-machine triggered its own read. If
	131	* so, our request could get deferred by one access cycle. We
	132	* defensively allow for 4 access cycles.
	133	*/
	134	data->access_time = usecs_to_jiffies(access_time * 4);
	135	if (!data->access_time)
	136	data->access_time = 1;
	137	}
	138
28f0ccb9 GS	139	static void davinci_mdio_enable(struct davinci_mdio_data *data)
	140	{
	141	/* set enable and clock divider */
	142	__raw_writel(data->clk_div \| CONTROL_ENABLE, &data->regs->control);
	143	}
	144
f20136eb CC	145	static int davinci_mdio_reset(struct mii_bus *bus)
	146	{
	147	struct davinci_mdio_data *data = bus->priv;
	148	u32 phy_mask, ver;
8ea63bba	149	int ret;
f20136eb	150
8ea63bba GS	151	ret = pm_runtime_get_sync(data->dev);
	152	if (ret < 0) {
	153	pm_runtime_put_noidle(data->dev);
	154	return ret;
	155	}
f20136eb CC	156
	157	/* wait for scan logic to settle */
	158	msleep(PHY_MAX_ADDR * data->access_time);
	159
	160	/* dump hardware version info */
	161	ver = __raw_readl(&data->regs->version);
	162	dev_info(data->dev, "davinci mdio revision %d.%d\n",
	163	(ver >> 8) & 0xff, ver & 0xff);
	164
0a0ea068	165	if (data->skip_scan)
8ea63bba	166	goto done;
0a0ea068	167
f20136eb CC	168	/* get phy mask from the alive register */
	169	phy_mask = __raw_readl(&data->regs->alive);
	170	if (phy_mask) {
	171	/* restrict mdio bus to live phys only */
	172	dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
	173	phy_mask = ~phy_mask;
	174	} else {
	175	/* desperately scan all phys */
	176	dev_warn(data->dev, "no live phy, scanning all\n");
	177	phy_mask = 0;
	178	}
	179	data->bus->phy_mask = phy_mask;
	180
8ea63bba GS	181	done:
	182	pm_runtime_mark_last_busy(data->dev);
	183	pm_runtime_put_autosuspend(data->dev);
	184
f20136eb CC	185	return 0;
	186	}
	187
	188	/* wait until hardware is ready for another user access */
	189	static inline int wait_for_user_access(struct davinci_mdio_data *data)
	190	{
	191	struct davinci_mdio_regs __iomem *regs = data->regs;
	192	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
	193	u32 reg;
	194
	195	while (time_after(timeout, jiffies)) {
	196	reg = __raw_readl(&regs->user[0].access);
	197	if ((reg & USERACCESS_GO) == 0)
	198	return 0;
	199
	200	reg = __raw_readl(&regs->control);
	201	if ((reg & CONTROL_IDLE) == 0)
	202	continue;
	203
	204	/*
	205	* An emac soft_reset may have clobbered the mdio controller's
	206	* state machine. We need to reset and retry the current
	207	* operation
	208	*/
	209	dev_warn(data->dev, "resetting idled controller\n");
28f0ccb9	210	davinci_mdio_enable(data);
f20136eb CC	211	return -EAGAIN;
f20136eb CC	212	}
5b76d060 CR	213
	214	reg = __raw_readl(&regs->user[0].access);
	215	if ((reg & USERACCESS_GO) == 0)
	216	return 0;
	217
f20136eb CC	218	dev_err(data->dev, "timed out waiting for user access\n");
	219	return -ETIMEDOUT;
	220	}
	221
	222	/* wait until hardware state machine is idle */
	223	static inline int wait_for_idle(struct davinci_mdio_data *data)
	224	{
	225	struct davinci_mdio_regs __iomem *regs = data->regs;
	226	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
	227
	228	while (time_after(timeout, jiffies)) {
	229	if (__raw_readl(&regs->control) & CONTROL_IDLE)
	230	return 0;
	231	}
	232	dev_err(data->dev, "timed out waiting for idle\n");
	233	return -ETIMEDOUT;
	234	}
	235
	236	static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
	237	{
	238	struct davinci_mdio_data *data = bus->priv;
	239	u32 reg;
	240	int ret;
	241
	242	if (phy_reg & ~PHY_REG_MASK \|\| phy_id & ~PHY_ID_MASK)
	243	return -EINVAL;
	244
8ea63bba GS	245	ret = pm_runtime_get_sync(data->dev);
	246	if (ret < 0) {
	247	pm_runtime_put_noidle(data->dev);
	248	return ret;
	249	}
	250
f20136eb CC	251	reg = (USERACCESS_GO \| USERACCESS_READ \| (phy_reg << 21) \|
	252	(phy_id << 16));
	253
	254	while (1) {
	255	ret = wait_for_user_access(data);
	256	if (ret == -EAGAIN)
	257	continue;
	258	if (ret < 0)
	259	break;
	260
	261	__raw_writel(reg, &data->regs->user[0].access);
	262
	263	ret = wait_for_user_access(data);
	264	if (ret == -EAGAIN)
	265	continue;
	266	if (ret < 0)
	267	break;
	268
	269	reg = __raw_readl(&data->regs->user[0].access);
	270	ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
	271	break;
	272	}
	273
8ea63bba GS	274	pm_runtime_mark_last_busy(data->dev);
8ea63bba GS	275	pm_runtime_put_autosuspend(data->dev);
f20136eb CC	276	return ret;
	277	}
	278
	279	static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
	280	int phy_reg, u16 phy_data)
	281	{
	282	struct davinci_mdio_data *data = bus->priv;
	283	u32 reg;
	284	int ret;
	285
	286	if (phy_reg & ~PHY_REG_MASK \|\| phy_id & ~PHY_ID_MASK)
	287	return -EINVAL;
	288
8ea63bba GS	289	ret = pm_runtime_get_sync(data->dev);
	290	if (ret < 0) {
	291	pm_runtime_put_noidle(data->dev);
	292	return ret;
	293	}
	294
f20136eb CC	295	reg = (USERACCESS_GO \| USERACCESS_WRITE \| (phy_reg << 21) \|
	296	(phy_id << 16) \| (phy_data & USERACCESS_DATA));
	297
	298	while (1) {
	299	ret = wait_for_user_access(data);
	300	if (ret == -EAGAIN)
	301	continue;
	302	if (ret < 0)
	303	break;
	304
	305	__raw_writel(reg, &data->regs->user[0].access);
	306
	307	ret = wait_for_user_access(data);
	308	if (ret == -EAGAIN)
	309	continue;
	310	break;
	311	}
	312
8ea63bba GS	313	pm_runtime_mark_last_busy(data->dev);
	314	pm_runtime_put_autosuspend(data->dev);
	315
	316	return ret;
f20136eb CC	317	}
f20136eb CC	318
277e2a84	319	#if IS_ENABLED(CONFIG_OF)
ec03e6a8 M	320	static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
	321	struct platform_device *pdev)
	322	{
	323	struct device_node *node = pdev->dev.of_node;
	324	u32 prop;
	325
	326	if (!node)
	327	return -EINVAL;
	328
	329	if (of_property_read_u32(node, "bus_freq", &prop)) {
a92f40a9	330	dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n");
ec03e6a8 M	331	return -EINVAL;
	332	}
	333	data->bus_freq = prop;
	334
	335	return 0;
	336	}
277e2a84	337	#endif
ec03e6a8	338
9eae9c7d GS	339	#if IS_ENABLED(CONFIG_OF)
	340	static const struct davinci_mdio_of_param of_cpsw_mdio_data = {
	341	.autosuspend_delay_ms = 100,
	342	};
	343
	344	static const struct of_device_id davinci_mdio_of_mtable[] = {
	345	{ .compatible = "ti,davinci_mdio", },
	346	{ .compatible = "ti,cpsw-mdio", .data = &of_cpsw_mdio_data},
	347	{ /* sentinel */ },
	348	};
	349	MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
	350	#endif
	351
e38921d4	352	static int davinci_mdio_probe(struct platform_device *pdev)
f20136eb	353	{
894cdbb0	354	struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
f20136eb CC	355	struct device *dev = &pdev->dev;
	356	struct davinci_mdio_data *data;
	357	struct resource *res;
	358	struct phy_device *phy;
	359	int ret, addr;
9eae9c7d	360	int autosuspend_delay_ms = -1;
f20136eb	361
50d0636e	362	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
b2adaca9	363	if (!data)
f20136eb	364	return -ENOMEM;
f20136eb	365
50d0636e	366	data->bus = devm_mdiobus_alloc(dev);
f20136eb CC	367	if (!data->bus) {
f20136eb CC	368	dev_err(dev, "failed to alloc mii bus\n");
50d0636e	369	return -ENOMEM;
f20136eb CC	370	}
f20136eb CC	371
ec03e6a8	372	if (dev->of_node) {
9eae9c7d GS	373	const struct of_device_id *of_id;
	374
	375	ret = davinci_mdio_probe_dt(&data->pdata, pdev);
	376	if (ret)
	377	return ret;
ec03e6a8	378	snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
9eae9c7d GS	379
	380	of_id = of_match_device(davinci_mdio_of_mtable, &pdev->dev);
	381	if (of_id) {
	382	const struct davinci_mdio_of_param *of_mdio_data;
	383
	384	of_mdio_data = of_id->data;
	385	if (of_mdio_data)
	386	autosuspend_delay_ms =
	387	of_mdio_data->autosuspend_delay_ms;
	388	}
ec03e6a8 M	389	} else {
	390	data->pdata = pdata ? (*pdata) : default_pdata;
	391	snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
	392	pdev->name, pdev->id);
	393	}
	394
f20136eb CC	395	data->bus->name = dev_name(dev);
	396	data->bus->read = davinci_mdio_read,
	397	data->bus->write = davinci_mdio_write,
	398	data->bus->reset = davinci_mdio_reset,
	399	data->bus->parent = dev;
	400	data->bus->priv = data;
f20136eb	401
50d0636e	402	data->clk = devm_clk_get(dev, "fck");
f20136eb	403	if (IS_ERR(data->clk)) {
f20136eb	404	dev_err(dev, "failed to get device clock\n");
909892a6	405	return PTR_ERR(data->clk);
f20136eb CC	406	}
f20136eb CC	407
f20136eb CC	408	dev_set_drvdata(dev, data);
f20136eb CC	409	data->dev = dev;
f20136eb CC	410
f20136eb CC	411	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9728e1a7	412	data->regs = devm_ioremap_resource(dev, res);
909892a6 GS	413	if (IS_ERR(data->regs))
	414	return PTR_ERR(data->regs);
	415
28f0ccb9 GS	416	davinci_mdio_init_clk(data);
28f0ccb9 GS	417
9eae9c7d	418	pm_runtime_set_autosuspend_delay(&pdev->dev, autosuspend_delay_ms);
8ea63bba	419	pm_runtime_use_autosuspend(&pdev->dev);
909892a6	420	pm_runtime_enable(&pdev->dev);
f20136eb	421
0a0ea068 GS	422	/* register the mii bus
	423	* Create PHYs from DT only in case if PHY child nodes are explicitly
	424	* defined to support backward compatibility with DTs which assume that
	425	* Davinci MDIO will always scan the bus for PHYs detection.
	426	*/
	427	if (dev->of_node && of_get_child_count(dev->of_node)) {
	428	data->skip_scan = true;
	429	ret = of_mdiobus_register(data->bus, dev->of_node);
	430	} else {
	431	ret = mdiobus_register(data->bus);
	432	}
f20136eb CC	433	if (ret)
	434	goto bail_out;
	435
	436	/* scan and dump the bus */
	437	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
7f854420	438	phy = mdiobus_get_phy(data->bus, addr);
f20136eb CC	439	if (phy) {
f20136eb CC	440	dev_info(dev, "phy[%d]: device %s, driver %s\n",
e5a03bfd	441	phy->mdio.addr, phydev_name(phy),
f20136eb CC	442	phy->drv ? phy->drv->name : "unknown");
	443	}
	444	}
	445
	446	return 0;
	447
	448	bail_out:
8ea63bba	449	pm_runtime_dont_use_autosuspend(&pdev->dev);
8e476d9d	450	pm_runtime_disable(&pdev->dev);
f20136eb CC	451	return ret;
	452	}
	453
e38921d4	454	static int davinci_mdio_remove(struct platform_device *pdev)
f20136eb	455	{
84ce22df	456	struct davinci_mdio_data *data = platform_get_drvdata(pdev);
f20136eb	457
50d0636e	458	if (data->bus)
b27393ae	459	mdiobus_unregister(data->bus);
f20136eb	460
8ea63bba	461	pm_runtime_dont_use_autosuspend(&pdev->dev);
8e476d9d	462	pm_runtime_disable(&pdev->dev);
f20136eb	463
f20136eb CC	464	return 0;
	465	}
	466
651652aa GS	467	#ifdef CONFIG_PM
651652aa GS	468	static int davinci_mdio_runtime_suspend(struct device *dev)
f20136eb CC	469	{
	470	struct davinci_mdio_data *data = dev_get_drvdata(dev);
	471	u32 ctrl;
	472
f20136eb CC	473	/* shutdown the scan state machine */
	474	ctrl = __raw_readl(&data->regs->control);
	475	ctrl &= ~CONTROL_ENABLE;
	476	__raw_writel(ctrl, &data->regs->control);
	477	wait_for_idle(data);
	478
651652aa GS	479	return 0;
	480	}
	481
	482	static int davinci_mdio_runtime_resume(struct device *dev)
	483	{
	484	struct davinci_mdio_data *data = dev_get_drvdata(dev);
	485
	486	davinci_mdio_enable(data);
	487	return 0;
	488	}
	489	#endif
	490
	491	#ifdef CONFIG_PM_SLEEP
	492	static int davinci_mdio_suspend(struct device *dev)
	493	{
	494	struct davinci_mdio_data *data = dev_get_drvdata(dev);
	495	int ret = 0;
	496
8ea63bba GS	497	data->active_in_suspend = !pm_runtime_status_suspended(dev);
	498	if (data->active_in_suspend)
	499	ret = pm_runtime_force_suspend(dev);
651652aa GS	500	if (ret < 0)
	501	return ret;
	502
5c0e3580 M	503	/* Select sleep pin state */
	504	pinctrl_pm_select_sleep_state(dev);
	505
f20136eb CC	506	return 0;
	507	}
	508
	509	static int davinci_mdio_resume(struct device *dev)
	510	{
	511	struct davinci_mdio_data *data = dev_get_drvdata(dev);
f20136eb	512
5c0e3580 M	513	/* Select default pin state */
	514	pinctrl_pm_select_default_state(dev);
	515
8ea63bba GS	516	if (data->active_in_suspend)
8ea63bba GS	517	pm_runtime_force_resume(dev);
f20136eb	518
f20136eb CC	519	return 0;
f20136eb CC	520	}
2f5c54ce	521	#endif
f20136eb CC	522
f20136eb CC	523	static const struct dev_pm_ops davinci_mdio_pm_ops = {
651652aa GS	524	SET_RUNTIME_PM_OPS(davinci_mdio_runtime_suspend,
651652aa GS	525	davinci_mdio_runtime_resume, NULL)
2f5c54ce	526	SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume)
f20136eb CC	527	};
	528
	529	static struct platform_driver davinci_mdio_driver = {
	530	.driver = {
	531	.name = "davinci_mdio",
f20136eb	532	.pm = &davinci_mdio_pm_ops,
ec03e6a8	533	.of_match_table = of_match_ptr(davinci_mdio_of_mtable),
f20136eb CC	534	},
f20136eb CC	535	.probe = davinci_mdio_probe,
e38921d4	536	.remove = davinci_mdio_remove,
f20136eb CC	537	};
	538
	539	static int __init davinci_mdio_init(void)
	540	{
	541	return platform_driver_register(&davinci_mdio_driver);
	542	}
	543	device_initcall(davinci_mdio_init);
	544
	545	static void __exit davinci_mdio_exit(void)
	546	{
	547	platform_driver_unregister(&davinci_mdio_driver);
	548	}
	549	module_exit(davinci_mdio_exit);
	550
	551	MODULE_LICENSE("GPL");
	552	MODULE_DESCRIPTION("DaVinci MDIO driver");