Commit | Line | Data |
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ef8c2dab CC |
1 | /* |
2 | * Texas Instruments CPDMA Driver | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/device.h> | |
76fbc247 | 18 | #include <linux/module.h> |
ef8c2dab CC |
19 | #include <linux/slab.h> |
20 | #include <linux/err.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/io.h> | |
817f6d1a | 23 | #include <linux/delay.h> |
742fb20f | 24 | #include <linux/genalloc.h> |
ef8c2dab CC |
25 | #include "davinci_cpdma.h" |
26 | ||
27 | /* DMA Registers */ | |
28 | #define CPDMA_TXIDVER 0x00 | |
29 | #define CPDMA_TXCONTROL 0x04 | |
30 | #define CPDMA_TXTEARDOWN 0x08 | |
31 | #define CPDMA_RXIDVER 0x10 | |
32 | #define CPDMA_RXCONTROL 0x14 | |
33 | #define CPDMA_SOFTRESET 0x1c | |
34 | #define CPDMA_RXTEARDOWN 0x18 | |
35 | #define CPDMA_TXINTSTATRAW 0x80 | |
36 | #define CPDMA_TXINTSTATMASKED 0x84 | |
37 | #define CPDMA_TXINTMASKSET 0x88 | |
38 | #define CPDMA_TXINTMASKCLEAR 0x8c | |
39 | #define CPDMA_MACINVECTOR 0x90 | |
40 | #define CPDMA_MACEOIVECTOR 0x94 | |
41 | #define CPDMA_RXINTSTATRAW 0xa0 | |
42 | #define CPDMA_RXINTSTATMASKED 0xa4 | |
43 | #define CPDMA_RXINTMASKSET 0xa8 | |
44 | #define CPDMA_RXINTMASKCLEAR 0xac | |
45 | #define CPDMA_DMAINTSTATRAW 0xb0 | |
46 | #define CPDMA_DMAINTSTATMASKED 0xb4 | |
47 | #define CPDMA_DMAINTMASKSET 0xb8 | |
48 | #define CPDMA_DMAINTMASKCLEAR 0xbc | |
49 | #define CPDMA_DMAINT_HOSTERR BIT(1) | |
50 | ||
51 | /* the following exist only if has_ext_regs is set */ | |
52 | #define CPDMA_DMACONTROL 0x20 | |
53 | #define CPDMA_DMASTATUS 0x24 | |
54 | #define CPDMA_RXBUFFOFS 0x28 | |
55 | #define CPDMA_EM_CONTROL 0x2c | |
56 | ||
57 | /* Descriptor mode bits */ | |
58 | #define CPDMA_DESC_SOP BIT(31) | |
59 | #define CPDMA_DESC_EOP BIT(30) | |
60 | #define CPDMA_DESC_OWNER BIT(29) | |
61 | #define CPDMA_DESC_EOQ BIT(28) | |
62 | #define CPDMA_DESC_TD_COMPLETE BIT(27) | |
63 | #define CPDMA_DESC_PASS_CRC BIT(26) | |
f6e135c8 M |
64 | #define CPDMA_DESC_TO_PORT_EN BIT(20) |
65 | #define CPDMA_TO_PORT_SHIFT 16 | |
66 | #define CPDMA_DESC_PORT_MASK (BIT(18) | BIT(17) | BIT(16)) | |
28a19fe6 | 67 | #define CPDMA_DESC_CRC_LEN 4 |
ef8c2dab CC |
68 | |
69 | #define CPDMA_TEARDOWN_VALUE 0xfffffffc | |
70 | ||
71 | struct cpdma_desc { | |
72 | /* hardware fields */ | |
73 | u32 hw_next; | |
74 | u32 hw_buffer; | |
75 | u32 hw_len; | |
76 | u32 hw_mode; | |
77 | /* software fields */ | |
78 | void *sw_token; | |
79 | u32 sw_buffer; | |
80 | u32 sw_len; | |
81 | }; | |
82 | ||
83 | struct cpdma_desc_pool { | |
c767db51 | 84 | phys_addr_t phys; |
84092996 | 85 | dma_addr_t hw_addr; |
ef8c2dab CC |
86 | void __iomem *iomap; /* ioremap map */ |
87 | void *cpumap; /* dma_alloc map */ | |
88 | int desc_size, mem_size; | |
aeec3021 | 89 | int num_desc; |
ef8c2dab | 90 | struct device *dev; |
742fb20f | 91 | struct gen_pool *gen_pool; |
ef8c2dab CC |
92 | }; |
93 | ||
94 | enum cpdma_state { | |
95 | CPDMA_STATE_IDLE, | |
96 | CPDMA_STATE_ACTIVE, | |
97 | CPDMA_STATE_TEARDOWN, | |
98 | }; | |
99 | ||
ef8c2dab CC |
100 | struct cpdma_ctlr { |
101 | enum cpdma_state state; | |
102 | struct cpdma_params params; | |
103 | struct device *dev; | |
104 | struct cpdma_desc_pool *pool; | |
105 | spinlock_t lock; | |
106 | struct cpdma_chan *channels[2 * CPDMA_MAX_CHANNELS]; | |
3802dce1 | 107 | int chan_num; |
ef8c2dab CC |
108 | }; |
109 | ||
110 | struct cpdma_chan { | |
fae50823 M |
111 | struct cpdma_desc __iomem *head, *tail; |
112 | void __iomem *hdp, *cp, *rxfree; | |
ef8c2dab CC |
113 | enum cpdma_state state; |
114 | struct cpdma_ctlr *ctlr; | |
115 | int chan_num; | |
116 | spinlock_t lock; | |
ef8c2dab | 117 | int count; |
742fb20f | 118 | u32 desc_num; |
ef8c2dab CC |
119 | u32 mask; |
120 | cpdma_handler_fn handler; | |
121 | enum dma_data_direction dir; | |
122 | struct cpdma_chan_stats stats; | |
123 | /* offsets into dmaregs */ | |
124 | int int_set, int_clear, td; | |
125 | }; | |
126 | ||
991ddb1f IK |
127 | struct cpdma_control_info { |
128 | u32 reg; | |
129 | u32 shift, mask; | |
130 | int access; | |
131 | #define ACCESS_RO BIT(0) | |
132 | #define ACCESS_WO BIT(1) | |
133 | #define ACCESS_RW (ACCESS_RO | ACCESS_WO) | |
134 | }; | |
135 | ||
136 | static struct cpdma_control_info controls[] = { | |
137 | [CPDMA_CMD_IDLE] = {CPDMA_DMACONTROL, 3, 1, ACCESS_WO}, | |
138 | [CPDMA_COPY_ERROR_FRAMES] = {CPDMA_DMACONTROL, 4, 1, ACCESS_RW}, | |
139 | [CPDMA_RX_OFF_LEN_UPDATE] = {CPDMA_DMACONTROL, 2, 1, ACCESS_RW}, | |
140 | [CPDMA_RX_OWNERSHIP_FLIP] = {CPDMA_DMACONTROL, 1, 1, ACCESS_RW}, | |
141 | [CPDMA_TX_PRIO_FIXED] = {CPDMA_DMACONTROL, 0, 1, ACCESS_RW}, | |
142 | [CPDMA_STAT_IDLE] = {CPDMA_DMASTATUS, 31, 1, ACCESS_RO}, | |
143 | [CPDMA_STAT_TX_ERR_CODE] = {CPDMA_DMASTATUS, 20, 0xf, ACCESS_RW}, | |
144 | [CPDMA_STAT_TX_ERR_CHAN] = {CPDMA_DMASTATUS, 16, 0x7, ACCESS_RW}, | |
145 | [CPDMA_STAT_RX_ERR_CODE] = {CPDMA_DMASTATUS, 12, 0xf, ACCESS_RW}, | |
146 | [CPDMA_STAT_RX_ERR_CHAN] = {CPDMA_DMASTATUS, 8, 0x7, ACCESS_RW}, | |
147 | [CPDMA_RX_BUFFER_OFFSET] = {CPDMA_RXBUFFOFS, 0, 0xffff, ACCESS_RW}, | |
148 | }; | |
149 | ||
925d65e6 IK |
150 | #define tx_chan_num(chan) (chan) |
151 | #define rx_chan_num(chan) ((chan) + CPDMA_MAX_CHANNELS) | |
152 | #define is_rx_chan(chan) ((chan)->chan_num >= CPDMA_MAX_CHANNELS) | |
153 | #define is_tx_chan(chan) (!is_rx_chan(chan)) | |
154 | #define __chan_linear(chan_num) ((chan_num) & (CPDMA_MAX_CHANNELS - 1)) | |
155 | #define chan_linear(chan) __chan_linear((chan)->chan_num) | |
156 | ||
ef8c2dab CC |
157 | /* The following make access to common cpdma_ctlr params more readable */ |
158 | #define dmaregs params.dmaregs | |
159 | #define num_chan params.num_chan | |
160 | ||
161 | /* various accessors */ | |
162 | #define dma_reg_read(ctlr, ofs) __raw_readl((ctlr)->dmaregs + (ofs)) | |
163 | #define chan_read(chan, fld) __raw_readl((chan)->fld) | |
164 | #define desc_read(desc, fld) __raw_readl(&(desc)->fld) | |
165 | #define dma_reg_write(ctlr, ofs, v) __raw_writel(v, (ctlr)->dmaregs + (ofs)) | |
166 | #define chan_write(chan, fld, v) __raw_writel(v, (chan)->fld) | |
167 | #define desc_write(desc, fld, v) __raw_writel((u32)(v), &(desc)->fld) | |
168 | ||
f6e135c8 M |
169 | #define cpdma_desc_to_port(chan, mode, directed) \ |
170 | do { \ | |
171 | if (!is_rx_chan(chan) && ((directed == 1) || \ | |
172 | (directed == 2))) \ | |
173 | mode |= (CPDMA_DESC_TO_PORT_EN | \ | |
174 | (directed << CPDMA_TO_PORT_SHIFT)); \ | |
175 | } while (0) | |
176 | ||
742fb20f GS |
177 | static void cpdma_desc_pool_destroy(struct cpdma_desc_pool *pool) |
178 | { | |
179 | if (!pool) | |
180 | return; | |
181 | ||
aeec3021 GS |
182 | WARN(gen_pool_size(pool->gen_pool) != gen_pool_avail(pool->gen_pool), |
183 | "cpdma_desc_pool size %d != avail %d", | |
184 | gen_pool_size(pool->gen_pool), | |
185 | gen_pool_avail(pool->gen_pool)); | |
742fb20f GS |
186 | if (pool->cpumap) |
187 | dma_free_coherent(pool->dev, pool->mem_size, pool->cpumap, | |
188 | pool->phys); | |
189 | else | |
190 | iounmap(pool->iomap); | |
191 | } | |
192 | ||
ef8c2dab CC |
193 | /* |
194 | * Utility constructs for a cpdma descriptor pool. Some devices (e.g. davinci | |
195 | * emac) have dedicated on-chip memory for these descriptors. Some other | |
196 | * devices (e.g. cpsw switches) use plain old memory. Descriptor pools | |
197 | * abstract out these details | |
198 | */ | |
199 | static struct cpdma_desc_pool * | |
84092996 | 200 | cpdma_desc_pool_create(struct device *dev, u32 phys, dma_addr_t hw_addr, |
6a1fef6d | 201 | int size, int align) |
ef8c2dab | 202 | { |
ef8c2dab | 203 | struct cpdma_desc_pool *pool; |
742fb20f | 204 | int ret; |
ef8c2dab | 205 | |
e1943128 | 206 | pool = devm_kzalloc(dev, sizeof(*pool), GFP_KERNEL); |
ef8c2dab | 207 | if (!pool) |
742fb20f | 208 | goto gen_pool_create_fail; |
ef8c2dab CC |
209 | |
210 | pool->dev = dev; | |
211 | pool->mem_size = size; | |
212 | pool->desc_size = ALIGN(sizeof(struct cpdma_desc), align); | |
213 | pool->num_desc = size / pool->desc_size; | |
214 | ||
742fb20f GS |
215 | pool->gen_pool = devm_gen_pool_create(dev, ilog2(pool->desc_size), -1, |
216 | "cpdma"); | |
217 | if (IS_ERR(pool->gen_pool)) { | |
218 | dev_err(dev, "pool create failed %ld\n", | |
219 | PTR_ERR(pool->gen_pool)); | |
220 | goto gen_pool_create_fail; | |
221 | } | |
ef8c2dab CC |
222 | |
223 | if (phys) { | |
224 | pool->phys = phys; | |
84092996 | 225 | pool->iomap = ioremap(phys, size); /* should be memremap? */ |
6a1fef6d | 226 | pool->hw_addr = hw_addr; |
ef8c2dab | 227 | } else { |
84092996 | 228 | pool->cpumap = dma_alloc_coherent(dev, size, &pool->hw_addr, |
ef8c2dab | 229 | GFP_KERNEL); |
84092996 AB |
230 | pool->iomap = (void __iomem __force *)pool->cpumap; |
231 | pool->phys = pool->hw_addr; /* assumes no IOMMU, don't use this value */ | |
ef8c2dab CC |
232 | } |
233 | ||
742fb20f GS |
234 | if (!pool->iomap) |
235 | goto gen_pool_create_fail; | |
ef8c2dab | 236 | |
742fb20f GS |
237 | ret = gen_pool_add_virt(pool->gen_pool, (unsigned long)pool->iomap, |
238 | pool->phys, pool->mem_size, -1); | |
239 | if (ret < 0) { | |
240 | dev_err(dev, "pool add failed %d\n", ret); | |
241 | goto gen_pool_add_virt_fail; | |
ef8c2dab | 242 | } |
742fb20f GS |
243 | |
244 | return pool; | |
245 | ||
246 | gen_pool_add_virt_fail: | |
247 | cpdma_desc_pool_destroy(pool); | |
248 | gen_pool_create_fail: | |
249 | return NULL; | |
ef8c2dab CC |
250 | } |
251 | ||
252 | static inline dma_addr_t desc_phys(struct cpdma_desc_pool *pool, | |
253 | struct cpdma_desc __iomem *desc) | |
254 | { | |
255 | if (!desc) | |
256 | return 0; | |
c767db51 | 257 | return pool->hw_addr + (__force long)desc - (__force long)pool->iomap; |
ef8c2dab CC |
258 | } |
259 | ||
260 | static inline struct cpdma_desc __iomem * | |
261 | desc_from_phys(struct cpdma_desc_pool *pool, dma_addr_t dma) | |
262 | { | |
6a1fef6d | 263 | return dma ? pool->iomap + dma - pool->hw_addr : NULL; |
ef8c2dab CC |
264 | } |
265 | ||
266 | static struct cpdma_desc __iomem * | |
742fb20f | 267 | cpdma_desc_alloc(struct cpdma_desc_pool *pool) |
ef8c2dab | 268 | { |
aeec3021 GS |
269 | return (struct cpdma_desc __iomem *) |
270 | gen_pool_alloc(pool->gen_pool, pool->desc_size); | |
ef8c2dab CC |
271 | } |
272 | ||
273 | static void cpdma_desc_free(struct cpdma_desc_pool *pool, | |
274 | struct cpdma_desc __iomem *desc, int num_desc) | |
275 | { | |
742fb20f | 276 | gen_pool_free(pool->gen_pool, (unsigned long)desc, pool->desc_size); |
ef8c2dab CC |
277 | } |
278 | ||
991ddb1f IK |
279 | static int _cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value) |
280 | { | |
281 | struct cpdma_control_info *info = &controls[control]; | |
282 | u32 val; | |
283 | ||
284 | if (!ctlr->params.has_ext_regs) | |
285 | return -ENOTSUPP; | |
286 | ||
287 | if (ctlr->state != CPDMA_STATE_ACTIVE) | |
288 | return -EINVAL; | |
289 | ||
290 | if (control < 0 || control >= ARRAY_SIZE(controls)) | |
291 | return -ENOENT; | |
292 | ||
293 | if ((info->access & ACCESS_WO) != ACCESS_WO) | |
294 | return -EPERM; | |
295 | ||
296 | val = dma_reg_read(ctlr, info->reg); | |
297 | val &= ~(info->mask << info->shift); | |
298 | val |= (value & info->mask) << info->shift; | |
299 | dma_reg_write(ctlr, info->reg, val); | |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
ef8c2dab CC |
304 | struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params) |
305 | { | |
306 | struct cpdma_ctlr *ctlr; | |
307 | ||
e1943128 | 308 | ctlr = devm_kzalloc(params->dev, sizeof(*ctlr), GFP_KERNEL); |
ef8c2dab CC |
309 | if (!ctlr) |
310 | return NULL; | |
311 | ||
312 | ctlr->state = CPDMA_STATE_IDLE; | |
313 | ctlr->params = *params; | |
314 | ctlr->dev = params->dev; | |
3802dce1 | 315 | ctlr->chan_num = 0; |
ef8c2dab CC |
316 | spin_lock_init(&ctlr->lock); |
317 | ||
318 | ctlr->pool = cpdma_desc_pool_create(ctlr->dev, | |
319 | ctlr->params.desc_mem_phys, | |
6a1fef6d | 320 | ctlr->params.desc_hw_addr, |
ef8c2dab CC |
321 | ctlr->params.desc_mem_size, |
322 | ctlr->params.desc_align); | |
2f87208e | 323 | if (!ctlr->pool) |
ef8c2dab | 324 | return NULL; |
ef8c2dab CC |
325 | |
326 | if (WARN_ON(ctlr->num_chan > CPDMA_MAX_CHANNELS)) | |
327 | ctlr->num_chan = CPDMA_MAX_CHANNELS; | |
328 | return ctlr; | |
329 | } | |
32a6d90b | 330 | EXPORT_SYMBOL_GPL(cpdma_ctlr_create); |
ef8c2dab CC |
331 | |
332 | int cpdma_ctlr_start(struct cpdma_ctlr *ctlr) | |
333 | { | |
334 | unsigned long flags; | |
335 | int i; | |
336 | ||
337 | spin_lock_irqsave(&ctlr->lock, flags); | |
338 | if (ctlr->state != CPDMA_STATE_IDLE) { | |
339 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
340 | return -EBUSY; | |
341 | } | |
342 | ||
343 | if (ctlr->params.has_soft_reset) { | |
817f6d1a | 344 | unsigned timeout = 10 * 100; |
ef8c2dab CC |
345 | |
346 | dma_reg_write(ctlr, CPDMA_SOFTRESET, 1); | |
817f6d1a | 347 | while (timeout) { |
ef8c2dab CC |
348 | if (dma_reg_read(ctlr, CPDMA_SOFTRESET) == 0) |
349 | break; | |
817f6d1a SS |
350 | udelay(10); |
351 | timeout--; | |
ef8c2dab | 352 | } |
817f6d1a | 353 | WARN_ON(!timeout); |
ef8c2dab CC |
354 | } |
355 | ||
356 | for (i = 0; i < ctlr->num_chan; i++) { | |
357 | __raw_writel(0, ctlr->params.txhdp + 4 * i); | |
358 | __raw_writel(0, ctlr->params.rxhdp + 4 * i); | |
359 | __raw_writel(0, ctlr->params.txcp + 4 * i); | |
360 | __raw_writel(0, ctlr->params.rxcp + 4 * i); | |
361 | } | |
362 | ||
363 | dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff); | |
364 | dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff); | |
365 | ||
366 | dma_reg_write(ctlr, CPDMA_TXCONTROL, 1); | |
367 | dma_reg_write(ctlr, CPDMA_RXCONTROL, 1); | |
368 | ||
369 | ctlr->state = CPDMA_STATE_ACTIVE; | |
370 | ||
371 | for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { | |
372 | if (ctlr->channels[i]) | |
373 | cpdma_chan_start(ctlr->channels[i]); | |
374 | } | |
991ddb1f IK |
375 | |
376 | _cpdma_control_set(ctlr, CPDMA_TX_PRIO_FIXED, 1); | |
377 | _cpdma_control_set(ctlr, CPDMA_RX_BUFFER_OFFSET, 0); | |
378 | ||
ef8c2dab CC |
379 | spin_unlock_irqrestore(&ctlr->lock, flags); |
380 | return 0; | |
381 | } | |
32a6d90b | 382 | EXPORT_SYMBOL_GPL(cpdma_ctlr_start); |
ef8c2dab CC |
383 | |
384 | int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr) | |
385 | { | |
386 | unsigned long flags; | |
387 | int i; | |
388 | ||
389 | spin_lock_irqsave(&ctlr->lock, flags); | |
cd11cf50 | 390 | if (ctlr->state == CPDMA_STATE_TEARDOWN) { |
ef8c2dab CC |
391 | spin_unlock_irqrestore(&ctlr->lock, flags); |
392 | return -EINVAL; | |
393 | } | |
394 | ||
395 | ctlr->state = CPDMA_STATE_TEARDOWN; | |
080d5c5a | 396 | spin_unlock_irqrestore(&ctlr->lock, flags); |
ef8c2dab CC |
397 | |
398 | for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { | |
399 | if (ctlr->channels[i]) | |
400 | cpdma_chan_stop(ctlr->channels[i]); | |
401 | } | |
402 | ||
080d5c5a | 403 | spin_lock_irqsave(&ctlr->lock, flags); |
ef8c2dab CC |
404 | dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff); |
405 | dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff); | |
406 | ||
407 | dma_reg_write(ctlr, CPDMA_TXCONTROL, 0); | |
408 | dma_reg_write(ctlr, CPDMA_RXCONTROL, 0); | |
409 | ||
410 | ctlr->state = CPDMA_STATE_IDLE; | |
411 | ||
412 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
413 | return 0; | |
414 | } | |
32a6d90b | 415 | EXPORT_SYMBOL_GPL(cpdma_ctlr_stop); |
ef8c2dab | 416 | |
ef8c2dab CC |
417 | int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr) |
418 | { | |
ef8c2dab CC |
419 | int ret = 0, i; |
420 | ||
421 | if (!ctlr) | |
422 | return -EINVAL; | |
423 | ||
ef8c2dab CC |
424 | if (ctlr->state != CPDMA_STATE_IDLE) |
425 | cpdma_ctlr_stop(ctlr); | |
426 | ||
79876e03 CR |
427 | for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) |
428 | cpdma_chan_destroy(ctlr->channels[i]); | |
ef8c2dab CC |
429 | |
430 | cpdma_desc_pool_destroy(ctlr->pool); | |
ef8c2dab CC |
431 | return ret; |
432 | } | |
32a6d90b | 433 | EXPORT_SYMBOL_GPL(cpdma_ctlr_destroy); |
ef8c2dab CC |
434 | |
435 | int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable) | |
436 | { | |
437 | unsigned long flags; | |
438 | int i, reg; | |
439 | ||
440 | spin_lock_irqsave(&ctlr->lock, flags); | |
441 | if (ctlr->state != CPDMA_STATE_ACTIVE) { | |
442 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
443 | return -EINVAL; | |
444 | } | |
445 | ||
446 | reg = enable ? CPDMA_DMAINTMASKSET : CPDMA_DMAINTMASKCLEAR; | |
447 | dma_reg_write(ctlr, reg, CPDMA_DMAINT_HOSTERR); | |
448 | ||
449 | for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { | |
450 | if (ctlr->channels[i]) | |
451 | cpdma_chan_int_ctrl(ctlr->channels[i], enable); | |
452 | } | |
453 | ||
454 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
455 | return 0; | |
456 | } | |
6929e24e | 457 | EXPORT_SYMBOL_GPL(cpdma_ctlr_int_ctrl); |
ef8c2dab | 458 | |
510a1e72 | 459 | void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value) |
ef8c2dab | 460 | { |
510a1e72 | 461 | dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value); |
ef8c2dab | 462 | } |
6929e24e | 463 | EXPORT_SYMBOL_GPL(cpdma_ctlr_eoi); |
ef8c2dab | 464 | |
e05107e6 IK |
465 | u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr) |
466 | { | |
467 | return dma_reg_read(ctlr, CPDMA_RXINTSTATMASKED); | |
468 | } | |
469 | EXPORT_SYMBOL_GPL(cpdma_ctrl_rxchs_state); | |
470 | ||
471 | u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr) | |
472 | { | |
473 | return dma_reg_read(ctlr, CPDMA_TXINTSTATMASKED); | |
474 | } | |
475 | EXPORT_SYMBOL_GPL(cpdma_ctrl_txchs_state); | |
476 | ||
3802dce1 IK |
477 | /** |
478 | * cpdma_chan_split_pool - Splits ctrl pool between all channels. | |
479 | * Has to be called under ctlr lock | |
480 | */ | |
481 | static void cpdma_chan_split_pool(struct cpdma_ctlr *ctlr) | |
482 | { | |
483 | struct cpdma_desc_pool *pool = ctlr->pool; | |
484 | struct cpdma_chan *chan; | |
485 | int ch_desc_num; | |
486 | int i; | |
487 | ||
488 | if (!ctlr->chan_num) | |
489 | return; | |
490 | ||
491 | /* calculate average size of pool slice */ | |
492 | ch_desc_num = pool->num_desc / ctlr->chan_num; | |
493 | ||
494 | /* split ctlr pool */ | |
495 | for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { | |
496 | chan = ctlr->channels[i]; | |
497 | if (chan) | |
498 | chan->desc_num = ch_desc_num; | |
499 | } | |
500 | } | |
501 | ||
ef8c2dab | 502 | struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, |
925d65e6 | 503 | cpdma_handler_fn handler, int rx_type) |
ef8c2dab | 504 | { |
925d65e6 | 505 | int offset = chan_num * 4; |
ef8c2dab | 506 | struct cpdma_chan *chan; |
ef8c2dab CC |
507 | unsigned long flags; |
508 | ||
925d65e6 IK |
509 | chan_num = rx_type ? rx_chan_num(chan_num) : tx_chan_num(chan_num); |
510 | ||
ef8c2dab CC |
511 | if (__chan_linear(chan_num) >= ctlr->num_chan) |
512 | return NULL; | |
513 | ||
e1943128 | 514 | chan = devm_kzalloc(ctlr->dev, sizeof(*chan), GFP_KERNEL); |
ef8c2dab | 515 | if (!chan) |
e1943128 | 516 | return ERR_PTR(-ENOMEM); |
ef8c2dab CC |
517 | |
518 | spin_lock_irqsave(&ctlr->lock, flags); | |
e1943128 GC |
519 | if (ctlr->channels[chan_num]) { |
520 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
521 | devm_kfree(ctlr->dev, chan); | |
522 | return ERR_PTR(-EBUSY); | |
523 | } | |
ef8c2dab CC |
524 | |
525 | chan->ctlr = ctlr; | |
526 | chan->state = CPDMA_STATE_IDLE; | |
527 | chan->chan_num = chan_num; | |
528 | chan->handler = handler; | |
742fb20f | 529 | chan->desc_num = ctlr->pool->num_desc / 2; |
ef8c2dab CC |
530 | |
531 | if (is_rx_chan(chan)) { | |
532 | chan->hdp = ctlr->params.rxhdp + offset; | |
533 | chan->cp = ctlr->params.rxcp + offset; | |
534 | chan->rxfree = ctlr->params.rxfree + offset; | |
535 | chan->int_set = CPDMA_RXINTMASKSET; | |
536 | chan->int_clear = CPDMA_RXINTMASKCLEAR; | |
537 | chan->td = CPDMA_RXTEARDOWN; | |
538 | chan->dir = DMA_FROM_DEVICE; | |
539 | } else { | |
540 | chan->hdp = ctlr->params.txhdp + offset; | |
541 | chan->cp = ctlr->params.txcp + offset; | |
542 | chan->int_set = CPDMA_TXINTMASKSET; | |
543 | chan->int_clear = CPDMA_TXINTMASKCLEAR; | |
544 | chan->td = CPDMA_TXTEARDOWN; | |
545 | chan->dir = DMA_TO_DEVICE; | |
546 | } | |
547 | chan->mask = BIT(chan_linear(chan)); | |
548 | ||
549 | spin_lock_init(&chan->lock); | |
550 | ||
551 | ctlr->channels[chan_num] = chan; | |
3802dce1 IK |
552 | ctlr->chan_num++; |
553 | ||
554 | cpdma_chan_split_pool(ctlr); | |
555 | ||
ef8c2dab CC |
556 | spin_unlock_irqrestore(&ctlr->lock, flags); |
557 | return chan; | |
ef8c2dab | 558 | } |
32a6d90b | 559 | EXPORT_SYMBOL_GPL(cpdma_chan_create); |
ef8c2dab | 560 | |
3802dce1 | 561 | int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan) |
1793331e | 562 | { |
3802dce1 IK |
563 | unsigned long flags; |
564 | int desc_num; | |
565 | ||
566 | spin_lock_irqsave(&chan->lock, flags); | |
567 | desc_num = chan->desc_num; | |
568 | spin_unlock_irqrestore(&chan->lock, flags); | |
569 | ||
570 | return desc_num; | |
1793331e IK |
571 | } |
572 | EXPORT_SYMBOL_GPL(cpdma_chan_get_rx_buf_num); | |
573 | ||
ef8c2dab CC |
574 | int cpdma_chan_destroy(struct cpdma_chan *chan) |
575 | { | |
f37c54b6 | 576 | struct cpdma_ctlr *ctlr; |
ef8c2dab CC |
577 | unsigned long flags; |
578 | ||
579 | if (!chan) | |
580 | return -EINVAL; | |
f37c54b6 | 581 | ctlr = chan->ctlr; |
ef8c2dab CC |
582 | |
583 | spin_lock_irqsave(&ctlr->lock, flags); | |
584 | if (chan->state != CPDMA_STATE_IDLE) | |
585 | cpdma_chan_stop(chan); | |
586 | ctlr->channels[chan->chan_num] = NULL; | |
3802dce1 | 587 | ctlr->chan_num--; |
b602e491 | 588 | devm_kfree(ctlr->dev, chan); |
3802dce1 IK |
589 | cpdma_chan_split_pool(ctlr); |
590 | ||
ef8c2dab | 591 | spin_unlock_irqrestore(&ctlr->lock, flags); |
ef8c2dab CC |
592 | return 0; |
593 | } | |
32a6d90b | 594 | EXPORT_SYMBOL_GPL(cpdma_chan_destroy); |
ef8c2dab CC |
595 | |
596 | int cpdma_chan_get_stats(struct cpdma_chan *chan, | |
597 | struct cpdma_chan_stats *stats) | |
598 | { | |
599 | unsigned long flags; | |
600 | if (!chan) | |
601 | return -EINVAL; | |
602 | spin_lock_irqsave(&chan->lock, flags); | |
603 | memcpy(stats, &chan->stats, sizeof(*stats)); | |
604 | spin_unlock_irqrestore(&chan->lock, flags); | |
605 | return 0; | |
606 | } | |
0ca04b63 | 607 | EXPORT_SYMBOL_GPL(cpdma_chan_get_stats); |
ef8c2dab | 608 | |
ef8c2dab CC |
609 | static void __cpdma_chan_submit(struct cpdma_chan *chan, |
610 | struct cpdma_desc __iomem *desc) | |
611 | { | |
612 | struct cpdma_ctlr *ctlr = chan->ctlr; | |
613 | struct cpdma_desc __iomem *prev = chan->tail; | |
614 | struct cpdma_desc_pool *pool = ctlr->pool; | |
615 | dma_addr_t desc_dma; | |
616 | u32 mode; | |
617 | ||
618 | desc_dma = desc_phys(pool, desc); | |
619 | ||
620 | /* simple case - idle channel */ | |
621 | if (!chan->head) { | |
622 | chan->stats.head_enqueue++; | |
623 | chan->head = desc; | |
624 | chan->tail = desc; | |
625 | if (chan->state == CPDMA_STATE_ACTIVE) | |
626 | chan_write(chan, hdp, desc_dma); | |
627 | return; | |
628 | } | |
629 | ||
630 | /* first chain the descriptor at the tail of the list */ | |
631 | desc_write(prev, hw_next, desc_dma); | |
632 | chan->tail = desc; | |
633 | chan->stats.tail_enqueue++; | |
634 | ||
635 | /* next check if EOQ has been triggered already */ | |
636 | mode = desc_read(prev, hw_mode); | |
637 | if (((mode & (CPDMA_DESC_EOQ | CPDMA_DESC_OWNER)) == CPDMA_DESC_EOQ) && | |
638 | (chan->state == CPDMA_STATE_ACTIVE)) { | |
639 | desc_write(prev, hw_mode, mode & ~CPDMA_DESC_EOQ); | |
640 | chan_write(chan, hdp, desc_dma); | |
641 | chan->stats.misqueued++; | |
642 | } | |
643 | } | |
644 | ||
645 | int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data, | |
aef614e1 | 646 | int len, int directed) |
ef8c2dab CC |
647 | { |
648 | struct cpdma_ctlr *ctlr = chan->ctlr; | |
649 | struct cpdma_desc __iomem *desc; | |
650 | dma_addr_t buffer; | |
651 | unsigned long flags; | |
652 | u32 mode; | |
653 | int ret = 0; | |
654 | ||
655 | spin_lock_irqsave(&chan->lock, flags); | |
656 | ||
657 | if (chan->state == CPDMA_STATE_TEARDOWN) { | |
658 | ret = -EINVAL; | |
659 | goto unlock_ret; | |
660 | } | |
661 | ||
742fb20f GS |
662 | if (chan->count >= chan->desc_num) { |
663 | chan->stats.desc_alloc_fail++; | |
664 | ret = -ENOMEM; | |
665 | goto unlock_ret; | |
666 | } | |
667 | ||
668 | desc = cpdma_desc_alloc(ctlr->pool); | |
ef8c2dab CC |
669 | if (!desc) { |
670 | chan->stats.desc_alloc_fail++; | |
671 | ret = -ENOMEM; | |
672 | goto unlock_ret; | |
673 | } | |
674 | ||
675 | if (len < ctlr->params.min_packet_size) { | |
676 | len = ctlr->params.min_packet_size; | |
677 | chan->stats.runt_transmit_buff++; | |
678 | } | |
679 | ||
680 | buffer = dma_map_single(ctlr->dev, data, len, chan->dir); | |
14bd0769 SS |
681 | ret = dma_mapping_error(ctlr->dev, buffer); |
682 | if (ret) { | |
683 | cpdma_desc_free(ctlr->pool, desc, 1); | |
684 | ret = -EINVAL; | |
685 | goto unlock_ret; | |
686 | } | |
687 | ||
ef8c2dab | 688 | mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP; |
f6e135c8 | 689 | cpdma_desc_to_port(chan, mode, directed); |
ef8c2dab CC |
690 | |
691 | desc_write(desc, hw_next, 0); | |
692 | desc_write(desc, hw_buffer, buffer); | |
693 | desc_write(desc, hw_len, len); | |
694 | desc_write(desc, hw_mode, mode | len); | |
695 | desc_write(desc, sw_token, token); | |
696 | desc_write(desc, sw_buffer, buffer); | |
697 | desc_write(desc, sw_len, len); | |
698 | ||
699 | __cpdma_chan_submit(chan, desc); | |
700 | ||
701 | if (chan->state == CPDMA_STATE_ACTIVE && chan->rxfree) | |
702 | chan_write(chan, rxfree, 1); | |
703 | ||
704 | chan->count++; | |
705 | ||
706 | unlock_ret: | |
707 | spin_unlock_irqrestore(&chan->lock, flags); | |
708 | return ret; | |
709 | } | |
32a6d90b | 710 | EXPORT_SYMBOL_GPL(cpdma_chan_submit); |
ef8c2dab | 711 | |
fae50823 M |
712 | bool cpdma_check_free_tx_desc(struct cpdma_chan *chan) |
713 | { | |
fae50823 M |
714 | struct cpdma_ctlr *ctlr = chan->ctlr; |
715 | struct cpdma_desc_pool *pool = ctlr->pool; | |
742fb20f GS |
716 | bool free_tx_desc; |
717 | unsigned long flags; | |
fae50823 | 718 | |
742fb20f GS |
719 | spin_lock_irqsave(&chan->lock, flags); |
720 | free_tx_desc = (chan->count < chan->desc_num) && | |
721 | gen_pool_avail(pool->gen_pool); | |
722 | spin_unlock_irqrestore(&chan->lock, flags); | |
723 | return free_tx_desc; | |
fae50823 M |
724 | } |
725 | EXPORT_SYMBOL_GPL(cpdma_check_free_tx_desc); | |
726 | ||
ef8c2dab CC |
727 | static void __cpdma_chan_free(struct cpdma_chan *chan, |
728 | struct cpdma_desc __iomem *desc, | |
729 | int outlen, int status) | |
730 | { | |
731 | struct cpdma_ctlr *ctlr = chan->ctlr; | |
732 | struct cpdma_desc_pool *pool = ctlr->pool; | |
733 | dma_addr_t buff_dma; | |
734 | int origlen; | |
735 | void *token; | |
736 | ||
737 | token = (void *)desc_read(desc, sw_token); | |
738 | buff_dma = desc_read(desc, sw_buffer); | |
739 | origlen = desc_read(desc, sw_len); | |
740 | ||
741 | dma_unmap_single(ctlr->dev, buff_dma, origlen, chan->dir); | |
742 | cpdma_desc_free(pool, desc, 1); | |
743 | (*chan->handler)(token, outlen, status); | |
744 | } | |
745 | ||
746 | static int __cpdma_chan_process(struct cpdma_chan *chan) | |
747 | { | |
748 | struct cpdma_ctlr *ctlr = chan->ctlr; | |
749 | struct cpdma_desc __iomem *desc; | |
750 | int status, outlen; | |
b4727e69 | 751 | int cb_status = 0; |
ef8c2dab CC |
752 | struct cpdma_desc_pool *pool = ctlr->pool; |
753 | dma_addr_t desc_dma; | |
754 | unsigned long flags; | |
755 | ||
756 | spin_lock_irqsave(&chan->lock, flags); | |
757 | ||
758 | desc = chan->head; | |
759 | if (!desc) { | |
760 | chan->stats.empty_dequeue++; | |
761 | status = -ENOENT; | |
762 | goto unlock_ret; | |
763 | } | |
764 | desc_dma = desc_phys(pool, desc); | |
765 | ||
766 | status = __raw_readl(&desc->hw_mode); | |
767 | outlen = status & 0x7ff; | |
768 | if (status & CPDMA_DESC_OWNER) { | |
769 | chan->stats.busy_dequeue++; | |
770 | status = -EBUSY; | |
771 | goto unlock_ret; | |
772 | } | |
28a19fe6 M |
773 | |
774 | if (status & CPDMA_DESC_PASS_CRC) | |
775 | outlen -= CPDMA_DESC_CRC_LEN; | |
776 | ||
f6e135c8 M |
777 | status = status & (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE | |
778 | CPDMA_DESC_PORT_MASK); | |
ef8c2dab CC |
779 | |
780 | chan->head = desc_from_phys(pool, desc_read(desc, hw_next)); | |
781 | chan_write(chan, cp, desc_dma); | |
782 | chan->count--; | |
783 | chan->stats.good_dequeue++; | |
784 | ||
785 | if (status & CPDMA_DESC_EOQ) { | |
786 | chan->stats.requeue++; | |
787 | chan_write(chan, hdp, desc_phys(pool, chan->head)); | |
788 | } | |
789 | ||
790 | spin_unlock_irqrestore(&chan->lock, flags); | |
b4727e69 SS |
791 | if (unlikely(status & CPDMA_DESC_TD_COMPLETE)) |
792 | cb_status = -ENOSYS; | |
793 | else | |
794 | cb_status = status; | |
ef8c2dab | 795 | |
b4727e69 | 796 | __cpdma_chan_free(chan, desc, outlen, cb_status); |
ef8c2dab CC |
797 | return status; |
798 | ||
799 | unlock_ret: | |
800 | spin_unlock_irqrestore(&chan->lock, flags); | |
801 | return status; | |
802 | } | |
803 | ||
804 | int cpdma_chan_process(struct cpdma_chan *chan, int quota) | |
805 | { | |
806 | int used = 0, ret = 0; | |
807 | ||
808 | if (chan->state != CPDMA_STATE_ACTIVE) | |
809 | return -EINVAL; | |
810 | ||
811 | while (used < quota) { | |
812 | ret = __cpdma_chan_process(chan); | |
813 | if (ret < 0) | |
814 | break; | |
815 | used++; | |
816 | } | |
817 | return used; | |
818 | } | |
32a6d90b | 819 | EXPORT_SYMBOL_GPL(cpdma_chan_process); |
ef8c2dab CC |
820 | |
821 | int cpdma_chan_start(struct cpdma_chan *chan) | |
822 | { | |
823 | struct cpdma_ctlr *ctlr = chan->ctlr; | |
824 | struct cpdma_desc_pool *pool = ctlr->pool; | |
825 | unsigned long flags; | |
826 | ||
827 | spin_lock_irqsave(&chan->lock, flags); | |
828 | if (chan->state != CPDMA_STATE_IDLE) { | |
829 | spin_unlock_irqrestore(&chan->lock, flags); | |
830 | return -EBUSY; | |
831 | } | |
832 | if (ctlr->state != CPDMA_STATE_ACTIVE) { | |
833 | spin_unlock_irqrestore(&chan->lock, flags); | |
834 | return -EINVAL; | |
835 | } | |
836 | dma_reg_write(ctlr, chan->int_set, chan->mask); | |
837 | chan->state = CPDMA_STATE_ACTIVE; | |
838 | if (chan->head) { | |
839 | chan_write(chan, hdp, desc_phys(pool, chan->head)); | |
840 | if (chan->rxfree) | |
841 | chan_write(chan, rxfree, chan->count); | |
842 | } | |
843 | ||
844 | spin_unlock_irqrestore(&chan->lock, flags); | |
845 | return 0; | |
846 | } | |
32a6d90b | 847 | EXPORT_SYMBOL_GPL(cpdma_chan_start); |
ef8c2dab CC |
848 | |
849 | int cpdma_chan_stop(struct cpdma_chan *chan) | |
850 | { | |
851 | struct cpdma_ctlr *ctlr = chan->ctlr; | |
852 | struct cpdma_desc_pool *pool = ctlr->pool; | |
853 | unsigned long flags; | |
854 | int ret; | |
817f6d1a | 855 | unsigned timeout; |
ef8c2dab CC |
856 | |
857 | spin_lock_irqsave(&chan->lock, flags); | |
cd11cf50 | 858 | if (chan->state == CPDMA_STATE_TEARDOWN) { |
ef8c2dab CC |
859 | spin_unlock_irqrestore(&chan->lock, flags); |
860 | return -EINVAL; | |
861 | } | |
862 | ||
863 | chan->state = CPDMA_STATE_TEARDOWN; | |
864 | dma_reg_write(ctlr, chan->int_clear, chan->mask); | |
865 | ||
866 | /* trigger teardown */ | |
b4ad0428 | 867 | dma_reg_write(ctlr, chan->td, chan_linear(chan)); |
ef8c2dab CC |
868 | |
869 | /* wait for teardown complete */ | |
817f6d1a SS |
870 | timeout = 100 * 100; /* 100 ms */ |
871 | while (timeout) { | |
ef8c2dab CC |
872 | u32 cp = chan_read(chan, cp); |
873 | if ((cp & CPDMA_TEARDOWN_VALUE) == CPDMA_TEARDOWN_VALUE) | |
874 | break; | |
817f6d1a SS |
875 | udelay(10); |
876 | timeout--; | |
ef8c2dab | 877 | } |
817f6d1a | 878 | WARN_ON(!timeout); |
ef8c2dab CC |
879 | chan_write(chan, cp, CPDMA_TEARDOWN_VALUE); |
880 | ||
881 | /* handle completed packets */ | |
7746ab0a | 882 | spin_unlock_irqrestore(&chan->lock, flags); |
ef8c2dab CC |
883 | do { |
884 | ret = __cpdma_chan_process(chan); | |
885 | if (ret < 0) | |
886 | break; | |
887 | } while ((ret & CPDMA_DESC_TD_COMPLETE) == 0); | |
7746ab0a | 888 | spin_lock_irqsave(&chan->lock, flags); |
ef8c2dab CC |
889 | |
890 | /* remaining packets haven't been tx/rx'ed, clean them up */ | |
891 | while (chan->head) { | |
892 | struct cpdma_desc __iomem *desc = chan->head; | |
893 | dma_addr_t next_dma; | |
894 | ||
895 | next_dma = desc_read(desc, hw_next); | |
896 | chan->head = desc_from_phys(pool, next_dma); | |
ffb5ba90 | 897 | chan->count--; |
ef8c2dab CC |
898 | chan->stats.teardown_dequeue++; |
899 | ||
900 | /* issue callback without locks held */ | |
901 | spin_unlock_irqrestore(&chan->lock, flags); | |
902 | __cpdma_chan_free(chan, desc, 0, -ENOSYS); | |
903 | spin_lock_irqsave(&chan->lock, flags); | |
904 | } | |
905 | ||
906 | chan->state = CPDMA_STATE_IDLE; | |
907 | spin_unlock_irqrestore(&chan->lock, flags); | |
908 | return 0; | |
909 | } | |
32a6d90b | 910 | EXPORT_SYMBOL_GPL(cpdma_chan_stop); |
ef8c2dab CC |
911 | |
912 | int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable) | |
913 | { | |
914 | unsigned long flags; | |
915 | ||
916 | spin_lock_irqsave(&chan->lock, flags); | |
917 | if (chan->state != CPDMA_STATE_ACTIVE) { | |
918 | spin_unlock_irqrestore(&chan->lock, flags); | |
919 | return -EINVAL; | |
920 | } | |
921 | ||
922 | dma_reg_write(chan->ctlr, enable ? chan->int_set : chan->int_clear, | |
923 | chan->mask); | |
924 | spin_unlock_irqrestore(&chan->lock, flags); | |
925 | ||
926 | return 0; | |
927 | } | |
928 | ||
ef8c2dab CC |
929 | int cpdma_control_get(struct cpdma_ctlr *ctlr, int control) |
930 | { | |
931 | unsigned long flags; | |
932 | struct cpdma_control_info *info = &controls[control]; | |
933 | int ret; | |
934 | ||
935 | spin_lock_irqsave(&ctlr->lock, flags); | |
936 | ||
937 | ret = -ENOTSUPP; | |
938 | if (!ctlr->params.has_ext_regs) | |
939 | goto unlock_ret; | |
940 | ||
941 | ret = -EINVAL; | |
942 | if (ctlr->state != CPDMA_STATE_ACTIVE) | |
943 | goto unlock_ret; | |
944 | ||
945 | ret = -ENOENT; | |
946 | if (control < 0 || control >= ARRAY_SIZE(controls)) | |
947 | goto unlock_ret; | |
948 | ||
949 | ret = -EPERM; | |
950 | if ((info->access & ACCESS_RO) != ACCESS_RO) | |
951 | goto unlock_ret; | |
952 | ||
953 | ret = (dma_reg_read(ctlr, info->reg) >> info->shift) & info->mask; | |
954 | ||
955 | unlock_ret: | |
956 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
957 | return ret; | |
958 | } | |
959 | ||
960 | int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value) | |
961 | { | |
962 | unsigned long flags; | |
ef8c2dab | 963 | int ret; |
ef8c2dab CC |
964 | |
965 | spin_lock_irqsave(&ctlr->lock, flags); | |
991ddb1f | 966 | ret = _cpdma_control_set(ctlr, control, value); |
ef8c2dab CC |
967 | spin_unlock_irqrestore(&ctlr->lock, flags); |
968 | return ret; | |
969 | } | |
6929e24e | 970 | EXPORT_SYMBOL_GPL(cpdma_control_set); |
4bc21d41 SS |
971 | |
972 | MODULE_LICENSE("GPL"); |