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amd-xgbe: unwind on error in xgbe_mdio_register()
[linux-2.6-block.git] / drivers / net / ethernet / ti / davinci_cpdma.c
CommitLineData
ef8c2dab
CC		 1/*
2 * Texas Instruments CPDMA Driver
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/spinlock.h>
17#include <linux/device.h>
76fbc247 18#include <linux/module.h>
ef8c2dab
CC		 19#include <linux/slab.h>
20#include <linux/err.h>
21#include <linux/dma-mapping.h>
22#include <linux/io.h>
817f6d1a 23#include <linux/delay.h>
ef8c2dab
CC		 24
25#include "davinci_cpdma.h"
26
27/* DMA Registers */
28#define CPDMA_TXIDVER 0x00
29#define CPDMA_TXCONTROL 0x04
30#define CPDMA_TXTEARDOWN 0x08
31#define CPDMA_RXIDVER 0x10
32#define CPDMA_RXCONTROL 0x14
33#define CPDMA_SOFTRESET 0x1c
34#define CPDMA_RXTEARDOWN 0x18
35#define CPDMA_TXINTSTATRAW 0x80
36#define CPDMA_TXINTSTATMASKED 0x84
37#define CPDMA_TXINTMASKSET 0x88
38#define CPDMA_TXINTMASKCLEAR 0x8c
39#define CPDMA_MACINVECTOR 0x90
40#define CPDMA_MACEOIVECTOR 0x94
41#define CPDMA_RXINTSTATRAW 0xa0
42#define CPDMA_RXINTSTATMASKED 0xa4
43#define CPDMA_RXINTMASKSET 0xa8
44#define CPDMA_RXINTMASKCLEAR 0xac
45#define CPDMA_DMAINTSTATRAW 0xb0
46#define CPDMA_DMAINTSTATMASKED 0xb4
47#define CPDMA_DMAINTMASKSET 0xb8
48#define CPDMA_DMAINTMASKCLEAR 0xbc
49#define CPDMA_DMAINT_HOSTERR BIT(1)
50
51/* the following exist only if has_ext_regs is set */
52#define CPDMA_DMACONTROL 0x20
53#define CPDMA_DMASTATUS 0x24
54#define CPDMA_RXBUFFOFS 0x28
55#define CPDMA_EM_CONTROL 0x2c
56
57/* Descriptor mode bits */
58#define CPDMA_DESC_SOP BIT(31)
59#define CPDMA_DESC_EOP BIT(30)
60#define CPDMA_DESC_OWNER BIT(29)
61#define CPDMA_DESC_EOQ BIT(28)
62#define CPDMA_DESC_TD_COMPLETE BIT(27)
63#define CPDMA_DESC_PASS_CRC BIT(26)
f6e135c8
M		 64#define CPDMA_DESC_TO_PORT_EN BIT(20)
65#define CPDMA_TO_PORT_SHIFT 16
66#define CPDMA_DESC_PORT_MASK (BIT(18) | BIT(17) | BIT(16))
28a19fe6 67#define CPDMA_DESC_CRC_LEN 4
ef8c2dab
CC		 68
69#define CPDMA_TEARDOWN_VALUE 0xfffffffc
70
71struct cpdma_desc {
72 /* hardware fields */
73 u32 hw_next;
74 u32 hw_buffer;
75 u32 hw_len;
76 u32 hw_mode;
77 /* software fields */
78 void *sw_token;
79 u32 sw_buffer;
80 u32 sw_len;
81};
82
83struct cpdma_desc_pool {
c767db51 84 phys_addr_t phys;
6a1fef6d 85 u32 hw_addr;
ef8c2dab
CC		 86 void __iomem *iomap; /* ioremap map */
87 void *cpumap; /* dma_alloc map */
88 int desc_size, mem_size;
89 int num_desc, used_desc;
90 unsigned long *bitmap;
91 struct device *dev;
92 spinlock_t lock;
93};
94
95enum cpdma_state {
96 CPDMA_STATE_IDLE,
97 CPDMA_STATE_ACTIVE,
98 CPDMA_STATE_TEARDOWN,
99};
100
32a6d90b 101static const char *cpdma_state_str[] = { "idle", "active", "teardown" };
ef8c2dab
CC		 102
103struct cpdma_ctlr {
104 enum cpdma_state state;
105 struct cpdma_params params;
106 struct device *dev;
107 struct cpdma_desc_pool *pool;
108 spinlock_t lock;
109 struct cpdma_chan *channels[2 * CPDMA_MAX_CHANNELS];
110};
111
112struct cpdma_chan {
fae50823
M		 113 struct cpdma_desc __iomem *head, *tail;
114 void __iomem *hdp, *cp, *rxfree;
ef8c2dab
CC		 115 enum cpdma_state state;
116 struct cpdma_ctlr *ctlr;
117 int chan_num;
118 spinlock_t lock;
ef8c2dab 119 int count;
ef8c2dab
CC		 120 u32 mask;
121 cpdma_handler_fn handler;
122 enum dma_data_direction dir;
123 struct cpdma_chan_stats stats;
124 /* offsets into dmaregs */
125 int int_set, int_clear, td;
126};
127
128/* The following make access to common cpdma_ctlr params more readable */
129#define dmaregs params.dmaregs
130#define num_chan params.num_chan
131
132/* various accessors */
133#define dma_reg_read(ctlr, ofs) __raw_readl((ctlr)->dmaregs + (ofs))
134#define chan_read(chan, fld) __raw_readl((chan)->fld)
135#define desc_read(desc, fld) __raw_readl(&(desc)->fld)
136#define dma_reg_write(ctlr, ofs, v) __raw_writel(v, (ctlr)->dmaregs + (ofs))
137#define chan_write(chan, fld, v) __raw_writel(v, (chan)->fld)
138#define desc_write(desc, fld, v) __raw_writel((u32)(v), &(desc)->fld)
139
f6e135c8
M		 140#define cpdma_desc_to_port(chan, mode, directed) \
141 do { \
142 if (!is_rx_chan(chan) && ((directed == 1) || \
143 (directed == 2))) \
144 mode |= (CPDMA_DESC_TO_PORT_EN | \
145 (directed << CPDMA_TO_PORT_SHIFT)); \
146 } while (0)
147
ef8c2dab
CC		 148/*
149 * Utility constructs for a cpdma descriptor pool. Some devices (e.g. davinci
150 * emac) have dedicated on-chip memory for these descriptors. Some other
151 * devices (e.g. cpsw switches) use plain old memory. Descriptor pools
152 * abstract out these details
153 */
154static struct cpdma_desc_pool *
6a1fef6d
S		 155cpdma_desc_pool_create(struct device *dev, u32 phys, u32 hw_addr,
156 int size, int align)
ef8c2dab
CC		 157{
158 int bitmap_size;
159 struct cpdma_desc_pool *pool;
160
e1943128 161 pool = devm_kzalloc(dev, sizeof(*pool), GFP_KERNEL);
ef8c2dab 162 if (!pool)
e1943128 163 goto fail;
ef8c2dab
CC		 164
165 spin_lock_init(&pool->lock);
166
167 pool->dev = dev;
168 pool->mem_size = size;
169 pool->desc_size = ALIGN(sizeof(struct cpdma_desc), align);
170 pool->num_desc = size / pool->desc_size;
171
172 bitmap_size = (pool->num_desc / BITS_PER_LONG) * sizeof(long);
e1943128 173 pool->bitmap = devm_kzalloc(dev, bitmap_size, GFP_KERNEL);
ef8c2dab
CC		 174 if (!pool->bitmap)
175 goto fail;
176
177 if (phys) {
178 pool->phys = phys;
179 pool->iomap = ioremap(phys, size);
6a1fef6d 180 pool->hw_addr = hw_addr;
ef8c2dab
CC		 181 } else {
182 pool->cpumap = dma_alloc_coherent(dev, size, &pool->phys,
183 GFP_KERNEL);
43d620c8 184 pool->iomap = pool->cpumap;
6a1fef6d 185 pool->hw_addr = pool->phys;
ef8c2dab
CC		 186 }
187
188 if (pool->iomap)
189 return pool;
ef8c2dab 190fail:
ef8c2dab
CC		 191 return NULL;
192}
193
194static void cpdma_desc_pool_destroy(struct cpdma_desc_pool *pool)
195{
196 unsigned long flags;
197
198 if (!pool)
199 return;
200
201 spin_lock_irqsave(&pool->lock, flags);
202 WARN_ON(pool->used_desc);
ef8c2dab
CC		 203 if (pool->cpumap) {
204 dma_free_coherent(pool->dev, pool->mem_size, pool->cpumap,
205 pool->phys);
206 } else {
207 iounmap(pool->iomap);
208 }
209 spin_unlock_irqrestore(&pool->lock, flags);
ef8c2dab
CC		 210}
211
212static inline dma_addr_t desc_phys(struct cpdma_desc_pool *pool,
213 struct cpdma_desc __iomem *desc)
214{
215 if (!desc)
216 return 0;
c767db51 217 return pool->hw_addr + (__force long)desc - (__force long)pool->iomap;
ef8c2dab
CC		 218}
219
220static inline struct cpdma_desc __iomem *
221desc_from_phys(struct cpdma_desc_pool *pool, dma_addr_t dma)
222{
6a1fef6d 223 return dma ? pool->iomap + dma - pool->hw_addr : NULL;
ef8c2dab
CC		 224}
225
226static struct cpdma_desc __iomem *
fae50823 227cpdma_desc_alloc(struct cpdma_desc_pool *pool, int num_desc, bool is_rx)
ef8c2dab
CC		 228{
229 unsigned long flags;
230 int index;
fae50823
M		 231 int desc_start;
232 int desc_end;
ef8c2dab
CC		 233 struct cpdma_desc __iomem *desc = NULL;
234
235 spin_lock_irqsave(&pool->lock, flags);
236
fae50823
M		 237 if (is_rx) {
238 desc_start = 0;
239 desc_end = pool->num_desc/2;
240 } else {
241 desc_start = pool->num_desc/2;
242 desc_end = pool->num_desc;
243 }
244
245 index = bitmap_find_next_zero_area(pool->bitmap,
246 desc_end, desc_start, num_desc, 0);
247 if (index < desc_end) {
ef8c2dab
CC		 248 bitmap_set(pool->bitmap, index, num_desc);
249 desc = pool->iomap + pool->desc_size * index;
250 pool->used_desc++;
251 }
252
253 spin_unlock_irqrestore(&pool->lock, flags);
254 return desc;
255}
256
257static void cpdma_desc_free(struct cpdma_desc_pool *pool,
258 struct cpdma_desc __iomem *desc, int num_desc)
259{
260 unsigned long flags, index;
261
262 index = ((unsigned long)desc - (unsigned long)pool->iomap) /
263 pool->desc_size;
264 spin_lock_irqsave(&pool->lock, flags);
265 bitmap_clear(pool->bitmap, index, num_desc);
266 pool->used_desc--;
267 spin_unlock_irqrestore(&pool->lock, flags);
268}
269
270struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params)
271{
272 struct cpdma_ctlr *ctlr;
273
e1943128 274 ctlr = devm_kzalloc(params->dev, sizeof(*ctlr), GFP_KERNEL);
ef8c2dab
CC		 275 if (!ctlr)
276 return NULL;
277
278 ctlr->state = CPDMA_STATE_IDLE;
279 ctlr->params = *params;
280 ctlr->dev = params->dev;
281 spin_lock_init(&ctlr->lock);
282
283 ctlr->pool = cpdma_desc_pool_create(ctlr->dev,
284 ctlr->params.desc_mem_phys,
6a1fef6d 285 ctlr->params.desc_hw_addr,
ef8c2dab
CC		 286 ctlr->params.desc_mem_size,
287 ctlr->params.desc_align);
288 if (!ctlr->pool) {
289 kfree(ctlr);
290 return NULL;
291 }
292
293 if (WARN_ON(ctlr->num_chan > CPDMA_MAX_CHANNELS))
294 ctlr->num_chan = CPDMA_MAX_CHANNELS;
295 return ctlr;
296}
32a6d90b 297EXPORT_SYMBOL_GPL(cpdma_ctlr_create);
ef8c2dab
CC		 298
299int cpdma_ctlr_start(struct cpdma_ctlr *ctlr)
300{
301 unsigned long flags;
302 int i;
303
304 spin_lock_irqsave(&ctlr->lock, flags);
305 if (ctlr->state != CPDMA_STATE_IDLE) {
306 spin_unlock_irqrestore(&ctlr->lock, flags);
307 return -EBUSY;
308 }
309
310 if (ctlr->params.has_soft_reset) {
817f6d1a 311 unsigned timeout = 10 * 100;
ef8c2dab
CC		 312
313 dma_reg_write(ctlr, CPDMA_SOFTRESET, 1);
817f6d1a 314 while (timeout) {
ef8c2dab
CC		 315 if (dma_reg_read(ctlr, CPDMA_SOFTRESET) == 0)
316 break;
817f6d1a
SS		 317 udelay(10);
318 timeout--;
ef8c2dab 319 }
817f6d1a 320 WARN_ON(!timeout);
ef8c2dab
CC		 321 }
322
323 for (i = 0; i < ctlr->num_chan; i++) {
324 __raw_writel(0, ctlr->params.txhdp + 4 * i);
325 __raw_writel(0, ctlr->params.rxhdp + 4 * i);
326 __raw_writel(0, ctlr->params.txcp + 4 * i);
327 __raw_writel(0, ctlr->params.rxcp + 4 * i);
328 }
329
330 dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff);
331 dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff);
332
333 dma_reg_write(ctlr, CPDMA_TXCONTROL, 1);
334 dma_reg_write(ctlr, CPDMA_RXCONTROL, 1);
335
336 ctlr->state = CPDMA_STATE_ACTIVE;
337
338 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
339 if (ctlr->channels[i])
340 cpdma_chan_start(ctlr->channels[i]);
341 }
342 spin_unlock_irqrestore(&ctlr->lock, flags);
343 return 0;
344}
32a6d90b 345EXPORT_SYMBOL_GPL(cpdma_ctlr_start);
ef8c2dab
CC		 346
347int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr)
348{
349 unsigned long flags;
350 int i;
351
352 spin_lock_irqsave(&ctlr->lock, flags);
cd11cf50 353 if (ctlr->state == CPDMA_STATE_TEARDOWN) {
ef8c2dab
CC		 354 spin_unlock_irqrestore(&ctlr->lock, flags);
355 return -EINVAL;
356 }
357
358 ctlr->state = CPDMA_STATE_TEARDOWN;
359
360 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
361 if (ctlr->channels[i])
362 cpdma_chan_stop(ctlr->channels[i]);
363 }
364
365 dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff);
366 dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff);
367
368 dma_reg_write(ctlr, CPDMA_TXCONTROL, 0);
369 dma_reg_write(ctlr, CPDMA_RXCONTROL, 0);
370
371 ctlr->state = CPDMA_STATE_IDLE;
372
373 spin_unlock_irqrestore(&ctlr->lock, flags);
374 return 0;
375}
32a6d90b 376EXPORT_SYMBOL_GPL(cpdma_ctlr_stop);
ef8c2dab
CC		 377
378int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr)
379{
380 struct device *dev = ctlr->dev;
381 unsigned long flags;
382 int i;
383
384 spin_lock_irqsave(&ctlr->lock, flags);
385
386 dev_info(dev, "CPDMA: state: %s", cpdma_state_str[ctlr->state]);
387
388 dev_info(dev, "CPDMA: txidver: %x",
389 dma_reg_read(ctlr, CPDMA_TXIDVER));
390 dev_info(dev, "CPDMA: txcontrol: %x",
391 dma_reg_read(ctlr, CPDMA_TXCONTROL));
392 dev_info(dev, "CPDMA: txteardown: %x",
393 dma_reg_read(ctlr, CPDMA_TXTEARDOWN));
394 dev_info(dev, "CPDMA: rxidver: %x",
395 dma_reg_read(ctlr, CPDMA_RXIDVER));
396 dev_info(dev, "CPDMA: rxcontrol: %x",
397 dma_reg_read(ctlr, CPDMA_RXCONTROL));
398 dev_info(dev, "CPDMA: softreset: %x",
399 dma_reg_read(ctlr, CPDMA_SOFTRESET));
400 dev_info(dev, "CPDMA: rxteardown: %x",
401 dma_reg_read(ctlr, CPDMA_RXTEARDOWN));
402 dev_info(dev, "CPDMA: txintstatraw: %x",
403 dma_reg_read(ctlr, CPDMA_TXINTSTATRAW));
404 dev_info(dev, "CPDMA: txintstatmasked: %x",
405 dma_reg_read(ctlr, CPDMA_TXINTSTATMASKED));
406 dev_info(dev, "CPDMA: txintmaskset: %x",
407 dma_reg_read(ctlr, CPDMA_TXINTMASKSET));
408 dev_info(dev, "CPDMA: txintmaskclear: %x",
409 dma_reg_read(ctlr, CPDMA_TXINTMASKCLEAR));
410 dev_info(dev, "CPDMA: macinvector: %x",
411 dma_reg_read(ctlr, CPDMA_MACINVECTOR));
412 dev_info(dev, "CPDMA: maceoivector: %x",
413 dma_reg_read(ctlr, CPDMA_MACEOIVECTOR));
414 dev_info(dev, "CPDMA: rxintstatraw: %x",
415 dma_reg_read(ctlr, CPDMA_RXINTSTATRAW));
416 dev_info(dev, "CPDMA: rxintstatmasked: %x",
417 dma_reg_read(ctlr, CPDMA_RXINTSTATMASKED));
418 dev_info(dev, "CPDMA: rxintmaskset: %x",
419 dma_reg_read(ctlr, CPDMA_RXINTMASKSET));
420 dev_info(dev, "CPDMA: rxintmaskclear: %x",
421 dma_reg_read(ctlr, CPDMA_RXINTMASKCLEAR));
422 dev_info(dev, "CPDMA: dmaintstatraw: %x",
423 dma_reg_read(ctlr, CPDMA_DMAINTSTATRAW));
424 dev_info(dev, "CPDMA: dmaintstatmasked: %x",
425 dma_reg_read(ctlr, CPDMA_DMAINTSTATMASKED));
426 dev_info(dev, "CPDMA: dmaintmaskset: %x",
427 dma_reg_read(ctlr, CPDMA_DMAINTMASKSET));
428 dev_info(dev, "CPDMA: dmaintmaskclear: %x",
429 dma_reg_read(ctlr, CPDMA_DMAINTMASKCLEAR));
430
431 if (!ctlr->params.has_ext_regs) {
432 dev_info(dev, "CPDMA: dmacontrol: %x",
433 dma_reg_read(ctlr, CPDMA_DMACONTROL));
434 dev_info(dev, "CPDMA: dmastatus: %x",
435 dma_reg_read(ctlr, CPDMA_DMASTATUS));
436 dev_info(dev, "CPDMA: rxbuffofs: %x",
437 dma_reg_read(ctlr, CPDMA_RXBUFFOFS));
438 }
439
440 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++)
441 if (ctlr->channels[i])
442 cpdma_chan_dump(ctlr->channels[i]);
443
444 spin_unlock_irqrestore(&ctlr->lock, flags);
445 return 0;
446}
32a6d90b 447EXPORT_SYMBOL_GPL(cpdma_ctlr_dump);
ef8c2dab
CC		 448
449int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr)
450{
451 unsigned long flags;
452 int ret = 0, i;
453
454 if (!ctlr)
455 return -EINVAL;
456
457 spin_lock_irqsave(&ctlr->lock, flags);
458 if (ctlr->state != CPDMA_STATE_IDLE)
459 cpdma_ctlr_stop(ctlr);
460
79876e03
CR		 461 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++)
462 cpdma_chan_destroy(ctlr->channels[i]);
ef8c2dab
CC		 463
464 cpdma_desc_pool_destroy(ctlr->pool);
465 spin_unlock_irqrestore(&ctlr->lock, flags);
ef8c2dab
CC		 466 return ret;
467}
32a6d90b 468EXPORT_SYMBOL_GPL(cpdma_ctlr_destroy);
ef8c2dab
CC		 469
470int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable)
471{
472 unsigned long flags;
473 int i, reg;
474
475 spin_lock_irqsave(&ctlr->lock, flags);
476 if (ctlr->state != CPDMA_STATE_ACTIVE) {
477 spin_unlock_irqrestore(&ctlr->lock, flags);
478 return -EINVAL;
479 }
480
481 reg = enable ? CPDMA_DMAINTMASKSET : CPDMA_DMAINTMASKCLEAR;
482 dma_reg_write(ctlr, reg, CPDMA_DMAINT_HOSTERR);
483
484 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
485 if (ctlr->channels[i])
486 cpdma_chan_int_ctrl(ctlr->channels[i], enable);
487 }
488
489 spin_unlock_irqrestore(&ctlr->lock, flags);
490 return 0;
491}
6929e24e 492EXPORT_SYMBOL_GPL(cpdma_ctlr_int_ctrl);
ef8c2dab 493
510a1e72 494void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value)
ef8c2dab 495{
510a1e72 496 dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value);
ef8c2dab 497}
6929e24e 498EXPORT_SYMBOL_GPL(cpdma_ctlr_eoi);
ef8c2dab
CC		 499
500struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
501 cpdma_handler_fn handler)
502{
503 struct cpdma_chan *chan;
e1943128 504 int offset = (chan_num % CPDMA_MAX_CHANNELS) * 4;
ef8c2dab
CC		 505 unsigned long flags;
506
507 if (__chan_linear(chan_num) >= ctlr->num_chan)
508 return NULL;
509
e1943128 510 chan = devm_kzalloc(ctlr->dev, sizeof(*chan), GFP_KERNEL);
ef8c2dab 511 if (!chan)
e1943128 512 return ERR_PTR(-ENOMEM);
ef8c2dab
CC		 513
514 spin_lock_irqsave(&ctlr->lock, flags);
e1943128
GC		 515 if (ctlr->channels[chan_num]) {
516 spin_unlock_irqrestore(&ctlr->lock, flags);
517 devm_kfree(ctlr->dev, chan);
518 return ERR_PTR(-EBUSY);
519 }
ef8c2dab
CC		 520
521 chan->ctlr = ctlr;
522 chan->state = CPDMA_STATE_IDLE;
523 chan->chan_num = chan_num;
524 chan->handler = handler;
525
526 if (is_rx_chan(chan)) {
527 chan->hdp = ctlr->params.rxhdp + offset;
528 chan->cp = ctlr->params.rxcp + offset;
529 chan->rxfree = ctlr->params.rxfree + offset;
530 chan->int_set = CPDMA_RXINTMASKSET;
531 chan->int_clear = CPDMA_RXINTMASKCLEAR;
532 chan->td = CPDMA_RXTEARDOWN;
533 chan->dir = DMA_FROM_DEVICE;
534 } else {
535 chan->hdp = ctlr->params.txhdp + offset;
536 chan->cp = ctlr->params.txcp + offset;
537 chan->int_set = CPDMA_TXINTMASKSET;
538 chan->int_clear = CPDMA_TXINTMASKCLEAR;
539 chan->td = CPDMA_TXTEARDOWN;
540 chan->dir = DMA_TO_DEVICE;
541 }
542 chan->mask = BIT(chan_linear(chan));
543
544 spin_lock_init(&chan->lock);
545
546 ctlr->channels[chan_num] = chan;
547 spin_unlock_irqrestore(&ctlr->lock, flags);
548 return chan;
ef8c2dab 549}
32a6d90b 550EXPORT_SYMBOL_GPL(cpdma_chan_create);
ef8c2dab
CC		 551
552int cpdma_chan_destroy(struct cpdma_chan *chan)
553{
f37c54b6 554 struct cpdma_ctlr *ctlr;
ef8c2dab
CC		 555 unsigned long flags;
556
557 if (!chan)
558 return -EINVAL;
f37c54b6 559 ctlr = chan->ctlr;
ef8c2dab
CC		 560
561 spin_lock_irqsave(&ctlr->lock, flags);
562 if (chan->state != CPDMA_STATE_IDLE)
563 cpdma_chan_stop(chan);
564 ctlr->channels[chan->chan_num] = NULL;
565 spin_unlock_irqrestore(&ctlr->lock, flags);
566 kfree(chan);
567 return 0;
568}
32a6d90b 569EXPORT_SYMBOL_GPL(cpdma_chan_destroy);
ef8c2dab
CC		 570
571int cpdma_chan_get_stats(struct cpdma_chan *chan,
572 struct cpdma_chan_stats *stats)
573{
574 unsigned long flags;
575 if (!chan)
576 return -EINVAL;
577 spin_lock_irqsave(&chan->lock, flags);
578 memcpy(stats, &chan->stats, sizeof(*stats));
579 spin_unlock_irqrestore(&chan->lock, flags);
580 return 0;
581}
0ca04b63 582EXPORT_SYMBOL_GPL(cpdma_chan_get_stats);
ef8c2dab
CC		 583
584int cpdma_chan_dump(struct cpdma_chan *chan)
585{
586 unsigned long flags;
587 struct device *dev = chan->ctlr->dev;
588
589 spin_lock_irqsave(&chan->lock, flags);
590
591 dev_info(dev, "channel %d (%s %d) state %s",
592 chan->chan_num, is_rx_chan(chan) ? "rx" : "tx",
593 chan_linear(chan), cpdma_state_str[chan->state]);
594 dev_info(dev, "\thdp: %x\n", chan_read(chan, hdp));
595 dev_info(dev, "\tcp: %x\n", chan_read(chan, cp));
596 if (chan->rxfree) {
597 dev_info(dev, "\trxfree: %x\n",
598 chan_read(chan, rxfree));
599 }
600
601 dev_info(dev, "\tstats head_enqueue: %d\n",
602 chan->stats.head_enqueue);
603 dev_info(dev, "\tstats tail_enqueue: %d\n",
604 chan->stats.tail_enqueue);
605 dev_info(dev, "\tstats pad_enqueue: %d\n",
606 chan->stats.pad_enqueue);
607 dev_info(dev, "\tstats misqueued: %d\n",
608 chan->stats.misqueued);
609 dev_info(dev, "\tstats desc_alloc_fail: %d\n",
610 chan->stats.desc_alloc_fail);
611 dev_info(dev, "\tstats pad_alloc_fail: %d\n",
612 chan->stats.pad_alloc_fail);
613 dev_info(dev, "\tstats runt_receive_buff: %d\n",
614 chan->stats.runt_receive_buff);
615 dev_info(dev, "\tstats runt_transmit_buff: %d\n",
616 chan->stats.runt_transmit_buff);
617 dev_info(dev, "\tstats empty_dequeue: %d\n",
618 chan->stats.empty_dequeue);
619 dev_info(dev, "\tstats busy_dequeue: %d\n",
620 chan->stats.busy_dequeue);
621 dev_info(dev, "\tstats good_dequeue: %d\n",
622 chan->stats.good_dequeue);
623 dev_info(dev, "\tstats requeue: %d\n",
624 chan->stats.requeue);
625 dev_info(dev, "\tstats teardown_dequeue: %d\n",
626 chan->stats.teardown_dequeue);
627
628 spin_unlock_irqrestore(&chan->lock, flags);
629 return 0;
630}
631
632static void __cpdma_chan_submit(struct cpdma_chan *chan,
633 struct cpdma_desc __iomem *desc)
634{
635 struct cpdma_ctlr *ctlr = chan->ctlr;
636 struct cpdma_desc __iomem *prev = chan->tail;
637 struct cpdma_desc_pool *pool = ctlr->pool;
638 dma_addr_t desc_dma;
639 u32 mode;
640
641 desc_dma = desc_phys(pool, desc);
642
643 /* simple case - idle channel */
644 if (!chan->head) {
645 chan->stats.head_enqueue++;
646 chan->head = desc;
647 chan->tail = desc;
648 if (chan->state == CPDMA_STATE_ACTIVE)
649 chan_write(chan, hdp, desc_dma);
650 return;
651 }
652
653 /* first chain the descriptor at the tail of the list */
654 desc_write(prev, hw_next, desc_dma);
655 chan->tail = desc;
656 chan->stats.tail_enqueue++;
657
658 /* next check if EOQ has been triggered already */
659 mode = desc_read(prev, hw_mode);
660 if (((mode & (CPDMA_DESC_EOQ | CPDMA_DESC_OWNER)) == CPDMA_DESC_EOQ) &&
661 (chan->state == CPDMA_STATE_ACTIVE)) {
662 desc_write(prev, hw_mode, mode & ~CPDMA_DESC_EOQ);
663 chan_write(chan, hdp, desc_dma);
664 chan->stats.misqueued++;
665 }
666}
667
668int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
aef614e1 669 int len, int directed)
ef8c2dab
CC		 670{
671 struct cpdma_ctlr *ctlr = chan->ctlr;
672 struct cpdma_desc __iomem *desc;
673 dma_addr_t buffer;
674 unsigned long flags;
675 u32 mode;
676 int ret = 0;
677
678 spin_lock_irqsave(&chan->lock, flags);
679
680 if (chan->state == CPDMA_STATE_TEARDOWN) {
681 ret = -EINVAL;
682 goto unlock_ret;
683 }
684
fae50823 685 desc = cpdma_desc_alloc(ctlr->pool, 1, is_rx_chan(chan));
ef8c2dab
CC		 686 if (!desc) {
687 chan->stats.desc_alloc_fail++;
688 ret = -ENOMEM;
689 goto unlock_ret;
690 }
691
692 if (len < ctlr->params.min_packet_size) {
693 len = ctlr->params.min_packet_size;
694 chan->stats.runt_transmit_buff++;
695 }
696
697 buffer = dma_map_single(ctlr->dev, data, len, chan->dir);
14bd0769
SS		 698 ret = dma_mapping_error(ctlr->dev, buffer);
699 if (ret) {
700 cpdma_desc_free(ctlr->pool, desc, 1);
701 ret = -EINVAL;
702 goto unlock_ret;
703 }
704
ef8c2dab 705 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
f6e135c8 706 cpdma_desc_to_port(chan, mode, directed);
ef8c2dab
CC		 707
708 desc_write(desc, hw_next, 0);
709 desc_write(desc, hw_buffer, buffer);
710 desc_write(desc, hw_len, len);
711 desc_write(desc, hw_mode, mode | len);
712 desc_write(desc, sw_token, token);
713 desc_write(desc, sw_buffer, buffer);
714 desc_write(desc, sw_len, len);
715
716 __cpdma_chan_submit(chan, desc);
717
718 if (chan->state == CPDMA_STATE_ACTIVE && chan->rxfree)
719 chan_write(chan, rxfree, 1);
720
721 chan->count++;
722
723unlock_ret:
724 spin_unlock_irqrestore(&chan->lock, flags);
725 return ret;
726}
32a6d90b 727EXPORT_SYMBOL_GPL(cpdma_chan_submit);
ef8c2dab 728
fae50823
M		 729bool cpdma_check_free_tx_desc(struct cpdma_chan *chan)
730{
731 unsigned long flags;
732 int index;
733 bool ret;
734 struct cpdma_ctlr *ctlr = chan->ctlr;
735 struct cpdma_desc_pool *pool = ctlr->pool;
736
737 spin_lock_irqsave(&pool->lock, flags);
738
739 index = bitmap_find_next_zero_area(pool->bitmap,
740 pool->num_desc, pool->num_desc/2, 1, 0);
741
742 if (index < pool->num_desc)
743 ret = true;
744 else
745 ret = false;
746
747 spin_unlock_irqrestore(&pool->lock, flags);
748 return ret;
749}
750EXPORT_SYMBOL_GPL(cpdma_check_free_tx_desc);
751
ef8c2dab
CC		 752static void __cpdma_chan_free(struct cpdma_chan *chan,
753 struct cpdma_desc __iomem *desc,
754 int outlen, int status)
755{
756 struct cpdma_ctlr *ctlr = chan->ctlr;
757 struct cpdma_desc_pool *pool = ctlr->pool;
758 dma_addr_t buff_dma;
759 int origlen;
760 void *token;
761
762 token = (void *)desc_read(desc, sw_token);
763 buff_dma = desc_read(desc, sw_buffer);
764 origlen = desc_read(desc, sw_len);
765
766 dma_unmap_single(ctlr->dev, buff_dma, origlen, chan->dir);
767 cpdma_desc_free(pool, desc, 1);
768 (*chan->handler)(token, outlen, status);
769}
770
771static int __cpdma_chan_process(struct cpdma_chan *chan)
772{
773 struct cpdma_ctlr *ctlr = chan->ctlr;
774 struct cpdma_desc __iomem *desc;
775 int status, outlen;
b4727e69 776 int cb_status = 0;
ef8c2dab
CC		 777 struct cpdma_desc_pool *pool = ctlr->pool;
778 dma_addr_t desc_dma;
779 unsigned long flags;
780
781 spin_lock_irqsave(&chan->lock, flags);
782
783 desc = chan->head;
784 if (!desc) {
785 chan->stats.empty_dequeue++;
786 status = -ENOENT;
787 goto unlock_ret;
788 }
789 desc_dma = desc_phys(pool, desc);
790
791 status = __raw_readl(&desc->hw_mode);
792 outlen = status & 0x7ff;
793 if (status & CPDMA_DESC_OWNER) {
794 chan->stats.busy_dequeue++;
795 status = -EBUSY;
796 goto unlock_ret;
797 }
28a19fe6
M		 798
799 if (status & CPDMA_DESC_PASS_CRC)
800 outlen -= CPDMA_DESC_CRC_LEN;
801
f6e135c8
M		 802 status = status & (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE |
803 CPDMA_DESC_PORT_MASK);
ef8c2dab
CC		 804
805 chan->head = desc_from_phys(pool, desc_read(desc, hw_next));
806 chan_write(chan, cp, desc_dma);
807 chan->count--;
808 chan->stats.good_dequeue++;
809
810 if (status & CPDMA_DESC_EOQ) {
811 chan->stats.requeue++;
812 chan_write(chan, hdp, desc_phys(pool, chan->head));
813 }
814
815 spin_unlock_irqrestore(&chan->lock, flags);
b4727e69
SS		 816 if (unlikely(status & CPDMA_DESC_TD_COMPLETE))
817 cb_status = -ENOSYS;
818 else
819 cb_status = status;
ef8c2dab 820
b4727e69 821 __cpdma_chan_free(chan, desc, outlen, cb_status);
ef8c2dab
CC		 822 return status;
823
824unlock_ret:
825 spin_unlock_irqrestore(&chan->lock, flags);
826 return status;
827}
828
829int cpdma_chan_process(struct cpdma_chan *chan, int quota)
830{
831 int used = 0, ret = 0;
832
833 if (chan->state != CPDMA_STATE_ACTIVE)
834 return -EINVAL;
835
836 while (used < quota) {
837 ret = __cpdma_chan_process(chan);
838 if (ret < 0)
839 break;
840 used++;
841 }
842 return used;
843}
32a6d90b 844EXPORT_SYMBOL_GPL(cpdma_chan_process);
ef8c2dab
CC		 845
846int cpdma_chan_start(struct cpdma_chan *chan)
847{
848 struct cpdma_ctlr *ctlr = chan->ctlr;
849 struct cpdma_desc_pool *pool = ctlr->pool;
850 unsigned long flags;
851
852 spin_lock_irqsave(&chan->lock, flags);
853 if (chan->state != CPDMA_STATE_IDLE) {
854 spin_unlock_irqrestore(&chan->lock, flags);
855 return -EBUSY;
856 }
857 if (ctlr->state != CPDMA_STATE_ACTIVE) {
858 spin_unlock_irqrestore(&chan->lock, flags);
859 return -EINVAL;
860 }
861 dma_reg_write(ctlr, chan->int_set, chan->mask);
862 chan->state = CPDMA_STATE_ACTIVE;
863 if (chan->head) {
864 chan_write(chan, hdp, desc_phys(pool, chan->head));
865 if (chan->rxfree)
866 chan_write(chan, rxfree, chan->count);
867 }
868
869 spin_unlock_irqrestore(&chan->lock, flags);
870 return 0;
871}
32a6d90b 872EXPORT_SYMBOL_GPL(cpdma_chan_start);
ef8c2dab
CC		 873
874int cpdma_chan_stop(struct cpdma_chan *chan)
875{
876 struct cpdma_ctlr *ctlr = chan->ctlr;
877 struct cpdma_desc_pool *pool = ctlr->pool;
878 unsigned long flags;
879 int ret;
817f6d1a 880 unsigned timeout;
ef8c2dab
CC		 881
882 spin_lock_irqsave(&chan->lock, flags);
cd11cf50 883 if (chan->state == CPDMA_STATE_TEARDOWN) {
ef8c2dab
CC		 884 spin_unlock_irqrestore(&chan->lock, flags);
885 return -EINVAL;
886 }
887
888 chan->state = CPDMA_STATE_TEARDOWN;
889 dma_reg_write(ctlr, chan->int_clear, chan->mask);
890
891 /* trigger teardown */
b4ad0428 892 dma_reg_write(ctlr, chan->td, chan_linear(chan));
ef8c2dab
CC		 893
894 /* wait for teardown complete */
817f6d1a
SS		 895 timeout = 100 * 100; /* 100 ms */
896 while (timeout) {
ef8c2dab
CC		 897 u32 cp = chan_read(chan, cp);
898 if ((cp & CPDMA_TEARDOWN_VALUE) == CPDMA_TEARDOWN_VALUE)
899 break;
817f6d1a
SS		 900 udelay(10);
901 timeout--;
ef8c2dab 902 }
817f6d1a 903 WARN_ON(!timeout);
ef8c2dab
CC		 904 chan_write(chan, cp, CPDMA_TEARDOWN_VALUE);
905
906 /* handle completed packets */
7746ab0a 907 spin_unlock_irqrestore(&chan->lock, flags);
ef8c2dab
CC		 908 do {
909 ret = __cpdma_chan_process(chan);
910 if (ret < 0)
911 break;
912 } while ((ret & CPDMA_DESC_TD_COMPLETE) == 0);
7746ab0a 913 spin_lock_irqsave(&chan->lock, flags);
ef8c2dab
CC		 914
915 /* remaining packets haven't been tx/rx'ed, clean them up */
916 while (chan->head) {
917 struct cpdma_desc __iomem *desc = chan->head;
918 dma_addr_t next_dma;
919
920 next_dma = desc_read(desc, hw_next);
921 chan->head = desc_from_phys(pool, next_dma);
ffb5ba90 922 chan->count--;
ef8c2dab
CC		 923 chan->stats.teardown_dequeue++;
924
925 /* issue callback without locks held */
926 spin_unlock_irqrestore(&chan->lock, flags);
927 __cpdma_chan_free(chan, desc, 0, -ENOSYS);
928 spin_lock_irqsave(&chan->lock, flags);
929 }
930
931 chan->state = CPDMA_STATE_IDLE;
932 spin_unlock_irqrestore(&chan->lock, flags);
933 return 0;
934}
32a6d90b 935EXPORT_SYMBOL_GPL(cpdma_chan_stop);
ef8c2dab
CC		 936
937int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable)
938{
939 unsigned long flags;
940
941 spin_lock_irqsave(&chan->lock, flags);
942 if (chan->state != CPDMA_STATE_ACTIVE) {
943 spin_unlock_irqrestore(&chan->lock, flags);
944 return -EINVAL;
945 }
946
947 dma_reg_write(chan->ctlr, enable ? chan->int_set : chan->int_clear,
948 chan->mask);
949 spin_unlock_irqrestore(&chan->lock, flags);
950
951 return 0;
952}
953
954struct cpdma_control_info {
955 u32 reg;
956 u32 shift, mask;
957 int access;
958#define ACCESS_RO BIT(0)
959#define ACCESS_WO BIT(1)
960#define ACCESS_RW (ACCESS_RO | ACCESS_WO)
961};
962
df784160 963static struct cpdma_control_info controls[] = {
ef8c2dab
CC		 964 [CPDMA_CMD_IDLE] = {CPDMA_DMACONTROL, 3, 1, ACCESS_WO},
965 [CPDMA_COPY_ERROR_FRAMES] = {CPDMA_DMACONTROL, 4, 1, ACCESS_RW},
966 [CPDMA_RX_OFF_LEN_UPDATE] = {CPDMA_DMACONTROL, 2, 1, ACCESS_RW},
967 [CPDMA_RX_OWNERSHIP_FLIP] = {CPDMA_DMACONTROL, 1, 1, ACCESS_RW},
968 [CPDMA_TX_PRIO_FIXED] = {CPDMA_DMACONTROL, 0, 1, ACCESS_RW},
969 [CPDMA_STAT_IDLE] = {CPDMA_DMASTATUS, 31, 1, ACCESS_RO},
970 [CPDMA_STAT_TX_ERR_CODE] = {CPDMA_DMASTATUS, 20, 0xf, ACCESS_RW},
971 [CPDMA_STAT_TX_ERR_CHAN] = {CPDMA_DMASTATUS, 16, 0x7, ACCESS_RW},
972 [CPDMA_STAT_RX_ERR_CODE] = {CPDMA_DMASTATUS, 12, 0xf, ACCESS_RW},
973 [CPDMA_STAT_RX_ERR_CHAN] = {CPDMA_DMASTATUS, 8, 0x7, ACCESS_RW},
974 [CPDMA_RX_BUFFER_OFFSET] = {CPDMA_RXBUFFOFS, 0, 0xffff, ACCESS_RW},
975};
976
977int cpdma_control_get(struct cpdma_ctlr *ctlr, int control)
978{
979 unsigned long flags;
980 struct cpdma_control_info *info = &controls[control];
981 int ret;
982
983 spin_lock_irqsave(&ctlr->lock, flags);
984
985 ret = -ENOTSUPP;
986 if (!ctlr->params.has_ext_regs)
987 goto unlock_ret;
988
989 ret = -EINVAL;
990 if (ctlr->state != CPDMA_STATE_ACTIVE)
991 goto unlock_ret;
992
993 ret = -ENOENT;
994 if (control < 0 || control >= ARRAY_SIZE(controls))
995 goto unlock_ret;
996
997 ret = -EPERM;
998 if ((info->access & ACCESS_RO) != ACCESS_RO)
999 goto unlock_ret;
1000
1001 ret = (dma_reg_read(ctlr, info->reg) >> info->shift) & info->mask;
1002
1003unlock_ret:
1004 spin_unlock_irqrestore(&ctlr->lock, flags);
1005 return ret;
1006}
1007
1008int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value)
1009{
1010 unsigned long flags;
1011 struct cpdma_control_info *info = &controls[control];
1012 int ret;
1013 u32 val;
1014
1015 spin_lock_irqsave(&ctlr->lock, flags);
1016
1017 ret = -ENOTSUPP;
1018 if (!ctlr->params.has_ext_regs)
1019 goto unlock_ret;
1020
1021 ret = -EINVAL;
1022 if (ctlr->state != CPDMA_STATE_ACTIVE)
1023 goto unlock_ret;
1024
1025 ret = -ENOENT;
1026 if (control < 0 || control >= ARRAY_SIZE(controls))
1027 goto unlock_ret;
1028
1029 ret = -EPERM;
1030 if ((info->access & ACCESS_WO) != ACCESS_WO)
1031 goto unlock_ret;
1032
1033 val = dma_reg_read(ctlr, info->reg);
1034 val &= ~(info->mask << info->shift);
1035 val |= (value & info->mask) << info->shift;
1036 dma_reg_write(ctlr, info->reg, val);
1037 ret = 0;
1038
1039unlock_ret:
1040 spin_unlock_irqrestore(&ctlr->lock, flags);
1041 return ret;
1042}
6929e24e 1043EXPORT_SYMBOL_GPL(cpdma_control_set);
4bc21d41
SS		 1044
1045MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)