Commit | Line | Data |
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ef8c2dab CC |
1 | /* |
2 | * Texas Instruments CPDMA Driver | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/device.h> | |
76fbc247 | 18 | #include <linux/module.h> |
ef8c2dab CC |
19 | #include <linux/slab.h> |
20 | #include <linux/err.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/io.h> | |
817f6d1a | 23 | #include <linux/delay.h> |
742fb20f | 24 | #include <linux/genalloc.h> |
ef8c2dab CC |
25 | #include "davinci_cpdma.h" |
26 | ||
27 | /* DMA Registers */ | |
28 | #define CPDMA_TXIDVER 0x00 | |
29 | #define CPDMA_TXCONTROL 0x04 | |
30 | #define CPDMA_TXTEARDOWN 0x08 | |
31 | #define CPDMA_RXIDVER 0x10 | |
32 | #define CPDMA_RXCONTROL 0x14 | |
33 | #define CPDMA_SOFTRESET 0x1c | |
34 | #define CPDMA_RXTEARDOWN 0x18 | |
8f32b909 | 35 | #define CPDMA_TX_PRI0_RATE 0x30 |
ef8c2dab CC |
36 | #define CPDMA_TXINTSTATRAW 0x80 |
37 | #define CPDMA_TXINTSTATMASKED 0x84 | |
38 | #define CPDMA_TXINTMASKSET 0x88 | |
39 | #define CPDMA_TXINTMASKCLEAR 0x8c | |
40 | #define CPDMA_MACINVECTOR 0x90 | |
41 | #define CPDMA_MACEOIVECTOR 0x94 | |
42 | #define CPDMA_RXINTSTATRAW 0xa0 | |
43 | #define CPDMA_RXINTSTATMASKED 0xa4 | |
44 | #define CPDMA_RXINTMASKSET 0xa8 | |
45 | #define CPDMA_RXINTMASKCLEAR 0xac | |
46 | #define CPDMA_DMAINTSTATRAW 0xb0 | |
47 | #define CPDMA_DMAINTSTATMASKED 0xb4 | |
48 | #define CPDMA_DMAINTMASKSET 0xb8 | |
49 | #define CPDMA_DMAINTMASKCLEAR 0xbc | |
50 | #define CPDMA_DMAINT_HOSTERR BIT(1) | |
51 | ||
52 | /* the following exist only if has_ext_regs is set */ | |
53 | #define CPDMA_DMACONTROL 0x20 | |
54 | #define CPDMA_DMASTATUS 0x24 | |
55 | #define CPDMA_RXBUFFOFS 0x28 | |
56 | #define CPDMA_EM_CONTROL 0x2c | |
57 | ||
58 | /* Descriptor mode bits */ | |
59 | #define CPDMA_DESC_SOP BIT(31) | |
60 | #define CPDMA_DESC_EOP BIT(30) | |
61 | #define CPDMA_DESC_OWNER BIT(29) | |
62 | #define CPDMA_DESC_EOQ BIT(28) | |
63 | #define CPDMA_DESC_TD_COMPLETE BIT(27) | |
64 | #define CPDMA_DESC_PASS_CRC BIT(26) | |
f6e135c8 M |
65 | #define CPDMA_DESC_TO_PORT_EN BIT(20) |
66 | #define CPDMA_TO_PORT_SHIFT 16 | |
67 | #define CPDMA_DESC_PORT_MASK (BIT(18) | BIT(17) | BIT(16)) | |
28a19fe6 | 68 | #define CPDMA_DESC_CRC_LEN 4 |
ef8c2dab CC |
69 | |
70 | #define CPDMA_TEARDOWN_VALUE 0xfffffffc | |
71 | ||
8f32b909 IK |
72 | #define CPDMA_MAX_RLIM_CNT 16384 |
73 | ||
ef8c2dab CC |
74 | struct cpdma_desc { |
75 | /* hardware fields */ | |
76 | u32 hw_next; | |
77 | u32 hw_buffer; | |
78 | u32 hw_len; | |
79 | u32 hw_mode; | |
80 | /* software fields */ | |
81 | void *sw_token; | |
82 | u32 sw_buffer; | |
83 | u32 sw_len; | |
84 | }; | |
85 | ||
86 | struct cpdma_desc_pool { | |
c767db51 | 87 | phys_addr_t phys; |
84092996 | 88 | dma_addr_t hw_addr; |
ef8c2dab CC |
89 | void __iomem *iomap; /* ioremap map */ |
90 | void *cpumap; /* dma_alloc map */ | |
91 | int desc_size, mem_size; | |
aeec3021 | 92 | int num_desc; |
ef8c2dab | 93 | struct device *dev; |
742fb20f | 94 | struct gen_pool *gen_pool; |
ef8c2dab CC |
95 | }; |
96 | ||
97 | enum cpdma_state { | |
98 | CPDMA_STATE_IDLE, | |
99 | CPDMA_STATE_ACTIVE, | |
100 | CPDMA_STATE_TEARDOWN, | |
101 | }; | |
102 | ||
ef8c2dab CC |
103 | struct cpdma_ctlr { |
104 | enum cpdma_state state; | |
105 | struct cpdma_params params; | |
106 | struct device *dev; | |
107 | struct cpdma_desc_pool *pool; | |
108 | spinlock_t lock; | |
109 | struct cpdma_chan *channels[2 * CPDMA_MAX_CHANNELS]; | |
3802dce1 | 110 | int chan_num; |
ef8c2dab CC |
111 | }; |
112 | ||
113 | struct cpdma_chan { | |
fae50823 M |
114 | struct cpdma_desc __iomem *head, *tail; |
115 | void __iomem *hdp, *cp, *rxfree; | |
ef8c2dab CC |
116 | enum cpdma_state state; |
117 | struct cpdma_ctlr *ctlr; | |
118 | int chan_num; | |
119 | spinlock_t lock; | |
ef8c2dab | 120 | int count; |
742fb20f | 121 | u32 desc_num; |
ef8c2dab CC |
122 | u32 mask; |
123 | cpdma_handler_fn handler; | |
124 | enum dma_data_direction dir; | |
125 | struct cpdma_chan_stats stats; | |
126 | /* offsets into dmaregs */ | |
127 | int int_set, int_clear, td; | |
0fc6432c | 128 | int weight; |
8f32b909 IK |
129 | u32 rate_factor; |
130 | u32 rate; | |
ef8c2dab CC |
131 | }; |
132 | ||
991ddb1f IK |
133 | struct cpdma_control_info { |
134 | u32 reg; | |
135 | u32 shift, mask; | |
136 | int access; | |
137 | #define ACCESS_RO BIT(0) | |
138 | #define ACCESS_WO BIT(1) | |
139 | #define ACCESS_RW (ACCESS_RO | ACCESS_WO) | |
140 | }; | |
141 | ||
142 | static struct cpdma_control_info controls[] = { | |
8f32b909 | 143 | [CPDMA_TX_RLIM] = {CPDMA_DMACONTROL, 8, 0xffff, ACCESS_RW}, |
991ddb1f IK |
144 | [CPDMA_CMD_IDLE] = {CPDMA_DMACONTROL, 3, 1, ACCESS_WO}, |
145 | [CPDMA_COPY_ERROR_FRAMES] = {CPDMA_DMACONTROL, 4, 1, ACCESS_RW}, | |
146 | [CPDMA_RX_OFF_LEN_UPDATE] = {CPDMA_DMACONTROL, 2, 1, ACCESS_RW}, | |
147 | [CPDMA_RX_OWNERSHIP_FLIP] = {CPDMA_DMACONTROL, 1, 1, ACCESS_RW}, | |
148 | [CPDMA_TX_PRIO_FIXED] = {CPDMA_DMACONTROL, 0, 1, ACCESS_RW}, | |
149 | [CPDMA_STAT_IDLE] = {CPDMA_DMASTATUS, 31, 1, ACCESS_RO}, | |
150 | [CPDMA_STAT_TX_ERR_CODE] = {CPDMA_DMASTATUS, 20, 0xf, ACCESS_RW}, | |
151 | [CPDMA_STAT_TX_ERR_CHAN] = {CPDMA_DMASTATUS, 16, 0x7, ACCESS_RW}, | |
152 | [CPDMA_STAT_RX_ERR_CODE] = {CPDMA_DMASTATUS, 12, 0xf, ACCESS_RW}, | |
153 | [CPDMA_STAT_RX_ERR_CHAN] = {CPDMA_DMASTATUS, 8, 0x7, ACCESS_RW}, | |
154 | [CPDMA_RX_BUFFER_OFFSET] = {CPDMA_RXBUFFOFS, 0, 0xffff, ACCESS_RW}, | |
155 | }; | |
156 | ||
925d65e6 IK |
157 | #define tx_chan_num(chan) (chan) |
158 | #define rx_chan_num(chan) ((chan) + CPDMA_MAX_CHANNELS) | |
159 | #define is_rx_chan(chan) ((chan)->chan_num >= CPDMA_MAX_CHANNELS) | |
160 | #define is_tx_chan(chan) (!is_rx_chan(chan)) | |
161 | #define __chan_linear(chan_num) ((chan_num) & (CPDMA_MAX_CHANNELS - 1)) | |
162 | #define chan_linear(chan) __chan_linear((chan)->chan_num) | |
163 | ||
ef8c2dab CC |
164 | /* The following make access to common cpdma_ctlr params more readable */ |
165 | #define dmaregs params.dmaregs | |
166 | #define num_chan params.num_chan | |
167 | ||
168 | /* various accessors */ | |
a6c83ccf GS |
169 | #define dma_reg_read(ctlr, ofs) readl((ctlr)->dmaregs + (ofs)) |
170 | #define chan_read(chan, fld) readl((chan)->fld) | |
171 | #define desc_read(desc, fld) readl(&(desc)->fld) | |
172 | #define dma_reg_write(ctlr, ofs, v) writel(v, (ctlr)->dmaregs + (ofs)) | |
173 | #define chan_write(chan, fld, v) writel(v, (chan)->fld) | |
174 | #define desc_write(desc, fld, v) writel((u32)(v), &(desc)->fld) | |
ef8c2dab | 175 | |
f6e135c8 M |
176 | #define cpdma_desc_to_port(chan, mode, directed) \ |
177 | do { \ | |
178 | if (!is_rx_chan(chan) && ((directed == 1) || \ | |
179 | (directed == 2))) \ | |
180 | mode |= (CPDMA_DESC_TO_PORT_EN | \ | |
181 | (directed << CPDMA_TO_PORT_SHIFT)); \ | |
182 | } while (0) | |
183 | ||
5fcc40a9 | 184 | static void cpdma_desc_pool_destroy(struct cpdma_ctlr *ctlr) |
742fb20f | 185 | { |
5fcc40a9 GS |
186 | struct cpdma_desc_pool *pool = ctlr->pool; |
187 | ||
742fb20f GS |
188 | if (!pool) |
189 | return; | |
190 | ||
aeec3021 GS |
191 | WARN(gen_pool_size(pool->gen_pool) != gen_pool_avail(pool->gen_pool), |
192 | "cpdma_desc_pool size %d != avail %d", | |
193 | gen_pool_size(pool->gen_pool), | |
194 | gen_pool_avail(pool->gen_pool)); | |
742fb20f | 195 | if (pool->cpumap) |
5fcc40a9 | 196 | dma_free_coherent(ctlr->dev, pool->mem_size, pool->cpumap, |
742fb20f | 197 | pool->phys); |
742fb20f GS |
198 | } |
199 | ||
ef8c2dab CC |
200 | /* |
201 | * Utility constructs for a cpdma descriptor pool. Some devices (e.g. davinci | |
202 | * emac) have dedicated on-chip memory for these descriptors. Some other | |
203 | * devices (e.g. cpsw switches) use plain old memory. Descriptor pools | |
204 | * abstract out these details | |
205 | */ | |
5fcc40a9 | 206 | int cpdma_desc_pool_create(struct cpdma_ctlr *ctlr) |
ef8c2dab | 207 | { |
5fcc40a9 | 208 | struct cpdma_params *cpdma_params = &ctlr->params; |
ef8c2dab | 209 | struct cpdma_desc_pool *pool; |
5fcc40a9 | 210 | int ret = -ENOMEM; |
ef8c2dab | 211 | |
5fcc40a9 | 212 | pool = devm_kzalloc(ctlr->dev, sizeof(*pool), GFP_KERNEL); |
ef8c2dab | 213 | if (!pool) |
742fb20f | 214 | goto gen_pool_create_fail; |
5fcc40a9 | 215 | ctlr->pool = pool; |
ef8c2dab | 216 | |
5fcc40a9 GS |
217 | pool->mem_size = cpdma_params->desc_mem_size; |
218 | pool->desc_size = ALIGN(sizeof(struct cpdma_desc), | |
219 | cpdma_params->desc_align); | |
220 | pool->num_desc = pool->mem_size / pool->desc_size; | |
ef8c2dab | 221 | |
5fcc40a9 GS |
222 | pool->gen_pool = devm_gen_pool_create(ctlr->dev, ilog2(pool->desc_size), |
223 | -1, "cpdma"); | |
742fb20f | 224 | if (IS_ERR(pool->gen_pool)) { |
5fcc40a9 GS |
225 | ret = PTR_ERR(pool->gen_pool); |
226 | dev_err(ctlr->dev, "pool create failed %d\n", ret); | |
742fb20f GS |
227 | goto gen_pool_create_fail; |
228 | } | |
ef8c2dab | 229 | |
5fcc40a9 GS |
230 | if (cpdma_params->desc_mem_phys) { |
231 | pool->phys = cpdma_params->desc_mem_phys; | |
7f3b490a GS |
232 | pool->iomap = devm_ioremap(ctlr->dev, pool->phys, |
233 | pool->mem_size); | |
5fcc40a9 | 234 | pool->hw_addr = cpdma_params->desc_hw_addr; |
ef8c2dab | 235 | } else { |
5fcc40a9 GS |
236 | pool->cpumap = dma_alloc_coherent(ctlr->dev, pool->mem_size, |
237 | &pool->hw_addr, GFP_KERNEL); | |
84092996 AB |
238 | pool->iomap = (void __iomem __force *)pool->cpumap; |
239 | pool->phys = pool->hw_addr; /* assumes no IOMMU, don't use this value */ | |
ef8c2dab CC |
240 | } |
241 | ||
742fb20f GS |
242 | if (!pool->iomap) |
243 | goto gen_pool_create_fail; | |
ef8c2dab | 244 | |
742fb20f GS |
245 | ret = gen_pool_add_virt(pool->gen_pool, (unsigned long)pool->iomap, |
246 | pool->phys, pool->mem_size, -1); | |
247 | if (ret < 0) { | |
5fcc40a9 | 248 | dev_err(ctlr->dev, "pool add failed %d\n", ret); |
742fb20f | 249 | goto gen_pool_add_virt_fail; |
ef8c2dab | 250 | } |
742fb20f | 251 | |
5fcc40a9 | 252 | return 0; |
742fb20f GS |
253 | |
254 | gen_pool_add_virt_fail: | |
5fcc40a9 | 255 | cpdma_desc_pool_destroy(ctlr); |
742fb20f | 256 | gen_pool_create_fail: |
5fcc40a9 GS |
257 | ctlr->pool = NULL; |
258 | return ret; | |
ef8c2dab CC |
259 | } |
260 | ||
261 | static inline dma_addr_t desc_phys(struct cpdma_desc_pool *pool, | |
262 | struct cpdma_desc __iomem *desc) | |
263 | { | |
264 | if (!desc) | |
265 | return 0; | |
c767db51 | 266 | return pool->hw_addr + (__force long)desc - (__force long)pool->iomap; |
ef8c2dab CC |
267 | } |
268 | ||
269 | static inline struct cpdma_desc __iomem * | |
270 | desc_from_phys(struct cpdma_desc_pool *pool, dma_addr_t dma) | |
271 | { | |
6a1fef6d | 272 | return dma ? pool->iomap + dma - pool->hw_addr : NULL; |
ef8c2dab CC |
273 | } |
274 | ||
275 | static struct cpdma_desc __iomem * | |
742fb20f | 276 | cpdma_desc_alloc(struct cpdma_desc_pool *pool) |
ef8c2dab | 277 | { |
aeec3021 GS |
278 | return (struct cpdma_desc __iomem *) |
279 | gen_pool_alloc(pool->gen_pool, pool->desc_size); | |
ef8c2dab CC |
280 | } |
281 | ||
282 | static void cpdma_desc_free(struct cpdma_desc_pool *pool, | |
283 | struct cpdma_desc __iomem *desc, int num_desc) | |
284 | { | |
742fb20f | 285 | gen_pool_free(pool->gen_pool, (unsigned long)desc, pool->desc_size); |
ef8c2dab CC |
286 | } |
287 | ||
991ddb1f IK |
288 | static int _cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value) |
289 | { | |
290 | struct cpdma_control_info *info = &controls[control]; | |
291 | u32 val; | |
292 | ||
293 | if (!ctlr->params.has_ext_regs) | |
294 | return -ENOTSUPP; | |
295 | ||
296 | if (ctlr->state != CPDMA_STATE_ACTIVE) | |
297 | return -EINVAL; | |
298 | ||
299 | if (control < 0 || control >= ARRAY_SIZE(controls)) | |
300 | return -ENOENT; | |
301 | ||
302 | if ((info->access & ACCESS_WO) != ACCESS_WO) | |
303 | return -EPERM; | |
304 | ||
305 | val = dma_reg_read(ctlr, info->reg); | |
306 | val &= ~(info->mask << info->shift); | |
307 | val |= (value & info->mask) << info->shift; | |
308 | dma_reg_write(ctlr, info->reg, val); | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
8f32b909 IK |
313 | static int _cpdma_control_get(struct cpdma_ctlr *ctlr, int control) |
314 | { | |
315 | struct cpdma_control_info *info = &controls[control]; | |
316 | int ret; | |
317 | ||
318 | if (!ctlr->params.has_ext_regs) | |
319 | return -ENOTSUPP; | |
320 | ||
321 | if (ctlr->state != CPDMA_STATE_ACTIVE) | |
322 | return -EINVAL; | |
323 | ||
324 | if (control < 0 || control >= ARRAY_SIZE(controls)) | |
325 | return -ENOENT; | |
326 | ||
327 | if ((info->access & ACCESS_RO) != ACCESS_RO) | |
328 | return -EPERM; | |
329 | ||
330 | ret = (dma_reg_read(ctlr, info->reg) >> info->shift) & info->mask; | |
331 | return ret; | |
332 | } | |
333 | ||
334 | /* cpdma_chan_set_chan_shaper - set shaper for a channel | |
335 | * Has to be called under ctlr lock | |
336 | */ | |
337 | static int cpdma_chan_set_chan_shaper(struct cpdma_chan *chan) | |
338 | { | |
339 | struct cpdma_ctlr *ctlr = chan->ctlr; | |
340 | u32 rate_reg; | |
341 | u32 rmask; | |
342 | int ret; | |
343 | ||
344 | if (!chan->rate) | |
345 | return 0; | |
346 | ||
347 | rate_reg = CPDMA_TX_PRI0_RATE + 4 * chan->chan_num; | |
348 | dma_reg_write(ctlr, rate_reg, chan->rate_factor); | |
349 | ||
350 | rmask = _cpdma_control_get(ctlr, CPDMA_TX_RLIM); | |
351 | rmask |= chan->mask; | |
352 | ||
353 | ret = _cpdma_control_set(ctlr, CPDMA_TX_RLIM, rmask); | |
354 | return ret; | |
355 | } | |
356 | ||
357 | static int cpdma_chan_on(struct cpdma_chan *chan) | |
358 | { | |
359 | struct cpdma_ctlr *ctlr = chan->ctlr; | |
360 | struct cpdma_desc_pool *pool = ctlr->pool; | |
361 | unsigned long flags; | |
362 | ||
363 | spin_lock_irqsave(&chan->lock, flags); | |
364 | if (chan->state != CPDMA_STATE_IDLE) { | |
365 | spin_unlock_irqrestore(&chan->lock, flags); | |
366 | return -EBUSY; | |
367 | } | |
368 | if (ctlr->state != CPDMA_STATE_ACTIVE) { | |
369 | spin_unlock_irqrestore(&chan->lock, flags); | |
370 | return -EINVAL; | |
371 | } | |
372 | dma_reg_write(ctlr, chan->int_set, chan->mask); | |
373 | chan->state = CPDMA_STATE_ACTIVE; | |
374 | if (chan->head) { | |
375 | chan_write(chan, hdp, desc_phys(pool, chan->head)); | |
376 | if (chan->rxfree) | |
377 | chan_write(chan, rxfree, chan->count); | |
378 | } | |
379 | ||
380 | spin_unlock_irqrestore(&chan->lock, flags); | |
381 | return 0; | |
382 | } | |
383 | ||
384 | /* cpdma_chan_fit_rate - set rate for a channel and check if it's possible. | |
385 | * rmask - mask of rate limited channels | |
386 | * Returns min rate in Kb/s | |
387 | */ | |
388 | static int cpdma_chan_fit_rate(struct cpdma_chan *ch, u32 rate, | |
389 | u32 *rmask, int *prio_mode) | |
390 | { | |
391 | struct cpdma_ctlr *ctlr = ch->ctlr; | |
392 | struct cpdma_chan *chan; | |
393 | u32 old_rate = ch->rate; | |
394 | u32 new_rmask = 0; | |
395 | int rlim = 1; | |
396 | int i; | |
397 | ||
398 | *prio_mode = 0; | |
399 | for (i = tx_chan_num(0); i < tx_chan_num(CPDMA_MAX_CHANNELS); i++) { | |
400 | chan = ctlr->channels[i]; | |
401 | if (!chan) { | |
402 | rlim = 0; | |
403 | continue; | |
404 | } | |
405 | ||
406 | if (chan == ch) | |
407 | chan->rate = rate; | |
408 | ||
409 | if (chan->rate) { | |
410 | if (rlim) { | |
411 | new_rmask |= chan->mask; | |
412 | } else { | |
413 | ch->rate = old_rate; | |
414 | dev_err(ctlr->dev, "Prev channel of %dch is not rate limited\n", | |
415 | chan->chan_num); | |
416 | return -EINVAL; | |
417 | } | |
418 | } else { | |
419 | *prio_mode = 1; | |
420 | rlim = 0; | |
421 | } | |
422 | } | |
423 | ||
424 | *rmask = new_rmask; | |
425 | return 0; | |
426 | } | |
427 | ||
428 | static u32 cpdma_chan_set_factors(struct cpdma_ctlr *ctlr, | |
429 | struct cpdma_chan *ch) | |
430 | { | |
431 | u32 delta = UINT_MAX, prev_delta = UINT_MAX, best_delta = UINT_MAX; | |
432 | u32 best_send_cnt = 0, best_idle_cnt = 0; | |
433 | u32 new_rate, best_rate = 0, rate_reg; | |
434 | u64 send_cnt, idle_cnt; | |
435 | u32 min_send_cnt, freq; | |
436 | u64 divident, divisor; | |
437 | ||
438 | if (!ch->rate) { | |
439 | ch->rate_factor = 0; | |
440 | goto set_factor; | |
441 | } | |
442 | ||
443 | freq = ctlr->params.bus_freq_mhz * 1000 * 32; | |
444 | if (!freq) { | |
445 | dev_err(ctlr->dev, "The bus frequency is not set\n"); | |
446 | return -EINVAL; | |
447 | } | |
448 | ||
449 | min_send_cnt = freq - ch->rate; | |
450 | send_cnt = DIV_ROUND_UP(min_send_cnt, ch->rate); | |
451 | while (send_cnt <= CPDMA_MAX_RLIM_CNT) { | |
452 | divident = ch->rate * send_cnt; | |
453 | divisor = min_send_cnt; | |
454 | idle_cnt = DIV_ROUND_CLOSEST_ULL(divident, divisor); | |
455 | ||
456 | divident = freq * idle_cnt; | |
457 | divisor = idle_cnt + send_cnt; | |
458 | new_rate = DIV_ROUND_CLOSEST_ULL(divident, divisor); | |
459 | ||
460 | delta = new_rate >= ch->rate ? new_rate - ch->rate : delta; | |
461 | if (delta < best_delta) { | |
462 | best_delta = delta; | |
463 | best_send_cnt = send_cnt; | |
464 | best_idle_cnt = idle_cnt; | |
465 | best_rate = new_rate; | |
466 | ||
467 | if (!delta) | |
468 | break; | |
469 | } | |
470 | ||
471 | if (prev_delta >= delta) { | |
472 | prev_delta = delta; | |
473 | send_cnt++; | |
474 | continue; | |
475 | } | |
476 | ||
477 | idle_cnt++; | |
478 | divident = freq * idle_cnt; | |
479 | send_cnt = DIV_ROUND_CLOSEST_ULL(divident, ch->rate); | |
480 | send_cnt -= idle_cnt; | |
481 | prev_delta = UINT_MAX; | |
482 | } | |
483 | ||
484 | ch->rate = best_rate; | |
485 | ch->rate_factor = best_send_cnt | (best_idle_cnt << 16); | |
486 | ||
487 | set_factor: | |
488 | rate_reg = CPDMA_TX_PRI0_RATE + 4 * ch->chan_num; | |
489 | dma_reg_write(ctlr, rate_reg, ch->rate_factor); | |
490 | return 0; | |
491 | } | |
492 | ||
ef8c2dab CC |
493 | struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params) |
494 | { | |
495 | struct cpdma_ctlr *ctlr; | |
496 | ||
e1943128 | 497 | ctlr = devm_kzalloc(params->dev, sizeof(*ctlr), GFP_KERNEL); |
ef8c2dab CC |
498 | if (!ctlr) |
499 | return NULL; | |
500 | ||
501 | ctlr->state = CPDMA_STATE_IDLE; | |
502 | ctlr->params = *params; | |
503 | ctlr->dev = params->dev; | |
3802dce1 | 504 | ctlr->chan_num = 0; |
ef8c2dab CC |
505 | spin_lock_init(&ctlr->lock); |
506 | ||
5fcc40a9 | 507 | if (cpdma_desc_pool_create(ctlr)) |
ef8c2dab | 508 | return NULL; |
ef8c2dab CC |
509 | |
510 | if (WARN_ON(ctlr->num_chan > CPDMA_MAX_CHANNELS)) | |
511 | ctlr->num_chan = CPDMA_MAX_CHANNELS; | |
512 | return ctlr; | |
513 | } | |
32a6d90b | 514 | EXPORT_SYMBOL_GPL(cpdma_ctlr_create); |
ef8c2dab CC |
515 | |
516 | int cpdma_ctlr_start(struct cpdma_ctlr *ctlr) | |
517 | { | |
8f32b909 | 518 | struct cpdma_chan *chan; |
ef8c2dab | 519 | unsigned long flags; |
8f32b909 | 520 | int i, prio_mode; |
ef8c2dab CC |
521 | |
522 | spin_lock_irqsave(&ctlr->lock, flags); | |
523 | if (ctlr->state != CPDMA_STATE_IDLE) { | |
524 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
525 | return -EBUSY; | |
526 | } | |
527 | ||
528 | if (ctlr->params.has_soft_reset) { | |
817f6d1a | 529 | unsigned timeout = 10 * 100; |
ef8c2dab CC |
530 | |
531 | dma_reg_write(ctlr, CPDMA_SOFTRESET, 1); | |
817f6d1a | 532 | while (timeout) { |
ef8c2dab CC |
533 | if (dma_reg_read(ctlr, CPDMA_SOFTRESET) == 0) |
534 | break; | |
817f6d1a SS |
535 | udelay(10); |
536 | timeout--; | |
ef8c2dab | 537 | } |
817f6d1a | 538 | WARN_ON(!timeout); |
ef8c2dab CC |
539 | } |
540 | ||
541 | for (i = 0; i < ctlr->num_chan; i++) { | |
a6c83ccf GS |
542 | writel(0, ctlr->params.txhdp + 4 * i); |
543 | writel(0, ctlr->params.rxhdp + 4 * i); | |
544 | writel(0, ctlr->params.txcp + 4 * i); | |
545 | writel(0, ctlr->params.rxcp + 4 * i); | |
ef8c2dab CC |
546 | } |
547 | ||
548 | dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff); | |
549 | dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff); | |
550 | ||
551 | dma_reg_write(ctlr, CPDMA_TXCONTROL, 1); | |
552 | dma_reg_write(ctlr, CPDMA_RXCONTROL, 1); | |
553 | ||
554 | ctlr->state = CPDMA_STATE_ACTIVE; | |
555 | ||
8f32b909 | 556 | prio_mode = 0; |
ef8c2dab | 557 | for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { |
8f32b909 IK |
558 | chan = ctlr->channels[i]; |
559 | if (chan) { | |
560 | cpdma_chan_set_chan_shaper(chan); | |
561 | cpdma_chan_on(chan); | |
562 | ||
563 | /* off prio mode if all tx channels are rate limited */ | |
564 | if (is_tx_chan(chan) && !chan->rate) | |
565 | prio_mode = 1; | |
566 | } | |
ef8c2dab | 567 | } |
991ddb1f | 568 | |
8f32b909 | 569 | _cpdma_control_set(ctlr, CPDMA_TX_PRIO_FIXED, prio_mode); |
991ddb1f IK |
570 | _cpdma_control_set(ctlr, CPDMA_RX_BUFFER_OFFSET, 0); |
571 | ||
ef8c2dab CC |
572 | spin_unlock_irqrestore(&ctlr->lock, flags); |
573 | return 0; | |
574 | } | |
32a6d90b | 575 | EXPORT_SYMBOL_GPL(cpdma_ctlr_start); |
ef8c2dab CC |
576 | |
577 | int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr) | |
578 | { | |
579 | unsigned long flags; | |
580 | int i; | |
581 | ||
582 | spin_lock_irqsave(&ctlr->lock, flags); | |
b993eec0 | 583 | if (ctlr->state != CPDMA_STATE_ACTIVE) { |
ef8c2dab CC |
584 | spin_unlock_irqrestore(&ctlr->lock, flags); |
585 | return -EINVAL; | |
586 | } | |
587 | ||
588 | ctlr->state = CPDMA_STATE_TEARDOWN; | |
080d5c5a | 589 | spin_unlock_irqrestore(&ctlr->lock, flags); |
ef8c2dab CC |
590 | |
591 | for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { | |
592 | if (ctlr->channels[i]) | |
593 | cpdma_chan_stop(ctlr->channels[i]); | |
594 | } | |
595 | ||
080d5c5a | 596 | spin_lock_irqsave(&ctlr->lock, flags); |
ef8c2dab CC |
597 | dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff); |
598 | dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff); | |
599 | ||
600 | dma_reg_write(ctlr, CPDMA_TXCONTROL, 0); | |
601 | dma_reg_write(ctlr, CPDMA_RXCONTROL, 0); | |
602 | ||
603 | ctlr->state = CPDMA_STATE_IDLE; | |
604 | ||
605 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
606 | return 0; | |
607 | } | |
32a6d90b | 608 | EXPORT_SYMBOL_GPL(cpdma_ctlr_stop); |
ef8c2dab | 609 | |
ef8c2dab CC |
610 | int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr) |
611 | { | |
ef8c2dab CC |
612 | int ret = 0, i; |
613 | ||
614 | if (!ctlr) | |
615 | return -EINVAL; | |
616 | ||
ef8c2dab CC |
617 | if (ctlr->state != CPDMA_STATE_IDLE) |
618 | cpdma_ctlr_stop(ctlr); | |
619 | ||
79876e03 CR |
620 | for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) |
621 | cpdma_chan_destroy(ctlr->channels[i]); | |
ef8c2dab | 622 | |
5fcc40a9 | 623 | cpdma_desc_pool_destroy(ctlr); |
ef8c2dab CC |
624 | return ret; |
625 | } | |
32a6d90b | 626 | EXPORT_SYMBOL_GPL(cpdma_ctlr_destroy); |
ef8c2dab CC |
627 | |
628 | int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable) | |
629 | { | |
630 | unsigned long flags; | |
631 | int i, reg; | |
632 | ||
633 | spin_lock_irqsave(&ctlr->lock, flags); | |
634 | if (ctlr->state != CPDMA_STATE_ACTIVE) { | |
635 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
636 | return -EINVAL; | |
637 | } | |
638 | ||
639 | reg = enable ? CPDMA_DMAINTMASKSET : CPDMA_DMAINTMASKCLEAR; | |
640 | dma_reg_write(ctlr, reg, CPDMA_DMAINT_HOSTERR); | |
641 | ||
642 | for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { | |
643 | if (ctlr->channels[i]) | |
644 | cpdma_chan_int_ctrl(ctlr->channels[i], enable); | |
645 | } | |
646 | ||
647 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
648 | return 0; | |
649 | } | |
6929e24e | 650 | EXPORT_SYMBOL_GPL(cpdma_ctlr_int_ctrl); |
ef8c2dab | 651 | |
510a1e72 | 652 | void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value) |
ef8c2dab | 653 | { |
510a1e72 | 654 | dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value); |
ef8c2dab | 655 | } |
6929e24e | 656 | EXPORT_SYMBOL_GPL(cpdma_ctlr_eoi); |
ef8c2dab | 657 | |
e05107e6 IK |
658 | u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr) |
659 | { | |
660 | return dma_reg_read(ctlr, CPDMA_RXINTSTATMASKED); | |
661 | } | |
662 | EXPORT_SYMBOL_GPL(cpdma_ctrl_rxchs_state); | |
663 | ||
664 | u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr) | |
665 | { | |
666 | return dma_reg_read(ctlr, CPDMA_TXINTSTATMASKED); | |
667 | } | |
668 | EXPORT_SYMBOL_GPL(cpdma_ctrl_txchs_state); | |
669 | ||
0fc6432c IK |
670 | static void cpdma_chan_set_descs(struct cpdma_ctlr *ctlr, |
671 | int rx, int desc_num, | |
672 | int per_ch_desc) | |
673 | { | |
674 | struct cpdma_chan *chan, *most_chan = NULL; | |
675 | int desc_cnt = desc_num; | |
676 | int most_dnum = 0; | |
677 | int min, max, i; | |
678 | ||
679 | if (!desc_num) | |
680 | return; | |
681 | ||
682 | if (rx) { | |
683 | min = rx_chan_num(0); | |
684 | max = rx_chan_num(CPDMA_MAX_CHANNELS); | |
685 | } else { | |
686 | min = tx_chan_num(0); | |
687 | max = tx_chan_num(CPDMA_MAX_CHANNELS); | |
688 | } | |
689 | ||
690 | for (i = min; i < max; i++) { | |
691 | chan = ctlr->channels[i]; | |
692 | if (!chan) | |
693 | continue; | |
694 | ||
695 | if (chan->weight) | |
696 | chan->desc_num = (chan->weight * desc_num) / 100; | |
697 | else | |
698 | chan->desc_num = per_ch_desc; | |
699 | ||
700 | desc_cnt -= chan->desc_num; | |
701 | ||
702 | if (most_dnum < chan->desc_num) { | |
703 | most_dnum = chan->desc_num; | |
704 | most_chan = chan; | |
705 | } | |
706 | } | |
707 | /* use remains */ | |
708 | most_chan->desc_num += desc_cnt; | |
709 | } | |
710 | ||
3802dce1 IK |
711 | /** |
712 | * cpdma_chan_split_pool - Splits ctrl pool between all channels. | |
713 | * Has to be called under ctlr lock | |
714 | */ | |
0fc6432c | 715 | static int cpdma_chan_split_pool(struct cpdma_ctlr *ctlr) |
3802dce1 | 716 | { |
0fc6432c | 717 | int tx_per_ch_desc = 0, rx_per_ch_desc = 0; |
3802dce1 | 718 | struct cpdma_desc_pool *pool = ctlr->pool; |
0fc6432c IK |
719 | int free_rx_num = 0, free_tx_num = 0; |
720 | int rx_weight = 0, tx_weight = 0; | |
721 | int tx_desc_num, rx_desc_num; | |
3802dce1 | 722 | struct cpdma_chan *chan; |
0fc6432c | 723 | int i, tx_num = 0; |
3802dce1 IK |
724 | |
725 | if (!ctlr->chan_num) | |
0fc6432c | 726 | return 0; |
3802dce1 | 727 | |
3802dce1 IK |
728 | for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { |
729 | chan = ctlr->channels[i]; | |
0fc6432c IK |
730 | if (!chan) |
731 | continue; | |
732 | ||
733 | if (is_rx_chan(chan)) { | |
734 | if (!chan->weight) | |
735 | free_rx_num++; | |
736 | rx_weight += chan->weight; | |
737 | } else { | |
738 | if (!chan->weight) | |
739 | free_tx_num++; | |
740 | tx_weight += chan->weight; | |
741 | tx_num++; | |
742 | } | |
743 | } | |
744 | ||
745 | if (rx_weight > 100 || tx_weight > 100) | |
746 | return -EINVAL; | |
747 | ||
748 | tx_desc_num = (tx_num * pool->num_desc) / ctlr->chan_num; | |
749 | rx_desc_num = pool->num_desc - tx_desc_num; | |
750 | ||
751 | if (free_tx_num) { | |
752 | tx_per_ch_desc = tx_desc_num - (tx_weight * tx_desc_num) / 100; | |
753 | tx_per_ch_desc /= free_tx_num; | |
754 | } | |
755 | if (free_rx_num) { | |
756 | rx_per_ch_desc = rx_desc_num - (rx_weight * rx_desc_num) / 100; | |
757 | rx_per_ch_desc /= free_rx_num; | |
3802dce1 | 758 | } |
0fc6432c IK |
759 | |
760 | cpdma_chan_set_descs(ctlr, 0, tx_desc_num, tx_per_ch_desc); | |
761 | cpdma_chan_set_descs(ctlr, 1, rx_desc_num, rx_per_ch_desc); | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
766 | /* cpdma_chan_set_weight - set weight of a channel in percentage. | |
767 | * Tx and Rx channels have separate weights. That is 100% for RX | |
768 | * and 100% for Tx. The weight is used to split cpdma resources | |
769 | * in correct proportion required by the channels, including number | |
770 | * of descriptors. The channel rate is not enough to know the | |
771 | * weight of a channel as the maximum rate of an interface is needed. | |
772 | * If weight = 0, then channel uses rest of descriptors leaved by | |
773 | * weighted channels. | |
774 | */ | |
775 | int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight) | |
776 | { | |
777 | struct cpdma_ctlr *ctlr = ch->ctlr; | |
778 | unsigned long flags, ch_flags; | |
779 | int ret; | |
780 | ||
781 | spin_lock_irqsave(&ctlr->lock, flags); | |
782 | spin_lock_irqsave(&ch->lock, ch_flags); | |
783 | if (ch->weight == weight) { | |
784 | spin_unlock_irqrestore(&ch->lock, ch_flags); | |
785 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
786 | return 0; | |
787 | } | |
788 | ch->weight = weight; | |
789 | spin_unlock_irqrestore(&ch->lock, ch_flags); | |
790 | ||
791 | /* re-split pool using new channel weight */ | |
792 | ret = cpdma_chan_split_pool(ctlr); | |
793 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
794 | return ret; | |
3802dce1 | 795 | } |
397c5ad1 | 796 | EXPORT_SYMBOL_GPL(cpdma_chan_set_weight); |
3802dce1 | 797 | |
8f32b909 IK |
798 | /* cpdma_chan_get_min_rate - get minimum allowed rate for channel |
799 | * Should be called before cpdma_chan_set_rate. | |
800 | * Returns min rate in Kb/s | |
801 | */ | |
802 | u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr) | |
803 | { | |
804 | unsigned int divident, divisor; | |
805 | ||
806 | divident = ctlr->params.bus_freq_mhz * 32 * 1000; | |
807 | divisor = 1 + CPDMA_MAX_RLIM_CNT; | |
808 | ||
809 | return DIV_ROUND_UP(divident, divisor); | |
810 | } | |
397c5ad1 | 811 | EXPORT_SYMBOL_GPL(cpdma_chan_get_min_rate); |
8f32b909 IK |
812 | |
813 | /* cpdma_chan_set_rate - limits bandwidth for transmit channel. | |
814 | * The bandwidth * limited channels have to be in order beginning from lowest. | |
815 | * ch - transmit channel the bandwidth is configured for | |
816 | * rate - bandwidth in Kb/s, if 0 - then off shaper | |
817 | */ | |
818 | int cpdma_chan_set_rate(struct cpdma_chan *ch, u32 rate) | |
819 | { | |
820 | struct cpdma_ctlr *ctlr = ch->ctlr; | |
821 | unsigned long flags, ch_flags; | |
822 | int ret, prio_mode; | |
823 | u32 rmask; | |
824 | ||
825 | if (!ch || !is_tx_chan(ch)) | |
826 | return -EINVAL; | |
827 | ||
828 | if (ch->rate == rate) | |
829 | return rate; | |
830 | ||
831 | spin_lock_irqsave(&ctlr->lock, flags); | |
832 | spin_lock_irqsave(&ch->lock, ch_flags); | |
833 | ||
834 | ret = cpdma_chan_fit_rate(ch, rate, &rmask, &prio_mode); | |
835 | if (ret) | |
836 | goto err; | |
837 | ||
838 | ret = cpdma_chan_set_factors(ctlr, ch); | |
839 | if (ret) | |
840 | goto err; | |
841 | ||
842 | spin_unlock_irqrestore(&ch->lock, ch_flags); | |
843 | ||
844 | /* on shapers */ | |
845 | _cpdma_control_set(ctlr, CPDMA_TX_RLIM, rmask); | |
846 | _cpdma_control_set(ctlr, CPDMA_TX_PRIO_FIXED, prio_mode); | |
847 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
848 | return ret; | |
849 | ||
850 | err: | |
851 | spin_unlock_irqrestore(&ch->lock, ch_flags); | |
852 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
853 | return ret; | |
854 | } | |
397c5ad1 | 855 | EXPORT_SYMBOL_GPL(cpdma_chan_set_rate); |
8f32b909 IK |
856 | |
857 | u32 cpdma_chan_get_rate(struct cpdma_chan *ch) | |
858 | { | |
859 | unsigned long flags; | |
860 | u32 rate; | |
861 | ||
862 | spin_lock_irqsave(&ch->lock, flags); | |
863 | rate = ch->rate; | |
864 | spin_unlock_irqrestore(&ch->lock, flags); | |
865 | ||
866 | return rate; | |
867 | } | |
397c5ad1 | 868 | EXPORT_SYMBOL_GPL(cpdma_chan_get_rate); |
8f32b909 | 869 | |
ef8c2dab | 870 | struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, |
925d65e6 | 871 | cpdma_handler_fn handler, int rx_type) |
ef8c2dab | 872 | { |
925d65e6 | 873 | int offset = chan_num * 4; |
ef8c2dab | 874 | struct cpdma_chan *chan; |
ef8c2dab CC |
875 | unsigned long flags; |
876 | ||
925d65e6 IK |
877 | chan_num = rx_type ? rx_chan_num(chan_num) : tx_chan_num(chan_num); |
878 | ||
ef8c2dab CC |
879 | if (__chan_linear(chan_num) >= ctlr->num_chan) |
880 | return NULL; | |
881 | ||
e1943128 | 882 | chan = devm_kzalloc(ctlr->dev, sizeof(*chan), GFP_KERNEL); |
ef8c2dab | 883 | if (!chan) |
e1943128 | 884 | return ERR_PTR(-ENOMEM); |
ef8c2dab CC |
885 | |
886 | spin_lock_irqsave(&ctlr->lock, flags); | |
e1943128 GC |
887 | if (ctlr->channels[chan_num]) { |
888 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
889 | devm_kfree(ctlr->dev, chan); | |
890 | return ERR_PTR(-EBUSY); | |
891 | } | |
ef8c2dab CC |
892 | |
893 | chan->ctlr = ctlr; | |
894 | chan->state = CPDMA_STATE_IDLE; | |
895 | chan->chan_num = chan_num; | |
896 | chan->handler = handler; | |
8f32b909 | 897 | chan->rate = 0; |
742fb20f | 898 | chan->desc_num = ctlr->pool->num_desc / 2; |
0fc6432c | 899 | chan->weight = 0; |
ef8c2dab CC |
900 | |
901 | if (is_rx_chan(chan)) { | |
902 | chan->hdp = ctlr->params.rxhdp + offset; | |
903 | chan->cp = ctlr->params.rxcp + offset; | |
904 | chan->rxfree = ctlr->params.rxfree + offset; | |
905 | chan->int_set = CPDMA_RXINTMASKSET; | |
906 | chan->int_clear = CPDMA_RXINTMASKCLEAR; | |
907 | chan->td = CPDMA_RXTEARDOWN; | |
908 | chan->dir = DMA_FROM_DEVICE; | |
909 | } else { | |
910 | chan->hdp = ctlr->params.txhdp + offset; | |
911 | chan->cp = ctlr->params.txcp + offset; | |
912 | chan->int_set = CPDMA_TXINTMASKSET; | |
913 | chan->int_clear = CPDMA_TXINTMASKCLEAR; | |
914 | chan->td = CPDMA_TXTEARDOWN; | |
915 | chan->dir = DMA_TO_DEVICE; | |
916 | } | |
917 | chan->mask = BIT(chan_linear(chan)); | |
918 | ||
919 | spin_lock_init(&chan->lock); | |
920 | ||
921 | ctlr->channels[chan_num] = chan; | |
3802dce1 IK |
922 | ctlr->chan_num++; |
923 | ||
924 | cpdma_chan_split_pool(ctlr); | |
925 | ||
ef8c2dab CC |
926 | spin_unlock_irqrestore(&ctlr->lock, flags); |
927 | return chan; | |
ef8c2dab | 928 | } |
32a6d90b | 929 | EXPORT_SYMBOL_GPL(cpdma_chan_create); |
ef8c2dab | 930 | |
3802dce1 | 931 | int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan) |
1793331e | 932 | { |
3802dce1 IK |
933 | unsigned long flags; |
934 | int desc_num; | |
935 | ||
936 | spin_lock_irqsave(&chan->lock, flags); | |
937 | desc_num = chan->desc_num; | |
938 | spin_unlock_irqrestore(&chan->lock, flags); | |
939 | ||
940 | return desc_num; | |
1793331e IK |
941 | } |
942 | EXPORT_SYMBOL_GPL(cpdma_chan_get_rx_buf_num); | |
943 | ||
ef8c2dab CC |
944 | int cpdma_chan_destroy(struct cpdma_chan *chan) |
945 | { | |
f37c54b6 | 946 | struct cpdma_ctlr *ctlr; |
ef8c2dab CC |
947 | unsigned long flags; |
948 | ||
949 | if (!chan) | |
950 | return -EINVAL; | |
f37c54b6 | 951 | ctlr = chan->ctlr; |
ef8c2dab CC |
952 | |
953 | spin_lock_irqsave(&ctlr->lock, flags); | |
954 | if (chan->state != CPDMA_STATE_IDLE) | |
955 | cpdma_chan_stop(chan); | |
956 | ctlr->channels[chan->chan_num] = NULL; | |
3802dce1 | 957 | ctlr->chan_num--; |
b602e491 | 958 | devm_kfree(ctlr->dev, chan); |
3802dce1 IK |
959 | cpdma_chan_split_pool(ctlr); |
960 | ||
ef8c2dab | 961 | spin_unlock_irqrestore(&ctlr->lock, flags); |
ef8c2dab CC |
962 | return 0; |
963 | } | |
32a6d90b | 964 | EXPORT_SYMBOL_GPL(cpdma_chan_destroy); |
ef8c2dab CC |
965 | |
966 | int cpdma_chan_get_stats(struct cpdma_chan *chan, | |
967 | struct cpdma_chan_stats *stats) | |
968 | { | |
969 | unsigned long flags; | |
970 | if (!chan) | |
971 | return -EINVAL; | |
972 | spin_lock_irqsave(&chan->lock, flags); | |
973 | memcpy(stats, &chan->stats, sizeof(*stats)); | |
974 | spin_unlock_irqrestore(&chan->lock, flags); | |
975 | return 0; | |
976 | } | |
0ca04b63 | 977 | EXPORT_SYMBOL_GPL(cpdma_chan_get_stats); |
ef8c2dab | 978 | |
ef8c2dab CC |
979 | static void __cpdma_chan_submit(struct cpdma_chan *chan, |
980 | struct cpdma_desc __iomem *desc) | |
981 | { | |
982 | struct cpdma_ctlr *ctlr = chan->ctlr; | |
983 | struct cpdma_desc __iomem *prev = chan->tail; | |
984 | struct cpdma_desc_pool *pool = ctlr->pool; | |
985 | dma_addr_t desc_dma; | |
986 | u32 mode; | |
987 | ||
988 | desc_dma = desc_phys(pool, desc); | |
989 | ||
990 | /* simple case - idle channel */ | |
991 | if (!chan->head) { | |
992 | chan->stats.head_enqueue++; | |
993 | chan->head = desc; | |
994 | chan->tail = desc; | |
995 | if (chan->state == CPDMA_STATE_ACTIVE) | |
996 | chan_write(chan, hdp, desc_dma); | |
997 | return; | |
998 | } | |
999 | ||
1000 | /* first chain the descriptor at the tail of the list */ | |
1001 | desc_write(prev, hw_next, desc_dma); | |
1002 | chan->tail = desc; | |
1003 | chan->stats.tail_enqueue++; | |
1004 | ||
1005 | /* next check if EOQ has been triggered already */ | |
1006 | mode = desc_read(prev, hw_mode); | |
1007 | if (((mode & (CPDMA_DESC_EOQ | CPDMA_DESC_OWNER)) == CPDMA_DESC_EOQ) && | |
1008 | (chan->state == CPDMA_STATE_ACTIVE)) { | |
1009 | desc_write(prev, hw_mode, mode & ~CPDMA_DESC_EOQ); | |
1010 | chan_write(chan, hdp, desc_dma); | |
1011 | chan->stats.misqueued++; | |
1012 | } | |
1013 | } | |
1014 | ||
1015 | int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data, | |
aef614e1 | 1016 | int len, int directed) |
ef8c2dab CC |
1017 | { |
1018 | struct cpdma_ctlr *ctlr = chan->ctlr; | |
1019 | struct cpdma_desc __iomem *desc; | |
1020 | dma_addr_t buffer; | |
1021 | unsigned long flags; | |
1022 | u32 mode; | |
1023 | int ret = 0; | |
1024 | ||
1025 | spin_lock_irqsave(&chan->lock, flags); | |
1026 | ||
1027 | if (chan->state == CPDMA_STATE_TEARDOWN) { | |
1028 | ret = -EINVAL; | |
1029 | goto unlock_ret; | |
1030 | } | |
1031 | ||
742fb20f GS |
1032 | if (chan->count >= chan->desc_num) { |
1033 | chan->stats.desc_alloc_fail++; | |
1034 | ret = -ENOMEM; | |
1035 | goto unlock_ret; | |
1036 | } | |
1037 | ||
1038 | desc = cpdma_desc_alloc(ctlr->pool); | |
ef8c2dab CC |
1039 | if (!desc) { |
1040 | chan->stats.desc_alloc_fail++; | |
1041 | ret = -ENOMEM; | |
1042 | goto unlock_ret; | |
1043 | } | |
1044 | ||
1045 | if (len < ctlr->params.min_packet_size) { | |
1046 | len = ctlr->params.min_packet_size; | |
1047 | chan->stats.runt_transmit_buff++; | |
1048 | } | |
1049 | ||
1050 | buffer = dma_map_single(ctlr->dev, data, len, chan->dir); | |
14bd0769 SS |
1051 | ret = dma_mapping_error(ctlr->dev, buffer); |
1052 | if (ret) { | |
1053 | cpdma_desc_free(ctlr->pool, desc, 1); | |
1054 | ret = -EINVAL; | |
1055 | goto unlock_ret; | |
1056 | } | |
1057 | ||
ef8c2dab | 1058 | mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP; |
f6e135c8 | 1059 | cpdma_desc_to_port(chan, mode, directed); |
ef8c2dab | 1060 | |
a6c83ccf GS |
1061 | /* Relaxed IO accessors can be used here as there is read barrier |
1062 | * at the end of write sequence. | |
1063 | */ | |
1064 | writel_relaxed(0, &desc->hw_next); | |
1065 | writel_relaxed(buffer, &desc->hw_buffer); | |
1066 | writel_relaxed(len, &desc->hw_len); | |
1067 | writel_relaxed(mode | len, &desc->hw_mode); | |
1068 | writel_relaxed(token, &desc->sw_token); | |
1069 | writel_relaxed(buffer, &desc->sw_buffer); | |
1070 | writel_relaxed(len, &desc->sw_len); | |
1071 | desc_read(desc, sw_len); | |
ef8c2dab CC |
1072 | |
1073 | __cpdma_chan_submit(chan, desc); | |
1074 | ||
1075 | if (chan->state == CPDMA_STATE_ACTIVE && chan->rxfree) | |
1076 | chan_write(chan, rxfree, 1); | |
1077 | ||
1078 | chan->count++; | |
1079 | ||
1080 | unlock_ret: | |
1081 | spin_unlock_irqrestore(&chan->lock, flags); | |
1082 | return ret; | |
1083 | } | |
32a6d90b | 1084 | EXPORT_SYMBOL_GPL(cpdma_chan_submit); |
ef8c2dab | 1085 | |
fae50823 M |
1086 | bool cpdma_check_free_tx_desc(struct cpdma_chan *chan) |
1087 | { | |
fae50823 M |
1088 | struct cpdma_ctlr *ctlr = chan->ctlr; |
1089 | struct cpdma_desc_pool *pool = ctlr->pool; | |
742fb20f GS |
1090 | bool free_tx_desc; |
1091 | unsigned long flags; | |
fae50823 | 1092 | |
742fb20f GS |
1093 | spin_lock_irqsave(&chan->lock, flags); |
1094 | free_tx_desc = (chan->count < chan->desc_num) && | |
1095 | gen_pool_avail(pool->gen_pool); | |
1096 | spin_unlock_irqrestore(&chan->lock, flags); | |
1097 | return free_tx_desc; | |
fae50823 M |
1098 | } |
1099 | EXPORT_SYMBOL_GPL(cpdma_check_free_tx_desc); | |
1100 | ||
ef8c2dab CC |
1101 | static void __cpdma_chan_free(struct cpdma_chan *chan, |
1102 | struct cpdma_desc __iomem *desc, | |
1103 | int outlen, int status) | |
1104 | { | |
1105 | struct cpdma_ctlr *ctlr = chan->ctlr; | |
1106 | struct cpdma_desc_pool *pool = ctlr->pool; | |
1107 | dma_addr_t buff_dma; | |
1108 | int origlen; | |
1109 | void *token; | |
1110 | ||
1111 | token = (void *)desc_read(desc, sw_token); | |
1112 | buff_dma = desc_read(desc, sw_buffer); | |
1113 | origlen = desc_read(desc, sw_len); | |
1114 | ||
1115 | dma_unmap_single(ctlr->dev, buff_dma, origlen, chan->dir); | |
1116 | cpdma_desc_free(pool, desc, 1); | |
1117 | (*chan->handler)(token, outlen, status); | |
1118 | } | |
1119 | ||
1120 | static int __cpdma_chan_process(struct cpdma_chan *chan) | |
1121 | { | |
1122 | struct cpdma_ctlr *ctlr = chan->ctlr; | |
1123 | struct cpdma_desc __iomem *desc; | |
1124 | int status, outlen; | |
b4727e69 | 1125 | int cb_status = 0; |
ef8c2dab CC |
1126 | struct cpdma_desc_pool *pool = ctlr->pool; |
1127 | dma_addr_t desc_dma; | |
1128 | unsigned long flags; | |
1129 | ||
1130 | spin_lock_irqsave(&chan->lock, flags); | |
1131 | ||
1132 | desc = chan->head; | |
1133 | if (!desc) { | |
1134 | chan->stats.empty_dequeue++; | |
1135 | status = -ENOENT; | |
1136 | goto unlock_ret; | |
1137 | } | |
1138 | desc_dma = desc_phys(pool, desc); | |
1139 | ||
a6c83ccf | 1140 | status = desc_read(desc, hw_mode); |
ef8c2dab CC |
1141 | outlen = status & 0x7ff; |
1142 | if (status & CPDMA_DESC_OWNER) { | |
1143 | chan->stats.busy_dequeue++; | |
1144 | status = -EBUSY; | |
1145 | goto unlock_ret; | |
1146 | } | |
28a19fe6 M |
1147 | |
1148 | if (status & CPDMA_DESC_PASS_CRC) | |
1149 | outlen -= CPDMA_DESC_CRC_LEN; | |
1150 | ||
f6e135c8 M |
1151 | status = status & (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE | |
1152 | CPDMA_DESC_PORT_MASK); | |
ef8c2dab CC |
1153 | |
1154 | chan->head = desc_from_phys(pool, desc_read(desc, hw_next)); | |
1155 | chan_write(chan, cp, desc_dma); | |
1156 | chan->count--; | |
1157 | chan->stats.good_dequeue++; | |
1158 | ||
12a303e3 | 1159 | if ((status & CPDMA_DESC_EOQ) && chan->head) { |
ef8c2dab CC |
1160 | chan->stats.requeue++; |
1161 | chan_write(chan, hdp, desc_phys(pool, chan->head)); | |
1162 | } | |
1163 | ||
1164 | spin_unlock_irqrestore(&chan->lock, flags); | |
b4727e69 SS |
1165 | if (unlikely(status & CPDMA_DESC_TD_COMPLETE)) |
1166 | cb_status = -ENOSYS; | |
1167 | else | |
1168 | cb_status = status; | |
ef8c2dab | 1169 | |
b4727e69 | 1170 | __cpdma_chan_free(chan, desc, outlen, cb_status); |
ef8c2dab CC |
1171 | return status; |
1172 | ||
1173 | unlock_ret: | |
1174 | spin_unlock_irqrestore(&chan->lock, flags); | |
1175 | return status; | |
1176 | } | |
1177 | ||
1178 | int cpdma_chan_process(struct cpdma_chan *chan, int quota) | |
1179 | { | |
1180 | int used = 0, ret = 0; | |
1181 | ||
1182 | if (chan->state != CPDMA_STATE_ACTIVE) | |
1183 | return -EINVAL; | |
1184 | ||
1185 | while (used < quota) { | |
1186 | ret = __cpdma_chan_process(chan); | |
1187 | if (ret < 0) | |
1188 | break; | |
1189 | used++; | |
1190 | } | |
1191 | return used; | |
1192 | } | |
32a6d90b | 1193 | EXPORT_SYMBOL_GPL(cpdma_chan_process); |
ef8c2dab CC |
1194 | |
1195 | int cpdma_chan_start(struct cpdma_chan *chan) | |
1196 | { | |
8f32b909 IK |
1197 | struct cpdma_ctlr *ctlr = chan->ctlr; |
1198 | unsigned long flags; | |
1199 | int ret; | |
ef8c2dab | 1200 | |
8f32b909 IK |
1201 | spin_lock_irqsave(&ctlr->lock, flags); |
1202 | ret = cpdma_chan_set_chan_shaper(chan); | |
1203 | spin_unlock_irqrestore(&ctlr->lock, flags); | |
1204 | if (ret) | |
1205 | return ret; | |
1206 | ||
1207 | ret = cpdma_chan_on(chan); | |
1208 | if (ret) | |
1209 | return ret; | |
ef8c2dab | 1210 | |
ef8c2dab CC |
1211 | return 0; |
1212 | } | |
32a6d90b | 1213 | EXPORT_SYMBOL_GPL(cpdma_chan_start); |
ef8c2dab CC |
1214 | |
1215 | int cpdma_chan_stop(struct cpdma_chan *chan) | |
1216 | { | |
1217 | struct cpdma_ctlr *ctlr = chan->ctlr; | |
1218 | struct cpdma_desc_pool *pool = ctlr->pool; | |
1219 | unsigned long flags; | |
1220 | int ret; | |
817f6d1a | 1221 | unsigned timeout; |
ef8c2dab CC |
1222 | |
1223 | spin_lock_irqsave(&chan->lock, flags); | |
cd11cf50 | 1224 | if (chan->state == CPDMA_STATE_TEARDOWN) { |
ef8c2dab CC |
1225 | spin_unlock_irqrestore(&chan->lock, flags); |
1226 | return -EINVAL; | |
1227 | } | |
1228 | ||
1229 | chan->state = CPDMA_STATE_TEARDOWN; | |
1230 | dma_reg_write(ctlr, chan->int_clear, chan->mask); | |
1231 | ||
1232 | /* trigger teardown */ | |
b4ad0428 | 1233 | dma_reg_write(ctlr, chan->td, chan_linear(chan)); |
ef8c2dab CC |
1234 | |
1235 | /* wait for teardown complete */ | |
817f6d1a SS |
1236 | timeout = 100 * 100; /* 100 ms */ |
1237 | while (timeout) { | |
ef8c2dab CC |
1238 | u32 cp = chan_read(chan, cp); |
1239 | if ((cp & CPDMA_TEARDOWN_VALUE) == CPDMA_TEARDOWN_VALUE) | |
1240 | break; | |
817f6d1a SS |
1241 | udelay(10); |
1242 | timeout--; | |
ef8c2dab | 1243 | } |
817f6d1a | 1244 | WARN_ON(!timeout); |
ef8c2dab CC |
1245 | chan_write(chan, cp, CPDMA_TEARDOWN_VALUE); |
1246 | ||
1247 | /* handle completed packets */ | |
7746ab0a | 1248 | spin_unlock_irqrestore(&chan->lock, flags); |
ef8c2dab CC |
1249 | do { |
1250 | ret = __cpdma_chan_process(chan); | |
1251 | if (ret < 0) | |
1252 | break; | |
1253 | } while ((ret & CPDMA_DESC_TD_COMPLETE) == 0); | |
7746ab0a | 1254 | spin_lock_irqsave(&chan->lock, flags); |
ef8c2dab CC |
1255 | |
1256 | /* remaining packets haven't been tx/rx'ed, clean them up */ | |
1257 | while (chan->head) { | |
1258 | struct cpdma_desc __iomem *desc = chan->head; | |
1259 | dma_addr_t next_dma; | |
1260 | ||
1261 | next_dma = desc_read(desc, hw_next); | |
1262 | chan->head = desc_from_phys(pool, next_dma); | |
ffb5ba90 | 1263 | chan->count--; |
ef8c2dab CC |
1264 | chan->stats.teardown_dequeue++; |
1265 | ||
1266 | /* issue callback without locks held */ | |
1267 | spin_unlock_irqrestore(&chan->lock, flags); | |
1268 | __cpdma_chan_free(chan, desc, 0, -ENOSYS); | |
1269 | spin_lock_irqsave(&chan->lock, flags); | |
1270 | } | |
1271 | ||
1272 | chan->state = CPDMA_STATE_IDLE; | |
1273 | spin_unlock_irqrestore(&chan->lock, flags); | |
1274 | return 0; | |
1275 | } | |
32a6d90b | 1276 | EXPORT_SYMBOL_GPL(cpdma_chan_stop); |
ef8c2dab CC |
1277 | |
1278 | int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable) | |
1279 | { | |
1280 | unsigned long flags; | |
1281 | ||
1282 | spin_lock_irqsave(&chan->lock, flags); | |
1283 | if (chan->state != CPDMA_STATE_ACTIVE) { | |
1284 | spin_unlock_irqrestore(&chan->lock, flags); | |
1285 | return -EINVAL; | |
1286 | } | |
1287 | ||
1288 | dma_reg_write(chan->ctlr, enable ? chan->int_set : chan->int_clear, | |
1289 | chan->mask); | |
1290 | spin_unlock_irqrestore(&chan->lock, flags); | |
1291 | ||
1292 | return 0; | |
1293 | } | |
1294 | ||
ef8c2dab CC |
1295 | int cpdma_control_get(struct cpdma_ctlr *ctlr, int control) |
1296 | { | |
1297 | unsigned long flags; | |
ef8c2dab CC |
1298 | int ret; |
1299 | ||
1300 | spin_lock_irqsave(&ctlr->lock, flags); | |
8f32b909 | 1301 | ret = _cpdma_control_get(ctlr, control); |
ef8c2dab | 1302 | spin_unlock_irqrestore(&ctlr->lock, flags); |
8f32b909 | 1303 | |
ef8c2dab CC |
1304 | return ret; |
1305 | } | |
1306 | ||
1307 | int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value) | |
1308 | { | |
1309 | unsigned long flags; | |
ef8c2dab | 1310 | int ret; |
ef8c2dab CC |
1311 | |
1312 | spin_lock_irqsave(&ctlr->lock, flags); | |
991ddb1f | 1313 | ret = _cpdma_control_set(ctlr, control, value); |
ef8c2dab | 1314 | spin_unlock_irqrestore(&ctlr->lock, flags); |
8f32b909 | 1315 | |
ef8c2dab CC |
1316 | return ret; |
1317 | } | |
6929e24e | 1318 | EXPORT_SYMBOL_GPL(cpdma_control_set); |
4bc21d41 SS |
1319 | |
1320 | MODULE_LICENSE("GPL"); |