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net: ethernet: ti: davinci_cpdma: fix locking while ctrl_stop
[linux-2.6-block.git] / drivers / net / ethernet / ti / davinci_cpdma.c
CommitLineData
ef8c2dab
CC		 1/*
2 * Texas Instruments CPDMA Driver
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/spinlock.h>
17#include <linux/device.h>
76fbc247 18#include <linux/module.h>
ef8c2dab
CC		 19#include <linux/slab.h>
20#include <linux/err.h>
21#include <linux/dma-mapping.h>
22#include <linux/io.h>
817f6d1a 23#include <linux/delay.h>
742fb20f 24#include <linux/genalloc.h>
ef8c2dab
CC		 25#include "davinci_cpdma.h"
26
27/* DMA Registers */
28#define CPDMA_TXIDVER 0x00
29#define CPDMA_TXCONTROL 0x04
30#define CPDMA_TXTEARDOWN 0x08
31#define CPDMA_RXIDVER 0x10
32#define CPDMA_RXCONTROL 0x14
33#define CPDMA_SOFTRESET 0x1c
34#define CPDMA_RXTEARDOWN 0x18
35#define CPDMA_TXINTSTATRAW 0x80
36#define CPDMA_TXINTSTATMASKED 0x84
37#define CPDMA_TXINTMASKSET 0x88
38#define CPDMA_TXINTMASKCLEAR 0x8c
39#define CPDMA_MACINVECTOR 0x90
40#define CPDMA_MACEOIVECTOR 0x94
41#define CPDMA_RXINTSTATRAW 0xa0
42#define CPDMA_RXINTSTATMASKED 0xa4
43#define CPDMA_RXINTMASKSET 0xa8
44#define CPDMA_RXINTMASKCLEAR 0xac
45#define CPDMA_DMAINTSTATRAW 0xb0
46#define CPDMA_DMAINTSTATMASKED 0xb4
47#define CPDMA_DMAINTMASKSET 0xb8
48#define CPDMA_DMAINTMASKCLEAR 0xbc
49#define CPDMA_DMAINT_HOSTERR BIT(1)
50
51/* the following exist only if has_ext_regs is set */
52#define CPDMA_DMACONTROL 0x20
53#define CPDMA_DMASTATUS 0x24
54#define CPDMA_RXBUFFOFS 0x28
55#define CPDMA_EM_CONTROL 0x2c
56
57/* Descriptor mode bits */
58#define CPDMA_DESC_SOP BIT(31)
59#define CPDMA_DESC_EOP BIT(30)
60#define CPDMA_DESC_OWNER BIT(29)
61#define CPDMA_DESC_EOQ BIT(28)
62#define CPDMA_DESC_TD_COMPLETE BIT(27)
63#define CPDMA_DESC_PASS_CRC BIT(26)
f6e135c8
M		 64#define CPDMA_DESC_TO_PORT_EN BIT(20)
65#define CPDMA_TO_PORT_SHIFT 16
66#define CPDMA_DESC_PORT_MASK (BIT(18) | BIT(17) | BIT(16))
28a19fe6 67#define CPDMA_DESC_CRC_LEN 4
ef8c2dab
CC		 68
69#define CPDMA_TEARDOWN_VALUE 0xfffffffc
70
71struct cpdma_desc {
72 /* hardware fields */
73 u32 hw_next;
74 u32 hw_buffer;
75 u32 hw_len;
76 u32 hw_mode;
77 /* software fields */
78 void *sw_token;
79 u32 sw_buffer;
80 u32 sw_len;
81};
82
83struct cpdma_desc_pool {
c767db51 84 phys_addr_t phys;
84092996 85 dma_addr_t hw_addr;
ef8c2dab
CC		 86 void __iomem *iomap; /* ioremap map */
87 void *cpumap; /* dma_alloc map */
88 int desc_size, mem_size;
aeec3021 89 int num_desc;
ef8c2dab 90 struct device *dev;
742fb20f 91 struct gen_pool *gen_pool;
ef8c2dab
CC		 92};
93
94enum cpdma_state {
95 CPDMA_STATE_IDLE,
96 CPDMA_STATE_ACTIVE,
97 CPDMA_STATE_TEARDOWN,
98};
99
ef8c2dab
CC		 100struct cpdma_ctlr {
101 enum cpdma_state state;
102 struct cpdma_params params;
103 struct device *dev;
104 struct cpdma_desc_pool *pool;
105 spinlock_t lock;
106 struct cpdma_chan *channels[2 * CPDMA_MAX_CHANNELS];
3802dce1 107 int chan_num;
ef8c2dab
CC		 108};
109
110struct cpdma_chan {
fae50823
M		 111 struct cpdma_desc __iomem *head, *tail;
112 void __iomem *hdp, *cp, *rxfree;
ef8c2dab
CC		 113 enum cpdma_state state;
114 struct cpdma_ctlr *ctlr;
115 int chan_num;
116 spinlock_t lock;
ef8c2dab 117 int count;
742fb20f 118 u32 desc_num;
ef8c2dab
CC		 119 u32 mask;
120 cpdma_handler_fn handler;
121 enum dma_data_direction dir;
122 struct cpdma_chan_stats stats;
123 /* offsets into dmaregs */
124 int int_set, int_clear, td;
125};
126
127/* The following make access to common cpdma_ctlr params more readable */
128#define dmaregs params.dmaregs
129#define num_chan params.num_chan
130
131/* various accessors */
132#define dma_reg_read(ctlr, ofs) __raw_readl((ctlr)->dmaregs + (ofs))
133#define chan_read(chan, fld) __raw_readl((chan)->fld)
134#define desc_read(desc, fld) __raw_readl(&(desc)->fld)
135#define dma_reg_write(ctlr, ofs, v) __raw_writel(v, (ctlr)->dmaregs + (ofs))
136#define chan_write(chan, fld, v) __raw_writel(v, (chan)->fld)
137#define desc_write(desc, fld, v) __raw_writel((u32)(v), &(desc)->fld)
138
f6e135c8
M		 139#define cpdma_desc_to_port(chan, mode, directed) \
140 do { \
141 if (!is_rx_chan(chan) && ((directed == 1) || \
142 (directed == 2))) \
143 mode |= (CPDMA_DESC_TO_PORT_EN | \
144 (directed << CPDMA_TO_PORT_SHIFT)); \
145 } while (0)
146
742fb20f
GS		 147static void cpdma_desc_pool_destroy(struct cpdma_desc_pool *pool)
148{
149 if (!pool)
150 return;
151
aeec3021
GS		 152 WARN(gen_pool_size(pool->gen_pool) != gen_pool_avail(pool->gen_pool),
153 "cpdma_desc_pool size %d != avail %d",
154 gen_pool_size(pool->gen_pool),
155 gen_pool_avail(pool->gen_pool));
742fb20f
GS		 156 if (pool->cpumap)
157 dma_free_coherent(pool->dev, pool->mem_size, pool->cpumap,
158 pool->phys);
159 else
160 iounmap(pool->iomap);
161}
162
ef8c2dab
CC		 163/*
164 * Utility constructs for a cpdma descriptor pool. Some devices (e.g. davinci
165 * emac) have dedicated on-chip memory for these descriptors. Some other
166 * devices (e.g. cpsw switches) use plain old memory. Descriptor pools
167 * abstract out these details
168 */
169static struct cpdma_desc_pool *
84092996 170cpdma_desc_pool_create(struct device *dev, u32 phys, dma_addr_t hw_addr,
6a1fef6d 171 int size, int align)
ef8c2dab 172{
ef8c2dab 173 struct cpdma_desc_pool *pool;
742fb20f 174 int ret;
ef8c2dab 175
e1943128 176 pool = devm_kzalloc(dev, sizeof(*pool), GFP_KERNEL);
ef8c2dab 177 if (!pool)
742fb20f 178 goto gen_pool_create_fail;
ef8c2dab
CC		 179
180 pool->dev = dev;
181 pool->mem_size = size;
182 pool->desc_size = ALIGN(sizeof(struct cpdma_desc), align);
183 pool->num_desc = size / pool->desc_size;
184
742fb20f
GS		 185 pool->gen_pool = devm_gen_pool_create(dev, ilog2(pool->desc_size), -1,
186 "cpdma");
187 if (IS_ERR(pool->gen_pool)) {
188 dev_err(dev, "pool create failed %ld\n",
189 PTR_ERR(pool->gen_pool));
190 goto gen_pool_create_fail;
191 }
ef8c2dab
CC		 192
193 if (phys) {
194 pool->phys = phys;
84092996 195 pool->iomap = ioremap(phys, size); /* should be memremap? */
6a1fef6d 196 pool->hw_addr = hw_addr;
ef8c2dab 197 } else {
84092996 198 pool->cpumap = dma_alloc_coherent(dev, size, &pool->hw_addr,
ef8c2dab 199 GFP_KERNEL);
84092996
AB		 200 pool->iomap = (void __iomem __force *)pool->cpumap;
201 pool->phys = pool->hw_addr; /* assumes no IOMMU, don't use this value */
ef8c2dab
CC		 202 }
203
742fb20f
GS		 204 if (!pool->iomap)
205 goto gen_pool_create_fail;
ef8c2dab 206
742fb20f
GS		 207 ret = gen_pool_add_virt(pool->gen_pool, (unsigned long)pool->iomap,
208 pool->phys, pool->mem_size, -1);
209 if (ret < 0) {
210 dev_err(dev, "pool add failed %d\n", ret);
211 goto gen_pool_add_virt_fail;
ef8c2dab 212 }
742fb20f
GS		 213
214 return pool;
215
216gen_pool_add_virt_fail:
217 cpdma_desc_pool_destroy(pool);
218gen_pool_create_fail:
219 return NULL;
ef8c2dab
CC		 220}
221
222static inline dma_addr_t desc_phys(struct cpdma_desc_pool *pool,
223 struct cpdma_desc __iomem *desc)
224{
225 if (!desc)
226 return 0;
c767db51 227 return pool->hw_addr + (__force long)desc - (__force long)pool->iomap;
ef8c2dab
CC		 228}
229
230static inline struct cpdma_desc __iomem *
231desc_from_phys(struct cpdma_desc_pool *pool, dma_addr_t dma)
232{
6a1fef6d 233 return dma ? pool->iomap + dma - pool->hw_addr : NULL;
ef8c2dab
CC		 234}
235
236static struct cpdma_desc __iomem *
742fb20f 237cpdma_desc_alloc(struct cpdma_desc_pool *pool)
ef8c2dab 238{
aeec3021
GS		 239 return (struct cpdma_desc __iomem *)
240 gen_pool_alloc(pool->gen_pool, pool->desc_size);
ef8c2dab
CC		 241}
242
243static void cpdma_desc_free(struct cpdma_desc_pool *pool,
244 struct cpdma_desc __iomem *desc, int num_desc)
245{
742fb20f 246 gen_pool_free(pool->gen_pool, (unsigned long)desc, pool->desc_size);
ef8c2dab
CC		 247}
248
249struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params)
250{
251 struct cpdma_ctlr *ctlr;
252
e1943128 253 ctlr = devm_kzalloc(params->dev, sizeof(*ctlr), GFP_KERNEL);
ef8c2dab
CC		 254 if (!ctlr)
255 return NULL;
256
257 ctlr->state = CPDMA_STATE_IDLE;
258 ctlr->params = *params;
259 ctlr->dev = params->dev;
3802dce1 260 ctlr->chan_num = 0;
ef8c2dab
CC		 261 spin_lock_init(&ctlr->lock);
262
263 ctlr->pool = cpdma_desc_pool_create(ctlr->dev,
264 ctlr->params.desc_mem_phys,
6a1fef6d 265 ctlr->params.desc_hw_addr,
ef8c2dab
CC		 266 ctlr->params.desc_mem_size,
267 ctlr->params.desc_align);
2f87208e 268 if (!ctlr->pool)
ef8c2dab 269 return NULL;
ef8c2dab
CC		 270
271 if (WARN_ON(ctlr->num_chan > CPDMA_MAX_CHANNELS))
272 ctlr->num_chan = CPDMA_MAX_CHANNELS;
273 return ctlr;
274}
32a6d90b 275EXPORT_SYMBOL_GPL(cpdma_ctlr_create);
ef8c2dab
CC		 276
277int cpdma_ctlr_start(struct cpdma_ctlr *ctlr)
278{
279 unsigned long flags;
280 int i;
281
282 spin_lock_irqsave(&ctlr->lock, flags);
283 if (ctlr->state != CPDMA_STATE_IDLE) {
284 spin_unlock_irqrestore(&ctlr->lock, flags);
285 return -EBUSY;
286 }
287
288 if (ctlr->params.has_soft_reset) {
817f6d1a 289 unsigned timeout = 10 * 100;
ef8c2dab
CC		 290
291 dma_reg_write(ctlr, CPDMA_SOFTRESET, 1);
817f6d1a 292 while (timeout) {
ef8c2dab
CC		 293 if (dma_reg_read(ctlr, CPDMA_SOFTRESET) == 0)
294 break;
817f6d1a
SS		 295 udelay(10);
296 timeout--;
ef8c2dab 297 }
817f6d1a 298 WARN_ON(!timeout);
ef8c2dab
CC		 299 }
300
301 for (i = 0; i < ctlr->num_chan; i++) {
302 __raw_writel(0, ctlr->params.txhdp + 4 * i);
303 __raw_writel(0, ctlr->params.rxhdp + 4 * i);
304 __raw_writel(0, ctlr->params.txcp + 4 * i);
305 __raw_writel(0, ctlr->params.rxcp + 4 * i);
306 }
307
308 dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff);
309 dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff);
310
311 dma_reg_write(ctlr, CPDMA_TXCONTROL, 1);
312 dma_reg_write(ctlr, CPDMA_RXCONTROL, 1);
313
314 ctlr->state = CPDMA_STATE_ACTIVE;
315
316 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
317 if (ctlr->channels[i])
318 cpdma_chan_start(ctlr->channels[i]);
319 }
320 spin_unlock_irqrestore(&ctlr->lock, flags);
321 return 0;
322}
32a6d90b 323EXPORT_SYMBOL_GPL(cpdma_ctlr_start);
ef8c2dab
CC		 324
325int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr)
326{
327 unsigned long flags;
328 int i;
329
330 spin_lock_irqsave(&ctlr->lock, flags);
cd11cf50 331 if (ctlr->state == CPDMA_STATE_TEARDOWN) {
ef8c2dab
CC		 332 spin_unlock_irqrestore(&ctlr->lock, flags);
333 return -EINVAL;
334 }
335
336 ctlr->state = CPDMA_STATE_TEARDOWN;
080d5c5a 337 spin_unlock_irqrestore(&ctlr->lock, flags);
ef8c2dab
CC		 338
339 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
340 if (ctlr->channels[i])
341 cpdma_chan_stop(ctlr->channels[i]);
342 }
343
080d5c5a 344 spin_lock_irqsave(&ctlr->lock, flags);
ef8c2dab
CC		 345 dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff);
346 dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff);
347
348 dma_reg_write(ctlr, CPDMA_TXCONTROL, 0);
349 dma_reg_write(ctlr, CPDMA_RXCONTROL, 0);
350
351 ctlr->state = CPDMA_STATE_IDLE;
352
353 spin_unlock_irqrestore(&ctlr->lock, flags);
354 return 0;
355}
32a6d90b 356EXPORT_SYMBOL_GPL(cpdma_ctlr_stop);
ef8c2dab 357
ef8c2dab
CC		 358int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr)
359{
ef8c2dab
CC		 360 int ret = 0, i;
361
362 if (!ctlr)
363 return -EINVAL;
364
ef8c2dab
CC		 365 if (ctlr->state != CPDMA_STATE_IDLE)
366 cpdma_ctlr_stop(ctlr);
367
79876e03
CR		 368 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++)
369 cpdma_chan_destroy(ctlr->channels[i]);
ef8c2dab
CC		 370
371 cpdma_desc_pool_destroy(ctlr->pool);
ef8c2dab
CC		 372 return ret;
373}
32a6d90b 374EXPORT_SYMBOL_GPL(cpdma_ctlr_destroy);
ef8c2dab
CC		 375
376int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable)
377{
378 unsigned long flags;
379 int i, reg;
380
381 spin_lock_irqsave(&ctlr->lock, flags);
382 if (ctlr->state != CPDMA_STATE_ACTIVE) {
383 spin_unlock_irqrestore(&ctlr->lock, flags);
384 return -EINVAL;
385 }
386
387 reg = enable ? CPDMA_DMAINTMASKSET : CPDMA_DMAINTMASKCLEAR;
388 dma_reg_write(ctlr, reg, CPDMA_DMAINT_HOSTERR);
389
390 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
391 if (ctlr->channels[i])
392 cpdma_chan_int_ctrl(ctlr->channels[i], enable);
393 }
394
395 spin_unlock_irqrestore(&ctlr->lock, flags);
396 return 0;
397}
6929e24e 398EXPORT_SYMBOL_GPL(cpdma_ctlr_int_ctrl);
ef8c2dab 399
510a1e72 400void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value)
ef8c2dab 401{
510a1e72 402 dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value);
ef8c2dab 403}
6929e24e 404EXPORT_SYMBOL_GPL(cpdma_ctlr_eoi);
ef8c2dab 405
3802dce1
IK		 406/**
407 * cpdma_chan_split_pool - Splits ctrl pool between all channels.
408 * Has to be called under ctlr lock
409 */
410static void cpdma_chan_split_pool(struct cpdma_ctlr *ctlr)
411{
412 struct cpdma_desc_pool *pool = ctlr->pool;
413 struct cpdma_chan *chan;
414 int ch_desc_num;
415 int i;
416
417 if (!ctlr->chan_num)
418 return;
419
420 /* calculate average size of pool slice */
421 ch_desc_num = pool->num_desc / ctlr->chan_num;
422
423 /* split ctlr pool */
424 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) {
425 chan = ctlr->channels[i];
426 if (chan)
427 chan->desc_num = ch_desc_num;
428 }
429}
430
ef8c2dab
CC		 431struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
432 cpdma_handler_fn handler)
433{
434 struct cpdma_chan *chan;
e1943128 435 int offset = (chan_num % CPDMA_MAX_CHANNELS) * 4;
ef8c2dab
CC		 436 unsigned long flags;
437
438 if (__chan_linear(chan_num) >= ctlr->num_chan)
439 return NULL;
440
e1943128 441 chan = devm_kzalloc(ctlr->dev, sizeof(*chan), GFP_KERNEL);
ef8c2dab 442 if (!chan)
e1943128 443 return ERR_PTR(-ENOMEM);
ef8c2dab
CC		 444
445 spin_lock_irqsave(&ctlr->lock, flags);
e1943128
GC		 446 if (ctlr->channels[chan_num]) {
447 spin_unlock_irqrestore(&ctlr->lock, flags);
448 devm_kfree(ctlr->dev, chan);
449 return ERR_PTR(-EBUSY);
450 }
ef8c2dab
CC		 451
452 chan->ctlr = ctlr;
453 chan->state = CPDMA_STATE_IDLE;
454 chan->chan_num = chan_num;
455 chan->handler = handler;
742fb20f 456 chan->desc_num = ctlr->pool->num_desc / 2;
ef8c2dab
CC		 457
458 if (is_rx_chan(chan)) {
459 chan->hdp = ctlr->params.rxhdp + offset;
460 chan->cp = ctlr->params.rxcp + offset;
461 chan->rxfree = ctlr->params.rxfree + offset;
462 chan->int_set = CPDMA_RXINTMASKSET;
463 chan->int_clear = CPDMA_RXINTMASKCLEAR;
464 chan->td = CPDMA_RXTEARDOWN;
465 chan->dir = DMA_FROM_DEVICE;
466 } else {
467 chan->hdp = ctlr->params.txhdp + offset;
468 chan->cp = ctlr->params.txcp + offset;
469 chan->int_set = CPDMA_TXINTMASKSET;
470 chan->int_clear = CPDMA_TXINTMASKCLEAR;
471 chan->td = CPDMA_TXTEARDOWN;
472 chan->dir = DMA_TO_DEVICE;
473 }
474 chan->mask = BIT(chan_linear(chan));
475
476 spin_lock_init(&chan->lock);
477
478 ctlr->channels[chan_num] = chan;
3802dce1
IK		 479 ctlr->chan_num++;
480
481 cpdma_chan_split_pool(ctlr);
482
ef8c2dab
CC		 483 spin_unlock_irqrestore(&ctlr->lock, flags);
484 return chan;
ef8c2dab 485}
32a6d90b 486EXPORT_SYMBOL_GPL(cpdma_chan_create);
ef8c2dab 487
3802dce1 488int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan)
1793331e 489{
3802dce1
IK		 490 unsigned long flags;
491 int desc_num;
492
493 spin_lock_irqsave(&chan->lock, flags);
494 desc_num = chan->desc_num;
495 spin_unlock_irqrestore(&chan->lock, flags);
496
497 return desc_num;
1793331e
IK		 498}
499EXPORT_SYMBOL_GPL(cpdma_chan_get_rx_buf_num);
500
ef8c2dab
CC		 501int cpdma_chan_destroy(struct cpdma_chan *chan)
502{
f37c54b6 503 struct cpdma_ctlr *ctlr;
ef8c2dab
CC		 504 unsigned long flags;
505
506 if (!chan)
507 return -EINVAL;
f37c54b6 508 ctlr = chan->ctlr;
ef8c2dab
CC		 509
510 spin_lock_irqsave(&ctlr->lock, flags);
511 if (chan->state != CPDMA_STATE_IDLE)
512 cpdma_chan_stop(chan);
513 ctlr->channels[chan->chan_num] = NULL;
3802dce1
IK		 514 ctlr->chan_num--;
515
516 cpdma_chan_split_pool(ctlr);
517
ef8c2dab 518 spin_unlock_irqrestore(&ctlr->lock, flags);
ef8c2dab
CC		 519 return 0;
520}
32a6d90b 521EXPORT_SYMBOL_GPL(cpdma_chan_destroy);
ef8c2dab
CC		 522
523int cpdma_chan_get_stats(struct cpdma_chan *chan,
524 struct cpdma_chan_stats *stats)
525{
526 unsigned long flags;
527 if (!chan)
528 return -EINVAL;
529 spin_lock_irqsave(&chan->lock, flags);
530 memcpy(stats, &chan->stats, sizeof(*stats));
531 spin_unlock_irqrestore(&chan->lock, flags);
532 return 0;
533}
0ca04b63 534EXPORT_SYMBOL_GPL(cpdma_chan_get_stats);
ef8c2dab 535
ef8c2dab
CC		 536static void __cpdma_chan_submit(struct cpdma_chan *chan,
537 struct cpdma_desc __iomem *desc)
538{
539 struct cpdma_ctlr *ctlr = chan->ctlr;
540 struct cpdma_desc __iomem *prev = chan->tail;
541 struct cpdma_desc_pool *pool = ctlr->pool;
542 dma_addr_t desc_dma;
543 u32 mode;
544
545 desc_dma = desc_phys(pool, desc);
546
547 /* simple case - idle channel */
548 if (!chan->head) {
549 chan->stats.head_enqueue++;
550 chan->head = desc;
551 chan->tail = desc;
552 if (chan->state == CPDMA_STATE_ACTIVE)
553 chan_write(chan, hdp, desc_dma);
554 return;
555 }
556
557 /* first chain the descriptor at the tail of the list */
558 desc_write(prev, hw_next, desc_dma);
559 chan->tail = desc;
560 chan->stats.tail_enqueue++;
561
562 /* next check if EOQ has been triggered already */
563 mode = desc_read(prev, hw_mode);
564 if (((mode & (CPDMA_DESC_EOQ | CPDMA_DESC_OWNER)) == CPDMA_DESC_EOQ) &&
565 (chan->state == CPDMA_STATE_ACTIVE)) {
566 desc_write(prev, hw_mode, mode & ~CPDMA_DESC_EOQ);
567 chan_write(chan, hdp, desc_dma);
568 chan->stats.misqueued++;
569 }
570}
571
572int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
aef614e1 573 int len, int directed)
ef8c2dab
CC		 574{
575 struct cpdma_ctlr *ctlr = chan->ctlr;
576 struct cpdma_desc __iomem *desc;
577 dma_addr_t buffer;
578 unsigned long flags;
579 u32 mode;
580 int ret = 0;
581
582 spin_lock_irqsave(&chan->lock, flags);
583
584 if (chan->state == CPDMA_STATE_TEARDOWN) {
585 ret = -EINVAL;
586 goto unlock_ret;
587 }
588
742fb20f
GS		 589 if (chan->count >= chan->desc_num) {
590 chan->stats.desc_alloc_fail++;
591 ret = -ENOMEM;
592 goto unlock_ret;
593 }
594
595 desc = cpdma_desc_alloc(ctlr->pool);
ef8c2dab
CC		 596 if (!desc) {
597 chan->stats.desc_alloc_fail++;
598 ret = -ENOMEM;
599 goto unlock_ret;
600 }
601
602 if (len < ctlr->params.min_packet_size) {
603 len = ctlr->params.min_packet_size;
604 chan->stats.runt_transmit_buff++;
605 }
606
607 buffer = dma_map_single(ctlr->dev, data, len, chan->dir);
14bd0769
SS		 608 ret = dma_mapping_error(ctlr->dev, buffer);
609 if (ret) {
610 cpdma_desc_free(ctlr->pool, desc, 1);
611 ret = -EINVAL;
612 goto unlock_ret;
613 }
614
ef8c2dab 615 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
f6e135c8 616 cpdma_desc_to_port(chan, mode, directed);
ef8c2dab
CC		 617
618 desc_write(desc, hw_next, 0);
619 desc_write(desc, hw_buffer, buffer);
620 desc_write(desc, hw_len, len);
621 desc_write(desc, hw_mode, mode | len);
622 desc_write(desc, sw_token, token);
623 desc_write(desc, sw_buffer, buffer);
624 desc_write(desc, sw_len, len);
625
626 __cpdma_chan_submit(chan, desc);
627
628 if (chan->state == CPDMA_STATE_ACTIVE && chan->rxfree)
629 chan_write(chan, rxfree, 1);
630
631 chan->count++;
632
633unlock_ret:
634 spin_unlock_irqrestore(&chan->lock, flags);
635 return ret;
636}
32a6d90b 637EXPORT_SYMBOL_GPL(cpdma_chan_submit);
ef8c2dab 638
fae50823
M		 639bool cpdma_check_free_tx_desc(struct cpdma_chan *chan)
640{
fae50823
M		 641 struct cpdma_ctlr *ctlr = chan->ctlr;
642 struct cpdma_desc_pool *pool = ctlr->pool;
742fb20f
GS		 643 bool free_tx_desc;
644 unsigned long flags;
fae50823 645
742fb20f
GS		 646 spin_lock_irqsave(&chan->lock, flags);
647 free_tx_desc = (chan->count < chan->desc_num) &&
648 gen_pool_avail(pool->gen_pool);
649 spin_unlock_irqrestore(&chan->lock, flags);
650 return free_tx_desc;
fae50823
M		 651}
652EXPORT_SYMBOL_GPL(cpdma_check_free_tx_desc);
653
ef8c2dab
CC		 654static void __cpdma_chan_free(struct cpdma_chan *chan,
655 struct cpdma_desc __iomem *desc,
656 int outlen, int status)
657{
658 struct cpdma_ctlr *ctlr = chan->ctlr;
659 struct cpdma_desc_pool *pool = ctlr->pool;
660 dma_addr_t buff_dma;
661 int origlen;
662 void *token;
663
664 token = (void *)desc_read(desc, sw_token);
665 buff_dma = desc_read(desc, sw_buffer);
666 origlen = desc_read(desc, sw_len);
667
668 dma_unmap_single(ctlr->dev, buff_dma, origlen, chan->dir);
669 cpdma_desc_free(pool, desc, 1);
670 (*chan->handler)(token, outlen, status);
671}
672
673static int __cpdma_chan_process(struct cpdma_chan *chan)
674{
675 struct cpdma_ctlr *ctlr = chan->ctlr;
676 struct cpdma_desc __iomem *desc;
677 int status, outlen;
b4727e69 678 int cb_status = 0;
ef8c2dab
CC		 679 struct cpdma_desc_pool *pool = ctlr->pool;
680 dma_addr_t desc_dma;
681 unsigned long flags;
682
683 spin_lock_irqsave(&chan->lock, flags);
684
685 desc = chan->head;
686 if (!desc) {
687 chan->stats.empty_dequeue++;
688 status = -ENOENT;
689 goto unlock_ret;
690 }
691 desc_dma = desc_phys(pool, desc);
692
693 status = __raw_readl(&desc->hw_mode);
694 outlen = status & 0x7ff;
695 if (status & CPDMA_DESC_OWNER) {
696 chan->stats.busy_dequeue++;
697 status = -EBUSY;
698 goto unlock_ret;
699 }
28a19fe6
M		 700
701 if (status & CPDMA_DESC_PASS_CRC)
702 outlen -= CPDMA_DESC_CRC_LEN;
703
f6e135c8
M		 704 status = status & (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE |
705 CPDMA_DESC_PORT_MASK);
ef8c2dab
CC		 706
707 chan->head = desc_from_phys(pool, desc_read(desc, hw_next));
708 chan_write(chan, cp, desc_dma);
709 chan->count--;
710 chan->stats.good_dequeue++;
711
712 if (status & CPDMA_DESC_EOQ) {
713 chan->stats.requeue++;
714 chan_write(chan, hdp, desc_phys(pool, chan->head));
715 }
716
717 spin_unlock_irqrestore(&chan->lock, flags);
b4727e69
SS		 718 if (unlikely(status & CPDMA_DESC_TD_COMPLETE))
719 cb_status = -ENOSYS;
720 else
721 cb_status = status;
ef8c2dab 722
b4727e69 723 __cpdma_chan_free(chan, desc, outlen, cb_status);
ef8c2dab
CC		 724 return status;
725
726unlock_ret:
727 spin_unlock_irqrestore(&chan->lock, flags);
728 return status;
729}
730
731int cpdma_chan_process(struct cpdma_chan *chan, int quota)
732{
733 int used = 0, ret = 0;
734
735 if (chan->state != CPDMA_STATE_ACTIVE)
736 return -EINVAL;
737
738 while (used < quota) {
739 ret = __cpdma_chan_process(chan);
740 if (ret < 0)
741 break;
742 used++;
743 }
744 return used;
745}
32a6d90b 746EXPORT_SYMBOL_GPL(cpdma_chan_process);
ef8c2dab
CC		 747
748int cpdma_chan_start(struct cpdma_chan *chan)
749{
750 struct cpdma_ctlr *ctlr = chan->ctlr;
751 struct cpdma_desc_pool *pool = ctlr->pool;
752 unsigned long flags;
753
754 spin_lock_irqsave(&chan->lock, flags);
755 if (chan->state != CPDMA_STATE_IDLE) {
756 spin_unlock_irqrestore(&chan->lock, flags);
757 return -EBUSY;
758 }
759 if (ctlr->state != CPDMA_STATE_ACTIVE) {
760 spin_unlock_irqrestore(&chan->lock, flags);
761 return -EINVAL;
762 }
763 dma_reg_write(ctlr, chan->int_set, chan->mask);
764 chan->state = CPDMA_STATE_ACTIVE;
765 if (chan->head) {
766 chan_write(chan, hdp, desc_phys(pool, chan->head));
767 if (chan->rxfree)
768 chan_write(chan, rxfree, chan->count);
769 }
770
771 spin_unlock_irqrestore(&chan->lock, flags);
772 return 0;
773}
32a6d90b 774EXPORT_SYMBOL_GPL(cpdma_chan_start);
ef8c2dab
CC		 775
776int cpdma_chan_stop(struct cpdma_chan *chan)
777{
778 struct cpdma_ctlr *ctlr = chan->ctlr;
779 struct cpdma_desc_pool *pool = ctlr->pool;
780 unsigned long flags;
781 int ret;
817f6d1a 782 unsigned timeout;
ef8c2dab
CC		 783
784 spin_lock_irqsave(&chan->lock, flags);
cd11cf50 785 if (chan->state == CPDMA_STATE_TEARDOWN) {
ef8c2dab
CC		 786 spin_unlock_irqrestore(&chan->lock, flags);
787 return -EINVAL;
788 }
789
790 chan->state = CPDMA_STATE_TEARDOWN;
791 dma_reg_write(ctlr, chan->int_clear, chan->mask);
792
793 /* trigger teardown */
b4ad0428 794 dma_reg_write(ctlr, chan->td, chan_linear(chan));
ef8c2dab
CC		 795
796 /* wait for teardown complete */
817f6d1a
SS		 797 timeout = 100 * 100; /* 100 ms */
798 while (timeout) {
ef8c2dab
CC		 799 u32 cp = chan_read(chan, cp);
800 if ((cp & CPDMA_TEARDOWN_VALUE) == CPDMA_TEARDOWN_VALUE)
801 break;
817f6d1a
SS		 802 udelay(10);
803 timeout--;
ef8c2dab 804 }
817f6d1a 805 WARN_ON(!timeout);
ef8c2dab
CC		 806 chan_write(chan, cp, CPDMA_TEARDOWN_VALUE);
807
808 /* handle completed packets */
7746ab0a 809 spin_unlock_irqrestore(&chan->lock, flags);
ef8c2dab
CC		 810 do {
811 ret = __cpdma_chan_process(chan);
812 if (ret < 0)
813 break;
814 } while ((ret & CPDMA_DESC_TD_COMPLETE) == 0);
7746ab0a 815 spin_lock_irqsave(&chan->lock, flags);
ef8c2dab
CC		 816
817 /* remaining packets haven't been tx/rx'ed, clean them up */
818 while (chan->head) {
819 struct cpdma_desc __iomem *desc = chan->head;
820 dma_addr_t next_dma;
821
822 next_dma = desc_read(desc, hw_next);
823 chan->head = desc_from_phys(pool, next_dma);
ffb5ba90 824 chan->count--;
ef8c2dab
CC		 825 chan->stats.teardown_dequeue++;
826
827 /* issue callback without locks held */
828 spin_unlock_irqrestore(&chan->lock, flags);
829 __cpdma_chan_free(chan, desc, 0, -ENOSYS);
830 spin_lock_irqsave(&chan->lock, flags);
831 }
832
833 chan->state = CPDMA_STATE_IDLE;
834 spin_unlock_irqrestore(&chan->lock, flags);
835 return 0;
836}
32a6d90b 837EXPORT_SYMBOL_GPL(cpdma_chan_stop);
ef8c2dab
CC		 838
839int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable)
840{
841 unsigned long flags;
842
843 spin_lock_irqsave(&chan->lock, flags);
844 if (chan->state != CPDMA_STATE_ACTIVE) {
845 spin_unlock_irqrestore(&chan->lock, flags);
846 return -EINVAL;
847 }
848
849 dma_reg_write(chan->ctlr, enable ? chan->int_set : chan->int_clear,
850 chan->mask);
851 spin_unlock_irqrestore(&chan->lock, flags);
852
853 return 0;
854}
855
856struct cpdma_control_info {
857 u32 reg;
858 u32 shift, mask;
859 int access;
860#define ACCESS_RO BIT(0)
861#define ACCESS_WO BIT(1)
862#define ACCESS_RW (ACCESS_RO | ACCESS_WO)
863};
864
df784160 865static struct cpdma_control_info controls[] = {
ef8c2dab
CC		 866 [CPDMA_CMD_IDLE] = {CPDMA_DMACONTROL, 3, 1, ACCESS_WO},
867 [CPDMA_COPY_ERROR_FRAMES] = {CPDMA_DMACONTROL, 4, 1, ACCESS_RW},
868 [CPDMA_RX_OFF_LEN_UPDATE] = {CPDMA_DMACONTROL, 2, 1, ACCESS_RW},
869 [CPDMA_RX_OWNERSHIP_FLIP] = {CPDMA_DMACONTROL, 1, 1, ACCESS_RW},
870 [CPDMA_TX_PRIO_FIXED] = {CPDMA_DMACONTROL, 0, 1, ACCESS_RW},
871 [CPDMA_STAT_IDLE] = {CPDMA_DMASTATUS, 31, 1, ACCESS_RO},
872 [CPDMA_STAT_TX_ERR_CODE] = {CPDMA_DMASTATUS, 20, 0xf, ACCESS_RW},
873 [CPDMA_STAT_TX_ERR_CHAN] = {CPDMA_DMASTATUS, 16, 0x7, ACCESS_RW},
874 [CPDMA_STAT_RX_ERR_CODE] = {CPDMA_DMASTATUS, 12, 0xf, ACCESS_RW},
875 [CPDMA_STAT_RX_ERR_CHAN] = {CPDMA_DMASTATUS, 8, 0x7, ACCESS_RW},
876 [CPDMA_RX_BUFFER_OFFSET] = {CPDMA_RXBUFFOFS, 0, 0xffff, ACCESS_RW},
877};
878
879int cpdma_control_get(struct cpdma_ctlr *ctlr, int control)
880{
881 unsigned long flags;
882 struct cpdma_control_info *info = &controls[control];
883 int ret;
884
885 spin_lock_irqsave(&ctlr->lock, flags);
886
887 ret = -ENOTSUPP;
888 if (!ctlr->params.has_ext_regs)
889 goto unlock_ret;
890
891 ret = -EINVAL;
892 if (ctlr->state != CPDMA_STATE_ACTIVE)
893 goto unlock_ret;
894
895 ret = -ENOENT;
896 if (control < 0 || control >= ARRAY_SIZE(controls))
897 goto unlock_ret;
898
899 ret = -EPERM;
900 if ((info->access & ACCESS_RO) != ACCESS_RO)
901 goto unlock_ret;
902
903 ret = (dma_reg_read(ctlr, info->reg) >> info->shift) & info->mask;
904
905unlock_ret:
906 spin_unlock_irqrestore(&ctlr->lock, flags);
907 return ret;
908}
909
910int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value)
911{
912 unsigned long flags;
913 struct cpdma_control_info *info = &controls[control];
914 int ret;
915 u32 val;
916
917 spin_lock_irqsave(&ctlr->lock, flags);
918
919 ret = -ENOTSUPP;
920 if (!ctlr->params.has_ext_regs)
921 goto unlock_ret;
922
923 ret = -EINVAL;
924 if (ctlr->state != CPDMA_STATE_ACTIVE)
925 goto unlock_ret;
926
927 ret = -ENOENT;
928 if (control < 0 || control >= ARRAY_SIZE(controls))
929 goto unlock_ret;
930
931 ret = -EPERM;
932 if ((info->access & ACCESS_WO) != ACCESS_WO)
933 goto unlock_ret;
934
935 val = dma_reg_read(ctlr, info->reg);
936 val &= ~(info->mask << info->shift);
937 val |= (value & info->mask) << info->shift;
938 dma_reg_write(ctlr, info->reg, val);
939 ret = 0;
940
941unlock_ret:
942 spin_unlock_irqrestore(&ctlr->lock, flags);
943 return ret;
944}
6929e24e 945EXPORT_SYMBOL_GPL(cpdma_control_set);
4bc21d41
SS		 946
947MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)