[linux-2.6-block.git] / drivers / net / ethernet / ti / cpsw_ale.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Texas Instruments N-Port Ethernet Switch Address Lookup Engine APIs
 *
 * Copyright (C) 2012 Texas Instruments
 *
 */
#ifndef __TI_CPSW_ALE_H__
#define __TI_CPSW_ALE_H__

struct reg_fields;

struct cpsw_ale_params {
	struct device		*dev;
	void __iomem		*ale_regs;
	unsigned long		ale_ageout;	/* in secs */
	unsigned long		ale_entries;
	unsigned long		num_policers;
	unsigned long		ale_ports;
	/* NU Switch has specific handling as number of bits in ALE entries
	 * are different than other versions of ALE. Also there are specific
	 * registers for unknown vlan specific fields. So use nu_switch_ale
	 * to identify this hardware.
	 */
	bool			nu_switch_ale;
	const struct reg_field *reg_fields;
	int			num_fields;
	const char		*dev_id;
	unsigned long		bus_freq;
};

struct ale_entry_fld;
struct regmap;

enum ale_fields {
	MINOR_VER,
	MAJOR_VER,
	ALE_ENTRIES,
	ALE_POLICERS,
	POL_PORT_MEN,
	POL_TRUNK_ID,
	POL_PORT_NUM,
	POL_PRI_MEN,
	POL_PRI_VAL,
	POL_OUI_MEN,
	POL_OUI_INDEX,
	POL_DST_MEN,
	POL_DST_INDEX,
	POL_SRC_MEN,
	POL_SRC_INDEX,
	POL_OVLAN_MEN,
	POL_OVLAN_INDEX,
	POL_IVLAN_MEN,
	POL_IVLAN_INDEX,
	POL_ETHERTYPE_MEN,
	POL_ETHERTYPE_INDEX,
	POL_IPSRC_MEN,
	POL_IPSRC_INDEX,
	POL_IPDST_MEN,
	POL_IPDST_INDEX,
	POL_EN,
	POL_RED_DROP_EN,
	POL_YELLOW_DROP_EN,
	POL_YELLOW_THRESH,
	POL_POL_MATCH_MODE,
	POL_PRIORITY_THREAD_EN,
	POL_MAC_ONLY_DEF_DIS,
	POL_TEST_CLR,
	POL_TEST_CLR_RED,
	POL_TEST_CLR_YELLOW,
	POL_TEST_CLR_SELECTED,
	POL_TEST_ENTRY,
	POL_STATUS_HIT,
	POL_STATUS_HIT_RED,
	POL_STATUS_HIT_YELLOW,
	ALE_DEFAULT_THREAD_EN,
	ALE_DEFAULT_THREAD_VAL,
	ALE_THREAD_CLASS_INDEX,
	ALE_THREAD_ENABLE,
	ALE_THREAD_VALUE,
	/* terminator */
	ALE_FIELDS_MAX,
};

struct cpsw_ale {
	struct cpsw_ale_params	params;
	struct timer_list	timer;
	struct regmap		*regmap;
	struct regmap_field	*fields[ALE_FIELDS_MAX];
	unsigned long		ageout;
	u32			version;
	u32			features;
	/* These bits are different on NetCP NU Switch ALE */
	u32			port_mask_bits;
	u32			port_num_bits;
	u32			vlan_field_bits;
	unsigned long		*p0_untag_vid_mask;
	const struct ale_entry_fld *vlan_entry_tbl;
};

enum cpsw_ale_control {
	/* global */
	ALE_ENABLE,
	ALE_CLEAR,
	ALE_AGEOUT,
	ALE_P0_UNI_FLOOD,
	ALE_VLAN_NOLEARN,
	ALE_NO_PORT_VLAN,
	ALE_OUI_DENY,
	ALE_BYPASS,
	ALE_RATE_LIMIT_TX,
	ALE_VLAN_AWARE,
	ALE_AUTH_ENABLE,
	ALE_RATE_LIMIT,
	/* port controls */
	ALE_PORT_STATE,
	ALE_PORT_DROP_UNTAGGED,
	ALE_PORT_DROP_UNKNOWN_VLAN,
	ALE_PORT_NOLEARN,
	ALE_PORT_NO_SA_UPDATE,
	ALE_PORT_UNKNOWN_VLAN_MEMBER,
	ALE_PORT_UNKNOWN_MCAST_FLOOD,
	ALE_PORT_UNKNOWN_REG_MCAST_FLOOD,
	ALE_PORT_UNTAGGED_EGRESS,
	ALE_PORT_MACONLY,
	ALE_PORT_MACONLY_CAF,
	ALE_PORT_BCAST_LIMIT,
	ALE_PORT_MCAST_LIMIT,
	ALE_DEFAULT_THREAD_ID,
	ALE_DEFAULT_THREAD_ENABLE,
	ALE_NUM_CONTROLS,
};

enum cpsw_ale_port_state {
	ALE_PORT_STATE_DISABLE	= 0x00,
	ALE_PORT_STATE_BLOCK	= 0x01,
	ALE_PORT_STATE_LEARN	= 0x02,
	ALE_PORT_STATE_FORWARD	= 0x03,
};

/* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
#define ALE_SECURE			BIT(0)
#define ALE_BLOCKED			BIT(1)
#define ALE_SUPER			BIT(2)
#define ALE_VLAN			BIT(3)

#define ALE_PORT_HOST			BIT(0)
#define ALE_PORT_1			BIT(1)
#define ALE_PORT_2			BIT(2)

#define ALE_MCAST_FWD			0
#define ALE_MCAST_BLOCK_LEARN_FWD	1
#define ALE_MCAST_FWD_LEARN		2
#define ALE_MCAST_FWD_2			3

#define ALE_ENTRY_BITS		68
#define ALE_ENTRY_WORDS	DIV_ROUND_UP(ALE_ENTRY_BITS, 32)

struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params);

void cpsw_ale_start(struct cpsw_ale *ale);
void cpsw_ale_stop(struct cpsw_ale *ale);

int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid);
int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
		       int flags, u16 vid);
int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
		       int flags, u16 vid);
int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
		       int flags, u16 vid, int mcast_state);
int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
		       int flags, u16 vid);
int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag,
			int reg_mcast, int unreg_mcast);
int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port);
void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port);
int cpsw_ale_rx_ratelimit_bc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps);
int cpsw_ale_rx_ratelimit_mc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps);

int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control);
int cpsw_ale_control_set(struct cpsw_ale *ale, int port,
			 int control, int value);
void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data);
void cpsw_ale_restore(struct cpsw_ale *ale, u32 *data);
u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale);

static inline int cpsw_ale_get_vlan_p0_untag(struct cpsw_ale *ale, u16 vid)
{
	return test_bit(vid, ale->p0_untag_vid_mask);
}

int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask,
			     int untag_mask, int reg_mcast, int unreg_mcast);
int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask);
void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask,
			      bool add);
void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch);

#endif
Commit	Line	Data
68cf027f	1	/* SPDX-License-Identifier: GPL-2.0 */
db82173f	2	/*
ca47130a	3	* Texas Instruments N-Port Ethernet Switch Address Lookup Engine APIs
db82173f M	4	*
	5	* Copyright (C) 2012 Texas Instruments
	6	*
db82173f M	7	*/
	8	#ifndef __TI_CPSW_ALE_H__
	9	#define __TI_CPSW_ALE_H__
	10
bbfc7e2b RQ	11	struct reg_fields;
bbfc7e2b RQ	12
db82173f M	13	struct cpsw_ale_params {
	14	struct device *dev;
	15	void __iomem *ale_regs;
	16	unsigned long ale_ageout; /* in secs */
	17	unsigned long ale_entries;
11cbcfea	18	unsigned long num_policers;
db82173f	19	unsigned long ale_ports;
ca47130a KM	20	/* NU Switch has specific handling as number of bits in ALE entries
	21	* are different than other versions of ALE. Also there are specific
	22	* registers for unknown vlan specific fields. So use nu_switch_ale
	23	* to identify this hardware.
	24	*/
	25	bool nu_switch_ale;
bbfc7e2b	26	const struct reg_field *reg_fields;
e9d591b1	27	int num_fields;
6a68df93	28	const char *dev_id;
23015ff1	29	unsigned long bus_freq;
db82173f M	30	};
db82173f M	31
aa61296c	32	struct ale_entry_fld;
bbfc7e2b RQ	33	struct regmap;
	34
	35	enum ale_fields {
	36	MINOR_VER,
	37	MAJOR_VER,
11cbcfea RQ	38	ALE_ENTRIES,
11cbcfea RQ	39	ALE_POLICERS,
eb41dd76 RQ	40	POL_PORT_MEN,
	41	POL_TRUNK_ID,
	42	POL_PORT_NUM,
	43	POL_PRI_MEN,
	44	POL_PRI_VAL,
	45	POL_OUI_MEN,
	46	POL_OUI_INDEX,
	47	POL_DST_MEN,
	48	POL_DST_INDEX,
	49	POL_SRC_MEN,
	50	POL_SRC_INDEX,
	51	POL_OVLAN_MEN,
	52	POL_OVLAN_INDEX,
	53	POL_IVLAN_MEN,
	54	POL_IVLAN_INDEX,
	55	POL_ETHERTYPE_MEN,
	56	POL_ETHERTYPE_INDEX,
	57	POL_IPSRC_MEN,
	58	POL_IPSRC_INDEX,
	59	POL_IPDST_MEN,
	60	POL_IPDST_INDEX,
	61	POL_EN,
	62	POL_RED_DROP_EN,
	63	POL_YELLOW_DROP_EN,
	64	POL_YELLOW_THRESH,
	65	POL_POL_MATCH_MODE,
	66	POL_PRIORITY_THREAD_EN,
	67	POL_MAC_ONLY_DEF_DIS,
	68	POL_TEST_CLR,
	69	POL_TEST_CLR_RED,
	70	POL_TEST_CLR_YELLOW,
	71	POL_TEST_CLR_SELECTED,
	72	POL_TEST_ENTRY,
	73	POL_STATUS_HIT,
	74	POL_STATUS_HIT_RED,
	75	POL_STATUS_HIT_YELLOW,
	76	ALE_DEFAULT_THREAD_EN,
	77	ALE_DEFAULT_THREAD_VAL,
	78	ALE_THREAD_CLASS_INDEX,
	79	ALE_THREAD_ENABLE,
	80	ALE_THREAD_VALUE,
bbfc7e2b RQ	81	/* terminator */
	82	ALE_FIELDS_MAX,
	83	};
aa61296c	84
db82173f M	85	struct cpsw_ale {
	86	struct cpsw_ale_params params;
	87	struct timer_list timer;
bbfc7e2b RQ	88	struct regmap *regmap;
bbfc7e2b RQ	89	struct regmap_field *fields[ALE_FIELDS_MAX];
db82173f	90	unsigned long ageout;
ca47130a	91	u32 version;
186f5c99	92	u32 features;
b361da83 KM	93	/* These bits are different on NetCP NU Switch ALE */
	94	u32 port_mask_bits;
	95	u32 port_num_bits;
	96	u32 vlan_field_bits;
4b41d343	97	unsigned long *p0_untag_vid_mask;
aa61296c	98	const struct ale_entry_fld *vlan_entry_tbl;
db82173f M	99	};
	100
	101	enum cpsw_ale_control {
	102	/* global */
	103	ALE_ENABLE,
	104	ALE_CLEAR,
	105	ALE_AGEOUT,
0cd8f9cc	106	ALE_P0_UNI_FLOOD,
db82173f M	107	ALE_VLAN_NOLEARN,
	108	ALE_NO_PORT_VLAN,
	109	ALE_OUI_DENY,
	110	ALE_BYPASS,
	111	ALE_RATE_LIMIT_TX,
	112	ALE_VLAN_AWARE,
	113	ALE_AUTH_ENABLE,
	114	ALE_RATE_LIMIT,
	115	/* port controls */
	116	ALE_PORT_STATE,
	117	ALE_PORT_DROP_UNTAGGED,
	118	ALE_PORT_DROP_UNKNOWN_VLAN,
	119	ALE_PORT_NOLEARN,
0cd8f9cc	120	ALE_PORT_NO_SA_UPDATE,
db82173f M	121	ALE_PORT_UNKNOWN_VLAN_MEMBER,
	122	ALE_PORT_UNKNOWN_MCAST_FLOOD,
	123	ALE_PORT_UNKNOWN_REG_MCAST_FLOOD,
	124	ALE_PORT_UNTAGGED_EGRESS,
6c0b849c GS	125	ALE_PORT_MACONLY,
6c0b849c GS	126	ALE_PORT_MACONLY_CAF,
db82173f M	127	ALE_PORT_BCAST_LIMIT,
db82173f M	128	ALE_PORT_MCAST_LIMIT,
4ed59504 GS	129	ALE_DEFAULT_THREAD_ID,
4ed59504 GS	130	ALE_DEFAULT_THREAD_ENABLE,
db82173f M	131	ALE_NUM_CONTROLS,
	132	};
	133
	134	enum cpsw_ale_port_state {
	135	ALE_PORT_STATE_DISABLE = 0x00,
	136	ALE_PORT_STATE_BLOCK = 0x01,
	137	ALE_PORT_STATE_LEARN = 0x02,
	138	ALE_PORT_STATE_FORWARD = 0x03,
	139	};
	140
	141	/* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
e11b220f M	142	#define ALE_SECURE BIT(0)
	143	#define ALE_BLOCKED BIT(1)
	144	#define ALE_SUPER BIT(2)
	145	#define ALE_VLAN BIT(3)
db82173f	146
3b72c2fe M	147	#define ALE_PORT_HOST BIT(0)
	148	#define ALE_PORT_1 BIT(1)
	149	#define ALE_PORT_2 BIT(2)
	150
db82173f M	151	#define ALE_MCAST_FWD 0
	152	#define ALE_MCAST_BLOCK_LEARN_FWD 1
	153	#define ALE_MCAST_FWD_LEARN 2
	154	#define ALE_MCAST_FWD_2 3
	155
52c4f0ec M	156	#define ALE_ENTRY_BITS 68
	157	#define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
	158
db82173f	159	struct cpsw_ale cpsw_ale_create(struct cpsw_ale_params params);
db82173f M	160
	161	void cpsw_ale_start(struct cpsw_ale *ale);
	162	void cpsw_ale_stop(struct cpsw_ale *ale);
	163
25906052	164	int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid);
58bdeac8	165	int cpsw_ale_add_ucast(struct cpsw_ale ale, const u8 addr, int port,
e11b220f	166	int flags, u16 vid);
58bdeac8	167	int cpsw_ale_del_ucast(struct cpsw_ale ale, const u8 addr, int port,
e11b220f	168	int flags, u16 vid);
58bdeac8	169	int cpsw_ale_add_mcast(struct cpsw_ale ale, const u8 addr, int port_mask,
e11b220f	170	int flags, u16 vid, int mcast_state);
58bdeac8	171	int cpsw_ale_del_mcast(struct cpsw_ale ale, const u8 addr, int port_mask,
e11b220f M	172	int flags, u16 vid);
	173	int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag,
	174	int reg_mcast, int unreg_mcast);
	175	int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port);
06095f34	176	void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port);
e3a5e33f GS	177	int cpsw_ale_rx_ratelimit_bc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps);
e3a5e33f GS	178	int cpsw_ale_rx_ratelimit_mc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps);
db82173f M	179
	180	int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control);
	181	int cpsw_ale_control_set(struct cpsw_ale *ale, int port,
	182	int control, int value);
52c4f0ec	183	void cpsw_ale_dump(struct cpsw_ale ale, u32 data);
eadb4343	184	void cpsw_ale_restore(struct cpsw_ale ale, u32 data);
b574bf0c	185	u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale);
db82173f	186
4b41d343 GS	187	static inline int cpsw_ale_get_vlan_p0_untag(struct cpsw_ale *ale, u16 vid)
	188	{
	189	return test_bit(vid, ale->p0_untag_vid_mask);
	190	}
e85c1437 IA	191
	192	int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask,
	193	int untag_mask, int reg_mcast, int unreg_mcast);
82882bd5	194	int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask);
e85c1437 IA	195	void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask,
e85c1437 IA	196	bool add);
961d4187	197	void cpsw_ale_classifier_setup_default(struct cpsw_ale *ale, int num_rx_ch);
e85c1437	198
db82173f	199	#endif