Commit | Line | Data |
---|---|---|
df828598 M |
1 | /* |
2 | * Texas Instruments Ethernet Switch Driver | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/timer.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/irqreturn.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/if_ether.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/netdevice.h> | |
2e5b38ab | 27 | #include <linux/net_tstamp.h> |
df828598 M |
28 | #include <linux/phy.h> |
29 | #include <linux/workqueue.h> | |
30 | #include <linux/delay.h> | |
f150bd7f | 31 | #include <linux/pm_runtime.h> |
2eb32b0a M |
32 | #include <linux/of.h> |
33 | #include <linux/of_net.h> | |
34 | #include <linux/of_device.h> | |
3b72c2fe | 35 | #include <linux/if_vlan.h> |
df828598 | 36 | |
739683b4 | 37 | #include <linux/pinctrl/consumer.h> |
df828598 | 38 | |
dbe34724 | 39 | #include "cpsw.h" |
df828598 | 40 | #include "cpsw_ale.h" |
2e5b38ab | 41 | #include "cpts.h" |
df828598 M |
42 | #include "davinci_cpdma.h" |
43 | ||
44 | #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ | |
45 | NETIF_MSG_DRV | NETIF_MSG_LINK | \ | |
46 | NETIF_MSG_IFUP | NETIF_MSG_INTR | \ | |
47 | NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ | |
48 | NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ | |
49 | NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ | |
50 | NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ | |
51 | NETIF_MSG_RX_STATUS) | |
52 | ||
53 | #define cpsw_info(priv, type, format, ...) \ | |
54 | do { \ | |
55 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
56 | dev_info(priv->dev, format, ## __VA_ARGS__); \ | |
57 | } while (0) | |
58 | ||
59 | #define cpsw_err(priv, type, format, ...) \ | |
60 | do { \ | |
61 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
62 | dev_err(priv->dev, format, ## __VA_ARGS__); \ | |
63 | } while (0) | |
64 | ||
65 | #define cpsw_dbg(priv, type, format, ...) \ | |
66 | do { \ | |
67 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
68 | dev_dbg(priv->dev, format, ## __VA_ARGS__); \ | |
69 | } while (0) | |
70 | ||
71 | #define cpsw_notice(priv, type, format, ...) \ | |
72 | do { \ | |
73 | if (netif_msg_##type(priv) && net_ratelimit()) \ | |
74 | dev_notice(priv->dev, format, ## __VA_ARGS__); \ | |
75 | } while (0) | |
76 | ||
5c50a856 M |
77 | #define ALE_ALL_PORTS 0x7 |
78 | ||
df828598 M |
79 | #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) |
80 | #define CPSW_MINOR_VERSION(reg) (reg & 0xff) | |
81 | #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) | |
82 | ||
e90cfac6 RC |
83 | #define CPSW_VERSION_1 0x19010a |
84 | #define CPSW_VERSION_2 0x19010c | |
c193f365 | 85 | #define CPSW_VERSION_3 0x19010f |
926489be | 86 | #define CPSW_VERSION_4 0x190112 |
549985ee RC |
87 | |
88 | #define HOST_PORT_NUM 0 | |
89 | #define SLIVER_SIZE 0x40 | |
90 | ||
91 | #define CPSW1_HOST_PORT_OFFSET 0x028 | |
92 | #define CPSW1_SLAVE_OFFSET 0x050 | |
93 | #define CPSW1_SLAVE_SIZE 0x040 | |
94 | #define CPSW1_CPDMA_OFFSET 0x100 | |
95 | #define CPSW1_STATERAM_OFFSET 0x200 | |
d9718546 | 96 | #define CPSW1_HW_STATS 0x400 |
549985ee RC |
97 | #define CPSW1_CPTS_OFFSET 0x500 |
98 | #define CPSW1_ALE_OFFSET 0x600 | |
99 | #define CPSW1_SLIVER_OFFSET 0x700 | |
100 | ||
101 | #define CPSW2_HOST_PORT_OFFSET 0x108 | |
102 | #define CPSW2_SLAVE_OFFSET 0x200 | |
103 | #define CPSW2_SLAVE_SIZE 0x100 | |
104 | #define CPSW2_CPDMA_OFFSET 0x800 | |
d9718546 | 105 | #define CPSW2_HW_STATS 0x900 |
549985ee RC |
106 | #define CPSW2_STATERAM_OFFSET 0xa00 |
107 | #define CPSW2_CPTS_OFFSET 0xc00 | |
108 | #define CPSW2_ALE_OFFSET 0xd00 | |
109 | #define CPSW2_SLIVER_OFFSET 0xd80 | |
110 | #define CPSW2_BD_OFFSET 0x2000 | |
111 | ||
df828598 M |
112 | #define CPDMA_RXTHRESH 0x0c0 |
113 | #define CPDMA_RXFREE 0x0e0 | |
114 | #define CPDMA_TXHDP 0x00 | |
115 | #define CPDMA_RXHDP 0x20 | |
116 | #define CPDMA_TXCP 0x40 | |
117 | #define CPDMA_RXCP 0x60 | |
118 | ||
df828598 M |
119 | #define CPSW_POLL_WEIGHT 64 |
120 | #define CPSW_MIN_PACKET_SIZE 60 | |
121 | #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) | |
122 | ||
123 | #define RX_PRIORITY_MAPPING 0x76543210 | |
124 | #define TX_PRIORITY_MAPPING 0x33221100 | |
125 | #define CPDMA_TX_PRIORITY_MAP 0x76543210 | |
126 | ||
3b72c2fe M |
127 | #define CPSW_VLAN_AWARE BIT(1) |
128 | #define CPSW_ALE_VLAN_AWARE 1 | |
129 | ||
d9ba8f9e M |
130 | #define CPSW_FIFO_NORMAL_MODE (0 << 15) |
131 | #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15) | |
132 | #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15) | |
133 | ||
ff5b8ef2 M |
134 | #define CPSW_INTPACEEN (0x3f << 16) |
135 | #define CPSW_INTPRESCALE_MASK (0x7FF << 0) | |
136 | #define CPSW_CMINTMAX_CNT 63 | |
137 | #define CPSW_CMINTMIN_CNT 2 | |
138 | #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) | |
139 | #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) | |
140 | ||
df828598 M |
141 | #define cpsw_enable_irq(priv) \ |
142 | do { \ | |
143 | u32 i; \ | |
144 | for (i = 0; i < priv->num_irqs; i++) \ | |
145 | enable_irq(priv->irqs_table[i]); \ | |
146 | } while (0); | |
147 | #define cpsw_disable_irq(priv) \ | |
148 | do { \ | |
149 | u32 i; \ | |
150 | for (i = 0; i < priv->num_irqs; i++) \ | |
151 | disable_irq_nosync(priv->irqs_table[i]); \ | |
152 | } while (0); | |
153 | ||
d3bb9c58 M |
154 | #define cpsw_slave_index(priv) \ |
155 | ((priv->data.dual_emac) ? priv->emac_port : \ | |
156 | priv->data.active_slave) | |
157 | ||
df828598 M |
158 | static int debug_level; |
159 | module_param(debug_level, int, 0); | |
160 | MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); | |
161 | ||
162 | static int ale_ageout = 10; | |
163 | module_param(ale_ageout, int, 0); | |
164 | MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); | |
165 | ||
166 | static int rx_packet_max = CPSW_MAX_PACKET_SIZE; | |
167 | module_param(rx_packet_max, int, 0); | |
168 | MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); | |
169 | ||
996a5c27 | 170 | struct cpsw_wr_regs { |
df828598 M |
171 | u32 id_ver; |
172 | u32 soft_reset; | |
173 | u32 control; | |
174 | u32 int_control; | |
175 | u32 rx_thresh_en; | |
176 | u32 rx_en; | |
177 | u32 tx_en; | |
178 | u32 misc_en; | |
ff5b8ef2 M |
179 | u32 mem_allign1[8]; |
180 | u32 rx_thresh_stat; | |
181 | u32 rx_stat; | |
182 | u32 tx_stat; | |
183 | u32 misc_stat; | |
184 | u32 mem_allign2[8]; | |
185 | u32 rx_imax; | |
186 | u32 tx_imax; | |
187 | ||
df828598 M |
188 | }; |
189 | ||
996a5c27 | 190 | struct cpsw_ss_regs { |
df828598 M |
191 | u32 id_ver; |
192 | u32 control; | |
193 | u32 soft_reset; | |
194 | u32 stat_port_en; | |
195 | u32 ptype; | |
bd357af2 RC |
196 | u32 soft_idle; |
197 | u32 thru_rate; | |
198 | u32 gap_thresh; | |
199 | u32 tx_start_wds; | |
200 | u32 flow_control; | |
201 | u32 vlan_ltype; | |
202 | u32 ts_ltype; | |
203 | u32 dlr_ltype; | |
df828598 M |
204 | }; |
205 | ||
9750a3ad RC |
206 | /* CPSW_PORT_V1 */ |
207 | #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ | |
208 | #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ | |
209 | #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ | |
210 | #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ | |
211 | #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ | |
212 | #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ | |
213 | #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ | |
214 | #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ | |
215 | ||
216 | /* CPSW_PORT_V2 */ | |
217 | #define CPSW2_CONTROL 0x00 /* Control Register */ | |
218 | #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ | |
219 | #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ | |
220 | #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ | |
221 | #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ | |
222 | #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ | |
223 | #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ | |
224 | ||
225 | /* CPSW_PORT_V1 and V2 */ | |
226 | #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ | |
227 | #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ | |
228 | #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ | |
229 | ||
230 | /* CPSW_PORT_V2 only */ | |
231 | #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ | |
232 | #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ | |
233 | #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ | |
234 | #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ | |
235 | #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ | |
236 | #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ | |
237 | #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ | |
238 | #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ | |
239 | ||
240 | /* Bit definitions for the CPSW2_CONTROL register */ | |
241 | #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ | |
242 | #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ | |
243 | #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ | |
244 | #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ | |
245 | #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ | |
246 | #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ | |
247 | #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ | |
248 | #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ | |
249 | #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ | |
250 | #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ | |
251 | #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ | |
252 | #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ | |
253 | #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ | |
254 | #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ | |
255 | #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ | |
256 | #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ | |
257 | ||
258 | #define CTRL_TS_BITS \ | |
259 | (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ | |
260 | TS_ANNEX_D_EN | TS_LTYPE1_EN) | |
261 | ||
262 | #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) | |
263 | #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) | |
264 | #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) | |
265 | ||
266 | /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ | |
267 | #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ | |
268 | #define TS_SEQ_ID_OFFSET_MASK (0x3f) | |
269 | #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ | |
270 | #define TS_MSG_TYPE_EN_MASK (0xffff) | |
271 | ||
272 | /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ | |
273 | #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) | |
df828598 | 274 | |
2e5b38ab RC |
275 | /* Bit definitions for the CPSW1_TS_CTL register */ |
276 | #define CPSW_V1_TS_RX_EN BIT(0) | |
277 | #define CPSW_V1_TS_TX_EN BIT(4) | |
278 | #define CPSW_V1_MSG_TYPE_OFS 16 | |
279 | ||
280 | /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ | |
281 | #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 | |
282 | ||
df828598 M |
283 | struct cpsw_host_regs { |
284 | u32 max_blks; | |
285 | u32 blk_cnt; | |
d9ba8f9e | 286 | u32 tx_in_ctl; |
df828598 M |
287 | u32 port_vlan; |
288 | u32 tx_pri_map; | |
289 | u32 cpdma_tx_pri_map; | |
290 | u32 cpdma_rx_chan_map; | |
291 | }; | |
292 | ||
293 | struct cpsw_sliver_regs { | |
294 | u32 id_ver; | |
295 | u32 mac_control; | |
296 | u32 mac_status; | |
297 | u32 soft_reset; | |
298 | u32 rx_maxlen; | |
299 | u32 __reserved_0; | |
300 | u32 rx_pause; | |
301 | u32 tx_pause; | |
302 | u32 __reserved_1; | |
303 | u32 rx_pri_map; | |
304 | }; | |
305 | ||
d9718546 M |
306 | struct cpsw_hw_stats { |
307 | u32 rxgoodframes; | |
308 | u32 rxbroadcastframes; | |
309 | u32 rxmulticastframes; | |
310 | u32 rxpauseframes; | |
311 | u32 rxcrcerrors; | |
312 | u32 rxaligncodeerrors; | |
313 | u32 rxoversizedframes; | |
314 | u32 rxjabberframes; | |
315 | u32 rxundersizedframes; | |
316 | u32 rxfragments; | |
317 | u32 __pad_0[2]; | |
318 | u32 rxoctets; | |
319 | u32 txgoodframes; | |
320 | u32 txbroadcastframes; | |
321 | u32 txmulticastframes; | |
322 | u32 txpauseframes; | |
323 | u32 txdeferredframes; | |
324 | u32 txcollisionframes; | |
325 | u32 txsinglecollframes; | |
326 | u32 txmultcollframes; | |
327 | u32 txexcessivecollisions; | |
328 | u32 txlatecollisions; | |
329 | u32 txunderrun; | |
330 | u32 txcarriersenseerrors; | |
331 | u32 txoctets; | |
332 | u32 octetframes64; | |
333 | u32 octetframes65t127; | |
334 | u32 octetframes128t255; | |
335 | u32 octetframes256t511; | |
336 | u32 octetframes512t1023; | |
337 | u32 octetframes1024tup; | |
338 | u32 netoctets; | |
339 | u32 rxsofoverruns; | |
340 | u32 rxmofoverruns; | |
341 | u32 rxdmaoverruns; | |
342 | }; | |
343 | ||
df828598 | 344 | struct cpsw_slave { |
9750a3ad | 345 | void __iomem *regs; |
df828598 M |
346 | struct cpsw_sliver_regs __iomem *sliver; |
347 | int slave_num; | |
348 | u32 mac_control; | |
349 | struct cpsw_slave_data *data; | |
350 | struct phy_device *phy; | |
d9ba8f9e M |
351 | struct net_device *ndev; |
352 | u32 port_vlan; | |
353 | u32 open_stat; | |
df828598 M |
354 | }; |
355 | ||
9750a3ad RC |
356 | static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) |
357 | { | |
358 | return __raw_readl(slave->regs + offset); | |
359 | } | |
360 | ||
361 | static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) | |
362 | { | |
363 | __raw_writel(val, slave->regs + offset); | |
364 | } | |
365 | ||
df828598 M |
366 | struct cpsw_priv { |
367 | spinlock_t lock; | |
368 | struct platform_device *pdev; | |
369 | struct net_device *ndev; | |
df828598 M |
370 | struct napi_struct napi; |
371 | struct device *dev; | |
372 | struct cpsw_platform_data data; | |
996a5c27 RC |
373 | struct cpsw_ss_regs __iomem *regs; |
374 | struct cpsw_wr_regs __iomem *wr_regs; | |
d9718546 | 375 | u8 __iomem *hw_stats; |
df828598 M |
376 | struct cpsw_host_regs __iomem *host_port_regs; |
377 | u32 msg_enable; | |
e90cfac6 | 378 | u32 version; |
ff5b8ef2 M |
379 | u32 coal_intvl; |
380 | u32 bus_freq_mhz; | |
df828598 M |
381 | struct net_device_stats stats; |
382 | int rx_packet_max; | |
383 | int host_port; | |
384 | struct clk *clk; | |
385 | u8 mac_addr[ETH_ALEN]; | |
386 | struct cpsw_slave *slaves; | |
387 | struct cpdma_ctlr *dma; | |
388 | struct cpdma_chan *txch, *rxch; | |
389 | struct cpsw_ale *ale; | |
390 | /* snapshot of IRQ numbers */ | |
391 | u32 irqs_table[4]; | |
392 | u32 num_irqs; | |
a11fbba9 | 393 | bool irq_enabled; |
9232b16d | 394 | struct cpts *cpts; |
d9ba8f9e | 395 | u32 emac_port; |
df828598 M |
396 | }; |
397 | ||
d9718546 M |
398 | struct cpsw_stats { |
399 | char stat_string[ETH_GSTRING_LEN]; | |
400 | int type; | |
401 | int sizeof_stat; | |
402 | int stat_offset; | |
403 | }; | |
404 | ||
405 | enum { | |
406 | CPSW_STATS, | |
407 | CPDMA_RX_STATS, | |
408 | CPDMA_TX_STATS, | |
409 | }; | |
410 | ||
411 | #define CPSW_STAT(m) CPSW_STATS, \ | |
412 | sizeof(((struct cpsw_hw_stats *)0)->m), \ | |
413 | offsetof(struct cpsw_hw_stats, m) | |
414 | #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ | |
415 | sizeof(((struct cpdma_chan_stats *)0)->m), \ | |
416 | offsetof(struct cpdma_chan_stats, m) | |
417 | #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ | |
418 | sizeof(((struct cpdma_chan_stats *)0)->m), \ | |
419 | offsetof(struct cpdma_chan_stats, m) | |
420 | ||
421 | static const struct cpsw_stats cpsw_gstrings_stats[] = { | |
422 | { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, | |
423 | { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, | |
424 | { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, | |
425 | { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, | |
426 | { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, | |
427 | { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, | |
428 | { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, | |
429 | { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, | |
430 | { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, | |
431 | { "Rx Fragments", CPSW_STAT(rxfragments) }, | |
432 | { "Rx Octets", CPSW_STAT(rxoctets) }, | |
433 | { "Good Tx Frames", CPSW_STAT(txgoodframes) }, | |
434 | { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, | |
435 | { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, | |
436 | { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, | |
437 | { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, | |
438 | { "Collisions", CPSW_STAT(txcollisionframes) }, | |
439 | { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, | |
440 | { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, | |
441 | { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, | |
442 | { "Late Collisions", CPSW_STAT(txlatecollisions) }, | |
443 | { "Tx Underrun", CPSW_STAT(txunderrun) }, | |
444 | { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, | |
445 | { "Tx Octets", CPSW_STAT(txoctets) }, | |
446 | { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, | |
447 | { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, | |
448 | { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, | |
449 | { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, | |
450 | { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, | |
451 | { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, | |
452 | { "Net Octets", CPSW_STAT(netoctets) }, | |
453 | { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, | |
454 | { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, | |
455 | { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, | |
456 | { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) }, | |
457 | { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, | |
458 | { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, | |
459 | { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) }, | |
460 | { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, | |
461 | { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, | |
462 | { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, | |
463 | { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, | |
464 | { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, | |
465 | { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, | |
466 | { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) }, | |
467 | { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) }, | |
468 | { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, | |
469 | { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) }, | |
470 | { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) }, | |
471 | { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) }, | |
472 | { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) }, | |
473 | { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) }, | |
474 | { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) }, | |
475 | { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) }, | |
476 | { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) }, | |
477 | { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) }, | |
478 | { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) }, | |
479 | { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) }, | |
480 | { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) }, | |
481 | { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) }, | |
482 | }; | |
483 | ||
484 | #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats) | |
485 | ||
df828598 | 486 | #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) |
d9ba8f9e M |
487 | #define for_each_slave(priv, func, arg...) \ |
488 | do { \ | |
6e6ceaed SS |
489 | struct cpsw_slave *slave; \ |
490 | int n; \ | |
d9ba8f9e M |
491 | if (priv->data.dual_emac) \ |
492 | (func)((priv)->slaves + priv->emac_port, ##arg);\ | |
493 | else \ | |
6e6ceaed SS |
494 | for (n = (priv)->data.slaves, \ |
495 | slave = (priv)->slaves; \ | |
496 | n; n--) \ | |
497 | (func)(slave++, ##arg); \ | |
d9ba8f9e M |
498 | } while (0) |
499 | #define cpsw_get_slave_ndev(priv, __slave_no__) \ | |
500 | (priv->slaves[__slave_no__].ndev) | |
501 | #define cpsw_get_slave_priv(priv, __slave_no__) \ | |
502 | ((priv->slaves[__slave_no__].ndev) ? \ | |
503 | netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ | |
504 | ||
505 | #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ | |
506 | do { \ | |
507 | if (!priv->data.dual_emac) \ | |
508 | break; \ | |
509 | if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ | |
510 | ndev = cpsw_get_slave_ndev(priv, 0); \ | |
511 | priv = netdev_priv(ndev); \ | |
512 | skb->dev = ndev; \ | |
513 | } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ | |
514 | ndev = cpsw_get_slave_ndev(priv, 1); \ | |
515 | priv = netdev_priv(ndev); \ | |
516 | skb->dev = ndev; \ | |
517 | } \ | |
df828598 | 518 | } while (0) |
d9ba8f9e M |
519 | #define cpsw_add_mcast(priv, addr) \ |
520 | do { \ | |
521 | if (priv->data.dual_emac) { \ | |
522 | struct cpsw_slave *slave = priv->slaves + \ | |
523 | priv->emac_port; \ | |
524 | int slave_port = cpsw_get_slave_port(priv, \ | |
525 | slave->slave_num); \ | |
526 | cpsw_ale_add_mcast(priv->ale, addr, \ | |
527 | 1 << slave_port | 1 << priv->host_port, \ | |
528 | ALE_VLAN, slave->port_vlan, 0); \ | |
529 | } else { \ | |
530 | cpsw_ale_add_mcast(priv->ale, addr, \ | |
531 | ALE_ALL_PORTS << priv->host_port, \ | |
532 | 0, 0, 0); \ | |
533 | } \ | |
534 | } while (0) | |
535 | ||
536 | static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) | |
537 | { | |
538 | if (priv->host_port == 0) | |
539 | return slave_num + 1; | |
540 | else | |
541 | return slave_num; | |
542 | } | |
df828598 | 543 | |
0cd8f9cc M |
544 | static void cpsw_set_promiscious(struct net_device *ndev, bool enable) |
545 | { | |
546 | struct cpsw_priv *priv = netdev_priv(ndev); | |
547 | struct cpsw_ale *ale = priv->ale; | |
548 | int i; | |
549 | ||
550 | if (priv->data.dual_emac) { | |
551 | bool flag = false; | |
552 | ||
553 | /* Enabling promiscuous mode for one interface will be | |
554 | * common for both the interface as the interface shares | |
555 | * the same hardware resource. | |
556 | */ | |
0d961b3b | 557 | for (i = 0; i < priv->data.slaves; i++) |
0cd8f9cc M |
558 | if (priv->slaves[i].ndev->flags & IFF_PROMISC) |
559 | flag = true; | |
560 | ||
561 | if (!enable && flag) { | |
562 | enable = true; | |
563 | dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n"); | |
564 | } | |
565 | ||
566 | if (enable) { | |
567 | /* Enable Bypass */ | |
568 | cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1); | |
569 | ||
570 | dev_dbg(&ndev->dev, "promiscuity enabled\n"); | |
571 | } else { | |
572 | /* Disable Bypass */ | |
573 | cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0); | |
574 | dev_dbg(&ndev->dev, "promiscuity disabled\n"); | |
575 | } | |
576 | } else { | |
577 | if (enable) { | |
578 | unsigned long timeout = jiffies + HZ; | |
579 | ||
580 | /* Disable Learn for all ports */ | |
0d961b3b | 581 | for (i = 0; i < priv->data.slaves; i++) { |
0cd8f9cc M |
582 | cpsw_ale_control_set(ale, i, |
583 | ALE_PORT_NOLEARN, 1); | |
584 | cpsw_ale_control_set(ale, i, | |
585 | ALE_PORT_NO_SA_UPDATE, 1); | |
586 | } | |
587 | ||
588 | /* Clear All Untouched entries */ | |
589 | cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); | |
590 | do { | |
591 | cpu_relax(); | |
592 | if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT)) | |
593 | break; | |
594 | } while (time_after(timeout, jiffies)); | |
595 | cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); | |
596 | ||
597 | /* Clear all mcast from ALE */ | |
598 | cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS << | |
599 | priv->host_port); | |
600 | ||
601 | /* Flood All Unicast Packets to Host port */ | |
602 | cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1); | |
603 | dev_dbg(&ndev->dev, "promiscuity enabled\n"); | |
604 | } else { | |
605 | /* Flood All Unicast Packets to Host port */ | |
606 | cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0); | |
607 | ||
608 | /* Enable Learn for all ports */ | |
0d961b3b | 609 | for (i = 0; i < priv->data.slaves; i++) { |
0cd8f9cc M |
610 | cpsw_ale_control_set(ale, i, |
611 | ALE_PORT_NOLEARN, 0); | |
612 | cpsw_ale_control_set(ale, i, | |
613 | ALE_PORT_NO_SA_UPDATE, 0); | |
614 | } | |
615 | dev_dbg(&ndev->dev, "promiscuity disabled\n"); | |
616 | } | |
617 | } | |
618 | } | |
619 | ||
5c50a856 M |
620 | static void cpsw_ndo_set_rx_mode(struct net_device *ndev) |
621 | { | |
622 | struct cpsw_priv *priv = netdev_priv(ndev); | |
623 | ||
624 | if (ndev->flags & IFF_PROMISC) { | |
625 | /* Enable promiscuous mode */ | |
0cd8f9cc | 626 | cpsw_set_promiscious(ndev, true); |
5c50a856 | 627 | return; |
0cd8f9cc M |
628 | } else { |
629 | /* Disable promiscuous mode */ | |
630 | cpsw_set_promiscious(ndev, false); | |
5c50a856 M |
631 | } |
632 | ||
633 | /* Clear all mcast from ALE */ | |
634 | cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); | |
635 | ||
636 | if (!netdev_mc_empty(ndev)) { | |
637 | struct netdev_hw_addr *ha; | |
638 | ||
639 | /* program multicast address list into ALE register */ | |
640 | netdev_for_each_mc_addr(ha, ndev) { | |
d9ba8f9e | 641 | cpsw_add_mcast(priv, (u8 *)ha->addr); |
5c50a856 M |
642 | } |
643 | } | |
644 | } | |
645 | ||
df828598 M |
646 | static void cpsw_intr_enable(struct cpsw_priv *priv) |
647 | { | |
996a5c27 RC |
648 | __raw_writel(0xFF, &priv->wr_regs->tx_en); |
649 | __raw_writel(0xFF, &priv->wr_regs->rx_en); | |
df828598 M |
650 | |
651 | cpdma_ctlr_int_ctrl(priv->dma, true); | |
652 | return; | |
653 | } | |
654 | ||
655 | static void cpsw_intr_disable(struct cpsw_priv *priv) | |
656 | { | |
996a5c27 RC |
657 | __raw_writel(0, &priv->wr_regs->tx_en); |
658 | __raw_writel(0, &priv->wr_regs->rx_en); | |
df828598 M |
659 | |
660 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
661 | return; | |
662 | } | |
663 | ||
1a3b5056 | 664 | static void cpsw_tx_handler(void *token, int len, int status) |
df828598 M |
665 | { |
666 | struct sk_buff *skb = token; | |
667 | struct net_device *ndev = skb->dev; | |
668 | struct cpsw_priv *priv = netdev_priv(ndev); | |
669 | ||
fae50823 M |
670 | /* Check whether the queue is stopped due to stalled tx dma, if the |
671 | * queue is stopped then start the queue as we have free desc for tx | |
672 | */ | |
df828598 | 673 | if (unlikely(netif_queue_stopped(ndev))) |
b56d6b3f | 674 | netif_wake_queue(ndev); |
9232b16d | 675 | cpts_tx_timestamp(priv->cpts, skb); |
df828598 M |
676 | priv->stats.tx_packets++; |
677 | priv->stats.tx_bytes += len; | |
678 | dev_kfree_skb_any(skb); | |
679 | } | |
680 | ||
1a3b5056 | 681 | static void cpsw_rx_handler(void *token, int len, int status) |
df828598 M |
682 | { |
683 | struct sk_buff *skb = token; | |
b4727e69 | 684 | struct sk_buff *new_skb; |
df828598 M |
685 | struct net_device *ndev = skb->dev; |
686 | struct cpsw_priv *priv = netdev_priv(ndev); | |
687 | int ret = 0; | |
688 | ||
d9ba8f9e M |
689 | cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); |
690 | ||
b4727e69 SS |
691 | if (unlikely(status < 0)) { |
692 | /* the interface is going down, skbs are purged */ | |
df828598 M |
693 | dev_kfree_skb_any(skb); |
694 | return; | |
695 | } | |
b4727e69 SS |
696 | |
697 | new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); | |
698 | if (new_skb) { | |
df828598 | 699 | skb_put(skb, len); |
9232b16d | 700 | cpts_rx_timestamp(priv->cpts, skb); |
df828598 M |
701 | skb->protocol = eth_type_trans(skb, ndev); |
702 | netif_receive_skb(skb); | |
703 | priv->stats.rx_bytes += len; | |
704 | priv->stats.rx_packets++; | |
b4727e69 SS |
705 | } else { |
706 | priv->stats.rx_dropped++; | |
707 | new_skb = skb; | |
df828598 M |
708 | } |
709 | ||
b4727e69 SS |
710 | ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, |
711 | skb_tailroom(new_skb), 0); | |
712 | if (WARN_ON(ret < 0)) | |
713 | dev_kfree_skb_any(new_skb); | |
df828598 M |
714 | } |
715 | ||
716 | static irqreturn_t cpsw_interrupt(int irq, void *dev_id) | |
717 | { | |
718 | struct cpsw_priv *priv = dev_id; | |
fd51cf19 SS |
719 | |
720 | cpsw_intr_disable(priv); | |
a11fbba9 SS |
721 | if (priv->irq_enabled == true) { |
722 | cpsw_disable_irq(priv); | |
723 | priv->irq_enabled = false; | |
724 | } | |
fd51cf19 SS |
725 | |
726 | if (netif_running(priv->ndev)) { | |
df828598 | 727 | napi_schedule(&priv->napi); |
fd51cf19 SS |
728 | return IRQ_HANDLED; |
729 | } | |
730 | ||
731 | priv = cpsw_get_slave_priv(priv, 1); | |
732 | if (!priv) | |
733 | return IRQ_NONE; | |
734 | ||
735 | if (netif_running(priv->ndev)) { | |
736 | napi_schedule(&priv->napi); | |
737 | return IRQ_HANDLED; | |
df828598 | 738 | } |
fd51cf19 | 739 | return IRQ_NONE; |
df828598 M |
740 | } |
741 | ||
df828598 M |
742 | static int cpsw_poll(struct napi_struct *napi, int budget) |
743 | { | |
744 | struct cpsw_priv *priv = napi_to_priv(napi); | |
745 | int num_tx, num_rx; | |
746 | ||
747 | num_tx = cpdma_chan_process(priv->txch, 128); | |
510a1e72 M |
748 | if (num_tx) |
749 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); | |
df828598 | 750 | |
510a1e72 | 751 | num_rx = cpdma_chan_process(priv->rxch, budget); |
df828598 | 752 | if (num_rx < budget) { |
a11fbba9 SS |
753 | struct cpsw_priv *prim_cpsw; |
754 | ||
df828598 M |
755 | napi_complete(napi); |
756 | cpsw_intr_enable(priv); | |
510a1e72 | 757 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); |
a11fbba9 SS |
758 | prim_cpsw = cpsw_get_slave_priv(priv, 0); |
759 | if (prim_cpsw->irq_enabled == false) { | |
a11fbba9 | 760 | prim_cpsw->irq_enabled = true; |
af5c6df7 | 761 | cpsw_enable_irq(priv); |
a11fbba9 | 762 | } |
df828598 M |
763 | } |
764 | ||
510a1e72 M |
765 | if (num_rx || num_tx) |
766 | cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", | |
767 | num_rx, num_tx); | |
768 | ||
df828598 M |
769 | return num_rx; |
770 | } | |
771 | ||
772 | static inline void soft_reset(const char *module, void __iomem *reg) | |
773 | { | |
774 | unsigned long timeout = jiffies + HZ; | |
775 | ||
776 | __raw_writel(1, reg); | |
777 | do { | |
778 | cpu_relax(); | |
779 | } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); | |
780 | ||
781 | WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); | |
782 | } | |
783 | ||
784 | #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ | |
785 | ((mac)[2] << 16) | ((mac)[3] << 24)) | |
786 | #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) | |
787 | ||
788 | static void cpsw_set_slave_mac(struct cpsw_slave *slave, | |
789 | struct cpsw_priv *priv) | |
790 | { | |
9750a3ad RC |
791 | slave_write(slave, mac_hi(priv->mac_addr), SA_HI); |
792 | slave_write(slave, mac_lo(priv->mac_addr), SA_LO); | |
df828598 M |
793 | } |
794 | ||
795 | static void _cpsw_adjust_link(struct cpsw_slave *slave, | |
796 | struct cpsw_priv *priv, bool *link) | |
797 | { | |
798 | struct phy_device *phy = slave->phy; | |
799 | u32 mac_control = 0; | |
800 | u32 slave_port; | |
801 | ||
802 | if (!phy) | |
803 | return; | |
804 | ||
805 | slave_port = cpsw_get_slave_port(priv, slave->slave_num); | |
806 | ||
807 | if (phy->link) { | |
808 | mac_control = priv->data.mac_control; | |
809 | ||
810 | /* enable forwarding */ | |
811 | cpsw_ale_control_set(priv->ale, slave_port, | |
812 | ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); | |
813 | ||
814 | if (phy->speed == 1000) | |
815 | mac_control |= BIT(7); /* GIGABITEN */ | |
816 | if (phy->duplex) | |
817 | mac_control |= BIT(0); /* FULLDUPLEXEN */ | |
342b7b74 DM |
818 | |
819 | /* set speed_in input in case RMII mode is used in 100Mbps */ | |
820 | if (phy->speed == 100) | |
821 | mac_control |= BIT(15); | |
a81d8762 M |
822 | else if (phy->speed == 10) |
823 | mac_control |= BIT(18); /* In Band mode */ | |
342b7b74 | 824 | |
df828598 M |
825 | *link = true; |
826 | } else { | |
827 | mac_control = 0; | |
828 | /* disable forwarding */ | |
829 | cpsw_ale_control_set(priv->ale, slave_port, | |
830 | ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); | |
831 | } | |
832 | ||
833 | if (mac_control != slave->mac_control) { | |
834 | phy_print_status(phy); | |
835 | __raw_writel(mac_control, &slave->sliver->mac_control); | |
836 | } | |
837 | ||
838 | slave->mac_control = mac_control; | |
839 | } | |
840 | ||
841 | static void cpsw_adjust_link(struct net_device *ndev) | |
842 | { | |
843 | struct cpsw_priv *priv = netdev_priv(ndev); | |
844 | bool link = false; | |
845 | ||
846 | for_each_slave(priv, _cpsw_adjust_link, priv, &link); | |
847 | ||
848 | if (link) { | |
849 | netif_carrier_on(ndev); | |
850 | if (netif_running(ndev)) | |
851 | netif_wake_queue(ndev); | |
852 | } else { | |
853 | netif_carrier_off(ndev); | |
854 | netif_stop_queue(ndev); | |
855 | } | |
856 | } | |
857 | ||
ff5b8ef2 M |
858 | static int cpsw_get_coalesce(struct net_device *ndev, |
859 | struct ethtool_coalesce *coal) | |
860 | { | |
861 | struct cpsw_priv *priv = netdev_priv(ndev); | |
862 | ||
863 | coal->rx_coalesce_usecs = priv->coal_intvl; | |
864 | return 0; | |
865 | } | |
866 | ||
867 | static int cpsw_set_coalesce(struct net_device *ndev, | |
868 | struct ethtool_coalesce *coal) | |
869 | { | |
870 | struct cpsw_priv *priv = netdev_priv(ndev); | |
871 | u32 int_ctrl; | |
872 | u32 num_interrupts = 0; | |
873 | u32 prescale = 0; | |
874 | u32 addnl_dvdr = 1; | |
875 | u32 coal_intvl = 0; | |
876 | ||
877 | if (!coal->rx_coalesce_usecs) | |
878 | return -EINVAL; | |
879 | ||
880 | coal_intvl = coal->rx_coalesce_usecs; | |
881 | ||
882 | int_ctrl = readl(&priv->wr_regs->int_control); | |
883 | prescale = priv->bus_freq_mhz * 4; | |
884 | ||
885 | if (coal_intvl < CPSW_CMINTMIN_INTVL) | |
886 | coal_intvl = CPSW_CMINTMIN_INTVL; | |
887 | ||
888 | if (coal_intvl > CPSW_CMINTMAX_INTVL) { | |
889 | /* Interrupt pacer works with 4us Pulse, we can | |
890 | * throttle further by dilating the 4us pulse. | |
891 | */ | |
892 | addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; | |
893 | ||
894 | if (addnl_dvdr > 1) { | |
895 | prescale *= addnl_dvdr; | |
896 | if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) | |
897 | coal_intvl = (CPSW_CMINTMAX_INTVL | |
898 | * addnl_dvdr); | |
899 | } else { | |
900 | addnl_dvdr = 1; | |
901 | coal_intvl = CPSW_CMINTMAX_INTVL; | |
902 | } | |
903 | } | |
904 | ||
905 | num_interrupts = (1000 * addnl_dvdr) / coal_intvl; | |
906 | writel(num_interrupts, &priv->wr_regs->rx_imax); | |
907 | writel(num_interrupts, &priv->wr_regs->tx_imax); | |
908 | ||
909 | int_ctrl |= CPSW_INTPACEEN; | |
910 | int_ctrl &= (~CPSW_INTPRESCALE_MASK); | |
911 | int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); | |
912 | writel(int_ctrl, &priv->wr_regs->int_control); | |
913 | ||
914 | cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); | |
915 | if (priv->data.dual_emac) { | |
916 | int i; | |
917 | ||
918 | for (i = 0; i < priv->data.slaves; i++) { | |
919 | priv = netdev_priv(priv->slaves[i].ndev); | |
920 | priv->coal_intvl = coal_intvl; | |
921 | } | |
922 | } else { | |
923 | priv->coal_intvl = coal_intvl; | |
924 | } | |
925 | ||
926 | return 0; | |
927 | } | |
928 | ||
d9718546 M |
929 | static int cpsw_get_sset_count(struct net_device *ndev, int sset) |
930 | { | |
931 | switch (sset) { | |
932 | case ETH_SS_STATS: | |
933 | return CPSW_STATS_LEN; | |
934 | default: | |
935 | return -EOPNOTSUPP; | |
936 | } | |
937 | } | |
938 | ||
939 | static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) | |
940 | { | |
941 | u8 *p = data; | |
942 | int i; | |
943 | ||
944 | switch (stringset) { | |
945 | case ETH_SS_STATS: | |
946 | for (i = 0; i < CPSW_STATS_LEN; i++) { | |
947 | memcpy(p, cpsw_gstrings_stats[i].stat_string, | |
948 | ETH_GSTRING_LEN); | |
949 | p += ETH_GSTRING_LEN; | |
950 | } | |
951 | break; | |
952 | } | |
953 | } | |
954 | ||
955 | static void cpsw_get_ethtool_stats(struct net_device *ndev, | |
956 | struct ethtool_stats *stats, u64 *data) | |
957 | { | |
958 | struct cpsw_priv *priv = netdev_priv(ndev); | |
959 | struct cpdma_chan_stats rx_stats; | |
960 | struct cpdma_chan_stats tx_stats; | |
961 | u32 val; | |
962 | u8 *p; | |
963 | int i; | |
964 | ||
965 | /* Collect Davinci CPDMA stats for Rx and Tx Channel */ | |
966 | cpdma_chan_get_stats(priv->rxch, &rx_stats); | |
967 | cpdma_chan_get_stats(priv->txch, &tx_stats); | |
968 | ||
969 | for (i = 0; i < CPSW_STATS_LEN; i++) { | |
970 | switch (cpsw_gstrings_stats[i].type) { | |
971 | case CPSW_STATS: | |
972 | val = readl(priv->hw_stats + | |
973 | cpsw_gstrings_stats[i].stat_offset); | |
974 | data[i] = val; | |
975 | break; | |
976 | ||
977 | case CPDMA_RX_STATS: | |
978 | p = (u8 *)&rx_stats + | |
979 | cpsw_gstrings_stats[i].stat_offset; | |
980 | data[i] = *(u32 *)p; | |
981 | break; | |
982 | ||
983 | case CPDMA_TX_STATS: | |
984 | p = (u8 *)&tx_stats + | |
985 | cpsw_gstrings_stats[i].stat_offset; | |
986 | data[i] = *(u32 *)p; | |
987 | break; | |
988 | } | |
989 | } | |
990 | } | |
991 | ||
df828598 M |
992 | static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) |
993 | { | |
994 | static char *leader = "........................................"; | |
995 | ||
996 | if (!val) | |
997 | return 0; | |
998 | else | |
999 | return snprintf(buf, maxlen, "%s %s %10d\n", name, | |
1000 | leader + strlen(name), val); | |
1001 | } | |
1002 | ||
d9ba8f9e M |
1003 | static int cpsw_common_res_usage_state(struct cpsw_priv *priv) |
1004 | { | |
1005 | u32 i; | |
1006 | u32 usage_count = 0; | |
1007 | ||
1008 | if (!priv->data.dual_emac) | |
1009 | return 0; | |
1010 | ||
1011 | for (i = 0; i < priv->data.slaves; i++) | |
1012 | if (priv->slaves[i].open_stat) | |
1013 | usage_count++; | |
1014 | ||
1015 | return usage_count; | |
1016 | } | |
1017 | ||
1018 | static inline int cpsw_tx_packet_submit(struct net_device *ndev, | |
1019 | struct cpsw_priv *priv, struct sk_buff *skb) | |
1020 | { | |
1021 | if (!priv->data.dual_emac) | |
1022 | return cpdma_chan_submit(priv->txch, skb, skb->data, | |
aef614e1 | 1023 | skb->len, 0); |
d9ba8f9e M |
1024 | |
1025 | if (ndev == cpsw_get_slave_ndev(priv, 0)) | |
1026 | return cpdma_chan_submit(priv->txch, skb, skb->data, | |
aef614e1 | 1027 | skb->len, 1); |
d9ba8f9e M |
1028 | else |
1029 | return cpdma_chan_submit(priv->txch, skb, skb->data, | |
aef614e1 | 1030 | skb->len, 2); |
d9ba8f9e M |
1031 | } |
1032 | ||
1033 | static inline void cpsw_add_dual_emac_def_ale_entries( | |
1034 | struct cpsw_priv *priv, struct cpsw_slave *slave, | |
1035 | u32 slave_port) | |
1036 | { | |
1037 | u32 port_mask = 1 << slave_port | 1 << priv->host_port; | |
1038 | ||
1039 | if (priv->version == CPSW_VERSION_1) | |
1040 | slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); | |
1041 | else | |
1042 | slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); | |
1043 | cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, | |
1044 | port_mask, port_mask, 0); | |
1045 | cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, | |
1046 | port_mask, ALE_VLAN, slave->port_vlan, 0); | |
1047 | cpsw_ale_add_ucast(priv->ale, priv->mac_addr, | |
1048 | priv->host_port, ALE_VLAN, slave->port_vlan); | |
1049 | } | |
1050 | ||
1e7a2e21 | 1051 | static void soft_reset_slave(struct cpsw_slave *slave) |
df828598 M |
1052 | { |
1053 | char name[32]; | |
df828598 | 1054 | |
1e7a2e21 | 1055 | snprintf(name, sizeof(name), "slave-%d", slave->slave_num); |
df828598 | 1056 | soft_reset(name, &slave->sliver->soft_reset); |
1e7a2e21 DM |
1057 | } |
1058 | ||
1059 | static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) | |
1060 | { | |
1061 | u32 slave_port; | |
1062 | ||
1063 | soft_reset_slave(slave); | |
df828598 M |
1064 | |
1065 | /* setup priority mapping */ | |
1066 | __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); | |
9750a3ad RC |
1067 | |
1068 | switch (priv->version) { | |
1069 | case CPSW_VERSION_1: | |
1070 | slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); | |
1071 | break; | |
1072 | case CPSW_VERSION_2: | |
c193f365 | 1073 | case CPSW_VERSION_3: |
926489be | 1074 | case CPSW_VERSION_4: |
9750a3ad RC |
1075 | slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); |
1076 | break; | |
1077 | } | |
df828598 M |
1078 | |
1079 | /* setup max packet size, and mac address */ | |
1080 | __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); | |
1081 | cpsw_set_slave_mac(slave, priv); | |
1082 | ||
1083 | slave->mac_control = 0; /* no link yet */ | |
1084 | ||
1085 | slave_port = cpsw_get_slave_port(priv, slave->slave_num); | |
1086 | ||
d9ba8f9e M |
1087 | if (priv->data.dual_emac) |
1088 | cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); | |
1089 | else | |
1090 | cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, | |
1091 | 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); | |
df828598 M |
1092 | |
1093 | slave->phy = phy_connect(priv->ndev, slave->data->phy_id, | |
f9a8f83b | 1094 | &cpsw_adjust_link, slave->data->phy_if); |
df828598 M |
1095 | if (IS_ERR(slave->phy)) { |
1096 | dev_err(priv->dev, "phy %s not found on slave %d\n", | |
1097 | slave->data->phy_id, slave->slave_num); | |
1098 | slave->phy = NULL; | |
1099 | } else { | |
1100 | dev_info(priv->dev, "phy found : id is : 0x%x\n", | |
1101 | slave->phy->phy_id); | |
1102 | phy_start(slave->phy); | |
388367a5 M |
1103 | |
1104 | /* Configure GMII_SEL register */ | |
1105 | cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, | |
1106 | slave->slave_num); | |
df828598 M |
1107 | } |
1108 | } | |
1109 | ||
3b72c2fe M |
1110 | static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) |
1111 | { | |
1112 | const int vlan = priv->data.default_vlan; | |
1113 | const int port = priv->host_port; | |
1114 | u32 reg; | |
1115 | int i; | |
1116 | ||
1117 | reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : | |
1118 | CPSW2_PORT_VLAN; | |
1119 | ||
1120 | writel(vlan, &priv->host_port_regs->port_vlan); | |
1121 | ||
0237c110 | 1122 | for (i = 0; i < priv->data.slaves; i++) |
3b72c2fe M |
1123 | slave_write(priv->slaves + i, vlan, reg); |
1124 | ||
1125 | cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, | |
1126 | ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, | |
1127 | (ALE_PORT_1 | ALE_PORT_2) << port); | |
1128 | } | |
1129 | ||
df828598 M |
1130 | static void cpsw_init_host_port(struct cpsw_priv *priv) |
1131 | { | |
3b72c2fe | 1132 | u32 control_reg; |
d9ba8f9e | 1133 | u32 fifo_mode; |
3b72c2fe | 1134 | |
df828598 M |
1135 | /* soft reset the controller and initialize ale */ |
1136 | soft_reset("cpsw", &priv->regs->soft_reset); | |
1137 | cpsw_ale_start(priv->ale); | |
1138 | ||
1139 | /* switch to vlan unaware mode */ | |
3b72c2fe M |
1140 | cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, |
1141 | CPSW_ALE_VLAN_AWARE); | |
1142 | control_reg = readl(&priv->regs->control); | |
1143 | control_reg |= CPSW_VLAN_AWARE; | |
1144 | writel(control_reg, &priv->regs->control); | |
d9ba8f9e M |
1145 | fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : |
1146 | CPSW_FIFO_NORMAL_MODE; | |
1147 | writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); | |
df828598 M |
1148 | |
1149 | /* setup host port priority mapping */ | |
1150 | __raw_writel(CPDMA_TX_PRIORITY_MAP, | |
1151 | &priv->host_port_regs->cpdma_tx_pri_map); | |
1152 | __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); | |
1153 | ||
1154 | cpsw_ale_control_set(priv->ale, priv->host_port, | |
1155 | ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); | |
1156 | ||
d9ba8f9e M |
1157 | if (!priv->data.dual_emac) { |
1158 | cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, | |
1159 | 0, 0); | |
1160 | cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, | |
1161 | 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); | |
1162 | } | |
df828598 M |
1163 | } |
1164 | ||
aacebbf8 SS |
1165 | static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) |
1166 | { | |
3995d265 SP |
1167 | u32 slave_port; |
1168 | ||
1169 | slave_port = cpsw_get_slave_port(priv, slave->slave_num); | |
1170 | ||
aacebbf8 SS |
1171 | if (!slave->phy) |
1172 | return; | |
1173 | phy_stop(slave->phy); | |
1174 | phy_disconnect(slave->phy); | |
1175 | slave->phy = NULL; | |
3995d265 SP |
1176 | cpsw_ale_control_set(priv->ale, slave_port, |
1177 | ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); | |
aacebbf8 SS |
1178 | } |
1179 | ||
df828598 M |
1180 | static int cpsw_ndo_open(struct net_device *ndev) |
1181 | { | |
1182 | struct cpsw_priv *priv = netdev_priv(ndev); | |
a11fbba9 | 1183 | struct cpsw_priv *prim_cpsw; |
df828598 M |
1184 | int i, ret; |
1185 | u32 reg; | |
1186 | ||
d9ba8f9e M |
1187 | if (!cpsw_common_res_usage_state(priv)) |
1188 | cpsw_intr_disable(priv); | |
df828598 M |
1189 | netif_carrier_off(ndev); |
1190 | ||
f150bd7f | 1191 | pm_runtime_get_sync(&priv->pdev->dev); |
df828598 | 1192 | |
549985ee | 1193 | reg = priv->version; |
df828598 M |
1194 | |
1195 | dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", | |
1196 | CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), | |
1197 | CPSW_RTL_VERSION(reg)); | |
1198 | ||
1199 | /* initialize host and slave ports */ | |
d9ba8f9e M |
1200 | if (!cpsw_common_res_usage_state(priv)) |
1201 | cpsw_init_host_port(priv); | |
df828598 M |
1202 | for_each_slave(priv, cpsw_slave_open, priv); |
1203 | ||
3b72c2fe | 1204 | /* Add default VLAN */ |
d9ba8f9e M |
1205 | if (!priv->data.dual_emac) |
1206 | cpsw_add_default_vlan(priv); | |
3b72c2fe | 1207 | |
d9ba8f9e M |
1208 | if (!cpsw_common_res_usage_state(priv)) { |
1209 | /* setup tx dma to fixed prio and zero offset */ | |
1210 | cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); | |
1211 | cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); | |
df828598 | 1212 | |
d9ba8f9e M |
1213 | /* disable priority elevation */ |
1214 | __raw_writel(0, &priv->regs->ptype); | |
df828598 | 1215 | |
d9ba8f9e M |
1216 | /* enable statistics collection only on all ports */ |
1217 | __raw_writel(0x7, &priv->regs->stat_port_en); | |
df828598 | 1218 | |
d9ba8f9e M |
1219 | if (WARN_ON(!priv->data.rx_descs)) |
1220 | priv->data.rx_descs = 128; | |
df828598 | 1221 | |
d9ba8f9e M |
1222 | for (i = 0; i < priv->data.rx_descs; i++) { |
1223 | struct sk_buff *skb; | |
df828598 | 1224 | |
d9ba8f9e | 1225 | ret = -ENOMEM; |
aacebbf8 SS |
1226 | skb = __netdev_alloc_skb_ip_align(priv->ndev, |
1227 | priv->rx_packet_max, GFP_KERNEL); | |
d9ba8f9e | 1228 | if (!skb) |
aacebbf8 | 1229 | goto err_cleanup; |
d9ba8f9e | 1230 | ret = cpdma_chan_submit(priv->rxch, skb, skb->data, |
aef614e1 | 1231 | skb_tailroom(skb), 0); |
aacebbf8 SS |
1232 | if (ret < 0) { |
1233 | kfree_skb(skb); | |
1234 | goto err_cleanup; | |
1235 | } | |
d9ba8f9e M |
1236 | } |
1237 | /* continue even if we didn't manage to submit all | |
1238 | * receive descs | |
1239 | */ | |
1240 | cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); | |
f280e89a M |
1241 | |
1242 | if (cpts_register(&priv->pdev->dev, priv->cpts, | |
1243 | priv->data.cpts_clock_mult, | |
1244 | priv->data.cpts_clock_shift)) | |
1245 | dev_err(priv->dev, "error registering cpts device\n"); | |
1246 | ||
df828598 | 1247 | } |
df828598 | 1248 | |
ff5b8ef2 M |
1249 | /* Enable Interrupt pacing if configured */ |
1250 | if (priv->coal_intvl != 0) { | |
1251 | struct ethtool_coalesce coal; | |
1252 | ||
1253 | coal.rx_coalesce_usecs = (priv->coal_intvl << 4); | |
1254 | cpsw_set_coalesce(ndev, &coal); | |
1255 | } | |
1256 | ||
a11fbba9 SS |
1257 | prim_cpsw = cpsw_get_slave_priv(priv, 0); |
1258 | if (prim_cpsw->irq_enabled == false) { | |
1259 | if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) { | |
1260 | prim_cpsw->irq_enabled = true; | |
1261 | cpsw_enable_irq(prim_cpsw); | |
1262 | } | |
1263 | } | |
1264 | ||
dbbd2ad8 | 1265 | napi_enable(&priv->napi); |
df828598 M |
1266 | cpdma_ctlr_start(priv->dma); |
1267 | cpsw_intr_enable(priv); | |
510a1e72 M |
1268 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); |
1269 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); | |
df828598 | 1270 | |
d9ba8f9e M |
1271 | if (priv->data.dual_emac) |
1272 | priv->slaves[priv->emac_port].open_stat = true; | |
df828598 | 1273 | return 0; |
df828598 | 1274 | |
aacebbf8 SS |
1275 | err_cleanup: |
1276 | cpdma_ctlr_stop(priv->dma); | |
1277 | for_each_slave(priv, cpsw_slave_stop, priv); | |
1278 | pm_runtime_put_sync(&priv->pdev->dev); | |
1279 | netif_carrier_off(priv->ndev); | |
1280 | return ret; | |
df828598 M |
1281 | } |
1282 | ||
1283 | static int cpsw_ndo_stop(struct net_device *ndev) | |
1284 | { | |
1285 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1286 | ||
1287 | cpsw_info(priv, ifdown, "shutting down cpsw device\n"); | |
df828598 M |
1288 | netif_stop_queue(priv->ndev); |
1289 | napi_disable(&priv->napi); | |
1290 | netif_carrier_off(priv->ndev); | |
d9ba8f9e M |
1291 | |
1292 | if (cpsw_common_res_usage_state(priv) <= 1) { | |
f280e89a | 1293 | cpts_unregister(priv->cpts); |
d9ba8f9e M |
1294 | cpsw_intr_disable(priv); |
1295 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
1296 | cpdma_ctlr_stop(priv->dma); | |
1297 | cpsw_ale_stop(priv->ale); | |
1298 | } | |
df828598 | 1299 | for_each_slave(priv, cpsw_slave_stop, priv); |
f150bd7f | 1300 | pm_runtime_put_sync(&priv->pdev->dev); |
d9ba8f9e M |
1301 | if (priv->data.dual_emac) |
1302 | priv->slaves[priv->emac_port].open_stat = false; | |
df828598 M |
1303 | return 0; |
1304 | } | |
1305 | ||
1306 | static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, | |
1307 | struct net_device *ndev) | |
1308 | { | |
1309 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1310 | int ret; | |
1311 | ||
1312 | ndev->trans_start = jiffies; | |
1313 | ||
1314 | if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { | |
1315 | cpsw_err(priv, tx_err, "packet pad failed\n"); | |
1316 | priv->stats.tx_dropped++; | |
1317 | return NETDEV_TX_OK; | |
1318 | } | |
1319 | ||
9232b16d M |
1320 | if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && |
1321 | priv->cpts->tx_enable) | |
2e5b38ab RC |
1322 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
1323 | ||
1324 | skb_tx_timestamp(skb); | |
1325 | ||
d9ba8f9e | 1326 | ret = cpsw_tx_packet_submit(ndev, priv, skb); |
df828598 M |
1327 | if (unlikely(ret != 0)) { |
1328 | cpsw_err(priv, tx_err, "desc submit failed\n"); | |
1329 | goto fail; | |
1330 | } | |
1331 | ||
fae50823 M |
1332 | /* If there is no more tx desc left free then we need to |
1333 | * tell the kernel to stop sending us tx frames. | |
1334 | */ | |
d35162f8 | 1335 | if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) |
fae50823 M |
1336 | netif_stop_queue(ndev); |
1337 | ||
df828598 M |
1338 | return NETDEV_TX_OK; |
1339 | fail: | |
1340 | priv->stats.tx_dropped++; | |
1341 | netif_stop_queue(ndev); | |
1342 | return NETDEV_TX_BUSY; | |
1343 | } | |
1344 | ||
2e5b38ab RC |
1345 | #ifdef CONFIG_TI_CPTS |
1346 | ||
1347 | static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) | |
1348 | { | |
e86ac13b | 1349 | struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; |
2e5b38ab RC |
1350 | u32 ts_en, seq_id; |
1351 | ||
9232b16d | 1352 | if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { |
2e5b38ab RC |
1353 | slave_write(slave, 0, CPSW1_TS_CTL); |
1354 | return; | |
1355 | } | |
1356 | ||
1357 | seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; | |
1358 | ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; | |
1359 | ||
9232b16d | 1360 | if (priv->cpts->tx_enable) |
2e5b38ab RC |
1361 | ts_en |= CPSW_V1_TS_TX_EN; |
1362 | ||
9232b16d | 1363 | if (priv->cpts->rx_enable) |
2e5b38ab RC |
1364 | ts_en |= CPSW_V1_TS_RX_EN; |
1365 | ||
1366 | slave_write(slave, ts_en, CPSW1_TS_CTL); | |
1367 | slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); | |
1368 | } | |
1369 | ||
1370 | static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) | |
1371 | { | |
d9ba8f9e | 1372 | struct cpsw_slave *slave; |
2e5b38ab RC |
1373 | u32 ctrl, mtype; |
1374 | ||
d9ba8f9e M |
1375 | if (priv->data.dual_emac) |
1376 | slave = &priv->slaves[priv->emac_port]; | |
1377 | else | |
e86ac13b | 1378 | slave = &priv->slaves[priv->data.active_slave]; |
d9ba8f9e | 1379 | |
2e5b38ab RC |
1380 | ctrl = slave_read(slave, CPSW2_CONTROL); |
1381 | ctrl &= ~CTRL_ALL_TS_MASK; | |
1382 | ||
9232b16d | 1383 | if (priv->cpts->tx_enable) |
2e5b38ab RC |
1384 | ctrl |= CTRL_TX_TS_BITS; |
1385 | ||
9232b16d | 1386 | if (priv->cpts->rx_enable) |
2e5b38ab RC |
1387 | ctrl |= CTRL_RX_TS_BITS; |
1388 | ||
1389 | mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; | |
1390 | ||
1391 | slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); | |
1392 | slave_write(slave, ctrl, CPSW2_CONTROL); | |
1393 | __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); | |
1394 | } | |
1395 | ||
a5b4145b | 1396 | static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) |
2e5b38ab | 1397 | { |
3177bf6f | 1398 | struct cpsw_priv *priv = netdev_priv(dev); |
9232b16d | 1399 | struct cpts *cpts = priv->cpts; |
2e5b38ab RC |
1400 | struct hwtstamp_config cfg; |
1401 | ||
2ee91e54 BH |
1402 | if (priv->version != CPSW_VERSION_1 && |
1403 | priv->version != CPSW_VERSION_2) | |
1404 | return -EOPNOTSUPP; | |
1405 | ||
2e5b38ab RC |
1406 | if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) |
1407 | return -EFAULT; | |
1408 | ||
1409 | /* reserved for future extensions */ | |
1410 | if (cfg.flags) | |
1411 | return -EINVAL; | |
1412 | ||
2ee91e54 | 1413 | if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) |
2e5b38ab | 1414 | return -ERANGE; |
2e5b38ab RC |
1415 | |
1416 | switch (cfg.rx_filter) { | |
1417 | case HWTSTAMP_FILTER_NONE: | |
1418 | cpts->rx_enable = 0; | |
1419 | break; | |
1420 | case HWTSTAMP_FILTER_ALL: | |
1421 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
1422 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
1423 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
1424 | return -ERANGE; | |
1425 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
1426 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
1427 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
1428 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
1429 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
1430 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
1431 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
1432 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
1433 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
1434 | cpts->rx_enable = 1; | |
1435 | cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
1436 | break; | |
1437 | default: | |
1438 | return -ERANGE; | |
1439 | } | |
1440 | ||
2ee91e54 BH |
1441 | cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON; |
1442 | ||
2e5b38ab RC |
1443 | switch (priv->version) { |
1444 | case CPSW_VERSION_1: | |
1445 | cpsw_hwtstamp_v1(priv); | |
1446 | break; | |
1447 | case CPSW_VERSION_2: | |
1448 | cpsw_hwtstamp_v2(priv); | |
1449 | break; | |
1450 | default: | |
2ee91e54 | 1451 | WARN_ON(1); |
2e5b38ab RC |
1452 | } |
1453 | ||
1454 | return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; | |
1455 | } | |
1456 | ||
a5b4145b BH |
1457 | static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) |
1458 | { | |
1459 | struct cpsw_priv *priv = netdev_priv(dev); | |
1460 | struct cpts *cpts = priv->cpts; | |
1461 | struct hwtstamp_config cfg; | |
1462 | ||
1463 | if (priv->version != CPSW_VERSION_1 && | |
1464 | priv->version != CPSW_VERSION_2) | |
1465 | return -EOPNOTSUPP; | |
1466 | ||
1467 | cfg.flags = 0; | |
1468 | cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; | |
1469 | cfg.rx_filter = (cpts->rx_enable ? | |
1470 | HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE); | |
1471 | ||
1472 | return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; | |
1473 | } | |
1474 | ||
2e5b38ab RC |
1475 | #endif /*CONFIG_TI_CPTS*/ |
1476 | ||
1477 | static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) | |
1478 | { | |
11f2c988 M |
1479 | struct cpsw_priv *priv = netdev_priv(dev); |
1480 | struct mii_ioctl_data *data = if_mii(req); | |
1481 | int slave_no = cpsw_slave_index(priv); | |
1482 | ||
2e5b38ab RC |
1483 | if (!netif_running(dev)) |
1484 | return -EINVAL; | |
1485 | ||
11f2c988 | 1486 | switch (cmd) { |
2e5b38ab | 1487 | #ifdef CONFIG_TI_CPTS |
11f2c988 | 1488 | case SIOCSHWTSTAMP: |
a5b4145b BH |
1489 | return cpsw_hwtstamp_set(dev, req); |
1490 | case SIOCGHWTSTAMP: | |
1491 | return cpsw_hwtstamp_get(dev, req); | |
2e5b38ab | 1492 | #endif |
11f2c988 M |
1493 | case SIOCGMIIPHY: |
1494 | data->phy_id = priv->slaves[slave_no].phy->addr; | |
1495 | break; | |
1496 | default: | |
1497 | return -ENOTSUPP; | |
1498 | } | |
1499 | ||
1500 | return 0; | |
2e5b38ab RC |
1501 | } |
1502 | ||
df828598 M |
1503 | static void cpsw_ndo_tx_timeout(struct net_device *ndev) |
1504 | { | |
1505 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1506 | ||
1507 | cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); | |
1508 | priv->stats.tx_errors++; | |
1509 | cpsw_intr_disable(priv); | |
1510 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
1511 | cpdma_chan_stop(priv->txch); | |
1512 | cpdma_chan_start(priv->txch); | |
1513 | cpdma_ctlr_int_ctrl(priv->dma, true); | |
1514 | cpsw_intr_enable(priv); | |
510a1e72 M |
1515 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); |
1516 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); | |
1517 | ||
df828598 M |
1518 | } |
1519 | ||
dcfd8d58 M |
1520 | static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) |
1521 | { | |
1522 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1523 | struct sockaddr *addr = (struct sockaddr *)p; | |
1524 | int flags = 0; | |
1525 | u16 vid = 0; | |
1526 | ||
1527 | if (!is_valid_ether_addr(addr->sa_data)) | |
1528 | return -EADDRNOTAVAIL; | |
1529 | ||
1530 | if (priv->data.dual_emac) { | |
1531 | vid = priv->slaves[priv->emac_port].port_vlan; | |
1532 | flags = ALE_VLAN; | |
1533 | } | |
1534 | ||
1535 | cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port, | |
1536 | flags, vid); | |
1537 | cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port, | |
1538 | flags, vid); | |
1539 | ||
1540 | memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); | |
1541 | memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); | |
1542 | for_each_slave(priv, cpsw_set_slave_mac, priv); | |
1543 | ||
1544 | return 0; | |
1545 | } | |
1546 | ||
df828598 M |
1547 | static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) |
1548 | { | |
1549 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1550 | return &priv->stats; | |
1551 | } | |
1552 | ||
1553 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1554 | static void cpsw_ndo_poll_controller(struct net_device *ndev) | |
1555 | { | |
1556 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1557 | ||
1558 | cpsw_intr_disable(priv); | |
1559 | cpdma_ctlr_int_ctrl(priv->dma, false); | |
1560 | cpsw_interrupt(ndev->irq, priv); | |
1561 | cpdma_ctlr_int_ctrl(priv->dma, true); | |
1562 | cpsw_intr_enable(priv); | |
510a1e72 M |
1563 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); |
1564 | cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); | |
1565 | ||
df828598 M |
1566 | } |
1567 | #endif | |
1568 | ||
3b72c2fe M |
1569 | static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, |
1570 | unsigned short vid) | |
1571 | { | |
1572 | int ret; | |
1573 | ||
1574 | ret = cpsw_ale_add_vlan(priv->ale, vid, | |
1575 | ALE_ALL_PORTS << priv->host_port, | |
1576 | 0, ALE_ALL_PORTS << priv->host_port, | |
1577 | (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); | |
1578 | if (ret != 0) | |
1579 | return ret; | |
1580 | ||
1581 | ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, | |
1582 | priv->host_port, ALE_VLAN, vid); | |
1583 | if (ret != 0) | |
1584 | goto clean_vid; | |
1585 | ||
1586 | ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, | |
1587 | ALE_ALL_PORTS << priv->host_port, | |
1588 | ALE_VLAN, vid, 0); | |
1589 | if (ret != 0) | |
1590 | goto clean_vlan_ucast; | |
1591 | return 0; | |
1592 | ||
1593 | clean_vlan_ucast: | |
1594 | cpsw_ale_del_ucast(priv->ale, priv->mac_addr, | |
1595 | priv->host_port, ALE_VLAN, vid); | |
1596 | clean_vid: | |
1597 | cpsw_ale_del_vlan(priv->ale, vid, 0); | |
1598 | return ret; | |
1599 | } | |
1600 | ||
1601 | static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, | |
80d5c368 | 1602 | __be16 proto, u16 vid) |
3b72c2fe M |
1603 | { |
1604 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1605 | ||
1606 | if (vid == priv->data.default_vlan) | |
1607 | return 0; | |
1608 | ||
1609 | dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); | |
1610 | return cpsw_add_vlan_ale_entry(priv, vid); | |
1611 | } | |
1612 | ||
1613 | static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, | |
80d5c368 | 1614 | __be16 proto, u16 vid) |
3b72c2fe M |
1615 | { |
1616 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1617 | int ret; | |
1618 | ||
1619 | if (vid == priv->data.default_vlan) | |
1620 | return 0; | |
1621 | ||
1622 | dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); | |
1623 | ret = cpsw_ale_del_vlan(priv->ale, vid, 0); | |
1624 | if (ret != 0) | |
1625 | return ret; | |
1626 | ||
1627 | ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, | |
1628 | priv->host_port, ALE_VLAN, vid); | |
1629 | if (ret != 0) | |
1630 | return ret; | |
1631 | ||
1632 | return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, | |
1633 | 0, ALE_VLAN, vid); | |
1634 | } | |
1635 | ||
df828598 M |
1636 | static const struct net_device_ops cpsw_netdev_ops = { |
1637 | .ndo_open = cpsw_ndo_open, | |
1638 | .ndo_stop = cpsw_ndo_stop, | |
1639 | .ndo_start_xmit = cpsw_ndo_start_xmit, | |
dcfd8d58 | 1640 | .ndo_set_mac_address = cpsw_ndo_set_mac_address, |
2e5b38ab | 1641 | .ndo_do_ioctl = cpsw_ndo_ioctl, |
df828598 | 1642 | .ndo_validate_addr = eth_validate_addr, |
5c473ed2 | 1643 | .ndo_change_mtu = eth_change_mtu, |
df828598 M |
1644 | .ndo_tx_timeout = cpsw_ndo_tx_timeout, |
1645 | .ndo_get_stats = cpsw_ndo_get_stats, | |
5c50a856 | 1646 | .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, |
df828598 M |
1647 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1648 | .ndo_poll_controller = cpsw_ndo_poll_controller, | |
1649 | #endif | |
3b72c2fe M |
1650 | .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, |
1651 | .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, | |
df828598 M |
1652 | }; |
1653 | ||
1654 | static void cpsw_get_drvinfo(struct net_device *ndev, | |
1655 | struct ethtool_drvinfo *info) | |
1656 | { | |
1657 | struct cpsw_priv *priv = netdev_priv(ndev); | |
7826d43f JP |
1658 | |
1659 | strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); | |
1660 | strlcpy(info->version, "1.0", sizeof(info->version)); | |
1661 | strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); | |
df828598 M |
1662 | } |
1663 | ||
1664 | static u32 cpsw_get_msglevel(struct net_device *ndev) | |
1665 | { | |
1666 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1667 | return priv->msg_enable; | |
1668 | } | |
1669 | ||
1670 | static void cpsw_set_msglevel(struct net_device *ndev, u32 value) | |
1671 | { | |
1672 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1673 | priv->msg_enable = value; | |
1674 | } | |
1675 | ||
2e5b38ab RC |
1676 | static int cpsw_get_ts_info(struct net_device *ndev, |
1677 | struct ethtool_ts_info *info) | |
1678 | { | |
1679 | #ifdef CONFIG_TI_CPTS | |
1680 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1681 | ||
1682 | info->so_timestamping = | |
1683 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1684 | SOF_TIMESTAMPING_TX_SOFTWARE | | |
1685 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1686 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1687 | SOF_TIMESTAMPING_SOFTWARE | | |
1688 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
9232b16d | 1689 | info->phc_index = priv->cpts->phc_index; |
2e5b38ab RC |
1690 | info->tx_types = |
1691 | (1 << HWTSTAMP_TX_OFF) | | |
1692 | (1 << HWTSTAMP_TX_ON); | |
1693 | info->rx_filters = | |
1694 | (1 << HWTSTAMP_FILTER_NONE) | | |
1695 | (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); | |
1696 | #else | |
1697 | info->so_timestamping = | |
1698 | SOF_TIMESTAMPING_TX_SOFTWARE | | |
1699 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1700 | SOF_TIMESTAMPING_SOFTWARE; | |
1701 | info->phc_index = -1; | |
1702 | info->tx_types = 0; | |
1703 | info->rx_filters = 0; | |
1704 | #endif | |
1705 | return 0; | |
1706 | } | |
1707 | ||
d3bb9c58 M |
1708 | static int cpsw_get_settings(struct net_device *ndev, |
1709 | struct ethtool_cmd *ecmd) | |
1710 | { | |
1711 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1712 | int slave_no = cpsw_slave_index(priv); | |
1713 | ||
1714 | if (priv->slaves[slave_no].phy) | |
1715 | return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); | |
1716 | else | |
1717 | return -EOPNOTSUPP; | |
1718 | } | |
1719 | ||
1720 | static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) | |
1721 | { | |
1722 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1723 | int slave_no = cpsw_slave_index(priv); | |
1724 | ||
1725 | if (priv->slaves[slave_no].phy) | |
1726 | return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); | |
1727 | else | |
1728 | return -EOPNOTSUPP; | |
1729 | } | |
1730 | ||
d8a64420 MU |
1731 | static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) |
1732 | { | |
1733 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1734 | int slave_no = cpsw_slave_index(priv); | |
1735 | ||
1736 | wol->supported = 0; | |
1737 | wol->wolopts = 0; | |
1738 | ||
1739 | if (priv->slaves[slave_no].phy) | |
1740 | phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol); | |
1741 | } | |
1742 | ||
1743 | static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) | |
1744 | { | |
1745 | struct cpsw_priv *priv = netdev_priv(ndev); | |
1746 | int slave_no = cpsw_slave_index(priv); | |
1747 | ||
1748 | if (priv->slaves[slave_no].phy) | |
1749 | return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol); | |
1750 | else | |
1751 | return -EOPNOTSUPP; | |
1752 | } | |
1753 | ||
df828598 M |
1754 | static const struct ethtool_ops cpsw_ethtool_ops = { |
1755 | .get_drvinfo = cpsw_get_drvinfo, | |
1756 | .get_msglevel = cpsw_get_msglevel, | |
1757 | .set_msglevel = cpsw_set_msglevel, | |
1758 | .get_link = ethtool_op_get_link, | |
2e5b38ab | 1759 | .get_ts_info = cpsw_get_ts_info, |
d3bb9c58 M |
1760 | .get_settings = cpsw_get_settings, |
1761 | .set_settings = cpsw_set_settings, | |
ff5b8ef2 M |
1762 | .get_coalesce = cpsw_get_coalesce, |
1763 | .set_coalesce = cpsw_set_coalesce, | |
d9718546 M |
1764 | .get_sset_count = cpsw_get_sset_count, |
1765 | .get_strings = cpsw_get_strings, | |
1766 | .get_ethtool_stats = cpsw_get_ethtool_stats, | |
d8a64420 MU |
1767 | .get_wol = cpsw_get_wol, |
1768 | .set_wol = cpsw_set_wol, | |
df828598 M |
1769 | }; |
1770 | ||
549985ee RC |
1771 | static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, |
1772 | u32 slave_reg_ofs, u32 sliver_reg_ofs) | |
df828598 M |
1773 | { |
1774 | void __iomem *regs = priv->regs; | |
1775 | int slave_num = slave->slave_num; | |
1776 | struct cpsw_slave_data *data = priv->data.slave_data + slave_num; | |
1777 | ||
1778 | slave->data = data; | |
549985ee RC |
1779 | slave->regs = regs + slave_reg_ofs; |
1780 | slave->sliver = regs + sliver_reg_ofs; | |
d9ba8f9e | 1781 | slave->port_vlan = data->dual_emac_res_vlan; |
df828598 M |
1782 | } |
1783 | ||
2eb32b0a M |
1784 | static int cpsw_probe_dt(struct cpsw_platform_data *data, |
1785 | struct platform_device *pdev) | |
1786 | { | |
1787 | struct device_node *node = pdev->dev.of_node; | |
1788 | struct device_node *slave_node; | |
1789 | int i = 0, ret; | |
1790 | u32 prop; | |
1791 | ||
1792 | if (!node) | |
1793 | return -EINVAL; | |
1794 | ||
1795 | if (of_property_read_u32(node, "slaves", &prop)) { | |
1796 | pr_err("Missing slaves property in the DT.\n"); | |
1797 | return -EINVAL; | |
1798 | } | |
1799 | data->slaves = prop; | |
1800 | ||
e86ac13b M |
1801 | if (of_property_read_u32(node, "active_slave", &prop)) { |
1802 | pr_err("Missing active_slave property in the DT.\n"); | |
aa1a15e2 | 1803 | return -EINVAL; |
78ca0b28 | 1804 | } |
e86ac13b | 1805 | data->active_slave = prop; |
78ca0b28 | 1806 | |
00ab94ee RC |
1807 | if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { |
1808 | pr_err("Missing cpts_clock_mult property in the DT.\n"); | |
aa1a15e2 | 1809 | return -EINVAL; |
00ab94ee RC |
1810 | } |
1811 | data->cpts_clock_mult = prop; | |
1812 | ||
1813 | if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { | |
1814 | pr_err("Missing cpts_clock_shift property in the DT.\n"); | |
aa1a15e2 | 1815 | return -EINVAL; |
00ab94ee RC |
1816 | } |
1817 | data->cpts_clock_shift = prop; | |
1818 | ||
aa1a15e2 DM |
1819 | data->slave_data = devm_kzalloc(&pdev->dev, data->slaves |
1820 | * sizeof(struct cpsw_slave_data), | |
1821 | GFP_KERNEL); | |
b2adaca9 | 1822 | if (!data->slave_data) |
aa1a15e2 | 1823 | return -ENOMEM; |
2eb32b0a | 1824 | |
2eb32b0a M |
1825 | if (of_property_read_u32(node, "cpdma_channels", &prop)) { |
1826 | pr_err("Missing cpdma_channels property in the DT.\n"); | |
aa1a15e2 | 1827 | return -EINVAL; |
2eb32b0a M |
1828 | } |
1829 | data->channels = prop; | |
1830 | ||
2eb32b0a M |
1831 | if (of_property_read_u32(node, "ale_entries", &prop)) { |
1832 | pr_err("Missing ale_entries property in the DT.\n"); | |
aa1a15e2 | 1833 | return -EINVAL; |
2eb32b0a M |
1834 | } |
1835 | data->ale_entries = prop; | |
1836 | ||
2eb32b0a M |
1837 | if (of_property_read_u32(node, "bd_ram_size", &prop)) { |
1838 | pr_err("Missing bd_ram_size property in the DT.\n"); | |
aa1a15e2 | 1839 | return -EINVAL; |
2eb32b0a M |
1840 | } |
1841 | data->bd_ram_size = prop; | |
1842 | ||
1843 | if (of_property_read_u32(node, "rx_descs", &prop)) { | |
1844 | pr_err("Missing rx_descs property in the DT.\n"); | |
aa1a15e2 | 1845 | return -EINVAL; |
2eb32b0a M |
1846 | } |
1847 | data->rx_descs = prop; | |
1848 | ||
1849 | if (of_property_read_u32(node, "mac_control", &prop)) { | |
1850 | pr_err("Missing mac_control property in the DT.\n"); | |
aa1a15e2 | 1851 | return -EINVAL; |
2eb32b0a M |
1852 | } |
1853 | data->mac_control = prop; | |
1854 | ||
281abd96 MP |
1855 | if (of_property_read_bool(node, "dual_emac")) |
1856 | data->dual_emac = 1; | |
d9ba8f9e | 1857 | |
549985ee RC |
1858 | /* |
1859 | * Populate all the child nodes here... | |
1860 | */ | |
1861 | ret = of_platform_populate(node, NULL, NULL, &pdev->dev); | |
1862 | /* We do not want to force this, as in some cases may not have child */ | |
1863 | if (ret) | |
1864 | pr_warn("Doesn't have any child node\n"); | |
1865 | ||
f468b10e | 1866 | for_each_child_of_node(node, slave_node) { |
2eb32b0a | 1867 | struct cpsw_slave_data *slave_data = data->slave_data + i; |
2eb32b0a | 1868 | const void *mac_addr = NULL; |
549985ee RC |
1869 | u32 phyid; |
1870 | int lenp; | |
1871 | const __be32 *parp; | |
1872 | struct device_node *mdio_node; | |
1873 | struct platform_device *mdio; | |
1874 | ||
f468b10e MP |
1875 | /* This is no slave child node, continue */ |
1876 | if (strcmp(slave_node->name, "slave")) | |
1877 | continue; | |
1878 | ||
549985ee | 1879 | parp = of_get_property(slave_node, "phy_id", &lenp); |
ce16294f | 1880 | if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) { |
2eb32b0a | 1881 | pr_err("Missing slave[%d] phy_id property\n", i); |
aa1a15e2 | 1882 | return -EINVAL; |
2eb32b0a | 1883 | } |
549985ee RC |
1884 | mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); |
1885 | phyid = be32_to_cpup(parp+1); | |
1886 | mdio = of_find_device_by_node(mdio_node); | |
f8d56d8f SR |
1887 | |
1888 | if (strncmp(mdio->name, "gpio", 4) == 0) { | |
1889 | /* GPIO bitbang MDIO driver attached */ | |
1890 | struct mii_bus *bus = dev_get_drvdata(&mdio->dev); | |
1891 | ||
1892 | snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), | |
1893 | PHY_ID_FMT, bus->id, phyid); | |
1894 | } else { | |
1895 | /* davinci MDIO driver attached */ | |
1896 | snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), | |
1897 | PHY_ID_FMT, mdio->name, phyid); | |
1898 | } | |
2eb32b0a M |
1899 | |
1900 | mac_addr = of_get_mac_address(slave_node); | |
1901 | if (mac_addr) | |
1902 | memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); | |
1903 | ||
c5ceea7a | 1904 | slave_data->phy_if = of_get_phy_mode(slave_node); |
89e10172 UKK |
1905 | if (slave_data->phy_if < 0) { |
1906 | pr_err("Missing or malformed slave[%d] phy-mode property\n", | |
1907 | i); | |
1908 | return slave_data->phy_if; | |
1909 | } | |
c5ceea7a | 1910 | |
d9ba8f9e | 1911 | if (data->dual_emac) { |
91c4166c | 1912 | if (of_property_read_u32(slave_node, "dual_emac_res_vlan", |
d9ba8f9e M |
1913 | &prop)) { |
1914 | pr_err("Missing dual_emac_res_vlan in DT.\n"); | |
1915 | slave_data->dual_emac_res_vlan = i+1; | |
1916 | pr_err("Using %d as Reserved VLAN for %d slave\n", | |
1917 | slave_data->dual_emac_res_vlan, i); | |
1918 | } else { | |
1919 | slave_data->dual_emac_res_vlan = prop; | |
1920 | } | |
1921 | } | |
1922 | ||
2eb32b0a | 1923 | i++; |
3a27bfac M |
1924 | if (i == data->slaves) |
1925 | break; | |
2eb32b0a M |
1926 | } |
1927 | ||
1928 | return 0; | |
2eb32b0a M |
1929 | } |
1930 | ||
d9ba8f9e M |
1931 | static int cpsw_probe_dual_emac(struct platform_device *pdev, |
1932 | struct cpsw_priv *priv) | |
1933 | { | |
1934 | struct cpsw_platform_data *data = &priv->data; | |
1935 | struct net_device *ndev; | |
1936 | struct cpsw_priv *priv_sl2; | |
1937 | int ret = 0, i; | |
1938 | ||
1939 | ndev = alloc_etherdev(sizeof(struct cpsw_priv)); | |
1940 | if (!ndev) { | |
1941 | pr_err("cpsw: error allocating net_device\n"); | |
1942 | return -ENOMEM; | |
1943 | } | |
1944 | ||
1945 | priv_sl2 = netdev_priv(ndev); | |
1946 | spin_lock_init(&priv_sl2->lock); | |
1947 | priv_sl2->data = *data; | |
1948 | priv_sl2->pdev = pdev; | |
1949 | priv_sl2->ndev = ndev; | |
1950 | priv_sl2->dev = &ndev->dev; | |
1951 | priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); | |
1952 | priv_sl2->rx_packet_max = max(rx_packet_max, 128); | |
1953 | ||
1954 | if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { | |
1955 | memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, | |
1956 | ETH_ALEN); | |
1957 | pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); | |
1958 | } else { | |
1959 | random_ether_addr(priv_sl2->mac_addr); | |
1960 | pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); | |
1961 | } | |
1962 | memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); | |
1963 | ||
1964 | priv_sl2->slaves = priv->slaves; | |
1965 | priv_sl2->clk = priv->clk; | |
1966 | ||
ff5b8ef2 M |
1967 | priv_sl2->coal_intvl = 0; |
1968 | priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; | |
1969 | ||
d9ba8f9e M |
1970 | priv_sl2->regs = priv->regs; |
1971 | priv_sl2->host_port = priv->host_port; | |
1972 | priv_sl2->host_port_regs = priv->host_port_regs; | |
1973 | priv_sl2->wr_regs = priv->wr_regs; | |
d9718546 | 1974 | priv_sl2->hw_stats = priv->hw_stats; |
d9ba8f9e M |
1975 | priv_sl2->dma = priv->dma; |
1976 | priv_sl2->txch = priv->txch; | |
1977 | priv_sl2->rxch = priv->rxch; | |
1978 | priv_sl2->ale = priv->ale; | |
1979 | priv_sl2->emac_port = 1; | |
1980 | priv->slaves[1].ndev = ndev; | |
1981 | priv_sl2->cpts = priv->cpts; | |
1982 | priv_sl2->version = priv->version; | |
1983 | ||
1984 | for (i = 0; i < priv->num_irqs; i++) { | |
1985 | priv_sl2->irqs_table[i] = priv->irqs_table[i]; | |
1986 | priv_sl2->num_irqs = priv->num_irqs; | |
1987 | } | |
f646968f | 1988 | ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; |
d9ba8f9e M |
1989 | |
1990 | ndev->netdev_ops = &cpsw_netdev_ops; | |
1991 | SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); | |
1992 | netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); | |
1993 | ||
1994 | /* register the network device */ | |
1995 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1996 | ret = register_netdev(ndev); | |
1997 | if (ret) { | |
1998 | pr_err("cpsw: error registering net device\n"); | |
1999 | free_netdev(ndev); | |
2000 | ret = -ENODEV; | |
2001 | } | |
2002 | ||
2003 | return ret; | |
2004 | } | |
2005 | ||
663e12e6 | 2006 | static int cpsw_probe(struct platform_device *pdev) |
df828598 | 2007 | { |
d1bd9acf | 2008 | struct cpsw_platform_data *data; |
df828598 M |
2009 | struct net_device *ndev; |
2010 | struct cpsw_priv *priv; | |
2011 | struct cpdma_params dma_params; | |
2012 | struct cpsw_ale_params ale_params; | |
aa1a15e2 DM |
2013 | void __iomem *ss_regs; |
2014 | struct resource *res, *ss_res; | |
549985ee | 2015 | u32 slave_offset, sliver_offset, slave_size; |
df828598 M |
2016 | int ret = 0, i, k = 0; |
2017 | ||
df828598 M |
2018 | ndev = alloc_etherdev(sizeof(struct cpsw_priv)); |
2019 | if (!ndev) { | |
2020 | pr_err("error allocating net_device\n"); | |
2021 | return -ENOMEM; | |
2022 | } | |
2023 | ||
2024 | platform_set_drvdata(pdev, ndev); | |
2025 | priv = netdev_priv(ndev); | |
2026 | spin_lock_init(&priv->lock); | |
df828598 M |
2027 | priv->pdev = pdev; |
2028 | priv->ndev = ndev; | |
2029 | priv->dev = &ndev->dev; | |
2030 | priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); | |
2031 | priv->rx_packet_max = max(rx_packet_max, 128); | |
9232b16d | 2032 | priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); |
7dcf313a | 2033 | priv->irq_enabled = true; |
ab8e99d2 | 2034 | if (!priv->cpts) { |
9232b16d M |
2035 | pr_err("error allocating cpts\n"); |
2036 | goto clean_ndev_ret; | |
2037 | } | |
df828598 | 2038 | |
1fb19aa7 VH |
2039 | /* |
2040 | * This may be required here for child devices. | |
2041 | */ | |
2042 | pm_runtime_enable(&pdev->dev); | |
2043 | ||
739683b4 M |
2044 | /* Select default pin state */ |
2045 | pinctrl_pm_select_default_state(&pdev->dev); | |
2046 | ||
2eb32b0a M |
2047 | if (cpsw_probe_dt(&priv->data, pdev)) { |
2048 | pr_err("cpsw: platform data missing\n"); | |
2049 | ret = -ENODEV; | |
aa1a15e2 | 2050 | goto clean_runtime_disable_ret; |
2eb32b0a M |
2051 | } |
2052 | data = &priv->data; | |
2053 | ||
df828598 M |
2054 | if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { |
2055 | memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); | |
cf6122be | 2056 | pr_info("Detected MACID = %pM\n", priv->mac_addr); |
df828598 | 2057 | } else { |
7efd26d0 | 2058 | eth_random_addr(priv->mac_addr); |
cf6122be | 2059 | pr_info("Random MACID = %pM\n", priv->mac_addr); |
df828598 M |
2060 | } |
2061 | ||
2062 | memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); | |
2063 | ||
aa1a15e2 DM |
2064 | priv->slaves = devm_kzalloc(&pdev->dev, |
2065 | sizeof(struct cpsw_slave) * data->slaves, | |
2066 | GFP_KERNEL); | |
df828598 | 2067 | if (!priv->slaves) { |
aa1a15e2 DM |
2068 | ret = -ENOMEM; |
2069 | goto clean_runtime_disable_ret; | |
df828598 M |
2070 | } |
2071 | for (i = 0; i < data->slaves; i++) | |
2072 | priv->slaves[i].slave_num = i; | |
2073 | ||
d9ba8f9e M |
2074 | priv->slaves[0].ndev = ndev; |
2075 | priv->emac_port = 0; | |
2076 | ||
aa1a15e2 | 2077 | priv->clk = devm_clk_get(&pdev->dev, "fck"); |
df828598 | 2078 | if (IS_ERR(priv->clk)) { |
aa1a15e2 | 2079 | dev_err(priv->dev, "fck is not found\n"); |
f150bd7f | 2080 | ret = -ENODEV; |
aa1a15e2 | 2081 | goto clean_runtime_disable_ret; |
df828598 | 2082 | } |
ff5b8ef2 M |
2083 | priv->coal_intvl = 0; |
2084 | priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; | |
df828598 | 2085 | |
aa1a15e2 DM |
2086 | ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2087 | ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); | |
2088 | if (IS_ERR(ss_regs)) { | |
2089 | ret = PTR_ERR(ss_regs); | |
2090 | goto clean_runtime_disable_ret; | |
df828598 | 2091 | } |
549985ee | 2092 | priv->regs = ss_regs; |
549985ee | 2093 | priv->host_port = HOST_PORT_NUM; |
df828598 | 2094 | |
f280e89a M |
2095 | /* Need to enable clocks with runtime PM api to access module |
2096 | * registers | |
2097 | */ | |
2098 | pm_runtime_get_sync(&pdev->dev); | |
2099 | priv->version = readl(&priv->regs->id_ver); | |
2100 | pm_runtime_put_sync(&pdev->dev); | |
2101 | ||
aa1a15e2 DM |
2102 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
2103 | priv->wr_regs = devm_ioremap_resource(&pdev->dev, res); | |
2104 | if (IS_ERR(priv->wr_regs)) { | |
2105 | ret = PTR_ERR(priv->wr_regs); | |
2106 | goto clean_runtime_disable_ret; | |
df828598 | 2107 | } |
df828598 M |
2108 | |
2109 | memset(&dma_params, 0, sizeof(dma_params)); | |
549985ee RC |
2110 | memset(&ale_params, 0, sizeof(ale_params)); |
2111 | ||
2112 | switch (priv->version) { | |
2113 | case CPSW_VERSION_1: | |
2114 | priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; | |
d9718546 M |
2115 | priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; |
2116 | priv->hw_stats = ss_regs + CPSW1_HW_STATS; | |
549985ee RC |
2117 | dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; |
2118 | dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; | |
2119 | ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; | |
2120 | slave_offset = CPSW1_SLAVE_OFFSET; | |
2121 | slave_size = CPSW1_SLAVE_SIZE; | |
2122 | sliver_offset = CPSW1_SLIVER_OFFSET; | |
2123 | dma_params.desc_mem_phys = 0; | |
2124 | break; | |
2125 | case CPSW_VERSION_2: | |
c193f365 | 2126 | case CPSW_VERSION_3: |
926489be | 2127 | case CPSW_VERSION_4: |
549985ee | 2128 | priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; |
d9718546 M |
2129 | priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; |
2130 | priv->hw_stats = ss_regs + CPSW2_HW_STATS; | |
549985ee RC |
2131 | dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; |
2132 | dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; | |
2133 | ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; | |
2134 | slave_offset = CPSW2_SLAVE_OFFSET; | |
2135 | slave_size = CPSW2_SLAVE_SIZE; | |
2136 | sliver_offset = CPSW2_SLIVER_OFFSET; | |
2137 | dma_params.desc_mem_phys = | |
aa1a15e2 | 2138 | (u32 __force) ss_res->start + CPSW2_BD_OFFSET; |
549985ee RC |
2139 | break; |
2140 | default: | |
2141 | dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); | |
2142 | ret = -ENODEV; | |
aa1a15e2 | 2143 | goto clean_runtime_disable_ret; |
549985ee RC |
2144 | } |
2145 | for (i = 0; i < priv->data.slaves; i++) { | |
2146 | struct cpsw_slave *slave = &priv->slaves[i]; | |
2147 | cpsw_slave_init(slave, priv, slave_offset, sliver_offset); | |
2148 | slave_offset += slave_size; | |
2149 | sliver_offset += SLIVER_SIZE; | |
2150 | } | |
2151 | ||
df828598 | 2152 | dma_params.dev = &pdev->dev; |
549985ee RC |
2153 | dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; |
2154 | dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; | |
2155 | dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; | |
2156 | dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; | |
2157 | dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; | |
df828598 M |
2158 | |
2159 | dma_params.num_chan = data->channels; | |
2160 | dma_params.has_soft_reset = true; | |
2161 | dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; | |
2162 | dma_params.desc_mem_size = data->bd_ram_size; | |
2163 | dma_params.desc_align = 16; | |
2164 | dma_params.has_ext_regs = true; | |
549985ee | 2165 | dma_params.desc_hw_addr = dma_params.desc_mem_phys; |
df828598 M |
2166 | |
2167 | priv->dma = cpdma_ctlr_create(&dma_params); | |
2168 | if (!priv->dma) { | |
2169 | dev_err(priv->dev, "error initializing dma\n"); | |
2170 | ret = -ENOMEM; | |
aa1a15e2 | 2171 | goto clean_runtime_disable_ret; |
df828598 M |
2172 | } |
2173 | ||
2174 | priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), | |
2175 | cpsw_tx_handler); | |
2176 | priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), | |
2177 | cpsw_rx_handler); | |
2178 | ||
2179 | if (WARN_ON(!priv->txch || !priv->rxch)) { | |
2180 | dev_err(priv->dev, "error initializing dma channels\n"); | |
2181 | ret = -ENOMEM; | |
2182 | goto clean_dma_ret; | |
2183 | } | |
2184 | ||
df828598 | 2185 | ale_params.dev = &ndev->dev; |
df828598 M |
2186 | ale_params.ale_ageout = ale_ageout; |
2187 | ale_params.ale_entries = data->ale_entries; | |
2188 | ale_params.ale_ports = data->slaves; | |
2189 | ||
2190 | priv->ale = cpsw_ale_create(&ale_params); | |
2191 | if (!priv->ale) { | |
2192 | dev_err(priv->dev, "error initializing ale engine\n"); | |
2193 | ret = -ENODEV; | |
2194 | goto clean_dma_ret; | |
2195 | } | |
2196 | ||
2197 | ndev->irq = platform_get_irq(pdev, 0); | |
2198 | if (ndev->irq < 0) { | |
2199 | dev_err(priv->dev, "error getting irq resource\n"); | |
2200 | ret = -ENOENT; | |
2201 | goto clean_ale_ret; | |
2202 | } | |
2203 | ||
2204 | while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { | |
2205 | for (i = res->start; i <= res->end; i++) { | |
aa1a15e2 | 2206 | if (devm_request_irq(&pdev->dev, i, cpsw_interrupt, 0, |
db850559 | 2207 | dev_name(&pdev->dev), priv)) { |
df828598 M |
2208 | dev_err(priv->dev, "error attaching irq\n"); |
2209 | goto clean_ale_ret; | |
2210 | } | |
2211 | priv->irqs_table[k] = i; | |
d1bd9acf | 2212 | priv->num_irqs = k + 1; |
df828598 M |
2213 | } |
2214 | k++; | |
2215 | } | |
2216 | ||
f646968f | 2217 | ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; |
df828598 M |
2218 | |
2219 | ndev->netdev_ops = &cpsw_netdev_ops; | |
2220 | SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); | |
2221 | netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); | |
2222 | ||
2223 | /* register the network device */ | |
2224 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
2225 | ret = register_netdev(ndev); | |
2226 | if (ret) { | |
2227 | dev_err(priv->dev, "error registering net device\n"); | |
2228 | ret = -ENODEV; | |
aa1a15e2 | 2229 | goto clean_ale_ret; |
df828598 M |
2230 | } |
2231 | ||
9232b16d | 2232 | if (cpts_register(&pdev->dev, priv->cpts, |
2e5b38ab RC |
2233 | data->cpts_clock_mult, data->cpts_clock_shift)) |
2234 | dev_err(priv->dev, "error registering cpts device\n"); | |
2235 | ||
1a3b5056 OJ |
2236 | cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n", |
2237 | &ss_res->start, ndev->irq); | |
df828598 | 2238 | |
d9ba8f9e M |
2239 | if (priv->data.dual_emac) { |
2240 | ret = cpsw_probe_dual_emac(pdev, priv); | |
2241 | if (ret) { | |
2242 | cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); | |
aa1a15e2 | 2243 | goto clean_ale_ret; |
d9ba8f9e M |
2244 | } |
2245 | } | |
2246 | ||
df828598 M |
2247 | return 0; |
2248 | ||
df828598 M |
2249 | clean_ale_ret: |
2250 | cpsw_ale_destroy(priv->ale); | |
2251 | clean_dma_ret: | |
2252 | cpdma_chan_destroy(priv->txch); | |
2253 | cpdma_chan_destroy(priv->rxch); | |
2254 | cpdma_ctlr_destroy(priv->dma); | |
aa1a15e2 | 2255 | clean_runtime_disable_ret: |
f150bd7f | 2256 | pm_runtime_disable(&pdev->dev); |
df828598 | 2257 | clean_ndev_ret: |
d1bd9acf | 2258 | free_netdev(priv->ndev); |
df828598 M |
2259 | return ret; |
2260 | } | |
2261 | ||
663e12e6 | 2262 | static int cpsw_remove(struct platform_device *pdev) |
df828598 M |
2263 | { |
2264 | struct net_device *ndev = platform_get_drvdata(pdev); | |
2265 | struct cpsw_priv *priv = netdev_priv(ndev); | |
2266 | ||
d1bd9acf SS |
2267 | if (priv->data.dual_emac) |
2268 | unregister_netdev(cpsw_get_slave_ndev(priv, 1)); | |
2269 | unregister_netdev(ndev); | |
df828598 | 2270 | |
df828598 M |
2271 | cpsw_ale_destroy(priv->ale); |
2272 | cpdma_chan_destroy(priv->txch); | |
2273 | cpdma_chan_destroy(priv->rxch); | |
2274 | cpdma_ctlr_destroy(priv->dma); | |
f150bd7f | 2275 | pm_runtime_disable(&pdev->dev); |
d1bd9acf SS |
2276 | if (priv->data.dual_emac) |
2277 | free_netdev(cpsw_get_slave_ndev(priv, 1)); | |
df828598 | 2278 | free_netdev(ndev); |
df828598 M |
2279 | return 0; |
2280 | } | |
2281 | ||
2282 | static int cpsw_suspend(struct device *dev) | |
2283 | { | |
2284 | struct platform_device *pdev = to_platform_device(dev); | |
2285 | struct net_device *ndev = platform_get_drvdata(pdev); | |
b90fc27a | 2286 | struct cpsw_priv *priv = netdev_priv(ndev); |
df828598 M |
2287 | |
2288 | if (netif_running(ndev)) | |
2289 | cpsw_ndo_stop(ndev); | |
1e7a2e21 DM |
2290 | |
2291 | for_each_slave(priv, soft_reset_slave); | |
2292 | ||
f150bd7f M |
2293 | pm_runtime_put_sync(&pdev->dev); |
2294 | ||
739683b4 M |
2295 | /* Select sleep pin state */ |
2296 | pinctrl_pm_select_sleep_state(&pdev->dev); | |
2297 | ||
df828598 M |
2298 | return 0; |
2299 | } | |
2300 | ||
2301 | static int cpsw_resume(struct device *dev) | |
2302 | { | |
2303 | struct platform_device *pdev = to_platform_device(dev); | |
2304 | struct net_device *ndev = platform_get_drvdata(pdev); | |
2305 | ||
f150bd7f | 2306 | pm_runtime_get_sync(&pdev->dev); |
739683b4 M |
2307 | |
2308 | /* Select default pin state */ | |
2309 | pinctrl_pm_select_default_state(&pdev->dev); | |
2310 | ||
df828598 M |
2311 | if (netif_running(ndev)) |
2312 | cpsw_ndo_open(ndev); | |
2313 | return 0; | |
2314 | } | |
2315 | ||
2316 | static const struct dev_pm_ops cpsw_pm_ops = { | |
2317 | .suspend = cpsw_suspend, | |
2318 | .resume = cpsw_resume, | |
2319 | }; | |
2320 | ||
2eb32b0a M |
2321 | static const struct of_device_id cpsw_of_mtable[] = { |
2322 | { .compatible = "ti,cpsw", }, | |
2323 | { /* sentinel */ }, | |
2324 | }; | |
4bc21d41 | 2325 | MODULE_DEVICE_TABLE(of, cpsw_of_mtable); |
2eb32b0a | 2326 | |
df828598 M |
2327 | static struct platform_driver cpsw_driver = { |
2328 | .driver = { | |
2329 | .name = "cpsw", | |
2330 | .owner = THIS_MODULE, | |
2331 | .pm = &cpsw_pm_ops, | |
1e5c76d4 | 2332 | .of_match_table = cpsw_of_mtable, |
df828598 M |
2333 | }, |
2334 | .probe = cpsw_probe, | |
663e12e6 | 2335 | .remove = cpsw_remove, |
df828598 M |
2336 | }; |
2337 | ||
2338 | static int __init cpsw_init(void) | |
2339 | { | |
2340 | return platform_driver_register(&cpsw_driver); | |
2341 | } | |
2342 | late_initcall(cpsw_init); | |
2343 | ||
2344 | static void __exit cpsw_exit(void) | |
2345 | { | |
2346 | platform_driver_unregister(&cpsw_driver); | |
2347 | } | |
2348 | module_exit(cpsw_exit); | |
2349 | ||
2350 | MODULE_LICENSE("GPL"); | |
2351 | MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); | |
2352 | MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); | |
2353 | MODULE_DESCRIPTION("TI CPSW Ethernet driver"); |