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cpsw: add a DT field for the active time stamping port
[linux-block.git] / drivers / net / ethernet / ti / cpsw.c
CommitLineData
df828598
M		 1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
27#include <linux/phy.h>
28#include <linux/workqueue.h>
29#include <linux/delay.h>
f150bd7f 30#include <linux/pm_runtime.h>
2eb32b0a
M		 31#include <linux/of.h>
32#include <linux/of_net.h>
33#include <linux/of_device.h>
df828598
M		 34
35#include <linux/platform_data/cpsw.h>
36
37#include "cpsw_ale.h"
38#include "davinci_cpdma.h"
39
40#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
41 NETIF_MSG_DRV | NETIF_MSG_LINK | \
42 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
43 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
44 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
45 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
46 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
47 NETIF_MSG_RX_STATUS)
48
49#define cpsw_info(priv, type, format, ...) \
50do { \
51 if (netif_msg_##type(priv) && net_ratelimit()) \
52 dev_info(priv->dev, format, ## __VA_ARGS__); \
53} while (0)
54
55#define cpsw_err(priv, type, format, ...) \
56do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_err(priv->dev, format, ## __VA_ARGS__); \
59} while (0)
60
61#define cpsw_dbg(priv, type, format, ...) \
62do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
65} while (0)
66
67#define cpsw_notice(priv, type, format, ...) \
68do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_notice(priv->dev, format, ## __VA_ARGS__); \
71} while (0)
72
5c50a856
M		 73#define ALE_ALL_PORTS 0x7
74
df828598
M		 75#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
76#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
77#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
78
e90cfac6
RC		 79#define CPSW_VERSION_1 0x19010a
80#define CPSW_VERSION_2 0x19010c
df828598
M		 81#define CPDMA_RXTHRESH 0x0c0
82#define CPDMA_RXFREE 0x0e0
83#define CPDMA_TXHDP 0x00
84#define CPDMA_RXHDP 0x20
85#define CPDMA_TXCP 0x40
86#define CPDMA_RXCP 0x60
87
88#define cpsw_dma_regs(base, offset) \
89 (void __iomem *)((base) + (offset))
90#define cpsw_dma_rxthresh(base, offset) \
91 (void __iomem *)((base) + (offset) + CPDMA_RXTHRESH)
92#define cpsw_dma_rxfree(base, offset) \
93 (void __iomem *)((base) + (offset) + CPDMA_RXFREE)
94#define cpsw_dma_txhdp(base, offset) \
95 (void __iomem *)((base) + (offset) + CPDMA_TXHDP)
96#define cpsw_dma_rxhdp(base, offset) \
97 (void __iomem *)((base) + (offset) + CPDMA_RXHDP)
98#define cpsw_dma_txcp(base, offset) \
99 (void __iomem *)((base) + (offset) + CPDMA_TXCP)
100#define cpsw_dma_rxcp(base, offset) \
101 (void __iomem *)((base) + (offset) + CPDMA_RXCP)
102
103#define CPSW_POLL_WEIGHT 64
104#define CPSW_MIN_PACKET_SIZE 60
105#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
106
107#define RX_PRIORITY_MAPPING 0x76543210
108#define TX_PRIORITY_MAPPING 0x33221100
109#define CPDMA_TX_PRIORITY_MAP 0x76543210
110
111#define cpsw_enable_irq(priv) \
112 do { \
113 u32 i; \
114 for (i = 0; i < priv->num_irqs; i++) \
115 enable_irq(priv->irqs_table[i]); \
116 } while (0);
117#define cpsw_disable_irq(priv) \
118 do { \
119 u32 i; \
120 for (i = 0; i < priv->num_irqs; i++) \
121 disable_irq_nosync(priv->irqs_table[i]); \
122 } while (0);
123
124static int debug_level;
125module_param(debug_level, int, 0);
126MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
127
128static int ale_ageout = 10;
129module_param(ale_ageout, int, 0);
130MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
131
132static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
133module_param(rx_packet_max, int, 0);
134MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
135
996a5c27 136struct cpsw_wr_regs {
df828598
M		 137 u32 id_ver;
138 u32 soft_reset;
139 u32 control;
140 u32 int_control;
141 u32 rx_thresh_en;
142 u32 rx_en;
143 u32 tx_en;
144 u32 misc_en;
145};
146
996a5c27 147struct cpsw_ss_regs {
df828598
M		 148 u32 id_ver;
149 u32 control;
150 u32 soft_reset;
151 u32 stat_port_en;
152 u32 ptype;
bd357af2
RC		 153 u32 soft_idle;
154 u32 thru_rate;
155 u32 gap_thresh;
156 u32 tx_start_wds;
157 u32 flow_control;
158 u32 vlan_ltype;
159 u32 ts_ltype;
160 u32 dlr_ltype;
df828598
M		 161};
162
9750a3ad
RC		 163/* CPSW_PORT_V1 */
164#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
165#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
166#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
167#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
168#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
169#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
170#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
171#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
172
173/* CPSW_PORT_V2 */
174#define CPSW2_CONTROL 0x00 /* Control Register */
175#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
176#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
177#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
178#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
179#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
180#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
181
182/* CPSW_PORT_V1 and V2 */
183#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
184#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
185#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
186
187/* CPSW_PORT_V2 only */
188#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
189#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
190#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
191#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
192#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
193#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
194#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
195#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
196
197/* Bit definitions for the CPSW2_CONTROL register */
198#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
199#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
200#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
201#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
202#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
203#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
204#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
205#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
206#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
207#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
208#define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */
209#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
210#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
211#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
212#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
213#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
214
215#define CTRL_TS_BITS \
216 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
217 TS_ANNEX_D_EN | TS_LTYPE1_EN)
218
219#define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
220#define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN)
221#define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN)
222
223/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
224#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
225#define TS_SEQ_ID_OFFSET_MASK (0x3f)
226#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
227#define TS_MSG_TYPE_EN_MASK (0xffff)
228
229/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
230#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
df828598
M		 231
232struct cpsw_host_regs {
233 u32 max_blks;
234 u32 blk_cnt;
235 u32 flow_thresh;
236 u32 port_vlan;
237 u32 tx_pri_map;
238 u32 cpdma_tx_pri_map;
239 u32 cpdma_rx_chan_map;
240};
241
242struct cpsw_sliver_regs {
243 u32 id_ver;
244 u32 mac_control;
245 u32 mac_status;
246 u32 soft_reset;
247 u32 rx_maxlen;
248 u32 __reserved_0;
249 u32 rx_pause;
250 u32 tx_pause;
251 u32 __reserved_1;
252 u32 rx_pri_map;
253};
254
255struct cpsw_slave {
9750a3ad 256 void __iomem *regs;
df828598
M		 257 struct cpsw_sliver_regs __iomem *sliver;
258 int slave_num;
259 u32 mac_control;
260 struct cpsw_slave_data *data;
261 struct phy_device *phy;
262};
263
9750a3ad
RC		 264static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
265{
266 return __raw_readl(slave->regs + offset);
267}
268
269static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
270{
271 __raw_writel(val, slave->regs + offset);
272}
273
df828598
M		 274struct cpsw_priv {
275 spinlock_t lock;
276 struct platform_device *pdev;
277 struct net_device *ndev;
278 struct resource *cpsw_res;
279 struct resource *cpsw_ss_res;
280 struct napi_struct napi;
281 struct device *dev;
282 struct cpsw_platform_data data;
996a5c27
RC		 283 struct cpsw_ss_regs __iomem *regs;
284 struct cpsw_wr_regs __iomem *wr_regs;
df828598
M		 285 struct cpsw_host_regs __iomem *host_port_regs;
286 u32 msg_enable;
e90cfac6 287 u32 version;
df828598
M		 288 struct net_device_stats stats;
289 int rx_packet_max;
290 int host_port;
291 struct clk *clk;
292 u8 mac_addr[ETH_ALEN];
293 struct cpsw_slave *slaves;
294 struct cpdma_ctlr *dma;
295 struct cpdma_chan *txch, *rxch;
296 struct cpsw_ale *ale;
297 /* snapshot of IRQ numbers */
298 u32 irqs_table[4];
299 u32 num_irqs;
300};
301
302#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
303#define for_each_slave(priv, func, arg...) \
304 do { \
305 int idx; \
306 for (idx = 0; idx < (priv)->data.slaves; idx++) \
307 (func)((priv)->slaves + idx, ##arg); \
308 } while (0)
309
5c50a856
M		 310static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
311{
312 struct cpsw_priv *priv = netdev_priv(ndev);
313
314 if (ndev->flags & IFF_PROMISC) {
315 /* Enable promiscuous mode */
316 dev_err(priv->dev, "Ignoring Promiscuous mode\n");
317 return;
318 }
319
320 /* Clear all mcast from ALE */
321 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
322
323 if (!netdev_mc_empty(ndev)) {
324 struct netdev_hw_addr *ha;
325
326 /* program multicast address list into ALE register */
327 netdev_for_each_mc_addr(ha, ndev) {
328 cpsw_ale_add_mcast(priv->ale, (u8 *)ha->addr,
329 ALE_ALL_PORTS << priv->host_port, 0, 0);
330 }
331 }
332}
333
df828598
M		 334static void cpsw_intr_enable(struct cpsw_priv *priv)
335{
996a5c27
RC		 336 __raw_writel(0xFF, &priv->wr_regs->tx_en);
337 __raw_writel(0xFF, &priv->wr_regs->rx_en);
df828598
M		 338
339 cpdma_ctlr_int_ctrl(priv->dma, true);
340 return;
341}
342
343static void cpsw_intr_disable(struct cpsw_priv *priv)
344{
996a5c27
RC		 345 __raw_writel(0, &priv->wr_regs->tx_en);
346 __raw_writel(0, &priv->wr_regs->rx_en);
df828598
M		 347
348 cpdma_ctlr_int_ctrl(priv->dma, false);
349 return;
350}
351
352void cpsw_tx_handler(void *token, int len, int status)
353{
354 struct sk_buff *skb = token;
355 struct net_device *ndev = skb->dev;
356 struct cpsw_priv *priv = netdev_priv(ndev);
357
358 if (unlikely(netif_queue_stopped(ndev)))
359 netif_start_queue(ndev);
360 priv->stats.tx_packets++;
361 priv->stats.tx_bytes += len;
362 dev_kfree_skb_any(skb);
363}
364
365void cpsw_rx_handler(void *token, int len, int status)
366{
367 struct sk_buff *skb = token;
368 struct net_device *ndev = skb->dev;
369 struct cpsw_priv *priv = netdev_priv(ndev);
370 int ret = 0;
371
372 /* free and bail if we are shutting down */
373 if (unlikely(!netif_running(ndev)) ||
374 unlikely(!netif_carrier_ok(ndev))) {
375 dev_kfree_skb_any(skb);
376 return;
377 }
378 if (likely(status >= 0)) {
379 skb_put(skb, len);
380 skb->protocol = eth_type_trans(skb, ndev);
381 netif_receive_skb(skb);
382 priv->stats.rx_bytes += len;
383 priv->stats.rx_packets++;
384 skb = NULL;
385 }
386
387 if (unlikely(!netif_running(ndev))) {
388 if (skb)
389 dev_kfree_skb_any(skb);
390 return;
391 }
392
393 if (likely(!skb)) {
394 skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
395 if (WARN_ON(!skb))
396 return;
397
398 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
399 skb_tailroom(skb), GFP_KERNEL);
400 }
401 WARN_ON(ret < 0);
402}
403
404static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
405{
406 struct cpsw_priv *priv = dev_id;
407
408 if (likely(netif_running(priv->ndev))) {
409 cpsw_intr_disable(priv);
410 cpsw_disable_irq(priv);
411 napi_schedule(&priv->napi);
412 }
413 return IRQ_HANDLED;
414}
415
416static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
417{
418 if (priv->host_port == 0)
419 return slave_num + 1;
420 else
421 return slave_num;
422}
423
424static int cpsw_poll(struct napi_struct *napi, int budget)
425{
426 struct cpsw_priv *priv = napi_to_priv(napi);
427 int num_tx, num_rx;
428
429 num_tx = cpdma_chan_process(priv->txch, 128);
430 num_rx = cpdma_chan_process(priv->rxch, budget);
431
432 if (num_rx || num_tx)
433 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
434 num_rx, num_tx);
435
436 if (num_rx < budget) {
437 napi_complete(napi);
438 cpsw_intr_enable(priv);
439 cpdma_ctlr_eoi(priv->dma);
440 cpsw_enable_irq(priv);
441 }
442
443 return num_rx;
444}
445
446static inline void soft_reset(const char *module, void __iomem *reg)
447{
448 unsigned long timeout = jiffies + HZ;
449
450 __raw_writel(1, reg);
451 do {
452 cpu_relax();
453 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
454
455 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
456}
457
458#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
459 ((mac)[2] << 16) | ((mac)[3] << 24))
460#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
461
462static void cpsw_set_slave_mac(struct cpsw_slave *slave,
463 struct cpsw_priv *priv)
464{
9750a3ad
RC		 465 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
466 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
df828598
M		 467}
468
469static void _cpsw_adjust_link(struct cpsw_slave *slave,
470 struct cpsw_priv *priv, bool *link)
471{
472 struct phy_device *phy = slave->phy;
473 u32 mac_control = 0;
474 u32 slave_port;
475
476 if (!phy)
477 return;
478
479 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
480
481 if (phy->link) {
482 mac_control = priv->data.mac_control;
483
484 /* enable forwarding */
485 cpsw_ale_control_set(priv->ale, slave_port,
486 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
487
488 if (phy->speed == 1000)
489 mac_control |= BIT(7); /* GIGABITEN */
490 if (phy->duplex)
491 mac_control |= BIT(0); /* FULLDUPLEXEN */
342b7b74
DM		 492
493 /* set speed_in input in case RMII mode is used in 100Mbps */
494 if (phy->speed == 100)
495 mac_control |= BIT(15);
496
df828598
M		 497 *link = true;
498 } else {
499 mac_control = 0;
500 /* disable forwarding */
501 cpsw_ale_control_set(priv->ale, slave_port,
502 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
503 }
504
505 if (mac_control != slave->mac_control) {
506 phy_print_status(phy);
507 __raw_writel(mac_control, &slave->sliver->mac_control);
508 }
509
510 slave->mac_control = mac_control;
511}
512
513static void cpsw_adjust_link(struct net_device *ndev)
514{
515 struct cpsw_priv *priv = netdev_priv(ndev);
516 bool link = false;
517
518 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
519
520 if (link) {
521 netif_carrier_on(ndev);
522 if (netif_running(ndev))
523 netif_wake_queue(ndev);
524 } else {
525 netif_carrier_off(ndev);
526 netif_stop_queue(ndev);
527 }
528}
529
530static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
531{
532 static char *leader = "........................................";
533
534 if (!val)
535 return 0;
536 else
537 return snprintf(buf, maxlen, "%s %s %10d\n", name,
538 leader + strlen(name), val);
539}
540
541static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
542{
543 char name[32];
544 u32 slave_port;
545
546 sprintf(name, "slave-%d", slave->slave_num);
547
548 soft_reset(name, &slave->sliver->soft_reset);
549
550 /* setup priority mapping */
551 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
9750a3ad
RC		 552
553 switch (priv->version) {
554 case CPSW_VERSION_1:
555 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
556 break;
557 case CPSW_VERSION_2:
558 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
559 break;
560 }
df828598
M		 561
562 /* setup max packet size, and mac address */
563 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
564 cpsw_set_slave_mac(slave, priv);
565
566 slave->mac_control = 0; /* no link yet */
567
568 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
569
570 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
571 1 << slave_port, 0, ALE_MCAST_FWD_2);
572
573 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
574 &cpsw_adjust_link, 0, slave->data->phy_if);
575 if (IS_ERR(slave->phy)) {
576 dev_err(priv->dev, "phy %s not found on slave %d\n",
577 slave->data->phy_id, slave->slave_num);
578 slave->phy = NULL;
579 } else {
580 dev_info(priv->dev, "phy found : id is : 0x%x\n",
581 slave->phy->phy_id);
582 phy_start(slave->phy);
583 }
584}
585
586static void cpsw_init_host_port(struct cpsw_priv *priv)
587{
588 /* soft reset the controller and initialize ale */
589 soft_reset("cpsw", &priv->regs->soft_reset);
590 cpsw_ale_start(priv->ale);
591
592 /* switch to vlan unaware mode */
593 cpsw_ale_control_set(priv->ale, 0, ALE_VLAN_AWARE, 0);
594
595 /* setup host port priority mapping */
596 __raw_writel(CPDMA_TX_PRIORITY_MAP,
597 &priv->host_port_regs->cpdma_tx_pri_map);
598 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
599
600 cpsw_ale_control_set(priv->ale, priv->host_port,
601 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
602
603 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 0);
604 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
605 1 << priv->host_port, 0, ALE_MCAST_FWD_2);
606}
607
608static int cpsw_ndo_open(struct net_device *ndev)
609{
610 struct cpsw_priv *priv = netdev_priv(ndev);
611 int i, ret;
612 u32 reg;
613
614 cpsw_intr_disable(priv);
615 netif_carrier_off(ndev);
616
f150bd7f 617 pm_runtime_get_sync(&priv->pdev->dev);
df828598
M		 618
619 reg = __raw_readl(&priv->regs->id_ver);
e90cfac6 620 priv->version = reg;
df828598
M		 621
622 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
623 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
624 CPSW_RTL_VERSION(reg));
625
626 /* initialize host and slave ports */
627 cpsw_init_host_port(priv);
628 for_each_slave(priv, cpsw_slave_open, priv);
629
630 /* setup tx dma to fixed prio and zero offset */
631 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
632 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
633
634 /* disable priority elevation and enable statistics on all ports */
635 __raw_writel(0, &priv->regs->ptype);
636
637 /* enable statistics collection only on the host port */
638 __raw_writel(0x7, &priv->regs->stat_port_en);
639
640 if (WARN_ON(!priv->data.rx_descs))
641 priv->data.rx_descs = 128;
642
643 for (i = 0; i < priv->data.rx_descs; i++) {
644 struct sk_buff *skb;
645
646 ret = -ENOMEM;
647 skb = netdev_alloc_skb_ip_align(priv->ndev,
648 priv->rx_packet_max);
649 if (!skb)
650 break;
651 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
652 skb_tailroom(skb), GFP_KERNEL);
653 if (WARN_ON(ret < 0))
654 break;
655 }
656 /* continue even if we didn't manage to submit all receive descs */
657 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
658
659 cpdma_ctlr_start(priv->dma);
660 cpsw_intr_enable(priv);
661 napi_enable(&priv->napi);
662 cpdma_ctlr_eoi(priv->dma);
663
664 return 0;
665}
666
667static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
668{
669 if (!slave->phy)
670 return;
671 phy_stop(slave->phy);
672 phy_disconnect(slave->phy);
673 slave->phy = NULL;
674}
675
676static int cpsw_ndo_stop(struct net_device *ndev)
677{
678 struct cpsw_priv *priv = netdev_priv(ndev);
679
680 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
681 cpsw_intr_disable(priv);
682 cpdma_ctlr_int_ctrl(priv->dma, false);
683 cpdma_ctlr_stop(priv->dma);
684 netif_stop_queue(priv->ndev);
685 napi_disable(&priv->napi);
686 netif_carrier_off(priv->ndev);
687 cpsw_ale_stop(priv->ale);
688 for_each_slave(priv, cpsw_slave_stop, priv);
f150bd7f 689 pm_runtime_put_sync(&priv->pdev->dev);
df828598
M		 690 return 0;
691}
692
693static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
694 struct net_device *ndev)
695{
696 struct cpsw_priv *priv = netdev_priv(ndev);
697 int ret;
698
699 ndev->trans_start = jiffies;
700
701 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
702 cpsw_err(priv, tx_err, "packet pad failed\n");
703 priv->stats.tx_dropped++;
704 return NETDEV_TX_OK;
705 }
706
707 ret = cpdma_chan_submit(priv->txch, skb, skb->data,
708 skb->len, GFP_KERNEL);
709 if (unlikely(ret != 0)) {
710 cpsw_err(priv, tx_err, "desc submit failed\n");
711 goto fail;
712 }
713
714 return NETDEV_TX_OK;
715fail:
716 priv->stats.tx_dropped++;
717 netif_stop_queue(ndev);
718 return NETDEV_TX_BUSY;
719}
720
721static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
722{
723 /*
724 * The switch cannot operate in promiscuous mode without substantial
725 * headache. For promiscuous mode to work, we would need to put the
726 * ALE in bypass mode and route all traffic to the host port.
727 * Subsequently, the host will need to operate as a "bridge", learn,
728 * and flood as needed. For now, we simply complain here and
729 * do nothing about it :-)
730 */
731 if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
732 dev_err(&ndev->dev, "promiscuity ignored!\n");
733
734 /*
735 * The switch cannot filter multicast traffic unless it is configured
736 * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a
737 * whole bunch of additional logic that this driver does not implement
738 * at present.
739 */
740 if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
741 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
742}
743
744static void cpsw_ndo_tx_timeout(struct net_device *ndev)
745{
746 struct cpsw_priv *priv = netdev_priv(ndev);
747
748 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
749 priv->stats.tx_errors++;
750 cpsw_intr_disable(priv);
751 cpdma_ctlr_int_ctrl(priv->dma, false);
752 cpdma_chan_stop(priv->txch);
753 cpdma_chan_start(priv->txch);
754 cpdma_ctlr_int_ctrl(priv->dma, true);
755 cpsw_intr_enable(priv);
756 cpdma_ctlr_eoi(priv->dma);
757}
758
759static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
760{
761 struct cpsw_priv *priv = netdev_priv(ndev);
762 return &priv->stats;
763}
764
765#ifdef CONFIG_NET_POLL_CONTROLLER
766static void cpsw_ndo_poll_controller(struct net_device *ndev)
767{
768 struct cpsw_priv *priv = netdev_priv(ndev);
769
770 cpsw_intr_disable(priv);
771 cpdma_ctlr_int_ctrl(priv->dma, false);
772 cpsw_interrupt(ndev->irq, priv);
773 cpdma_ctlr_int_ctrl(priv->dma, true);
774 cpsw_intr_enable(priv);
775 cpdma_ctlr_eoi(priv->dma);
776}
777#endif
778
779static const struct net_device_ops cpsw_netdev_ops = {
780 .ndo_open = cpsw_ndo_open,
781 .ndo_stop = cpsw_ndo_stop,
782 .ndo_start_xmit = cpsw_ndo_start_xmit,
783 .ndo_change_rx_flags = cpsw_ndo_change_rx_flags,
784 .ndo_validate_addr = eth_validate_addr,
5c473ed2 785 .ndo_change_mtu = eth_change_mtu,
df828598
M		 786 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
787 .ndo_get_stats = cpsw_ndo_get_stats,
5c50a856 788 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
df828598
M		 789#ifdef CONFIG_NET_POLL_CONTROLLER
790 .ndo_poll_controller = cpsw_ndo_poll_controller,
791#endif
792};
793
794static void cpsw_get_drvinfo(struct net_device *ndev,
795 struct ethtool_drvinfo *info)
796{
797 struct cpsw_priv *priv = netdev_priv(ndev);
798 strcpy(info->driver, "TI CPSW Driver v1.0");
799 strcpy(info->version, "1.0");
800 strcpy(info->bus_info, priv->pdev->name);
801}
802
803static u32 cpsw_get_msglevel(struct net_device *ndev)
804{
805 struct cpsw_priv *priv = netdev_priv(ndev);
806 return priv->msg_enable;
807}
808
809static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
810{
811 struct cpsw_priv *priv = netdev_priv(ndev);
812 priv->msg_enable = value;
813}
814
815static const struct ethtool_ops cpsw_ethtool_ops = {
816 .get_drvinfo = cpsw_get_drvinfo,
817 .get_msglevel = cpsw_get_msglevel,
818 .set_msglevel = cpsw_set_msglevel,
819 .get_link = ethtool_op_get_link,
820};
821
822static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
823{
824 void __iomem *regs = priv->regs;
825 int slave_num = slave->slave_num;
826 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
827
828 slave->data = data;
829 slave->regs = regs + data->slave_reg_ofs;
830 slave->sliver = regs + data->sliver_reg_ofs;
831}
832
2eb32b0a
M		 833static int cpsw_probe_dt(struct cpsw_platform_data *data,
834 struct platform_device *pdev)
835{
836 struct device_node *node = pdev->dev.of_node;
837 struct device_node *slave_node;
838 int i = 0, ret;
839 u32 prop;
840
841 if (!node)
842 return -EINVAL;
843
844 if (of_property_read_u32(node, "slaves", &prop)) {
845 pr_err("Missing slaves property in the DT.\n");
846 return -EINVAL;
847 }
848 data->slaves = prop;
849
78ca0b28
RC		 850 if (of_property_read_u32(node, "cpts_active_slave", &prop)) {
851 pr_err("Missing cpts_active_slave property in the DT.\n");
852 ret = -EINVAL;
853 goto error_ret;
854 }
855 data->cpts_active_slave = prop;
856
2eb32b0a
M		 857 data->slave_data = kzalloc(sizeof(struct cpsw_slave_data) *
858 data->slaves, GFP_KERNEL);
859 if (!data->slave_data) {
860 pr_err("Could not allocate slave memory.\n");
861 return -EINVAL;
862 }
863
864 data->no_bd_ram = of_property_read_bool(node, "no_bd_ram");
865
866 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
867 pr_err("Missing cpdma_channels property in the DT.\n");
868 ret = -EINVAL;
869 goto error_ret;
870 }
871 data->channels = prop;
872
873 if (of_property_read_u32(node, "host_port_no", &prop)) {
874 pr_err("Missing host_port_no property in the DT.\n");
875 ret = -EINVAL;
876 goto error_ret;
877 }
878 data->host_port_num = prop;
879
880 if (of_property_read_u32(node, "cpdma_reg_ofs", &prop)) {
881 pr_err("Missing cpdma_reg_ofs property in the DT.\n");
882 ret = -EINVAL;
883 goto error_ret;
884 }
885 data->cpdma_reg_ofs = prop;
886
887 if (of_property_read_u32(node, "cpdma_sram_ofs", &prop)) {
888 pr_err("Missing cpdma_sram_ofs property in the DT.\n");
889 ret = -EINVAL;
890 goto error_ret;
891 }
892 data->cpdma_sram_ofs = prop;
893
894 if (of_property_read_u32(node, "ale_reg_ofs", &prop)) {
895 pr_err("Missing ale_reg_ofs property in the DT.\n");
896 ret = -EINVAL;
897 goto error_ret;
898 }
899 data->ale_reg_ofs = prop;
900
901 if (of_property_read_u32(node, "ale_entries", &prop)) {
902 pr_err("Missing ale_entries property in the DT.\n");
903 ret = -EINVAL;
904 goto error_ret;
905 }
906 data->ale_entries = prop;
907
908 if (of_property_read_u32(node, "host_port_reg_ofs", &prop)) {
909 pr_err("Missing host_port_reg_ofs property in the DT.\n");
910 ret = -EINVAL;
911 goto error_ret;
912 }
913 data->host_port_reg_ofs = prop;
914
915 if (of_property_read_u32(node, "hw_stats_reg_ofs", &prop)) {
916 pr_err("Missing hw_stats_reg_ofs property in the DT.\n");
917 ret = -EINVAL;
918 goto error_ret;
919 }
920 data->hw_stats_reg_ofs = prop;
921
6b60393e
RC		 922 if (of_property_read_u32(node, "cpts_reg_ofs", &prop)) {
923 pr_err("Missing cpts_reg_ofs property in the DT.\n");
924 ret = -EINVAL;
925 goto error_ret;
926 }
927 data->cpts_reg_ofs = prop;
928
2eb32b0a
M		 929 if (of_property_read_u32(node, "bd_ram_ofs", &prop)) {
930 pr_err("Missing bd_ram_ofs property in the DT.\n");
931 ret = -EINVAL;
932 goto error_ret;
933 }
934 data->bd_ram_ofs = prop;
935
936 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
937 pr_err("Missing bd_ram_size property in the DT.\n");
938 ret = -EINVAL;
939 goto error_ret;
940 }
941 data->bd_ram_size = prop;
942
943 if (of_property_read_u32(node, "rx_descs", &prop)) {
944 pr_err("Missing rx_descs property in the DT.\n");
945 ret = -EINVAL;
946 goto error_ret;
947 }
948 data->rx_descs = prop;
949
950 if (of_property_read_u32(node, "mac_control", &prop)) {
951 pr_err("Missing mac_control property in the DT.\n");
952 ret = -EINVAL;
953 goto error_ret;
954 }
955 data->mac_control = prop;
956
957 for_each_child_of_node(node, slave_node) {
958 struct cpsw_slave_data *slave_data = data->slave_data + i;
959 const char *phy_id = NULL;
960 const void *mac_addr = NULL;
961
962 if (of_property_read_string(slave_node, "phy_id", &phy_id)) {
963 pr_err("Missing slave[%d] phy_id property\n", i);
964 ret = -EINVAL;
965 goto error_ret;
966 }
967 slave_data->phy_id = phy_id;
968
969 if (of_property_read_u32(slave_node, "slave_reg_ofs", &prop)) {
970 pr_err("Missing slave[%d] slave_reg_ofs property\n", i);
971 ret = -EINVAL;
972 goto error_ret;
973 }
974 slave_data->slave_reg_ofs = prop;
975
976 if (of_property_read_u32(slave_node, "sliver_reg_ofs",
977 &prop)) {
978 pr_err("Missing slave[%d] sliver_reg_ofs property\n",
979 i);
980 ret = -EINVAL;
981 goto error_ret;
982 }
983 slave_data->sliver_reg_ofs = prop;
984
985 mac_addr = of_get_mac_address(slave_node);
986 if (mac_addr)
987 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
988
989 i++;
990 }
991
992 return 0;
993
994error_ret:
995 kfree(data->slave_data);
996 return ret;
997}
998
df828598
M		 999static int __devinit cpsw_probe(struct platform_device *pdev)
1000{
1001 struct cpsw_platform_data *data = pdev->dev.platform_data;
1002 struct net_device *ndev;
1003 struct cpsw_priv *priv;
1004 struct cpdma_params dma_params;
1005 struct cpsw_ale_params ale_params;
1006 void __iomem *regs;
1007 struct resource *res;
1008 int ret = 0, i, k = 0;
1009
df828598
M		 1010 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1011 if (!ndev) {
1012 pr_err("error allocating net_device\n");
1013 return -ENOMEM;
1014 }
1015
1016 platform_set_drvdata(pdev, ndev);
1017 priv = netdev_priv(ndev);
1018 spin_lock_init(&priv->lock);
df828598
M		 1019 priv->pdev = pdev;
1020 priv->ndev = ndev;
1021 priv->dev = &ndev->dev;
1022 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1023 priv->rx_packet_max = max(rx_packet_max, 128);
1024
2eb32b0a
M		 1025 if (cpsw_probe_dt(&priv->data, pdev)) {
1026 pr_err("cpsw: platform data missing\n");
1027 ret = -ENODEV;
1028 goto clean_ndev_ret;
1029 }
1030 data = &priv->data;
1031
df828598
M		 1032 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
1033 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
1034 pr_info("Detected MACID = %pM", priv->mac_addr);
1035 } else {
7efd26d0 1036 eth_random_addr(priv->mac_addr);
df828598
M		 1037 pr_info("Random MACID = %pM", priv->mac_addr);
1038 }
1039
1040 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1041
1042 priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
1043 GFP_KERNEL);
1044 if (!priv->slaves) {
1045 ret = -EBUSY;
1046 goto clean_ndev_ret;
1047 }
1048 for (i = 0; i < data->slaves; i++)
1049 priv->slaves[i].slave_num = i;
1050
f150bd7f
M		 1051 pm_runtime_enable(&pdev->dev);
1052 priv->clk = clk_get(&pdev->dev, "fck");
df828598 1053 if (IS_ERR(priv->clk)) {
f150bd7f
M		 1054 dev_err(&pdev->dev, "fck is not found\n");
1055 ret = -ENODEV;
1056 goto clean_slave_ret;
df828598
M		 1057 }
1058
1059 priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1060 if (!priv->cpsw_res) {
1061 dev_err(priv->dev, "error getting i/o resource\n");
1062 ret = -ENOENT;
1063 goto clean_clk_ret;
1064 }
1065
1066 if (!request_mem_region(priv->cpsw_res->start,
1067 resource_size(priv->cpsw_res), ndev->name)) {
1068 dev_err(priv->dev, "failed request i/o region\n");
1069 ret = -ENXIO;
1070 goto clean_clk_ret;
1071 }
1072
1073 regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
1074 if (!regs) {
1075 dev_err(priv->dev, "unable to map i/o region\n");
1076 goto clean_cpsw_iores_ret;
1077 }
1078 priv->regs = regs;
1079 priv->host_port = data->host_port_num;
1080 priv->host_port_regs = regs + data->host_port_reg_ofs;
1081
1082 priv->cpsw_ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1083 if (!priv->cpsw_ss_res) {
1084 dev_err(priv->dev, "error getting i/o resource\n");
1085 ret = -ENOENT;
1086 goto clean_clk_ret;
1087 }
1088
1089 if (!request_mem_region(priv->cpsw_ss_res->start,
1090 resource_size(priv->cpsw_ss_res), ndev->name)) {
1091 dev_err(priv->dev, "failed request i/o region\n");
1092 ret = -ENXIO;
1093 goto clean_clk_ret;
1094 }
1095
1096 regs = ioremap(priv->cpsw_ss_res->start,
1097 resource_size(priv->cpsw_ss_res));
1098 if (!regs) {
1099 dev_err(priv->dev, "unable to map i/o region\n");
1100 goto clean_cpsw_ss_iores_ret;
1101 }
996a5c27 1102 priv->wr_regs = regs;
df828598
M		 1103
1104 for_each_slave(priv, cpsw_slave_init, priv);
1105
1106 memset(&dma_params, 0, sizeof(dma_params));
1107 dma_params.dev = &pdev->dev;
1108 dma_params.dmaregs = cpsw_dma_regs((u32)priv->regs,
1109 data->cpdma_reg_ofs);
1110 dma_params.rxthresh = cpsw_dma_rxthresh((u32)priv->regs,
1111 data->cpdma_reg_ofs);
1112 dma_params.rxfree = cpsw_dma_rxfree((u32)priv->regs,
1113 data->cpdma_reg_ofs);
1114 dma_params.txhdp = cpsw_dma_txhdp((u32)priv->regs,
1115 data->cpdma_sram_ofs);
1116 dma_params.rxhdp = cpsw_dma_rxhdp((u32)priv->regs,
1117 data->cpdma_sram_ofs);
1118 dma_params.txcp = cpsw_dma_txcp((u32)priv->regs,
1119 data->cpdma_sram_ofs);
1120 dma_params.rxcp = cpsw_dma_rxcp((u32)priv->regs,
1121 data->cpdma_sram_ofs);
1122
1123 dma_params.num_chan = data->channels;
1124 dma_params.has_soft_reset = true;
1125 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
1126 dma_params.desc_mem_size = data->bd_ram_size;
1127 dma_params.desc_align = 16;
1128 dma_params.has_ext_regs = true;
1129 dma_params.desc_mem_phys = data->no_bd_ram ? 0 :
1130 (u32 __force)priv->cpsw_res->start + data->bd_ram_ofs;
1131 dma_params.desc_hw_addr = data->hw_ram_addr ?
1132 data->hw_ram_addr : dma_params.desc_mem_phys ;
1133
1134 priv->dma = cpdma_ctlr_create(&dma_params);
1135 if (!priv->dma) {
1136 dev_err(priv->dev, "error initializing dma\n");
1137 ret = -ENOMEM;
1138 goto clean_iomap_ret;
1139 }
1140
1141 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
1142 cpsw_tx_handler);
1143 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
1144 cpsw_rx_handler);
1145
1146 if (WARN_ON(!priv->txch || !priv->rxch)) {
1147 dev_err(priv->dev, "error initializing dma channels\n");
1148 ret = -ENOMEM;
1149 goto clean_dma_ret;
1150 }
1151
1152 memset(&ale_params, 0, sizeof(ale_params));
1153 ale_params.dev = &ndev->dev;
1154 ale_params.ale_regs = (void *)((u32)priv->regs) +
1155 ((u32)data->ale_reg_ofs);
1156 ale_params.ale_ageout = ale_ageout;
1157 ale_params.ale_entries = data->ale_entries;
1158 ale_params.ale_ports = data->slaves;
1159
1160 priv->ale = cpsw_ale_create(&ale_params);
1161 if (!priv->ale) {
1162 dev_err(priv->dev, "error initializing ale engine\n");
1163 ret = -ENODEV;
1164 goto clean_dma_ret;
1165 }
1166
1167 ndev->irq = platform_get_irq(pdev, 0);
1168 if (ndev->irq < 0) {
1169 dev_err(priv->dev, "error getting irq resource\n");
1170 ret = -ENOENT;
1171 goto clean_ale_ret;
1172 }
1173
1174 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1175 for (i = res->start; i <= res->end; i++) {
1176 if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
1177 dev_name(&pdev->dev), priv)) {
1178 dev_err(priv->dev, "error attaching irq\n");
1179 goto clean_ale_ret;
1180 }
1181 priv->irqs_table[k] = i;
1182 priv->num_irqs = k;
1183 }
1184 k++;
1185 }
1186
1187 ndev->flags |= IFF_ALLMULTI; /* see cpsw_ndo_change_rx_flags() */
1188
1189 ndev->netdev_ops = &cpsw_netdev_ops;
1190 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1191 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1192
1193 /* register the network device */
1194 SET_NETDEV_DEV(ndev, &pdev->dev);
1195 ret = register_netdev(ndev);
1196 if (ret) {
1197 dev_err(priv->dev, "error registering net device\n");
1198 ret = -ENODEV;
1199 goto clean_irq_ret;
1200 }
1201
1202 cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
1203 priv->cpsw_res->start, ndev->irq);
1204
1205 return 0;
1206
1207clean_irq_ret:
1208 free_irq(ndev->irq, priv);
1209clean_ale_ret:
1210 cpsw_ale_destroy(priv->ale);
1211clean_dma_ret:
1212 cpdma_chan_destroy(priv->txch);
1213 cpdma_chan_destroy(priv->rxch);
1214 cpdma_ctlr_destroy(priv->dma);
1215clean_iomap_ret:
1216 iounmap(priv->regs);
1217clean_cpsw_ss_iores_ret:
1218 release_mem_region(priv->cpsw_ss_res->start,
1219 resource_size(priv->cpsw_ss_res));
1220clean_cpsw_iores_ret:
1221 release_mem_region(priv->cpsw_res->start,
1222 resource_size(priv->cpsw_res));
1223clean_clk_ret:
1224 clk_put(priv->clk);
f150bd7f
M		 1225clean_slave_ret:
1226 pm_runtime_disable(&pdev->dev);
df828598
M		 1227 kfree(priv->slaves);
1228clean_ndev_ret:
1229 free_netdev(ndev);
1230 return ret;
1231}
1232
1233static int __devexit cpsw_remove(struct platform_device *pdev)
1234{
1235 struct net_device *ndev = platform_get_drvdata(pdev);
1236 struct cpsw_priv *priv = netdev_priv(ndev);
1237
1238 pr_info("removing device");
1239 platform_set_drvdata(pdev, NULL);
1240
1241 free_irq(ndev->irq, priv);
1242 cpsw_ale_destroy(priv->ale);
1243 cpdma_chan_destroy(priv->txch);
1244 cpdma_chan_destroy(priv->rxch);
1245 cpdma_ctlr_destroy(priv->dma);
1246 iounmap(priv->regs);
1247 release_mem_region(priv->cpsw_res->start,
1248 resource_size(priv->cpsw_res));
1249 release_mem_region(priv->cpsw_ss_res->start,
1250 resource_size(priv->cpsw_ss_res));
f150bd7f 1251 pm_runtime_disable(&pdev->dev);
df828598
M		 1252 clk_put(priv->clk);
1253 kfree(priv->slaves);
1254 free_netdev(ndev);
1255
1256 return 0;
1257}
1258
1259static int cpsw_suspend(struct device *dev)
1260{
1261 struct platform_device *pdev = to_platform_device(dev);
1262 struct net_device *ndev = platform_get_drvdata(pdev);
1263
1264 if (netif_running(ndev))
1265 cpsw_ndo_stop(ndev);
f150bd7f
M		 1266 pm_runtime_put_sync(&pdev->dev);
1267
df828598
M		 1268 return 0;
1269}
1270
1271static int cpsw_resume(struct device *dev)
1272{
1273 struct platform_device *pdev = to_platform_device(dev);
1274 struct net_device *ndev = platform_get_drvdata(pdev);
1275
f150bd7f 1276 pm_runtime_get_sync(&pdev->dev);
df828598
M		 1277 if (netif_running(ndev))
1278 cpsw_ndo_open(ndev);
1279 return 0;
1280}
1281
1282static const struct dev_pm_ops cpsw_pm_ops = {
1283 .suspend = cpsw_suspend,
1284 .resume = cpsw_resume,
1285};
1286
2eb32b0a
M		 1287static const struct of_device_id cpsw_of_mtable[] = {
1288 { .compatible = "ti,cpsw", },
1289 { /* sentinel */ },
1290};
1291
df828598
M		 1292static struct platform_driver cpsw_driver = {
1293 .driver = {
1294 .name = "cpsw",
1295 .owner = THIS_MODULE,
1296 .pm = &cpsw_pm_ops,
2eb32b0a 1297 .of_match_table = of_match_ptr(cpsw_of_mtable),
df828598
M		 1298 },
1299 .probe = cpsw_probe,
1300 .remove = __devexit_p(cpsw_remove),
1301};
1302
1303static int __init cpsw_init(void)
1304{
1305 return platform_driver_register(&cpsw_driver);
1306}
1307late_initcall(cpsw_init);
1308
1309static void __exit cpsw_exit(void)
1310{
1311 platform_driver_unregister(&cpsw_driver);
1312}
1313module_exit(cpsw_exit);
1314
1315MODULE_LICENSE("GPL");
1316MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
1317MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
1318MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux 6.x block layer and io_uring tree(s)