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net: ethernet: ti: cpsw: create common struct to hold shared driver data
[linux-block.git] / drivers / net / ethernet / ti / cpsw.c
CommitLineData
df828598
M		 1/*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/timer.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/irqreturn.h>
23#include <linux/interrupt.h>
24#include <linux/if_ether.h>
25#include <linux/etherdevice.h>
26#include <linux/netdevice.h>
2e5b38ab 27#include <linux/net_tstamp.h>
df828598
M		 28#include <linux/phy.h>
29#include <linux/workqueue.h>
30#include <linux/delay.h>
f150bd7f 31#include <linux/pm_runtime.h>
1d147ccb 32#include <linux/gpio.h>
2eb32b0a 33#include <linux/of.h>
9e42f715 34#include <linux/of_mdio.h>
2eb32b0a
M		 35#include <linux/of_net.h>
36#include <linux/of_device.h>
3b72c2fe 37#include <linux/if_vlan.h>
df828598 38
739683b4 39#include <linux/pinctrl/consumer.h>
df828598 40
dbe34724 41#include "cpsw.h"
df828598 42#include "cpsw_ale.h"
2e5b38ab 43#include "cpts.h"
df828598
M		 44#include "davinci_cpdma.h"
45
46#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55#define cpsw_info(priv, type, format, ...) \
56do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59} while (0)
60
61#define cpsw_err(priv, type, format, ...) \
62do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65} while (0)
66
67#define cpsw_dbg(priv, type, format, ...) \
68do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71} while (0)
72
73#define cpsw_notice(priv, type, format, ...) \
74do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77} while (0)
78
5c50a856
M		 79#define ALE_ALL_PORTS 0x7
80
df828598
M		 81#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
e90cfac6
RC		 85#define CPSW_VERSION_1 0x19010a
86#define CPSW_VERSION_2 0x19010c
c193f365 87#define CPSW_VERSION_3 0x19010f
926489be 88#define CPSW_VERSION_4 0x190112
549985ee
RC		 89
90#define HOST_PORT_NUM 0
91#define SLIVER_SIZE 0x40
92
93#define CPSW1_HOST_PORT_OFFSET 0x028
94#define CPSW1_SLAVE_OFFSET 0x050
95#define CPSW1_SLAVE_SIZE 0x040
96#define CPSW1_CPDMA_OFFSET 0x100
97#define CPSW1_STATERAM_OFFSET 0x200
d9718546 98#define CPSW1_HW_STATS 0x400
549985ee
RC		 99#define CPSW1_CPTS_OFFSET 0x500
100#define CPSW1_ALE_OFFSET 0x600
101#define CPSW1_SLIVER_OFFSET 0x700
102
103#define CPSW2_HOST_PORT_OFFSET 0x108
104#define CPSW2_SLAVE_OFFSET 0x200
105#define CPSW2_SLAVE_SIZE 0x100
106#define CPSW2_CPDMA_OFFSET 0x800
d9718546 107#define CPSW2_HW_STATS 0x900
549985ee
RC		 108#define CPSW2_STATERAM_OFFSET 0xa00
109#define CPSW2_CPTS_OFFSET 0xc00
110#define CPSW2_ALE_OFFSET 0xd00
111#define CPSW2_SLIVER_OFFSET 0xd80
112#define CPSW2_BD_OFFSET 0x2000
113
df828598
M		 114#define CPDMA_RXTHRESH 0x0c0
115#define CPDMA_RXFREE 0x0e0
116#define CPDMA_TXHDP 0x00
117#define CPDMA_RXHDP 0x20
118#define CPDMA_TXCP 0x40
119#define CPDMA_RXCP 0x60
120
df828598
M		 121#define CPSW_POLL_WEIGHT 64
122#define CPSW_MIN_PACKET_SIZE 60
123#define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125#define RX_PRIORITY_MAPPING 0x76543210
126#define TX_PRIORITY_MAPPING 0x33221100
127#define CPDMA_TX_PRIORITY_MAP 0x76543210
128
3b72c2fe
M		 129#define CPSW_VLAN_AWARE BIT(1)
130#define CPSW_ALE_VLAN_AWARE 1
131
35717d8d
JO		 132#define CPSW_FIFO_NORMAL_MODE (0 << 16)
133#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
d9ba8f9e 135
ff5b8ef2
M		 136#define CPSW_INTPACEEN (0x3f << 16)
137#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138#define CPSW_CMINTMAX_CNT 63
139#define CPSW_CMINTMIN_CNT 2
140#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
d3bb9c58
M		 143#define cpsw_slave_index(priv) \
144 ((priv->data.dual_emac) ? priv->emac_port : \
145 priv->data.active_slave)
146
df828598
M		 147static int debug_level;
148module_param(debug_level, int, 0);
149MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
150
151static int ale_ageout = 10;
152module_param(ale_ageout, int, 0);
153MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
154
155static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
156module_param(rx_packet_max, int, 0);
157MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
158
996a5c27 159struct cpsw_wr_regs {
df828598
M		 160 u32 id_ver;
161 u32 soft_reset;
162 u32 control;
163 u32 int_control;
164 u32 rx_thresh_en;
165 u32 rx_en;
166 u32 tx_en;
167 u32 misc_en;
ff5b8ef2
M		 168 u32 mem_allign1[8];
169 u32 rx_thresh_stat;
170 u32 rx_stat;
171 u32 tx_stat;
172 u32 misc_stat;
173 u32 mem_allign2[8];
174 u32 rx_imax;
175 u32 tx_imax;
176
df828598
M		 177};
178
996a5c27 179struct cpsw_ss_regs {
df828598
M		 180 u32 id_ver;
181 u32 control;
182 u32 soft_reset;
183 u32 stat_port_en;
184 u32 ptype;
bd357af2
RC		 185 u32 soft_idle;
186 u32 thru_rate;
187 u32 gap_thresh;
188 u32 tx_start_wds;
189 u32 flow_control;
190 u32 vlan_ltype;
191 u32 ts_ltype;
192 u32 dlr_ltype;
df828598
M		 193};
194
9750a3ad
RC		 195/* CPSW_PORT_V1 */
196#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
197#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
198#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
199#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
200#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
201#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
202#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
203#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
204
205/* CPSW_PORT_V2 */
206#define CPSW2_CONTROL 0x00 /* Control Register */
207#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
208#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
209#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
210#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
211#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
212#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
213
214/* CPSW_PORT_V1 and V2 */
215#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
216#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
217#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
218
219/* CPSW_PORT_V2 only */
220#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
221#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
222#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
223#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
224#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
225#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
226#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
227#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
228
229/* Bit definitions for the CPSW2_CONTROL register */
230#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
231#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
232#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
233#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
234#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
235#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
236#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
237#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
238#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
239#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
09c55372
GC		 240#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
241#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
9750a3ad
RC		 242#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
243#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
244#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
245#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
246#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
247
09c55372
GC		 248#define CTRL_V2_TS_BITS \
249 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
250 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
9750a3ad 251
09c55372
GC		 252#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
253#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
254#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
255
256
257#define CTRL_V3_TS_BITS \
258 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
259 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
260 TS_LTYPE1_EN)
261
262#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
263#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
264#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
9750a3ad
RC		 265
266/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268#define TS_SEQ_ID_OFFSET_MASK (0x3f)
269#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270#define TS_MSG_TYPE_EN_MASK (0xffff)
271
272/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
df828598 274
2e5b38ab
RC		 275/* Bit definitions for the CPSW1_TS_CTL register */
276#define CPSW_V1_TS_RX_EN BIT(0)
277#define CPSW_V1_TS_TX_EN BIT(4)
278#define CPSW_V1_MSG_TYPE_OFS 16
279
280/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
282
df828598
M		 283struct cpsw_host_regs {
284 u32 max_blks;
285 u32 blk_cnt;
d9ba8f9e 286 u32 tx_in_ctl;
df828598
M		 287 u32 port_vlan;
288 u32 tx_pri_map;
289 u32 cpdma_tx_pri_map;
290 u32 cpdma_rx_chan_map;
291};
292
293struct cpsw_sliver_regs {
294 u32 id_ver;
295 u32 mac_control;
296 u32 mac_status;
297 u32 soft_reset;
298 u32 rx_maxlen;
299 u32 __reserved_0;
300 u32 rx_pause;
301 u32 tx_pause;
302 u32 __reserved_1;
303 u32 rx_pri_map;
304};
305
d9718546
M		 306struct cpsw_hw_stats {
307 u32 rxgoodframes;
308 u32 rxbroadcastframes;
309 u32 rxmulticastframes;
310 u32 rxpauseframes;
311 u32 rxcrcerrors;
312 u32 rxaligncodeerrors;
313 u32 rxoversizedframes;
314 u32 rxjabberframes;
315 u32 rxundersizedframes;
316 u32 rxfragments;
317 u32 __pad_0[2];
318 u32 rxoctets;
319 u32 txgoodframes;
320 u32 txbroadcastframes;
321 u32 txmulticastframes;
322 u32 txpauseframes;
323 u32 txdeferredframes;
324 u32 txcollisionframes;
325 u32 txsinglecollframes;
326 u32 txmultcollframes;
327 u32 txexcessivecollisions;
328 u32 txlatecollisions;
329 u32 txunderrun;
330 u32 txcarriersenseerrors;
331 u32 txoctets;
332 u32 octetframes64;
333 u32 octetframes65t127;
334 u32 octetframes128t255;
335 u32 octetframes256t511;
336 u32 octetframes512t1023;
337 u32 octetframes1024tup;
338 u32 netoctets;
339 u32 rxsofoverruns;
340 u32 rxmofoverruns;
341 u32 rxdmaoverruns;
342};
343
df828598 344struct cpsw_slave {
9750a3ad 345 void __iomem *regs;
df828598
M		 346 struct cpsw_sliver_regs __iomem *sliver;
347 int slave_num;
348 u32 mac_control;
349 struct cpsw_slave_data *data;
350 struct phy_device *phy;
d9ba8f9e
M		 351 struct net_device *ndev;
352 u32 port_vlan;
353 u32 open_stat;
df828598
M		 354};
355
9750a3ad
RC		 356static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
357{
358 return __raw_readl(slave->regs + offset);
359}
360
361static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
362{
363 __raw_writel(val, slave->regs + offset);
364}
365
649a1688 366struct cpsw_common {
df828598 367 struct platform_device *pdev;
649a1688
IK		 368};
369
370struct cpsw_priv {
df828598 371 struct net_device *ndev;
32a7432c
M		 372 struct napi_struct napi_rx;
373 struct napi_struct napi_tx;
df828598
M		 374 struct device *dev;
375 struct cpsw_platform_data data;
996a5c27
RC		 376 struct cpsw_ss_regs __iomem *regs;
377 struct cpsw_wr_regs __iomem *wr_regs;
d9718546 378 u8 __iomem *hw_stats;
df828598
M		 379 struct cpsw_host_regs __iomem *host_port_regs;
380 u32 msg_enable;
e90cfac6 381 u32 version;
ff5b8ef2
M		 382 u32 coal_intvl;
383 u32 bus_freq_mhz;
df828598 384 int rx_packet_max;
df828598
M		 385 u8 mac_addr[ETH_ALEN];
386 struct cpsw_slave *slaves;
387 struct cpdma_ctlr *dma;
388 struct cpdma_chan *txch, *rxch;
389 struct cpsw_ale *ale;
1923d6e4
M		 390 bool rx_pause;
391 bool tx_pause;
7da11600
M		 392 bool quirk_irq;
393 bool rx_irq_disabled;
394 bool tx_irq_disabled;
df828598
M		 395 /* snapshot of IRQ numbers */
396 u32 irqs_table[4];
397 u32 num_irqs;
9232b16d 398 struct cpts *cpts;
d9ba8f9e 399 u32 emac_port;
649a1688 400 struct cpsw_common *cpsw;
df828598
M		 401};
402
d9718546
M		 403struct cpsw_stats {
404 char stat_string[ETH_GSTRING_LEN];
405 int type;
406 int sizeof_stat;
407 int stat_offset;
408};
409
410enum {
411 CPSW_STATS,
412 CPDMA_RX_STATS,
413 CPDMA_TX_STATS,
414};
415
416#define CPSW_STAT(m) CPSW_STATS, \
417 sizeof(((struct cpsw_hw_stats *)0)->m), \
418 offsetof(struct cpsw_hw_stats, m)
419#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
420 sizeof(((struct cpdma_chan_stats *)0)->m), \
421 offsetof(struct cpdma_chan_stats, m)
422#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
423 sizeof(((struct cpdma_chan_stats *)0)->m), \
424 offsetof(struct cpdma_chan_stats, m)
425
426static const struct cpsw_stats cpsw_gstrings_stats[] = {
427 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
428 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
429 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
430 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
431 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
432 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
433 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
434 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
435 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
436 { "Rx Fragments", CPSW_STAT(rxfragments) },
437 { "Rx Octets", CPSW_STAT(rxoctets) },
438 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
439 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
440 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
441 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
442 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
443 { "Collisions", CPSW_STAT(txcollisionframes) },
444 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
445 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
446 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
447 { "Late Collisions", CPSW_STAT(txlatecollisions) },
448 { "Tx Underrun", CPSW_STAT(txunderrun) },
449 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
450 { "Tx Octets", CPSW_STAT(txoctets) },
451 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
452 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
453 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
454 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
455 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
456 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
457 { "Net Octets", CPSW_STAT(netoctets) },
458 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
459 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
460 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
461 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
462 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
463 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
464 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
465 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
466 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
467 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
468 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
469 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
470 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
471 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
472 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
473 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
474 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
475 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
476 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
477 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
478 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
479 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
480 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
481 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
482 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
483 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
484 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
485 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
486 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
487};
488
489#define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
490
649a1688 491#define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
df828598 492#define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
d9ba8f9e
M		 493#define for_each_slave(priv, func, arg...) \
494 do { \
6e6ceaed
SS		 495 struct cpsw_slave *slave; \
496 int n; \
d9ba8f9e
M		 497 if (priv->data.dual_emac) \
498 (func)((priv)->slaves + priv->emac_port, ##arg);\
499 else \
6e6ceaed
SS		 500 for (n = (priv)->data.slaves, \
501 slave = (priv)->slaves; \
502 n; n--) \
503 (func)(slave++, ##arg); \
d9ba8f9e 504 } while (0)
d9ba8f9e 505#define cpsw_get_slave_priv(priv, __slave_no__) \
1973db0d
M		 506 (((__slave_no__ < priv->data.slaves) && \
507 (priv->slaves[__slave_no__].ndev)) ? \
d9ba8f9e
M		 508 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
509
510#define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
511 do { \
512 if (!priv->data.dual_emac) \
513 break; \
514 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
82b52104 515 ndev = priv->slaves[0].ndev; \
d9ba8f9e
M		 516 priv = netdev_priv(ndev); \
517 skb->dev = ndev; \
518 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
82b52104 519 ndev = priv->slaves[1].ndev; \
d9ba8f9e
M		 520 priv = netdev_priv(ndev); \
521 skb->dev = ndev; \
522 } \
df828598 523 } while (0)
d9ba8f9e
M		 524#define cpsw_add_mcast(priv, addr) \
525 do { \
526 if (priv->data.dual_emac) { \
527 struct cpsw_slave *slave = priv->slaves + \
528 priv->emac_port; \
6f1f5836 529 int slave_port = cpsw_get_slave_port( \
d9ba8f9e
M		 530 slave->slave_num); \
531 cpsw_ale_add_mcast(priv->ale, addr, \
71a2cbb7 532 1 << slave_port | ALE_PORT_HOST, \
d9ba8f9e
M		 533 ALE_VLAN, slave->port_vlan, 0); \
534 } else { \
535 cpsw_ale_add_mcast(priv->ale, addr, \
61f1cef9 536 ALE_ALL_PORTS, \
d9ba8f9e
M		 537 0, 0, 0); \
538 } \
539 } while (0)
540
6f1f5836 541static inline int cpsw_get_slave_port(u32 slave_num)
d9ba8f9e 542{
71a2cbb7 543 return slave_num + 1;
d9ba8f9e 544}
df828598 545
0cd8f9cc
M		 546static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
547{
548 struct cpsw_priv *priv = netdev_priv(ndev);
549 struct cpsw_ale *ale = priv->ale;
550 int i;
551
552 if (priv->data.dual_emac) {
553 bool flag = false;
554
555 /* Enabling promiscuous mode for one interface will be
556 * common for both the interface as the interface shares
557 * the same hardware resource.
558 */
0d961b3b 559 for (i = 0; i < priv->data.slaves; i++)
0cd8f9cc
M		 560 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
561 flag = true;
562
563 if (!enable && flag) {
564 enable = true;
565 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
566 }
567
568 if (enable) {
569 /* Enable Bypass */
570 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
571
572 dev_dbg(&ndev->dev, "promiscuity enabled\n");
573 } else {
574 /* Disable Bypass */
575 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
576 dev_dbg(&ndev->dev, "promiscuity disabled\n");
577 }
578 } else {
579 if (enable) {
580 unsigned long timeout = jiffies + HZ;
581
6f979eb3
LS		 582 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
583 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 584 cpsw_ale_control_set(ale, i,
585 ALE_PORT_NOLEARN, 1);
586 cpsw_ale_control_set(ale, i,
587 ALE_PORT_NO_SA_UPDATE, 1);
588 }
589
590 /* Clear All Untouched entries */
591 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
592 do {
593 cpu_relax();
594 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
595 break;
596 } while (time_after(timeout, jiffies));
597 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
598
599 /* Clear all mcast from ALE */
61f1cef9 600 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
0cd8f9cc
M		 601
602 /* Flood All Unicast Packets to Host port */
603 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
604 dev_dbg(&ndev->dev, "promiscuity enabled\n");
605 } else {
6f979eb3 606 /* Don't Flood All Unicast Packets to Host port */
0cd8f9cc
M		 607 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
608
6f979eb3
LS		 609 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
610 for (i = 0; i <= priv->data.slaves; i++) {
0cd8f9cc
M		 611 cpsw_ale_control_set(ale, i,
612 ALE_PORT_NOLEARN, 0);
613 cpsw_ale_control_set(ale, i,
614 ALE_PORT_NO_SA_UPDATE, 0);
615 }
616 dev_dbg(&ndev->dev, "promiscuity disabled\n");
617 }
618 }
619}
620
5c50a856
M		 621static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
622{
623 struct cpsw_priv *priv = netdev_priv(ndev);
25906052
M		 624 int vid;
625
626 if (priv->data.dual_emac)
627 vid = priv->slaves[priv->emac_port].port_vlan;
628 else
629 vid = priv->data.default_vlan;
5c50a856
M		 630
631 if (ndev->flags & IFF_PROMISC) {
632 /* Enable promiscuous mode */
0cd8f9cc 633 cpsw_set_promiscious(ndev, true);
1e5c4bc4 634 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
5c50a856 635 return;
0cd8f9cc
M		 636 } else {
637 /* Disable promiscuous mode */
638 cpsw_set_promiscious(ndev, false);
5c50a856
M		 639 }
640
1e5c4bc4
LS		 641 /* Restore allmulti on vlans if necessary */
642 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
643
5c50a856 644 /* Clear all mcast from ALE */
61f1cef9 645 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS, vid);
5c50a856
M		 646
647 if (!netdev_mc_empty(ndev)) {
648 struct netdev_hw_addr *ha;
649
650 /* program multicast address list into ALE register */
651 netdev_for_each_mc_addr(ha, ndev) {
d9ba8f9e 652 cpsw_add_mcast(priv, (u8 *)ha->addr);
5c50a856
M		 653 }
654 }
655}
656
df828598
M		 657static void cpsw_intr_enable(struct cpsw_priv *priv)
658{
996a5c27
RC		 659 __raw_writel(0xFF, &priv->wr_regs->tx_en);
660 __raw_writel(0xFF, &priv->wr_regs->rx_en);
df828598
M		 661
662 cpdma_ctlr_int_ctrl(priv->dma, true);
663 return;
664}
665
666static void cpsw_intr_disable(struct cpsw_priv *priv)
667{
996a5c27
RC		 668 __raw_writel(0, &priv->wr_regs->tx_en);
669 __raw_writel(0, &priv->wr_regs->rx_en);
df828598
M		 670
671 cpdma_ctlr_int_ctrl(priv->dma, false);
672 return;
673}
674
1a3b5056 675static void cpsw_tx_handler(void *token, int len, int status)
df828598
M		 676{
677 struct sk_buff *skb = token;
678 struct net_device *ndev = skb->dev;
679 struct cpsw_priv *priv = netdev_priv(ndev);
680
fae50823
M		 681 /* Check whether the queue is stopped due to stalled tx dma, if the
682 * queue is stopped then start the queue as we have free desc for tx
683 */
df828598 684 if (unlikely(netif_queue_stopped(ndev)))
b56d6b3f 685 netif_wake_queue(ndev);
9232b16d 686 cpts_tx_timestamp(priv->cpts, skb);
8dc43ddc
TK		 687 ndev->stats.tx_packets++;
688 ndev->stats.tx_bytes += len;
df828598
M		 689 dev_kfree_skb_any(skb);
690}
691
1a3b5056 692static void cpsw_rx_handler(void *token, int len, int status)
df828598
M		 693{
694 struct sk_buff *skb = token;
b4727e69 695 struct sk_buff *new_skb;
df828598
M		 696 struct net_device *ndev = skb->dev;
697 struct cpsw_priv *priv = netdev_priv(ndev);
698 int ret = 0;
699
d9ba8f9e
M		 700 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
701
16e5c57d 702 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
a0e2c822
M		 703 bool ndev_status = false;
704 struct cpsw_slave *slave = priv->slaves;
705 int n;
706
707 if (priv->data.dual_emac) {
708 /* In dual emac mode check for all interfaces */
709 for (n = priv->data.slaves; n; n--, slave++)
710 if (netif_running(slave->ndev))
711 ndev_status = true;
712 }
713
714 if (ndev_status && (status >= 0)) {
715 /* The packet received is for the interface which
716 * is already down and the other interface is up
dbedd44e 717 * and running, instead of freeing which results
a0e2c822
M		 718 * in reducing of the number of rx descriptor in
719 * DMA engine, requeue skb back to cpdma.
720 */
721 new_skb = skb;
722 goto requeue;
723 }
724
b4727e69 725 /* the interface is going down, skbs are purged */
df828598
M		 726 dev_kfree_skb_any(skb);
727 return;
728 }
b4727e69
SS		 729
730 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
731 if (new_skb) {
df828598 732 skb_put(skb, len);
9232b16d 733 cpts_rx_timestamp(priv->cpts, skb);
df828598
M		 734 skb->protocol = eth_type_trans(skb, ndev);
735 netif_receive_skb(skb);
8dc43ddc
TK		 736 ndev->stats.rx_bytes += len;
737 ndev->stats.rx_packets++;
b4727e69 738 } else {
8dc43ddc 739 ndev->stats.rx_dropped++;
b4727e69 740 new_skb = skb;
df828598
M		 741 }
742
a0e2c822 743requeue:
b4727e69
SS		 744 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
745 skb_tailroom(new_skb), 0);
746 if (WARN_ON(ret < 0))
747 dev_kfree_skb_any(new_skb);
df828598
M		 748}
749
c03abd84 750static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
df828598
M		 751{
752 struct cpsw_priv *priv = dev_id;
7ce67a38 753
32a7432c 754 writel(0, &priv->wr_regs->tx_en);
c03abd84 755 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
c03abd84 756
7da11600
M		 757 if (priv->quirk_irq) {
758 disable_irq_nosync(priv->irqs_table[1]);
759 priv->tx_irq_disabled = true;
760 }
761
32a7432c 762 napi_schedule(&priv->napi_tx);
c03abd84
FB		 763 return IRQ_HANDLED;
764}
765
766static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
767{
768 struct cpsw_priv *priv = dev_id;
769
770 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
870915fe 771 writel(0, &priv->wr_regs->rx_en);
fd51cf19 772
7da11600
M		 773 if (priv->quirk_irq) {
774 disable_irq_nosync(priv->irqs_table[0]);
775 priv->rx_irq_disabled = true;
776 }
777
32a7432c 778 napi_schedule(&priv->napi_rx);
d354eb85 779 return IRQ_HANDLED;
df828598
M		 780}
781
32a7432c
M		 782static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
783{
784 struct cpsw_priv *priv = napi_to_priv(napi_tx);
785 int num_tx;
786
787 num_tx = cpdma_chan_process(priv->txch, budget);
788 if (num_tx < budget) {
789 napi_complete(napi_tx);
790 writel(0xff, &priv->wr_regs->tx_en);
7da11600
M		 791 if (priv->quirk_irq && priv->tx_irq_disabled) {
792 priv->tx_irq_disabled = false;
793 enable_irq(priv->irqs_table[1]);
794 }
32a7432c
M		 795 }
796
32a7432c
M		 797 return num_tx;
798}
799
800static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
df828598 801{
32a7432c 802 struct cpsw_priv *priv = napi_to_priv(napi_rx);
1e353cdd 803 int num_rx;
df828598 804
510a1e72 805 num_rx = cpdma_chan_process(priv->rxch, budget);
df828598 806 if (num_rx < budget) {
32a7432c 807 napi_complete(napi_rx);
870915fe 808 writel(0xff, &priv->wr_regs->rx_en);
7da11600
M		 809 if (priv->quirk_irq && priv->rx_irq_disabled) {
810 priv->rx_irq_disabled = false;
811 enable_irq(priv->irqs_table[0]);
812 }
df828598
M		 813 }
814
815 return num_rx;
816}
817
818static inline void soft_reset(const char *module, void __iomem *reg)
819{
820 unsigned long timeout = jiffies + HZ;
821
822 __raw_writel(1, reg);
823 do {
824 cpu_relax();
825 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
826
827 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
828}
829
830#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
831 ((mac)[2] << 16) | ((mac)[3] << 24))
832#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
833
834static void cpsw_set_slave_mac(struct cpsw_slave *slave,
835 struct cpsw_priv *priv)
836{
9750a3ad
RC		 837 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
838 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
df828598
M		 839}
840
841static void _cpsw_adjust_link(struct cpsw_slave *slave,
842 struct cpsw_priv *priv, bool *link)
843{
844 struct phy_device *phy = slave->phy;
845 u32 mac_control = 0;
846 u32 slave_port;
847
848 if (!phy)
849 return;
850
6f1f5836 851 slave_port = cpsw_get_slave_port(slave->slave_num);
df828598
M		 852
853 if (phy->link) {
854 mac_control = priv->data.mac_control;
855
856 /* enable forwarding */
857 cpsw_ale_control_set(priv->ale, slave_port,
858 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
859
860 if (phy->speed == 1000)
861 mac_control |= BIT(7); /* GIGABITEN */
862 if (phy->duplex)
863 mac_control |= BIT(0); /* FULLDUPLEXEN */
342b7b74
DM		 864
865 /* set speed_in input in case RMII mode is used in 100Mbps */
866 if (phy->speed == 100)
867 mac_control |= BIT(15);
a81d8762
M		 868 else if (phy->speed == 10)
869 mac_control |= BIT(18); /* In Band mode */
342b7b74 870
1923d6e4
M		 871 if (priv->rx_pause)
872 mac_control |= BIT(3);
873
874 if (priv->tx_pause)
875 mac_control |= BIT(4);
876
df828598
M		 877 *link = true;
878 } else {
879 mac_control = 0;
880 /* disable forwarding */
881 cpsw_ale_control_set(priv->ale, slave_port,
882 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
883 }
884
885 if (mac_control != slave->mac_control) {
886 phy_print_status(phy);
887 __raw_writel(mac_control, &slave->sliver->mac_control);
888 }
889
890 slave->mac_control = mac_control;
891}
892
893static void cpsw_adjust_link(struct net_device *ndev)
894{
895 struct cpsw_priv *priv = netdev_priv(ndev);
896 bool link = false;
897
898 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
899
900 if (link) {
901 netif_carrier_on(ndev);
902 if (netif_running(ndev))
903 netif_wake_queue(ndev);
904 } else {
905 netif_carrier_off(ndev);
906 netif_stop_queue(ndev);
907 }
908}
909
ff5b8ef2
M		 910static int cpsw_get_coalesce(struct net_device *ndev,
911 struct ethtool_coalesce *coal)
912{
913 struct cpsw_priv *priv = netdev_priv(ndev);
914
915 coal->rx_coalesce_usecs = priv->coal_intvl;
916 return 0;
917}
918
919static int cpsw_set_coalesce(struct net_device *ndev,
920 struct ethtool_coalesce *coal)
921{
922 struct cpsw_priv *priv = netdev_priv(ndev);
923 u32 int_ctrl;
924 u32 num_interrupts = 0;
925 u32 prescale = 0;
926 u32 addnl_dvdr = 1;
927 u32 coal_intvl = 0;
928
ff5b8ef2
M		 929 coal_intvl = coal->rx_coalesce_usecs;
930
931 int_ctrl = readl(&priv->wr_regs->int_control);
932 prescale = priv->bus_freq_mhz * 4;
933
a84bc2a9
M		 934 if (!coal->rx_coalesce_usecs) {
935 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
936 goto update_return;
937 }
938
ff5b8ef2
M		 939 if (coal_intvl < CPSW_CMINTMIN_INTVL)
940 coal_intvl = CPSW_CMINTMIN_INTVL;
941
942 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
943 /* Interrupt pacer works with 4us Pulse, we can
944 * throttle further by dilating the 4us pulse.
945 */
946 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
947
948 if (addnl_dvdr > 1) {
949 prescale *= addnl_dvdr;
950 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
951 coal_intvl = (CPSW_CMINTMAX_INTVL
952 * addnl_dvdr);
953 } else {
954 addnl_dvdr = 1;
955 coal_intvl = CPSW_CMINTMAX_INTVL;
956 }
957 }
958
959 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
960 writel(num_interrupts, &priv->wr_regs->rx_imax);
961 writel(num_interrupts, &priv->wr_regs->tx_imax);
962
963 int_ctrl |= CPSW_INTPACEEN;
964 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
965 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
a84bc2a9
M		 966
967update_return:
ff5b8ef2
M		 968 writel(int_ctrl, &priv->wr_regs->int_control);
969
970 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
971 if (priv->data.dual_emac) {
972 int i;
973
974 for (i = 0; i < priv->data.slaves; i++) {
975 priv = netdev_priv(priv->slaves[i].ndev);
976 priv->coal_intvl = coal_intvl;
977 }
978 } else {
979 priv->coal_intvl = coal_intvl;
980 }
981
982 return 0;
983}
984
d9718546
M		 985static int cpsw_get_sset_count(struct net_device *ndev, int sset)
986{
987 switch (sset) {
988 case ETH_SS_STATS:
989 return CPSW_STATS_LEN;
990 default:
991 return -EOPNOTSUPP;
992 }
993}
994
995static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
996{
997 u8 *p = data;
998 int i;
999
1000 switch (stringset) {
1001 case ETH_SS_STATS:
1002 for (i = 0; i < CPSW_STATS_LEN; i++) {
1003 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1004 ETH_GSTRING_LEN);
1005 p += ETH_GSTRING_LEN;
1006 }
1007 break;
1008 }
1009}
1010
1011static void cpsw_get_ethtool_stats(struct net_device *ndev,
1012 struct ethtool_stats *stats, u64 *data)
1013{
1014 struct cpsw_priv *priv = netdev_priv(ndev);
1015 struct cpdma_chan_stats rx_stats;
1016 struct cpdma_chan_stats tx_stats;
1017 u32 val;
1018 u8 *p;
1019 int i;
1020
1021 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1022 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1023 cpdma_chan_get_stats(priv->txch, &tx_stats);
1024
1025 for (i = 0; i < CPSW_STATS_LEN; i++) {
1026 switch (cpsw_gstrings_stats[i].type) {
1027 case CPSW_STATS:
1028 val = readl(priv->hw_stats +
1029 cpsw_gstrings_stats[i].stat_offset);
1030 data[i] = val;
1031 break;
1032
1033 case CPDMA_RX_STATS:
1034 p = (u8 *)&rx_stats +
1035 cpsw_gstrings_stats[i].stat_offset;
1036 data[i] = *(u32 *)p;
1037 break;
1038
1039 case CPDMA_TX_STATS:
1040 p = (u8 *)&tx_stats +
1041 cpsw_gstrings_stats[i].stat_offset;
1042 data[i] = *(u32 *)p;
1043 break;
1044 }
1045 }
1046}
1047
d9ba8f9e
M		 1048static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1049{
1050 u32 i;
1051 u32 usage_count = 0;
1052
1053 if (!priv->data.dual_emac)
1054 return 0;
1055
1056 for (i = 0; i < priv->data.slaves; i++)
1057 if (priv->slaves[i].open_stat)
1058 usage_count++;
1059
1060 return usage_count;
1061}
1062
27e9e103
IK		 1063static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1064 struct sk_buff *skb)
d9ba8f9e 1065{
27e9e103
IK		 1066 return cpdma_chan_submit(priv->txch, skb, skb->data, skb->len,
1067 priv->emac_port + priv->data.dual_emac);
d9ba8f9e
M		 1068}
1069
1070static inline void cpsw_add_dual_emac_def_ale_entries(
1071 struct cpsw_priv *priv, struct cpsw_slave *slave,
1072 u32 slave_port)
1073{
71a2cbb7 1074 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
d9ba8f9e
M		 1075
1076 if (priv->version == CPSW_VERSION_1)
1077 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1078 else
1079 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1080 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1081 port_mask, port_mask, 0);
1082 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1083 port_mask, ALE_VLAN, slave->port_vlan, 0);
1084 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
71a2cbb7 1085 HOST_PORT_NUM, ALE_VLAN | ALE_SECURE, slave->port_vlan);
d9ba8f9e
M		 1086}
1087
1e7a2e21 1088static void soft_reset_slave(struct cpsw_slave *slave)
df828598
M		 1089{
1090 char name[32];
df828598 1091
1e7a2e21 1092 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
df828598 1093 soft_reset(name, &slave->sliver->soft_reset);
1e7a2e21
DM		 1094}
1095
1096static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1097{
1098 u32 slave_port;
649a1688 1099 struct cpsw_common *cpsw = priv->cpsw;
1e7a2e21
DM		 1100
1101 soft_reset_slave(slave);
df828598
M		 1102
1103 /* setup priority mapping */
1104 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
9750a3ad
RC		 1105
1106 switch (priv->version) {
1107 case CPSW_VERSION_1:
1108 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1109 break;
1110 case CPSW_VERSION_2:
c193f365 1111 case CPSW_VERSION_3:
926489be 1112 case CPSW_VERSION_4:
9750a3ad
RC		 1113 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1114 break;
1115 }
df828598
M		 1116
1117 /* setup max packet size, and mac address */
1118 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1119 cpsw_set_slave_mac(slave, priv);
1120
1121 slave->mac_control = 0; /* no link yet */
1122
6f1f5836 1123 slave_port = cpsw_get_slave_port(slave->slave_num);
df828598 1124
d9ba8f9e
M		 1125 if (priv->data.dual_emac)
1126 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1127 else
1128 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1129 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
df828598 1130
d733f754 1131 if (slave->data->phy_node) {
552165bc 1132 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
9e42f715 1133 &cpsw_adjust_link, 0, slave->data->phy_if);
d733f754
DR		 1134 if (!slave->phy) {
1135 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1136 slave->data->phy_node->full_name,
1137 slave->slave_num);
1138 return;
1139 }
1140 } else {
9e42f715 1141 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
f9a8f83b 1142 &cpsw_adjust_link, slave->data->phy_if);
d733f754
DR		 1143 if (IS_ERR(slave->phy)) {
1144 dev_err(priv->dev,
1145 "phy \"%s\" not found on slave %d, err %ld\n",
1146 slave->data->phy_id, slave->slave_num,
1147 PTR_ERR(slave->phy));
1148 slave->phy = NULL;
1149 return;
1150 }
1151 }
2220943a 1152
d733f754 1153 phy_attached_info(slave->phy);
388367a5 1154
d733f754
DR		 1155 phy_start(slave->phy);
1156
1157 /* Configure GMII_SEL register */
649a1688 1158 cpsw_phy_sel(&cpsw->pdev->dev, slave->phy->interface, slave->slave_num);
df828598
M		 1159}
1160
3b72c2fe
M		 1161static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1162{
1163 const int vlan = priv->data.default_vlan;
3b72c2fe
M		 1164 u32 reg;
1165 int i;
1e5c4bc4 1166 int unreg_mcast_mask;
3b72c2fe
M		 1167
1168 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1169 CPSW2_PORT_VLAN;
1170
1171 writel(vlan, &priv->host_port_regs->port_vlan);
1172
0237c110 1173 for (i = 0; i < priv->data.slaves; i++)
3b72c2fe
M		 1174 slave_write(priv->slaves + i, vlan, reg);
1175
1e5c4bc4
LS		 1176 if (priv->ndev->flags & IFF_ALLMULTI)
1177 unreg_mcast_mask = ALE_ALL_PORTS;
1178 else
1179 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1180
61f1cef9
GS		 1181 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS,
1182 ALE_ALL_PORTS, ALE_ALL_PORTS,
1183 unreg_mcast_mask);
3b72c2fe
M		 1184}
1185
df828598
M		 1186static void cpsw_init_host_port(struct cpsw_priv *priv)
1187{
3b72c2fe 1188 u32 control_reg;
d9ba8f9e 1189 u32 fifo_mode;
3b72c2fe 1190
df828598
M		 1191 /* soft reset the controller and initialize ale */
1192 soft_reset("cpsw", &priv->regs->soft_reset);
1193 cpsw_ale_start(priv->ale);
1194
1195 /* switch to vlan unaware mode */
71a2cbb7 1196 cpsw_ale_control_set(priv->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
3b72c2fe
M		 1197 CPSW_ALE_VLAN_AWARE);
1198 control_reg = readl(&priv->regs->control);
1199 control_reg |= CPSW_VLAN_AWARE;
1200 writel(control_reg, &priv->regs->control);
d9ba8f9e
M		 1201 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1202 CPSW_FIFO_NORMAL_MODE;
1203 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
df828598
M		 1204
1205 /* setup host port priority mapping */
1206 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1207 &priv->host_port_regs->cpdma_tx_pri_map);
1208 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1209
71a2cbb7 1210 cpsw_ale_control_set(priv->ale, HOST_PORT_NUM,
df828598
M		 1211 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1212
d9ba8f9e 1213 if (!priv->data.dual_emac) {
71a2cbb7 1214 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
d9ba8f9e
M		 1215 0, 0);
1216 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
71a2cbb7 1217 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
d9ba8f9e 1218 }
df828598
M		 1219}
1220
aacebbf8
SS		 1221static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1222{
3995d265
SP		 1223 u32 slave_port;
1224
6f1f5836 1225 slave_port = cpsw_get_slave_port(slave->slave_num);
3995d265 1226
aacebbf8
SS		 1227 if (!slave->phy)
1228 return;
1229 phy_stop(slave->phy);
1230 phy_disconnect(slave->phy);
1231 slave->phy = NULL;
3995d265
SP		 1232 cpsw_ale_control_set(priv->ale, slave_port,
1233 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1f95ba00 1234 soft_reset_slave(slave);
aacebbf8
SS		 1235}
1236
df828598
M		 1237static int cpsw_ndo_open(struct net_device *ndev)
1238{
1239 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1240 struct cpsw_common *cpsw = priv->cpsw;
df828598
M		 1241 int i, ret;
1242 u32 reg;
1243
649a1688 1244 ret = pm_runtime_get_sync(&cpsw->pdev->dev);
108a6537 1245 if (ret < 0) {
649a1688 1246 pm_runtime_put_noidle(&cpsw->pdev->dev);
108a6537
GS		 1247 return ret;
1248 }
3fa88c51 1249
d9ba8f9e
M		 1250 if (!cpsw_common_res_usage_state(priv))
1251 cpsw_intr_disable(priv);
df828598
M		 1252 netif_carrier_off(ndev);
1253
549985ee 1254 reg = priv->version;
df828598
M		 1255
1256 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1257 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1258 CPSW_RTL_VERSION(reg));
1259
1260 /* initialize host and slave ports */
d9ba8f9e
M		 1261 if (!cpsw_common_res_usage_state(priv))
1262 cpsw_init_host_port(priv);
df828598
M		 1263 for_each_slave(priv, cpsw_slave_open, priv);
1264
3b72c2fe 1265 /* Add default VLAN */
e6afea0b
M		 1266 if (!priv->data.dual_emac)
1267 cpsw_add_default_vlan(priv);
1268 else
1269 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
61f1cef9 1270 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
3b72c2fe 1271
d9ba8f9e 1272 if (!cpsw_common_res_usage_state(priv)) {
d354eb85 1273 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1793331e 1274 int buf_num;
d354eb85 1275
d9ba8f9e
M		 1276 /* setup tx dma to fixed prio and zero offset */
1277 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1278 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
df828598 1279
d9ba8f9e
M		 1280 /* disable priority elevation */
1281 __raw_writel(0, &priv->regs->ptype);
df828598 1282
d9ba8f9e
M		 1283 /* enable statistics collection only on all ports */
1284 __raw_writel(0x7, &priv->regs->stat_port_en);
df828598 1285
1923d6e4
M		 1286 /* Enable internal fifo flow control */
1287 writel(0x7, &priv->regs->flow_control);
1288
32a7432c
M		 1289 napi_enable(&priv_sl0->napi_rx);
1290 napi_enable(&priv_sl0->napi_tx);
d354eb85 1291
7da11600
M		 1292 if (priv_sl0->tx_irq_disabled) {
1293 priv_sl0->tx_irq_disabled = false;
1294 enable_irq(priv->irqs_table[1]);
1295 }
1296
1297 if (priv_sl0->rx_irq_disabled) {
1298 priv_sl0->rx_irq_disabled = false;
1299 enable_irq(priv->irqs_table[0]);
1300 }
1301
1793331e
IK		 1302 buf_num = cpdma_chan_get_rx_buf_num(priv->dma);
1303 for (i = 0; i < buf_num; i++) {
d9ba8f9e 1304 struct sk_buff *skb;
df828598 1305
d9ba8f9e 1306 ret = -ENOMEM;
aacebbf8
SS		 1307 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1308 priv->rx_packet_max, GFP_KERNEL);
d9ba8f9e 1309 if (!skb)
aacebbf8 1310 goto err_cleanup;
d9ba8f9e 1311 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
aef614e1 1312 skb_tailroom(skb), 0);
aacebbf8
SS		 1313 if (ret < 0) {
1314 kfree_skb(skb);
1315 goto err_cleanup;
1316 }
d9ba8f9e
M		 1317 }
1318 /* continue even if we didn't manage to submit all
1319 * receive descs
1320 */
1321 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
f280e89a 1322
649a1688 1323 if (cpts_register(&cpsw->pdev->dev, priv->cpts,
f280e89a
M		 1324 priv->data.cpts_clock_mult,
1325 priv->data.cpts_clock_shift))
1326 dev_err(priv->dev, "error registering cpts device\n");
1327
df828598 1328 }
df828598 1329
ff5b8ef2
M		 1330 /* Enable Interrupt pacing if configured */
1331 if (priv->coal_intvl != 0) {
1332 struct ethtool_coalesce coal;
1333
8478b6cd 1334 coal.rx_coalesce_usecs = priv->coal_intvl;
ff5b8ef2
M		 1335 cpsw_set_coalesce(ndev, &coal);
1336 }
1337
f63a975e
M		 1338 cpdma_ctlr_start(priv->dma);
1339 cpsw_intr_enable(priv);
f63a975e 1340
d9ba8f9e
M		 1341 if (priv->data.dual_emac)
1342 priv->slaves[priv->emac_port].open_stat = true;
df828598 1343 return 0;
df828598 1344
aacebbf8
SS		 1345err_cleanup:
1346 cpdma_ctlr_stop(priv->dma);
1347 for_each_slave(priv, cpsw_slave_stop, priv);
649a1688 1348 pm_runtime_put_sync(&cpsw->pdev->dev);
aacebbf8
SS		 1349 netif_carrier_off(priv->ndev);
1350 return ret;
df828598
M		 1351}
1352
1353static int cpsw_ndo_stop(struct net_device *ndev)
1354{
1355 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1356 struct cpsw_common *cpsw = priv->cpsw;
df828598
M		 1357
1358 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
df828598 1359 netif_stop_queue(priv->ndev);
df828598 1360 netif_carrier_off(priv->ndev);
d9ba8f9e
M		 1361
1362 if (cpsw_common_res_usage_state(priv) <= 1) {
d354eb85
M		 1363 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1364
32a7432c
M		 1365 napi_disable(&priv_sl0->napi_rx);
1366 napi_disable(&priv_sl0->napi_tx);
f280e89a 1367 cpts_unregister(priv->cpts);
d9ba8f9e 1368 cpsw_intr_disable(priv);
d9ba8f9e
M		 1369 cpdma_ctlr_stop(priv->dma);
1370 cpsw_ale_stop(priv->ale);
1371 }
df828598 1372 for_each_slave(priv, cpsw_slave_stop, priv);
649a1688 1373 pm_runtime_put_sync(&cpsw->pdev->dev);
d9ba8f9e
M		 1374 if (priv->data.dual_emac)
1375 priv->slaves[priv->emac_port].open_stat = false;
df828598
M		 1376 return 0;
1377}
1378
1379static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1380 struct net_device *ndev)
1381{
1382 struct cpsw_priv *priv = netdev_priv(ndev);
1383 int ret;
1384
860e9538 1385 netif_trans_update(ndev);
df828598
M		 1386
1387 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1388 cpsw_err(priv, tx_err, "packet pad failed\n");
8dc43ddc 1389 ndev->stats.tx_dropped++;
df828598
M		 1390 return NETDEV_TX_OK;
1391 }
1392
9232b16d
M		 1393 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1394 priv->cpts->tx_enable)
2e5b38ab
RC		 1395 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1396
1397 skb_tx_timestamp(skb);
1398
27e9e103 1399 ret = cpsw_tx_packet_submit(priv, skb);
df828598
M		 1400 if (unlikely(ret != 0)) {
1401 cpsw_err(priv, tx_err, "desc submit failed\n");
1402 goto fail;
1403 }
1404
fae50823
M		 1405 /* If there is no more tx desc left free then we need to
1406 * tell the kernel to stop sending us tx frames.
1407 */
d35162f8 1408 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
fae50823
M		 1409 netif_stop_queue(ndev);
1410
df828598
M		 1411 return NETDEV_TX_OK;
1412fail:
8dc43ddc 1413 ndev->stats.tx_dropped++;
df828598
M		 1414 netif_stop_queue(ndev);
1415 return NETDEV_TX_BUSY;
1416}
1417
2e5b38ab
RC		 1418#ifdef CONFIG_TI_CPTS
1419
1420static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1421{
e86ac13b 1422 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
2e5b38ab
RC		 1423 u32 ts_en, seq_id;
1424
9232b16d 1425 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
2e5b38ab
RC		 1426 slave_write(slave, 0, CPSW1_TS_CTL);
1427 return;
1428 }
1429
1430 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1431 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1432
9232b16d 1433 if (priv->cpts->tx_enable)
2e5b38ab
RC		 1434 ts_en |= CPSW_V1_TS_TX_EN;
1435
9232b16d 1436 if (priv->cpts->rx_enable)
2e5b38ab
RC		 1437 ts_en |= CPSW_V1_TS_RX_EN;
1438
1439 slave_write(slave, ts_en, CPSW1_TS_CTL);
1440 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1441}
1442
1443static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1444{
d9ba8f9e 1445 struct cpsw_slave *slave;
2e5b38ab
RC		 1446 u32 ctrl, mtype;
1447
d9ba8f9e
M		 1448 if (priv->data.dual_emac)
1449 slave = &priv->slaves[priv->emac_port];
1450 else
e86ac13b 1451 slave = &priv->slaves[priv->data.active_slave];
d9ba8f9e 1452
2e5b38ab 1453 ctrl = slave_read(slave, CPSW2_CONTROL);
09c55372
GC		 1454 switch (priv->version) {
1455 case CPSW_VERSION_2:
1456 ctrl &= ~CTRL_V2_ALL_TS_MASK;
2e5b38ab 1457
09c55372
GC		 1458 if (priv->cpts->tx_enable)
1459 ctrl |= CTRL_V2_TX_TS_BITS;
2e5b38ab 1460
09c55372
GC		 1461 if (priv->cpts->rx_enable)
1462 ctrl |= CTRL_V2_RX_TS_BITS;
26fe7eb8 1463 break;
09c55372
GC		 1464 case CPSW_VERSION_3:
1465 default:
1466 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1467
1468 if (priv->cpts->tx_enable)
1469 ctrl |= CTRL_V3_TX_TS_BITS;
1470
1471 if (priv->cpts->rx_enable)
1472 ctrl |= CTRL_V3_RX_TS_BITS;
26fe7eb8 1473 break;
09c55372 1474 }
2e5b38ab
RC		 1475
1476 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1477
1478 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1479 slave_write(slave, ctrl, CPSW2_CONTROL);
1480 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1481}
1482
a5b4145b 1483static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2e5b38ab 1484{
3177bf6f 1485 struct cpsw_priv *priv = netdev_priv(dev);
9232b16d 1486 struct cpts *cpts = priv->cpts;
2e5b38ab
RC		 1487 struct hwtstamp_config cfg;
1488
2ee91e54 1489 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1490 priv->version != CPSW_VERSION_2 &&
1491 priv->version != CPSW_VERSION_3)
2ee91e54
BH		 1492 return -EOPNOTSUPP;
1493
2e5b38ab
RC		 1494 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1495 return -EFAULT;
1496
1497 /* reserved for future extensions */
1498 if (cfg.flags)
1499 return -EINVAL;
1500
2ee91e54 1501 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
2e5b38ab 1502 return -ERANGE;
2e5b38ab
RC		 1503
1504 switch (cfg.rx_filter) {
1505 case HWTSTAMP_FILTER_NONE:
1506 cpts->rx_enable = 0;
1507 break;
1508 case HWTSTAMP_FILTER_ALL:
1509 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1510 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1511 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1512 return -ERANGE;
1513 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1514 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1515 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1516 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1517 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1518 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1519 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1520 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1521 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1522 cpts->rx_enable = 1;
1523 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1524 break;
1525 default:
1526 return -ERANGE;
1527 }
1528
2ee91e54
BH		 1529 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1530
2e5b38ab
RC		 1531 switch (priv->version) {
1532 case CPSW_VERSION_1:
1533 cpsw_hwtstamp_v1(priv);
1534 break;
1535 case CPSW_VERSION_2:
f7d403cb 1536 case CPSW_VERSION_3:
2e5b38ab
RC		 1537 cpsw_hwtstamp_v2(priv);
1538 break;
1539 default:
2ee91e54 1540 WARN_ON(1);
2e5b38ab
RC		 1541 }
1542
1543 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1544}
1545
a5b4145b
BH		 1546static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1547{
1548 struct cpsw_priv *priv = netdev_priv(dev);
1549 struct cpts *cpts = priv->cpts;
1550 struct hwtstamp_config cfg;
1551
1552 if (priv->version != CPSW_VERSION_1 &&
f7d403cb
GC		 1553 priv->version != CPSW_VERSION_2 &&
1554 priv->version != CPSW_VERSION_3)
a5b4145b
BH		 1555 return -EOPNOTSUPP;
1556
1557 cfg.flags = 0;
1558 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1559 cfg.rx_filter = (cpts->rx_enable ?
1560 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1561
1562 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1563}
1564
2e5b38ab
RC		 1565#endif /*CONFIG_TI_CPTS*/
1566
1567static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1568{
11f2c988 1569 struct cpsw_priv *priv = netdev_priv(dev);
11f2c988
M		 1570 int slave_no = cpsw_slave_index(priv);
1571
2e5b38ab
RC		 1572 if (!netif_running(dev))
1573 return -EINVAL;
1574
11f2c988 1575 switch (cmd) {
2e5b38ab 1576#ifdef CONFIG_TI_CPTS
11f2c988 1577 case SIOCSHWTSTAMP:
a5b4145b
BH		 1578 return cpsw_hwtstamp_set(dev, req);
1579 case SIOCGHWTSTAMP:
1580 return cpsw_hwtstamp_get(dev, req);
2e5b38ab 1581#endif
11f2c988
M		 1582 }
1583
c1b59947
SS		 1584 if (!priv->slaves[slave_no].phy)
1585 return -EOPNOTSUPP;
1586 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
2e5b38ab
RC		 1587}
1588
df828598
M		 1589static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1590{
1591 struct cpsw_priv *priv = netdev_priv(ndev);
1592
1593 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
8dc43ddc 1594 ndev->stats.tx_errors++;
df828598 1595 cpsw_intr_disable(priv);
df828598
M		 1596 cpdma_chan_stop(priv->txch);
1597 cpdma_chan_start(priv->txch);
df828598 1598 cpsw_intr_enable(priv);
df828598
M		 1599}
1600
dcfd8d58
M		 1601static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1602{
1603 struct cpsw_priv *priv = netdev_priv(ndev);
1604 struct sockaddr *addr = (struct sockaddr *)p;
649a1688 1605 struct cpsw_common *cpsw = priv->cpsw;
dcfd8d58
M		 1606 int flags = 0;
1607 u16 vid = 0;
a6c5d14f 1608 int ret;
dcfd8d58
M		 1609
1610 if (!is_valid_ether_addr(addr->sa_data))
1611 return -EADDRNOTAVAIL;
1612
649a1688 1613 ret = pm_runtime_get_sync(&cpsw->pdev->dev);
a6c5d14f 1614 if (ret < 0) {
649a1688 1615 pm_runtime_put_noidle(&cpsw->pdev->dev);
a6c5d14f
GS		 1616 return ret;
1617 }
1618
dcfd8d58
M		 1619 if (priv->data.dual_emac) {
1620 vid = priv->slaves[priv->emac_port].port_vlan;
1621 flags = ALE_VLAN;
1622 }
1623
71a2cbb7 1624 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
dcfd8d58 1625 flags, vid);
71a2cbb7 1626 cpsw_ale_add_ucast(priv->ale, addr->sa_data, HOST_PORT_NUM,
dcfd8d58
M		 1627 flags, vid);
1628
1629 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1630 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1631 for_each_slave(priv, cpsw_set_slave_mac, priv);
1632
649a1688 1633 pm_runtime_put(&cpsw->pdev->dev);
a6c5d14f 1634
dcfd8d58
M		 1635 return 0;
1636}
1637
df828598
M		 1638#ifdef CONFIG_NET_POLL_CONTROLLER
1639static void cpsw_ndo_poll_controller(struct net_device *ndev)
1640{
1641 struct cpsw_priv *priv = netdev_priv(ndev);
1642
1643 cpsw_intr_disable(priv);
92cb13fb
FB		 1644 cpsw_rx_interrupt(priv->irqs_table[0], priv);
1645 cpsw_tx_interrupt(priv->irqs_table[1], priv);
df828598 1646 cpsw_intr_enable(priv);
df828598
M		 1647}
1648#endif
1649
3b72c2fe
M		 1650static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1651 unsigned short vid)
1652{
1653 int ret;
9f6bd8fa
M		 1654 int unreg_mcast_mask = 0;
1655 u32 port_mask;
1e5c4bc4 1656
9f6bd8fa
M		 1657 if (priv->data.dual_emac) {
1658 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
3b72c2fe 1659
9f6bd8fa
M		 1660 if (priv->ndev->flags & IFF_ALLMULTI)
1661 unreg_mcast_mask = port_mask;
1662 } else {
1663 port_mask = ALE_ALL_PORTS;
1664
1665 if (priv->ndev->flags & IFF_ALLMULTI)
1666 unreg_mcast_mask = ALE_ALL_PORTS;
1667 else
1668 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1669 }
3b72c2fe 1670
9f6bd8fa 1671 ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
61f1cef9 1672 unreg_mcast_mask);
3b72c2fe
M		 1673 if (ret != 0)
1674 return ret;
1675
1676 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
71a2cbb7 1677 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1678 if (ret != 0)
1679 goto clean_vid;
1680
1681 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
9f6bd8fa 1682 port_mask, ALE_VLAN, vid, 0);
3b72c2fe
M		 1683 if (ret != 0)
1684 goto clean_vlan_ucast;
1685 return 0;
1686
1687clean_vlan_ucast:
1688 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
71a2cbb7 1689 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1690clean_vid:
1691 cpsw_ale_del_vlan(priv->ale, vid, 0);
1692 return ret;
1693}
1694
1695static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
80d5c368 1696 __be16 proto, u16 vid)
3b72c2fe
M		 1697{
1698 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1699 struct cpsw_common *cpsw = priv->cpsw;
a6c5d14f 1700 int ret;
3b72c2fe
M		 1701
1702 if (vid == priv->data.default_vlan)
1703 return 0;
1704
649a1688 1705 ret = pm_runtime_get_sync(&cpsw->pdev->dev);
a6c5d14f 1706 if (ret < 0) {
649a1688 1707 pm_runtime_put_noidle(&cpsw->pdev->dev);
a6c5d14f
GS		 1708 return ret;
1709 }
1710
02a54164
M		 1711 if (priv->data.dual_emac) {
1712 /* In dual EMAC, reserved VLAN id should not be used for
1713 * creating VLAN interfaces as this can break the dual
1714 * EMAC port separation
1715 */
1716 int i;
1717
1718 for (i = 0; i < priv->data.slaves; i++) {
1719 if (vid == priv->slaves[i].port_vlan)
1720 return -EINVAL;
1721 }
1722 }
1723
3b72c2fe 1724 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
a6c5d14f
GS		 1725 ret = cpsw_add_vlan_ale_entry(priv, vid);
1726
649a1688 1727 pm_runtime_put(&cpsw->pdev->dev);
a6c5d14f 1728 return ret;
3b72c2fe
M		 1729}
1730
1731static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
80d5c368 1732 __be16 proto, u16 vid)
3b72c2fe
M		 1733{
1734 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1735 struct cpsw_common *cpsw = priv->cpsw;
3b72c2fe
M		 1736 int ret;
1737
1738 if (vid == priv->data.default_vlan)
1739 return 0;
1740
649a1688 1741 ret = pm_runtime_get_sync(&cpsw->pdev->dev);
a6c5d14f 1742 if (ret < 0) {
649a1688 1743 pm_runtime_put_noidle(&cpsw->pdev->dev);
a6c5d14f
GS		 1744 return ret;
1745 }
1746
02a54164
M		 1747 if (priv->data.dual_emac) {
1748 int i;
1749
1750 for (i = 0; i < priv->data.slaves; i++) {
1751 if (vid == priv->slaves[i].port_vlan)
1752 return -EINVAL;
1753 }
1754 }
1755
3b72c2fe
M		 1756 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1757 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1758 if (ret != 0)
1759 return ret;
1760
1761 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
61f1cef9 1762 HOST_PORT_NUM, ALE_VLAN, vid);
3b72c2fe
M		 1763 if (ret != 0)
1764 return ret;
1765
a6c5d14f
GS		 1766 ret = cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1767 0, ALE_VLAN, vid);
649a1688 1768 pm_runtime_put(&cpsw->pdev->dev);
a6c5d14f 1769 return ret;
3b72c2fe
M		 1770}
1771
df828598
M		 1772static const struct net_device_ops cpsw_netdev_ops = {
1773 .ndo_open = cpsw_ndo_open,
1774 .ndo_stop = cpsw_ndo_stop,
1775 .ndo_start_xmit = cpsw_ndo_start_xmit,
dcfd8d58 1776 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2e5b38ab 1777 .ndo_do_ioctl = cpsw_ndo_ioctl,
df828598 1778 .ndo_validate_addr = eth_validate_addr,
5c473ed2 1779 .ndo_change_mtu = eth_change_mtu,
df828598 1780 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
5c50a856 1781 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
df828598
M		 1782#ifdef CONFIG_NET_POLL_CONTROLLER
1783 .ndo_poll_controller = cpsw_ndo_poll_controller,
1784#endif
3b72c2fe
M		 1785 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1786 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
df828598
M		 1787};
1788
52c4f0ec
M		 1789static int cpsw_get_regs_len(struct net_device *ndev)
1790{
1791 struct cpsw_priv *priv = netdev_priv(ndev);
1792
1793 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1794}
1795
1796static void cpsw_get_regs(struct net_device *ndev,
1797 struct ethtool_regs *regs, void *p)
1798{
1799 struct cpsw_priv *priv = netdev_priv(ndev);
1800 u32 *reg = p;
1801
1802 /* update CPSW IP version */
1803 regs->version = priv->version;
1804
1805 cpsw_ale_dump(priv->ale, reg);
1806}
1807
df828598
M		 1808static void cpsw_get_drvinfo(struct net_device *ndev,
1809 struct ethtool_drvinfo *info)
1810{
649a1688 1811 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
7826d43f 1812
52c4f0ec 1813 strlcpy(info->driver, "cpsw", sizeof(info->driver));
7826d43f 1814 strlcpy(info->version, "1.0", sizeof(info->version));
649a1688 1815 strlcpy(info->bus_info, cpsw->pdev->name, sizeof(info->bus_info));
df828598
M		 1816}
1817
1818static u32 cpsw_get_msglevel(struct net_device *ndev)
1819{
1820 struct cpsw_priv *priv = netdev_priv(ndev);
1821 return priv->msg_enable;
1822}
1823
1824static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1825{
1826 struct cpsw_priv *priv = netdev_priv(ndev);
1827 priv->msg_enable = value;
1828}
1829
2e5b38ab
RC		 1830static int cpsw_get_ts_info(struct net_device *ndev,
1831 struct ethtool_ts_info *info)
1832{
1833#ifdef CONFIG_TI_CPTS
1834 struct cpsw_priv *priv = netdev_priv(ndev);
1835
1836 info->so_timestamping =
1837 SOF_TIMESTAMPING_TX_HARDWARE |
1838 SOF_TIMESTAMPING_TX_SOFTWARE |
1839 SOF_TIMESTAMPING_RX_HARDWARE |
1840 SOF_TIMESTAMPING_RX_SOFTWARE |
1841 SOF_TIMESTAMPING_SOFTWARE |
1842 SOF_TIMESTAMPING_RAW_HARDWARE;
9232b16d 1843 info->phc_index = priv->cpts->phc_index;
2e5b38ab
RC		 1844 info->tx_types =
1845 (1 << HWTSTAMP_TX_OFF) |
1846 (1 << HWTSTAMP_TX_ON);
1847 info->rx_filters =
1848 (1 << HWTSTAMP_FILTER_NONE) |
1849 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1850#else
1851 info->so_timestamping =
1852 SOF_TIMESTAMPING_TX_SOFTWARE |
1853 SOF_TIMESTAMPING_RX_SOFTWARE |
1854 SOF_TIMESTAMPING_SOFTWARE;
1855 info->phc_index = -1;
1856 info->tx_types = 0;
1857 info->rx_filters = 0;
1858#endif
1859 return 0;
1860}
1861
d3bb9c58
M		 1862static int cpsw_get_settings(struct net_device *ndev,
1863 struct ethtool_cmd *ecmd)
1864{
1865 struct cpsw_priv *priv = netdev_priv(ndev);
1866 int slave_no = cpsw_slave_index(priv);
1867
1868 if (priv->slaves[slave_no].phy)
1869 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1870 else
1871 return -EOPNOTSUPP;
1872}
1873
1874static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1875{
1876 struct cpsw_priv *priv = netdev_priv(ndev);
1877 int slave_no = cpsw_slave_index(priv);
1878
1879 if (priv->slaves[slave_no].phy)
1880 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1881 else
1882 return -EOPNOTSUPP;
1883}
1884
d8a64420
MU		 1885static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1886{
1887 struct cpsw_priv *priv = netdev_priv(ndev);
1888 int slave_no = cpsw_slave_index(priv);
1889
1890 wol->supported = 0;
1891 wol->wolopts = 0;
1892
1893 if (priv->slaves[slave_no].phy)
1894 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1895}
1896
1897static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1898{
1899 struct cpsw_priv *priv = netdev_priv(ndev);
1900 int slave_no = cpsw_slave_index(priv);
1901
1902 if (priv->slaves[slave_no].phy)
1903 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1904 else
1905 return -EOPNOTSUPP;
1906}
1907
1923d6e4
M		 1908static void cpsw_get_pauseparam(struct net_device *ndev,
1909 struct ethtool_pauseparam *pause)
1910{
1911 struct cpsw_priv *priv = netdev_priv(ndev);
1912
1913 pause->autoneg = AUTONEG_DISABLE;
1914 pause->rx_pause = priv->rx_pause ? true : false;
1915 pause->tx_pause = priv->tx_pause ? true : false;
1916}
1917
1918static int cpsw_set_pauseparam(struct net_device *ndev,
1919 struct ethtool_pauseparam *pause)
1920{
1921 struct cpsw_priv *priv = netdev_priv(ndev);
1922 bool link;
1923
1924 priv->rx_pause = pause->rx_pause ? true : false;
1925 priv->tx_pause = pause->tx_pause ? true : false;
1926
1927 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1923d6e4
M		 1928 return 0;
1929}
1930
7898b1da
GS		 1931static int cpsw_ethtool_op_begin(struct net_device *ndev)
1932{
1933 struct cpsw_priv *priv = netdev_priv(ndev);
649a1688 1934 struct cpsw_common *cpsw = priv->cpsw;
7898b1da
GS		 1935 int ret;
1936
649a1688 1937 ret = pm_runtime_get_sync(&cpsw->pdev->dev);
7898b1da
GS		 1938 if (ret < 0) {
1939 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
649a1688 1940 pm_runtime_put_noidle(&cpsw->pdev->dev);
7898b1da
GS		 1941 }
1942
1943 return ret;
1944}
1945
1946static void cpsw_ethtool_op_complete(struct net_device *ndev)
1947{
1948 struct cpsw_priv *priv = netdev_priv(ndev);
1949 int ret;
1950
649a1688 1951 ret = pm_runtime_put(&priv->cpsw->pdev->dev);
7898b1da
GS		 1952 if (ret < 0)
1953 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
1954}
1955
df828598
M		 1956static const struct ethtool_ops cpsw_ethtool_ops = {
1957 .get_drvinfo = cpsw_get_drvinfo,
1958 .get_msglevel = cpsw_get_msglevel,
1959 .set_msglevel = cpsw_set_msglevel,
1960 .get_link = ethtool_op_get_link,
2e5b38ab 1961 .get_ts_info = cpsw_get_ts_info,
d3bb9c58
M		 1962 .get_settings = cpsw_get_settings,
1963 .set_settings = cpsw_set_settings,
ff5b8ef2
M		 1964 .get_coalesce = cpsw_get_coalesce,
1965 .set_coalesce = cpsw_set_coalesce,
d9718546
M		 1966 .get_sset_count = cpsw_get_sset_count,
1967 .get_strings = cpsw_get_strings,
1968 .get_ethtool_stats = cpsw_get_ethtool_stats,
1923d6e4
M		 1969 .get_pauseparam = cpsw_get_pauseparam,
1970 .set_pauseparam = cpsw_set_pauseparam,
d8a64420
MU		 1971 .get_wol = cpsw_get_wol,
1972 .set_wol = cpsw_set_wol,
52c4f0ec
M		 1973 .get_regs_len = cpsw_get_regs_len,
1974 .get_regs = cpsw_get_regs,
7898b1da
GS		 1975 .begin = cpsw_ethtool_op_begin,
1976 .complete = cpsw_ethtool_op_complete,
df828598
M		 1977};
1978
549985ee
RC		 1979static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1980 u32 slave_reg_ofs, u32 sliver_reg_ofs)
df828598
M		 1981{
1982 void __iomem *regs = priv->regs;
1983 int slave_num = slave->slave_num;
1984 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1985
1986 slave->data = data;
549985ee
RC		 1987 slave->regs = regs + slave_reg_ofs;
1988 slave->sliver = regs + sliver_reg_ofs;
d9ba8f9e 1989 slave->port_vlan = data->dual_emac_res_vlan;
df828598
M		 1990}
1991
552165bc 1992static int cpsw_probe_dt(struct cpsw_platform_data *data,
2eb32b0a
M		 1993 struct platform_device *pdev)
1994{
1995 struct device_node *node = pdev->dev.of_node;
1996 struct device_node *slave_node;
1997 int i = 0, ret;
1998 u32 prop;
1999
2000 if (!node)
2001 return -EINVAL;
2002
2003 if (of_property_read_u32(node, "slaves", &prop)) {
88c99ff6 2004 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2eb32b0a
M		 2005 return -EINVAL;
2006 }
2007 data->slaves = prop;
2008
e86ac13b 2009 if (of_property_read_u32(node, "active_slave", &prop)) {
88c99ff6 2010 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
aa1a15e2 2011 return -EINVAL;
78ca0b28 2012 }
e86ac13b 2013 data->active_slave = prop;
78ca0b28 2014
00ab94ee 2015 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
88c99ff6 2016 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
aa1a15e2 2017 return -EINVAL;
00ab94ee
RC		 2018 }
2019 data->cpts_clock_mult = prop;
2020
2021 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
88c99ff6 2022 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
aa1a15e2 2023 return -EINVAL;
00ab94ee
RC		 2024 }
2025 data->cpts_clock_shift = prop;
2026
aa1a15e2
DM		 2027 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2028 * sizeof(struct cpsw_slave_data),
2029 GFP_KERNEL);
b2adaca9 2030 if (!data->slave_data)
aa1a15e2 2031 return -ENOMEM;
2eb32b0a 2032
2eb32b0a 2033 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
88c99ff6 2034 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
aa1a15e2 2035 return -EINVAL;
2eb32b0a
M		 2036 }
2037 data->channels = prop;
2038
2eb32b0a 2039 if (of_property_read_u32(node, "ale_entries", &prop)) {
88c99ff6 2040 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
aa1a15e2 2041 return -EINVAL;
2eb32b0a
M		 2042 }
2043 data->ale_entries = prop;
2044
2eb32b0a 2045 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
88c99ff6 2046 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
aa1a15e2 2047 return -EINVAL;
2eb32b0a
M		 2048 }
2049 data->bd_ram_size = prop;
2050
2eb32b0a 2051 if (of_property_read_u32(node, "mac_control", &prop)) {
88c99ff6 2052 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
aa1a15e2 2053 return -EINVAL;
2eb32b0a
M		 2054 }
2055 data->mac_control = prop;
2056
281abd96
MP		 2057 if (of_property_read_bool(node, "dual_emac"))
2058 data->dual_emac = 1;
d9ba8f9e 2059
549985ee
RC		 2060 /*
2061 * Populate all the child nodes here...
2062 */
2063 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2064 /* We do not want to force this, as in some cases may not have child */
2065 if (ret)
88c99ff6 2066 dev_warn(&pdev->dev, "Doesn't have any child node\n");
549985ee 2067
8658aaf2 2068 for_each_available_child_of_node(node, slave_node) {
2eb32b0a 2069 struct cpsw_slave_data *slave_data = data->slave_data + i;
2eb32b0a 2070 const void *mac_addr = NULL;
549985ee
RC		 2071 int lenp;
2072 const __be32 *parp;
549985ee 2073
f468b10e
MP		 2074 /* This is no slave child node, continue */
2075 if (strcmp(slave_node->name, "slave"))
2076 continue;
2077
552165bc
DR		 2078 slave_data->phy_node = of_parse_phandle(slave_node,
2079 "phy-handle", 0);
f1eea5c1 2080 parp = of_get_property(slave_node, "phy_id", &lenp);
ae092b5b
DR		 2081 if (slave_data->phy_node) {
2082 dev_dbg(&pdev->dev,
2083 "slave[%d] using phy-handle=\"%s\"\n",
2084 i, slave_data->phy_node->full_name);
2085 } else if (of_phy_is_fixed_link(slave_node)) {
dfc0a6d3
DR		 2086 /* In the case of a fixed PHY, the DT node associated
2087 * to the PHY is the Ethernet MAC DT node.
2088 */
1f71e8c9
MB		 2089 ret = of_phy_register_fixed_link(slave_node);
2090 if (ret)
2091 return ret;
06cd6d6e 2092 slave_data->phy_node = of_node_get(slave_node);
f1eea5c1
DR		 2093 } else if (parp) {
2094 u32 phyid;
2095 struct device_node *mdio_node;
2096 struct platform_device *mdio;
2097
2098 if (lenp != (sizeof(__be32) * 2)) {
2099 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2100 goto no_phy_slave;
2101 }
2102 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2103 phyid = be32_to_cpup(parp+1);
2104 mdio = of_find_device_by_node(mdio_node);
2105 of_node_put(mdio_node);
2106 if (!mdio) {
2107 dev_err(&pdev->dev, "Missing mdio platform device\n");
2108 return -EINVAL;
2109 }
2110 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2111 PHY_ID_FMT, mdio->name, phyid);
2112 } else {
ae092b5b
DR		 2113 dev_err(&pdev->dev,
2114 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2115 i);
47276fcc 2116 goto no_phy_slave;
2eb32b0a 2117 }
47276fcc
M		 2118 slave_data->phy_if = of_get_phy_mode(slave_node);
2119 if (slave_data->phy_if < 0) {
2120 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2121 i);
2122 return slave_data->phy_if;
2123 }
2124
2125no_phy_slave:
2eb32b0a 2126 mac_addr = of_get_mac_address(slave_node);
0ba517b1 2127 if (mac_addr) {
2eb32b0a 2128 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
0ba517b1 2129 } else {
b6745f6e
M		 2130 ret = ti_cm_get_macid(&pdev->dev, i,
2131 slave_data->mac_addr);
2132 if (ret)
2133 return ret;
0ba517b1 2134 }
d9ba8f9e 2135 if (data->dual_emac) {
91c4166c 2136 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
d9ba8f9e 2137 &prop)) {
88c99ff6 2138 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
d9ba8f9e 2139 slave_data->dual_emac_res_vlan = i+1;
88c99ff6
GC		 2140 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2141 slave_data->dual_emac_res_vlan, i);
d9ba8f9e
M		 2142 } else {
2143 slave_data->dual_emac_res_vlan = prop;
2144 }
2145 }
2146
2eb32b0a 2147 i++;
3a27bfac
M		 2148 if (i == data->slaves)
2149 break;
2eb32b0a
M		 2150 }
2151
2152 return 0;
2eb32b0a
M		 2153}
2154
d9ba8f9e
M		 2155static int cpsw_probe_dual_emac(struct platform_device *pdev,
2156 struct cpsw_priv *priv)
2157{
2158 struct cpsw_platform_data *data = &priv->data;
2159 struct net_device *ndev;
2160 struct cpsw_priv *priv_sl2;
2161 int ret = 0, i;
2162
2163 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2164 if (!ndev) {
88c99ff6 2165 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
d9ba8f9e
M		 2166 return -ENOMEM;
2167 }
2168
2169 priv_sl2 = netdev_priv(ndev);
649a1688 2170 priv_sl2->cpsw = priv->cpsw;
d9ba8f9e 2171 priv_sl2->data = *data;
d9ba8f9e
M		 2172 priv_sl2->ndev = ndev;
2173 priv_sl2->dev = &ndev->dev;
2174 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2175 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2176
2177 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2178 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2179 ETH_ALEN);
88c99ff6 2180 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
d9ba8f9e
M		 2181 } else {
2182 random_ether_addr(priv_sl2->mac_addr);
88c99ff6 2183 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
d9ba8f9e
M		 2184 }
2185 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2186
2187 priv_sl2->slaves = priv->slaves;
ff5b8ef2
M		 2188 priv_sl2->coal_intvl = 0;
2189 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2190
d9ba8f9e 2191 priv_sl2->regs = priv->regs;
d9ba8f9e
M		 2192 priv_sl2->host_port_regs = priv->host_port_regs;
2193 priv_sl2->wr_regs = priv->wr_regs;
d9718546 2194 priv_sl2->hw_stats = priv->hw_stats;
d9ba8f9e
M		 2195 priv_sl2->dma = priv->dma;
2196 priv_sl2->txch = priv->txch;
2197 priv_sl2->rxch = priv->rxch;
2198 priv_sl2->ale = priv->ale;
2199 priv_sl2->emac_port = 1;
2200 priv->slaves[1].ndev = ndev;
2201 priv_sl2->cpts = priv->cpts;
2202 priv_sl2->version = priv->version;
2203
2204 for (i = 0; i < priv->num_irqs; i++) {
2205 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2206 priv_sl2->num_irqs = priv->num_irqs;
2207 }
f646968f 2208 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
d9ba8f9e
M		 2209
2210 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2211 ndev->ethtool_ops = &cpsw_ethtool_ops;
d9ba8f9e
M		 2212
2213 /* register the network device */
2214 SET_NETDEV_DEV(ndev, &pdev->dev);
2215 ret = register_netdev(ndev);
2216 if (ret) {
88c99ff6 2217 dev_err(&pdev->dev, "cpsw: error registering net device\n");
d9ba8f9e
M		 2218 free_netdev(ndev);
2219 ret = -ENODEV;
2220 }
2221
2222 return ret;
2223}
2224
7da11600
M		 2225#define CPSW_QUIRK_IRQ BIT(0)
2226
2227static struct platform_device_id cpsw_devtype[] = {
2228 {
2229 /* keep it for existing comaptibles */
2230 .name = "cpsw",
2231 .driver_data = CPSW_QUIRK_IRQ,
2232 }, {
2233 .name = "am335x-cpsw",
2234 .driver_data = CPSW_QUIRK_IRQ,
2235 }, {
2236 .name = "am4372-cpsw",
2237 .driver_data = 0,
2238 }, {
2239 .name = "dra7-cpsw",
2240 .driver_data = 0,
2241 }, {
2242 /* sentinel */
2243 }
2244};
2245MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2246
2247enum ti_cpsw_type {
2248 CPSW = 0,
2249 AM335X_CPSW,
2250 AM4372_CPSW,
2251 DRA7_CPSW,
2252};
2253
2254static const struct of_device_id cpsw_of_mtable[] = {
2255 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2256 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2257 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2258 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2259 { /* sentinel */ },
2260};
2261MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2262
663e12e6 2263static int cpsw_probe(struct platform_device *pdev)
df828598 2264{
ef4183a1 2265 struct clk *clk;
d1bd9acf 2266 struct cpsw_platform_data *data;
df828598
M		 2267 struct net_device *ndev;
2268 struct cpsw_priv *priv;
2269 struct cpdma_params dma_params;
2270 struct cpsw_ale_params ale_params;
aa1a15e2
DM		 2271 void __iomem *ss_regs;
2272 struct resource *res, *ss_res;
7da11600 2273 const struct of_device_id *of_id;
1d147ccb 2274 struct gpio_descs *mode;
549985ee 2275 u32 slave_offset, sliver_offset, slave_size;
649a1688 2276 struct cpsw_common *cpsw;
5087b915
FB		 2277 int ret = 0, i;
2278 int irq;
df828598 2279
649a1688
IK		 2280 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2281 cpsw->pdev = pdev;
2282
df828598
M		 2283 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2284 if (!ndev) {
88c99ff6 2285 dev_err(&pdev->dev, "error allocating net_device\n");
df828598
M		 2286 return -ENOMEM;
2287 }
2288
2289 platform_set_drvdata(pdev, ndev);
2290 priv = netdev_priv(ndev);
649a1688 2291 priv->cpsw = cpsw;
df828598
M		 2292 priv->ndev = ndev;
2293 priv->dev = &ndev->dev;
2294 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2295 priv->rx_packet_max = max(rx_packet_max, 128);
9232b16d 2296 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
ab8e99d2 2297 if (!priv->cpts) {
88c99ff6 2298 dev_err(&pdev->dev, "error allocating cpts\n");
4d507dff 2299 ret = -ENOMEM;
9232b16d
M		 2300 goto clean_ndev_ret;
2301 }
df828598 2302
1d147ccb
M		 2303 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2304 if (IS_ERR(mode)) {
2305 ret = PTR_ERR(mode);
2306 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2307 goto clean_ndev_ret;
2308 }
2309
1fb19aa7
VH		 2310 /*
2311 * This may be required here for child devices.
2312 */
2313 pm_runtime_enable(&pdev->dev);
2314
739683b4
M		 2315 /* Select default pin state */
2316 pinctrl_pm_select_default_state(&pdev->dev);
2317
552165bc 2318 if (cpsw_probe_dt(&priv->data, pdev)) {
88c99ff6 2319 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2eb32b0a 2320 ret = -ENODEV;
aa1a15e2 2321 goto clean_runtime_disable_ret;
2eb32b0a
M		 2322 }
2323 data = &priv->data;
2324
df828598
M		 2325 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2326 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
88c99ff6 2327 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
df828598 2328 } else {
7efd26d0 2329 eth_random_addr(priv->mac_addr);
88c99ff6 2330 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
df828598
M		 2331 }
2332
2333 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2334
aa1a15e2
DM		 2335 priv->slaves = devm_kzalloc(&pdev->dev,
2336 sizeof(struct cpsw_slave) * data->slaves,
2337 GFP_KERNEL);
df828598 2338 if (!priv->slaves) {
aa1a15e2
DM		 2339 ret = -ENOMEM;
2340 goto clean_runtime_disable_ret;
df828598
M		 2341 }
2342 for (i = 0; i < data->slaves; i++)
2343 priv->slaves[i].slave_num = i;
2344
d9ba8f9e
M		 2345 priv->slaves[0].ndev = ndev;
2346 priv->emac_port = 0;
2347
ef4183a1
IK		 2348 clk = devm_clk_get(&pdev->dev, "fck");
2349 if (IS_ERR(clk)) {
aa1a15e2 2350 dev_err(priv->dev, "fck is not found\n");
f150bd7f 2351 ret = -ENODEV;
aa1a15e2 2352 goto clean_runtime_disable_ret;
df828598 2353 }
ff5b8ef2 2354 priv->coal_intvl = 0;
ef4183a1 2355 priv->bus_freq_mhz = clk_get_rate(clk) / 1000000;
df828598 2356
aa1a15e2
DM		 2357 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2358 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2359 if (IS_ERR(ss_regs)) {
2360 ret = PTR_ERR(ss_regs);
2361 goto clean_runtime_disable_ret;
df828598 2362 }
549985ee 2363 priv->regs = ss_regs;
df828598 2364
f280e89a
M		 2365 /* Need to enable clocks with runtime PM api to access module
2366 * registers
2367 */
108a6537
GS		 2368 ret = pm_runtime_get_sync(&pdev->dev);
2369 if (ret < 0) {
2370 pm_runtime_put_noidle(&pdev->dev);
2371 goto clean_runtime_disable_ret;
2372 }
f280e89a
M		 2373 priv->version = readl(&priv->regs->id_ver);
2374 pm_runtime_put_sync(&pdev->dev);
2375
aa1a15e2
DM		 2376 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2377 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2378 if (IS_ERR(priv->wr_regs)) {
2379 ret = PTR_ERR(priv->wr_regs);
2380 goto clean_runtime_disable_ret;
df828598 2381 }
df828598
M		 2382
2383 memset(&dma_params, 0, sizeof(dma_params));
549985ee
RC		 2384 memset(&ale_params, 0, sizeof(ale_params));
2385
2386 switch (priv->version) {
2387 case CPSW_VERSION_1:
2388 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
d9718546
M		 2389 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2390 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
549985ee
RC		 2391 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2392 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2393 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2394 slave_offset = CPSW1_SLAVE_OFFSET;
2395 slave_size = CPSW1_SLAVE_SIZE;
2396 sliver_offset = CPSW1_SLIVER_OFFSET;
2397 dma_params.desc_mem_phys = 0;
2398 break;
2399 case CPSW_VERSION_2:
c193f365 2400 case CPSW_VERSION_3:
926489be 2401 case CPSW_VERSION_4:
549985ee 2402 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
d9718546
M		 2403 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2404 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
549985ee
RC		 2405 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2406 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2407 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2408 slave_offset = CPSW2_SLAVE_OFFSET;
2409 slave_size = CPSW2_SLAVE_SIZE;
2410 sliver_offset = CPSW2_SLIVER_OFFSET;
2411 dma_params.desc_mem_phys =
aa1a15e2 2412 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
549985ee
RC		 2413 break;
2414 default:
2415 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2416 ret = -ENODEV;
aa1a15e2 2417 goto clean_runtime_disable_ret;
549985ee
RC		 2418 }
2419 for (i = 0; i < priv->data.slaves; i++) {
2420 struct cpsw_slave *slave = &priv->slaves[i];
2421 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2422 slave_offset += slave_size;
2423 sliver_offset += SLIVER_SIZE;
2424 }
2425
df828598 2426 dma_params.dev = &pdev->dev;
549985ee
RC		 2427 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2428 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2429 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2430 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2431 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
df828598
M		 2432
2433 dma_params.num_chan = data->channels;
2434 dma_params.has_soft_reset = true;
2435 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2436 dma_params.desc_mem_size = data->bd_ram_size;
2437 dma_params.desc_align = 16;
2438 dma_params.has_ext_regs = true;
549985ee 2439 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
df828598
M		 2440
2441 priv->dma = cpdma_ctlr_create(&dma_params);
2442 if (!priv->dma) {
2443 dev_err(priv->dev, "error initializing dma\n");
2444 ret = -ENOMEM;
aa1a15e2 2445 goto clean_runtime_disable_ret;
df828598
M		 2446 }
2447
2448 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2449 cpsw_tx_handler);
2450 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2451 cpsw_rx_handler);
2452
2453 if (WARN_ON(!priv->txch || !priv->rxch)) {
2454 dev_err(priv->dev, "error initializing dma channels\n");
2455 ret = -ENOMEM;
2456 goto clean_dma_ret;
2457 }
2458
df828598 2459 ale_params.dev = &ndev->dev;
df828598
M		 2460 ale_params.ale_ageout = ale_ageout;
2461 ale_params.ale_entries = data->ale_entries;
2462 ale_params.ale_ports = data->slaves;
2463
2464 priv->ale = cpsw_ale_create(&ale_params);
2465 if (!priv->ale) {
2466 dev_err(priv->dev, "error initializing ale engine\n");
2467 ret = -ENODEV;
2468 goto clean_dma_ret;
2469 }
2470
c03abd84 2471 ndev->irq = platform_get_irq(pdev, 1);
df828598
M		 2472 if (ndev->irq < 0) {
2473 dev_err(priv->dev, "error getting irq resource\n");
c1e3334f 2474 ret = ndev->irq;
df828598
M		 2475 goto clean_ale_ret;
2476 }
2477
7da11600
M		 2478 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2479 if (of_id) {
2480 pdev->id_entry = of_id->data;
2481 if (pdev->id_entry->driver_data)
2482 priv->quirk_irq = true;
2483 }
2484
c03abd84
FB		 2485 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2486 * MISC IRQs which are always kept disabled with this driver so
2487 * we will not request them.
2488 *
2489 * If anyone wants to implement support for those, make sure to
2490 * first request and append them to irqs_table array.
2491 */
c2b32e58 2492
c03abd84 2493 /* RX IRQ */
5087b915 2494 irq = platform_get_irq(pdev, 1);
c1e3334f
JL		 2495 if (irq < 0) {
2496 ret = irq;
5087b915 2497 goto clean_ale_ret;
c1e3334f 2498 }
5087b915 2499
c03abd84
FB		 2500 priv->irqs_table[0] = irq;
2501 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
5087b915
FB		 2502 0, dev_name(&pdev->dev), priv);
2503 if (ret < 0) {
2504 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2505 goto clean_ale_ret;
2506 }
2507
c03abd84 2508 /* TX IRQ */
5087b915 2509 irq = platform_get_irq(pdev, 2);
c1e3334f
JL		 2510 if (irq < 0) {
2511 ret = irq;
5087b915 2512 goto clean_ale_ret;
c1e3334f 2513 }
5087b915 2514
c03abd84
FB		 2515 priv->irqs_table[1] = irq;
2516 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
5087b915
FB		 2517 0, dev_name(&pdev->dev), priv);
2518 if (ret < 0) {
2519 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2520 goto clean_ale_ret;
df828598 2521 }
c03abd84 2522 priv->num_irqs = 2;
c2b32e58 2523
f646968f 2524 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
df828598
M		 2525
2526 ndev->netdev_ops = &cpsw_netdev_ops;
7ad24ea4 2527 ndev->ethtool_ops = &cpsw_ethtool_ops;
32a7432c 2528 netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
d64b5e85 2529 netif_tx_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
df828598
M		 2530
2531 /* register the network device */
2532 SET_NETDEV_DEV(ndev, &pdev->dev);
2533 ret = register_netdev(ndev);
2534 if (ret) {
2535 dev_err(priv->dev, "error registering net device\n");
2536 ret = -ENODEV;
aa1a15e2 2537 goto clean_ale_ret;
df828598
M		 2538 }
2539
1a3b5056
OJ		 2540 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2541 &ss_res->start, ndev->irq);
df828598 2542
d9ba8f9e
M		 2543 if (priv->data.dual_emac) {
2544 ret = cpsw_probe_dual_emac(pdev, priv);
2545 if (ret) {
2546 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
aa1a15e2 2547 goto clean_ale_ret;
d9ba8f9e
M		 2548 }
2549 }
2550
df828598
M		 2551 return 0;
2552
df828598
M		 2553clean_ale_ret:
2554 cpsw_ale_destroy(priv->ale);
2555clean_dma_ret:
df828598 2556 cpdma_ctlr_destroy(priv->dma);
aa1a15e2 2557clean_runtime_disable_ret:
f150bd7f 2558 pm_runtime_disable(&pdev->dev);
df828598 2559clean_ndev_ret:
d1bd9acf 2560 free_netdev(priv->ndev);
df828598
M		 2561 return ret;
2562}
2563
663e12e6 2564static int cpsw_remove(struct platform_device *pdev)
df828598
M		 2565{
2566 struct net_device *ndev = platform_get_drvdata(pdev);
2567 struct cpsw_priv *priv = netdev_priv(ndev);
8a0b6dc9
GS		 2568 int ret;
2569
2570 ret = pm_runtime_get_sync(&pdev->dev);
2571 if (ret < 0) {
2572 pm_runtime_put_noidle(&pdev->dev);
2573 return ret;
2574 }
df828598 2575
d1bd9acf 2576 if (priv->data.dual_emac)
82b52104 2577 unregister_netdev(priv->slaves[1].ndev);
d1bd9acf 2578 unregister_netdev(ndev);
df828598 2579
df828598 2580 cpsw_ale_destroy(priv->ale);
df828598 2581 cpdma_ctlr_destroy(priv->dma);
3bf2cb3a 2582 of_platform_depopulate(&pdev->dev);
8a0b6dc9
GS		 2583 pm_runtime_put_sync(&pdev->dev);
2584 pm_runtime_disable(&pdev->dev);
d1bd9acf 2585 if (priv->data.dual_emac)
82b52104 2586 free_netdev(priv->slaves[1].ndev);
df828598 2587 free_netdev(ndev);
df828598
M		 2588 return 0;
2589}
2590
8963a504 2591#ifdef CONFIG_PM_SLEEP
df828598
M		 2592static int cpsw_suspend(struct device *dev)
2593{
2594 struct platform_device *pdev = to_platform_device(dev);
2595 struct net_device *ndev = platform_get_drvdata(pdev);
b90fc27a 2596 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2597
618073e3
M		 2598 if (priv->data.dual_emac) {
2599 int i;
1e7a2e21 2600
618073e3
M		 2601 for (i = 0; i < priv->data.slaves; i++) {
2602 if (netif_running(priv->slaves[i].ndev))
2603 cpsw_ndo_stop(priv->slaves[i].ndev);
618073e3
M		 2604 }
2605 } else {
2606 if (netif_running(ndev))
2607 cpsw_ndo_stop(ndev);
618073e3 2608 }
1e7a2e21 2609
739683b4
M		 2610 /* Select sleep pin state */
2611 pinctrl_pm_select_sleep_state(&pdev->dev);
2612
df828598
M		 2613 return 0;
2614}
2615
2616static int cpsw_resume(struct device *dev)
2617{
2618 struct platform_device *pdev = to_platform_device(dev);
2619 struct net_device *ndev = platform_get_drvdata(pdev);
618073e3 2620 struct cpsw_priv *priv = netdev_priv(ndev);
df828598 2621
739683b4
M		 2622 /* Select default pin state */
2623 pinctrl_pm_select_default_state(&pdev->dev);
2624
618073e3
M		 2625 if (priv->data.dual_emac) {
2626 int i;
2627
2628 for (i = 0; i < priv->data.slaves; i++) {
2629 if (netif_running(priv->slaves[i].ndev))
2630 cpsw_ndo_open(priv->slaves[i].ndev);
2631 }
2632 } else {
2633 if (netif_running(ndev))
2634 cpsw_ndo_open(ndev);
2635 }
df828598
M		 2636 return 0;
2637}
8963a504 2638#endif
df828598 2639
8963a504 2640static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
df828598
M		 2641
2642static struct platform_driver cpsw_driver = {
2643 .driver = {
2644 .name = "cpsw",
df828598 2645 .pm = &cpsw_pm_ops,
1e5c76d4 2646 .of_match_table = cpsw_of_mtable,
df828598
M		 2647 },
2648 .probe = cpsw_probe,
663e12e6 2649 .remove = cpsw_remove,
df828598
M		 2650};
2651
6fb3b6b5 2652module_platform_driver(cpsw_driver);
df828598
M		 2653
2654MODULE_LICENSE("GPL");
2655MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2656MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2657MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux 6.x block layer and io_uring tree(s)