Commit | Line | Data |
---|---|---|
d95b39c3 MC |
1 | /* |
2 | * Copyright (C) 2006, 2007 Eugene Konev | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
539d3ee6 | 20 | #include <linux/interrupt.h> |
d95b39c3 MC |
21 | #include <linux/moduleparam.h> |
22 | ||
23 | #include <linux/sched.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/delay.h> | |
d95b39c3 MC |
29 | |
30 | #include <linux/netdevice.h> | |
30765d05 | 31 | #include <linux/if_vlan.h> |
d95b39c3 MC |
32 | #include <linux/etherdevice.h> |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/mii.h> | |
36 | #include <linux/phy.h> | |
b88219f8 | 37 | #include <linux/phy_fixed.h> |
d95b39c3 MC |
38 | #include <linux/platform_device.h> |
39 | #include <linux/dma-mapping.h> | |
780019dd | 40 | #include <linux/clk.h> |
559764d1 | 41 | #include <linux/gpio.h> |
60063497 | 42 | #include <linux/atomic.h> |
d95b39c3 | 43 | |
832f5dac AB |
44 | #include <asm/mach-ar7/ar7.h> |
45 | ||
d95b39c3 MC |
46 | MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>"); |
47 | MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)"); | |
48 | MODULE_LICENSE("GPL"); | |
72abb461 | 49 | MODULE_ALIAS("platform:cpmac"); |
d95b39c3 MC |
50 | |
51 | static int debug_level = 8; | |
52 | static int dumb_switch; | |
53 | ||
54 | /* Next 2 are only used in cpmac_probe, so it's pointless to change them */ | |
55 | module_param(debug_level, int, 0444); | |
56 | module_param(dumb_switch, int, 0444); | |
57 | ||
58 | MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable"); | |
59 | MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus"); | |
60 | ||
25dc27d1 | 61 | #define CPMAC_VERSION "0.5.2" |
30765d05 FF |
62 | /* frame size + 802.1q tag + FCS size */ |
63 | #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) | |
d95b39c3 MC |
64 | #define CPMAC_QUEUES 8 |
65 | ||
66 | /* Ethernet registers */ | |
67 | #define CPMAC_TX_CONTROL 0x0004 | |
68 | #define CPMAC_TX_TEARDOWN 0x0008 | |
69 | #define CPMAC_RX_CONTROL 0x0014 | |
70 | #define CPMAC_RX_TEARDOWN 0x0018 | |
71 | #define CPMAC_MBP 0x0100 | |
af595154 VB |
72 | #define MBP_RXPASSCRC 0x40000000 |
73 | #define MBP_RXQOS 0x20000000 | |
74 | #define MBP_RXNOCHAIN 0x10000000 | |
75 | #define MBP_RXCMF 0x01000000 | |
76 | #define MBP_RXSHORT 0x00800000 | |
77 | #define MBP_RXCEF 0x00400000 | |
78 | #define MBP_RXPROMISC 0x00200000 | |
79 | #define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16) | |
80 | #define MBP_RXBCAST 0x00002000 | |
81 | #define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8) | |
82 | #define MBP_RXMCAST 0x00000020 | |
83 | #define MBP_MCASTCHAN(channel) ((channel) & 0x7) | |
d95b39c3 MC |
84 | #define CPMAC_UNICAST_ENABLE 0x0104 |
85 | #define CPMAC_UNICAST_CLEAR 0x0108 | |
86 | #define CPMAC_MAX_LENGTH 0x010c | |
87 | #define CPMAC_BUFFER_OFFSET 0x0110 | |
88 | #define CPMAC_MAC_CONTROL 0x0160 | |
af595154 VB |
89 | #define MAC_TXPTYPE 0x00000200 |
90 | #define MAC_TXPACE 0x00000040 | |
91 | #define MAC_MII 0x00000020 | |
92 | #define MAC_TXFLOW 0x00000010 | |
93 | #define MAC_RXFLOW 0x00000008 | |
94 | #define MAC_MTEST 0x00000004 | |
95 | #define MAC_LOOPBACK 0x00000002 | |
96 | #define MAC_FDX 0x00000001 | |
d95b39c3 | 97 | #define CPMAC_MAC_STATUS 0x0164 |
af595154 VB |
98 | #define MAC_STATUS_QOS 0x00000004 |
99 | #define MAC_STATUS_RXFLOW 0x00000002 | |
100 | #define MAC_STATUS_TXFLOW 0x00000001 | |
d95b39c3 MC |
101 | #define CPMAC_TX_INT_ENABLE 0x0178 |
102 | #define CPMAC_TX_INT_CLEAR 0x017c | |
103 | #define CPMAC_MAC_INT_VECTOR 0x0180 | |
af595154 VB |
104 | #define MAC_INT_STATUS 0x00080000 |
105 | #define MAC_INT_HOST 0x00040000 | |
106 | #define MAC_INT_RX 0x00020000 | |
107 | #define MAC_INT_TX 0x00010000 | |
d95b39c3 MC |
108 | #define CPMAC_MAC_EOI_VECTOR 0x0184 |
109 | #define CPMAC_RX_INT_ENABLE 0x0198 | |
110 | #define CPMAC_RX_INT_CLEAR 0x019c | |
111 | #define CPMAC_MAC_INT_ENABLE 0x01a8 | |
112 | #define CPMAC_MAC_INT_CLEAR 0x01ac | |
559764d1 | 113 | #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4) |
d95b39c3 MC |
114 | #define CPMAC_MAC_ADDR_MID 0x01d0 |
115 | #define CPMAC_MAC_ADDR_HI 0x01d4 | |
116 | #define CPMAC_MAC_HASH_LO 0x01d8 | |
117 | #define CPMAC_MAC_HASH_HI 0x01dc | |
118 | #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4) | |
119 | #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4) | |
120 | #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4) | |
121 | #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4) | |
122 | #define CPMAC_REG_END 0x0680 | |
8bcd5c6d VB |
123 | |
124 | /* Rx/Tx statistics | |
d95b39c3 MC |
125 | * TODO: use some of them to fill stats in cpmac_stats() |
126 | */ | |
127 | #define CPMAC_STATS_RX_GOOD 0x0200 | |
128 | #define CPMAC_STATS_RX_BCAST 0x0204 | |
129 | #define CPMAC_STATS_RX_MCAST 0x0208 | |
130 | #define CPMAC_STATS_RX_PAUSE 0x020c | |
131 | #define CPMAC_STATS_RX_CRC 0x0210 | |
132 | #define CPMAC_STATS_RX_ALIGN 0x0214 | |
133 | #define CPMAC_STATS_RX_OVER 0x0218 | |
134 | #define CPMAC_STATS_RX_JABBER 0x021c | |
135 | #define CPMAC_STATS_RX_UNDER 0x0220 | |
136 | #define CPMAC_STATS_RX_FRAG 0x0224 | |
137 | #define CPMAC_STATS_RX_FILTER 0x0228 | |
138 | #define CPMAC_STATS_RX_QOSFILTER 0x022c | |
139 | #define CPMAC_STATS_RX_OCTETS 0x0230 | |
140 | ||
141 | #define CPMAC_STATS_TX_GOOD 0x0234 | |
142 | #define CPMAC_STATS_TX_BCAST 0x0238 | |
143 | #define CPMAC_STATS_TX_MCAST 0x023c | |
144 | #define CPMAC_STATS_TX_PAUSE 0x0240 | |
145 | #define CPMAC_STATS_TX_DEFER 0x0244 | |
146 | #define CPMAC_STATS_TX_COLLISION 0x0248 | |
147 | #define CPMAC_STATS_TX_SINGLECOLL 0x024c | |
148 | #define CPMAC_STATS_TX_MULTICOLL 0x0250 | |
149 | #define CPMAC_STATS_TX_EXCESSCOLL 0x0254 | |
150 | #define CPMAC_STATS_TX_LATECOLL 0x0258 | |
151 | #define CPMAC_STATS_TX_UNDERRUN 0x025c | |
152 | #define CPMAC_STATS_TX_CARRIERSENSE 0x0260 | |
153 | #define CPMAC_STATS_TX_OCTETS 0x0264 | |
154 | ||
155 | #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg))) | |
156 | #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \ | |
157 | (reg))) | |
158 | ||
159 | /* MDIO bus */ | |
160 | #define CPMAC_MDIO_VERSION 0x0000 | |
161 | #define CPMAC_MDIO_CONTROL 0x0004 | |
af595154 VB |
162 | #define MDIOC_IDLE 0x80000000 |
163 | #define MDIOC_ENABLE 0x40000000 | |
164 | #define MDIOC_PREAMBLE 0x00100000 | |
165 | #define MDIOC_FAULT 0x00080000 | |
166 | #define MDIOC_FAULTDETECT 0x00040000 | |
167 | #define MDIOC_INTTEST 0x00020000 | |
168 | #define MDIOC_CLKDIV(div) ((div) & 0xff) | |
d95b39c3 MC |
169 | #define CPMAC_MDIO_ALIVE 0x0008 |
170 | #define CPMAC_MDIO_LINK 0x000c | |
171 | #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8) | |
af595154 VB |
172 | #define MDIO_BUSY 0x80000000 |
173 | #define MDIO_WRITE 0x40000000 | |
174 | #define MDIO_REG(reg) (((reg) & 0x1f) << 21) | |
175 | #define MDIO_PHY(phy) (((phy) & 0x1f) << 16) | |
176 | #define MDIO_DATA(data) ((data) & 0xffff) | |
d95b39c3 | 177 | #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8) |
af595154 VB |
178 | #define PHYSEL_LINKSEL 0x00000040 |
179 | #define PHYSEL_LINKINT 0x00000020 | |
d95b39c3 MC |
180 | |
181 | struct cpmac_desc { | |
182 | u32 hw_next; | |
183 | u32 hw_data; | |
184 | u16 buflen; | |
185 | u16 bufflags; | |
186 | u16 datalen; | |
187 | u16 dataflags; | |
188 | #define CPMAC_SOP 0x8000 | |
189 | #define CPMAC_EOP 0x4000 | |
190 | #define CPMAC_OWN 0x2000 | |
191 | #define CPMAC_EOQ 0x1000 | |
192 | struct sk_buff *skb; | |
193 | struct cpmac_desc *next; | |
f917d580 | 194 | struct cpmac_desc *prev; |
d95b39c3 MC |
195 | dma_addr_t mapping; |
196 | dma_addr_t data_mapping; | |
197 | }; | |
198 | ||
199 | struct cpmac_priv { | |
200 | spinlock_t lock; | |
201 | spinlock_t rx_lock; | |
202 | struct cpmac_desc *rx_head; | |
203 | int ring_size; | |
204 | struct cpmac_desc *desc_ring; | |
205 | dma_addr_t dma_ring; | |
206 | void __iomem *regs; | |
207 | struct mii_bus *mii_bus; | |
21a8cfe1 | 208 | char phy_name[MII_BUS_ID_SIZE + 3]; |
d95b39c3 MC |
209 | int oldlink, oldspeed, oldduplex; |
210 | u32 msg_enable; | |
211 | struct net_device *dev; | |
212 | struct work_struct reset_work; | |
213 | struct platform_device *pdev; | |
67d129d1 | 214 | struct napi_struct napi; |
f917d580 | 215 | atomic_t reset_pending; |
d95b39c3 MC |
216 | }; |
217 | ||
218 | static irqreturn_t cpmac_irq(int, void *); | |
219 | static void cpmac_hw_start(struct net_device *dev); | |
220 | static void cpmac_hw_stop(struct net_device *dev); | |
221 | static int cpmac_stop(struct net_device *dev); | |
222 | static int cpmac_open(struct net_device *dev); | |
223 | ||
224 | static void cpmac_dump_regs(struct net_device *dev) | |
225 | { | |
226 | int i; | |
227 | struct cpmac_priv *priv = netdev_priv(dev); | |
59329d8b | 228 | |
d95b39c3 MC |
229 | for (i = 0; i < CPMAC_REG_END; i += 4) { |
230 | if (i % 16 == 0) { | |
231 | if (i) | |
ff32045e VB |
232 | printk("\n"); |
233 | printk("%s: reg[%p]:", dev->name, priv->regs + i); | |
d95b39c3 | 234 | } |
ff32045e | 235 | printk(" %08x", cpmac_read(priv->regs, i)); |
d95b39c3 | 236 | } |
ff32045e | 237 | printk("\n"); |
d95b39c3 MC |
238 | } |
239 | ||
240 | static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc) | |
241 | { | |
242 | int i; | |
59329d8b | 243 | |
ff32045e | 244 | printk("%s: desc[%p]:", dev->name, desc); |
d95b39c3 | 245 | for (i = 0; i < sizeof(*desc) / 4; i++) |
ff32045e VB |
246 | printk(" %08x", ((u32 *)desc)[i]); |
247 | printk("\n"); | |
d95b39c3 MC |
248 | } |
249 | ||
f917d580 MC |
250 | static void cpmac_dump_all_desc(struct net_device *dev) |
251 | { | |
252 | struct cpmac_priv *priv = netdev_priv(dev); | |
253 | struct cpmac_desc *dump = priv->rx_head; | |
59329d8b | 254 | |
f917d580 MC |
255 | do { |
256 | cpmac_dump_desc(dev, dump); | |
257 | dump = dump->next; | |
258 | } while (dump != priv->rx_head); | |
259 | } | |
260 | ||
d95b39c3 MC |
261 | static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb) |
262 | { | |
263 | int i; | |
59329d8b | 264 | |
ff32045e | 265 | printk("%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len); |
d95b39c3 MC |
266 | for (i = 0; i < skb->len; i++) { |
267 | if (i % 16 == 0) { | |
268 | if (i) | |
ff32045e VB |
269 | printk("\n"); |
270 | printk("%s: data[%p]:", dev->name, skb->data + i); | |
d95b39c3 | 271 | } |
ff32045e | 272 | printk(" %02x", ((u8 *)skb->data)[i]); |
d95b39c3 | 273 | } |
ff32045e | 274 | printk("\n"); |
d95b39c3 MC |
275 | } |
276 | ||
277 | static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg) | |
278 | { | |
279 | u32 val; | |
280 | ||
281 | while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY) | |
282 | cpu_relax(); | |
283 | cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) | | |
284 | MDIO_PHY(phy_id)); | |
285 | while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY) | |
286 | cpu_relax(); | |
55064efd | 287 | |
d95b39c3 MC |
288 | return MDIO_DATA(val); |
289 | } | |
290 | ||
291 | static int cpmac_mdio_write(struct mii_bus *bus, int phy_id, | |
292 | int reg, u16 val) | |
293 | { | |
294 | while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY) | |
295 | cpu_relax(); | |
296 | cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE | | |
297 | MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val)); | |
55064efd | 298 | |
d95b39c3 MC |
299 | return 0; |
300 | } | |
301 | ||
302 | static int cpmac_mdio_reset(struct mii_bus *bus) | |
303 | { | |
780019dd FF |
304 | struct clk *cpmac_clk; |
305 | ||
306 | cpmac_clk = clk_get(&bus->dev, "cpmac"); | |
307 | if (IS_ERR(cpmac_clk)) { | |
f160a2d0 | 308 | pr_err("unable to get cpmac clock\n"); |
780019dd FF |
309 | return -1; |
310 | } | |
d95b39c3 MC |
311 | ar7_device_reset(AR7_RESET_BIT_MDIO); |
312 | cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE | | |
780019dd | 313 | MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1)); |
55064efd | 314 | |
d95b39c3 MC |
315 | return 0; |
316 | } | |
317 | ||
298cf9be | 318 | static struct mii_bus *cpmac_mii; |
d95b39c3 | 319 | |
d95b39c3 MC |
320 | static void cpmac_set_multicast_list(struct net_device *dev) |
321 | { | |
22bedad3 | 322 | struct netdev_hw_addr *ha; |
d95b39c3 MC |
323 | u8 tmp; |
324 | u32 mbp, bit, hash[2] = { 0, }; | |
325 | struct cpmac_priv *priv = netdev_priv(dev); | |
326 | ||
327 | mbp = cpmac_read(priv->regs, CPMAC_MBP); | |
328 | if (dev->flags & IFF_PROMISC) { | |
329 | cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) | | |
330 | MBP_RXPROMISC); | |
331 | } else { | |
332 | cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC); | |
333 | if (dev->flags & IFF_ALLMULTI) { | |
334 | /* enable all multicast mode */ | |
335 | cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff); | |
336 | cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff); | |
337 | } else { | |
8bcd5c6d | 338 | /* cpmac uses some strange mac address hashing |
d95b39c3 MC |
339 | * (not crc32) |
340 | */ | |
22bedad3 | 341 | netdev_for_each_mc_addr(ha, dev) { |
d95b39c3 | 342 | bit = 0; |
22bedad3 | 343 | tmp = ha->addr[0]; |
d95b39c3 | 344 | bit ^= (tmp >> 2) ^ (tmp << 4); |
22bedad3 | 345 | tmp = ha->addr[1]; |
d95b39c3 | 346 | bit ^= (tmp >> 4) ^ (tmp << 2); |
22bedad3 | 347 | tmp = ha->addr[2]; |
d95b39c3 | 348 | bit ^= (tmp >> 6) ^ tmp; |
22bedad3 | 349 | tmp = ha->addr[3]; |
d95b39c3 | 350 | bit ^= (tmp >> 2) ^ (tmp << 4); |
22bedad3 | 351 | tmp = ha->addr[4]; |
d95b39c3 | 352 | bit ^= (tmp >> 4) ^ (tmp << 2); |
22bedad3 | 353 | tmp = ha->addr[5]; |
d95b39c3 MC |
354 | bit ^= (tmp >> 6) ^ tmp; |
355 | bit &= 0x3f; | |
356 | hash[bit / 32] |= 1 << (bit % 32); | |
357 | } | |
358 | ||
359 | cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]); | |
360 | cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]); | |
361 | } | |
362 | } | |
363 | } | |
364 | ||
67d129d1 | 365 | static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv, |
d95b39c3 MC |
366 | struct cpmac_desc *desc) |
367 | { | |
368 | struct sk_buff *skb, *result = NULL; | |
369 | ||
370 | if (unlikely(netif_msg_hw(priv))) | |
67d129d1 | 371 | cpmac_dump_desc(priv->dev, desc); |
d95b39c3 MC |
372 | cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping); |
373 | if (unlikely(!desc->datalen)) { | |
374 | if (netif_msg_rx_err(priv) && net_ratelimit()) | |
f160a2d0 VB |
375 | netdev_warn(priv->dev, "rx: spurious interrupt\n"); |
376 | ||
d95b39c3 MC |
377 | return NULL; |
378 | } | |
379 | ||
89d71a66 | 380 | skb = netdev_alloc_skb_ip_align(priv->dev, CPMAC_SKB_SIZE); |
d95b39c3 | 381 | if (likely(skb)) { |
d95b39c3 | 382 | skb_put(desc->skb, desc->datalen); |
67d129d1 | 383 | desc->skb->protocol = eth_type_trans(desc->skb, priv->dev); |
bc8acf2c | 384 | skb_checksum_none_assert(desc->skb); |
67d129d1 EK |
385 | priv->dev->stats.rx_packets++; |
386 | priv->dev->stats.rx_bytes += desc->datalen; | |
d95b39c3 | 387 | result = desc->skb; |
67d129d1 EK |
388 | dma_unmap_single(&priv->dev->dev, desc->data_mapping, |
389 | CPMAC_SKB_SIZE, DMA_FROM_DEVICE); | |
d95b39c3 | 390 | desc->skb = skb; |
67d129d1 | 391 | desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data, |
d95b39c3 MC |
392 | CPMAC_SKB_SIZE, |
393 | DMA_FROM_DEVICE); | |
394 | desc->hw_data = (u32)desc->data_mapping; | |
395 | if (unlikely(netif_msg_pktdata(priv))) { | |
f160a2d0 | 396 | netdev_dbg(priv->dev, "received packet:\n"); |
67d129d1 | 397 | cpmac_dump_skb(priv->dev, result); |
d95b39c3 MC |
398 | } |
399 | } else { | |
400 | if (netif_msg_rx_err(priv) && net_ratelimit()) | |
f160a2d0 VB |
401 | netdev_warn(priv->dev, |
402 | "low on skbs, dropping packet\n"); | |
403 | ||
67d129d1 | 404 | priv->dev->stats.rx_dropped++; |
d95b39c3 MC |
405 | } |
406 | ||
407 | desc->buflen = CPMAC_SKB_SIZE; | |
408 | desc->dataflags = CPMAC_OWN; | |
409 | ||
410 | return result; | |
411 | } | |
412 | ||
67d129d1 | 413 | static int cpmac_poll(struct napi_struct *napi, int budget) |
d95b39c3 MC |
414 | { |
415 | struct sk_buff *skb; | |
f917d580 | 416 | struct cpmac_desc *desc, *restart; |
67d129d1 | 417 | struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi); |
f917d580 | 418 | int received = 0, processed = 0; |
d95b39c3 MC |
419 | |
420 | spin_lock(&priv->rx_lock); | |
421 | if (unlikely(!priv->rx_head)) { | |
422 | if (netif_msg_rx_err(priv) && net_ratelimit()) | |
f160a2d0 VB |
423 | netdev_warn(priv->dev, "rx: polling, but no queue\n"); |
424 | ||
f917d580 | 425 | spin_unlock(&priv->rx_lock); |
288379f0 | 426 | napi_complete(napi); |
d95b39c3 MC |
427 | return 0; |
428 | } | |
429 | ||
430 | desc = priv->rx_head; | |
f917d580 | 431 | restart = NULL; |
67d129d1 | 432 | while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) { |
f917d580 MC |
433 | processed++; |
434 | ||
435 | if ((desc->dataflags & CPMAC_EOQ) != 0) { | |
436 | /* The last update to eoq->hw_next didn't happen | |
8bcd5c6d VB |
437 | * soon enough, and the receiver stopped here. |
438 | * Remember this descriptor so we can restart | |
439 | * the receiver after freeing some space. | |
440 | */ | |
f917d580 MC |
441 | if (unlikely(restart)) { |
442 | if (netif_msg_rx_err(priv)) | |
f160a2d0 VB |
443 | netdev_err(priv->dev, "poll found a" |
444 | " duplicate EOQ: %p and %p\n", | |
445 | restart, desc); | |
f917d580 MC |
446 | goto fatal_error; |
447 | } | |
448 | ||
449 | restart = desc->next; | |
450 | } | |
451 | ||
67d129d1 | 452 | skb = cpmac_rx_one(priv, desc); |
d95b39c3 MC |
453 | if (likely(skb)) { |
454 | netif_receive_skb(skb); | |
455 | received++; | |
456 | } | |
457 | desc = desc->next; | |
458 | } | |
459 | ||
f917d580 MC |
460 | if (desc != priv->rx_head) { |
461 | /* We freed some buffers, but not the whole ring, | |
8bcd5c6d VB |
462 | * add what we did free to the rx list |
463 | */ | |
f917d580 MC |
464 | desc->prev->hw_next = (u32)0; |
465 | priv->rx_head->prev->hw_next = priv->rx_head->mapping; | |
466 | } | |
467 | ||
468 | /* Optimization: If we did not actually process an EOQ (perhaps because | |
469 | * of quota limits), check to see if the tail of the queue has EOQ set. | |
8bcd5c6d VB |
470 | * We should immediately restart in that case so that the receiver can |
471 | * restart and run in parallel with more packet processing. | |
472 | * This lets us handle slightly larger bursts before running | |
473 | * out of ring space (assuming dev->weight < ring_size) | |
474 | */ | |
f917d580 MC |
475 | |
476 | if (!restart && | |
477 | (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ)) | |
478 | == CPMAC_EOQ && | |
479 | (priv->rx_head->dataflags & CPMAC_OWN) != 0) { | |
480 | /* reset EOQ so the poll loop (above) doesn't try to | |
8bcd5c6d VB |
481 | * restart this when it eventually gets to this descriptor. |
482 | */ | |
f917d580 MC |
483 | priv->rx_head->prev->dataflags &= ~CPMAC_EOQ; |
484 | restart = priv->rx_head; | |
485 | } | |
486 | ||
487 | if (restart) { | |
488 | priv->dev->stats.rx_errors++; | |
489 | priv->dev->stats.rx_fifo_errors++; | |
490 | if (netif_msg_rx_err(priv) && net_ratelimit()) | |
f160a2d0 | 491 | netdev_warn(priv->dev, "rx dma ring overrun\n"); |
f917d580 MC |
492 | |
493 | if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) { | |
494 | if (netif_msg_drv(priv)) | |
f160a2d0 VB |
495 | netdev_err(priv->dev, "cpmac_poll is trying " |
496 | "to restart rx from a descriptor " | |
497 | "that's not free: %p\n", restart); | |
9e1634a7 | 498 | goto fatal_error; |
f917d580 MC |
499 | } |
500 | ||
501 | cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping); | |
502 | } | |
503 | ||
d95b39c3 MC |
504 | priv->rx_head = desc; |
505 | spin_unlock(&priv->rx_lock); | |
d95b39c3 | 506 | if (unlikely(netif_msg_rx_status(priv))) |
f160a2d0 VB |
507 | netdev_dbg(priv->dev, "poll processed %d packets\n", received); |
508 | ||
f917d580 MC |
509 | if (processed == 0) { |
510 | /* we ran out of packets to read, | |
8bcd5c6d VB |
511 | * revert to interrupt-driven mode |
512 | */ | |
288379f0 | 513 | napi_complete(napi); |
d95b39c3 MC |
514 | cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1); |
515 | return 0; | |
516 | } | |
517 | ||
518 | return 1; | |
f917d580 MC |
519 | |
520 | fatal_error: | |
521 | /* Something went horribly wrong. | |
8bcd5c6d VB |
522 | * Reset hardware to try to recover rather than wedging. |
523 | */ | |
f917d580 | 524 | if (netif_msg_drv(priv)) { |
f160a2d0 VB |
525 | netdev_err(priv->dev, "cpmac_poll is confused. " |
526 | "Resetting hardware\n"); | |
f917d580 | 527 | cpmac_dump_all_desc(priv->dev); |
f160a2d0 VB |
528 | netdev_dbg(priv->dev, "RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n", |
529 | cpmac_read(priv->regs, CPMAC_RX_PTR(0)), | |
530 | cpmac_read(priv->regs, CPMAC_RX_ACK(0))); | |
f917d580 MC |
531 | } |
532 | ||
533 | spin_unlock(&priv->rx_lock); | |
288379f0 | 534 | napi_complete(napi); |
fd2ea0a7 | 535 | netif_tx_stop_all_queues(priv->dev); |
f917d580 MC |
536 | napi_disable(&priv->napi); |
537 | ||
538 | atomic_inc(&priv->reset_pending); | |
539 | cpmac_hw_stop(priv->dev); | |
540 | if (!schedule_work(&priv->reset_work)) | |
541 | atomic_dec(&priv->reset_pending); | |
55064efd | 542 | |
f917d580 MC |
543 | return 0; |
544 | ||
d95b39c3 MC |
545 | } |
546 | ||
547 | static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
548 | { | |
2f5281ba PB |
549 | int queue; |
550 | unsigned int len; | |
d95b39c3 MC |
551 | struct cpmac_desc *desc; |
552 | struct cpmac_priv *priv = netdev_priv(dev); | |
553 | ||
f917d580 MC |
554 | if (unlikely(atomic_read(&priv->reset_pending))) |
555 | return NETDEV_TX_BUSY; | |
556 | ||
6cd043d9 MC |
557 | if (unlikely(skb_padto(skb, ETH_ZLEN))) |
558 | return NETDEV_TX_OK; | |
d95b39c3 | 559 | |
2f5281ba | 560 | len = max_t(unsigned int, skb->len, ETH_ZLEN); |
ba596a01 | 561 | queue = skb_get_queue_mapping(skb); |
d95b39c3 | 562 | netif_stop_subqueue(dev, queue); |
d95b39c3 MC |
563 | |
564 | desc = &priv->desc_ring[queue]; | |
565 | if (unlikely(desc->dataflags & CPMAC_OWN)) { | |
566 | if (netif_msg_tx_err(priv) && net_ratelimit()) | |
f160a2d0 VB |
567 | netdev_warn(dev, "tx dma ring full\n"); |
568 | ||
6cd043d9 | 569 | return NETDEV_TX_BUSY; |
d95b39c3 MC |
570 | } |
571 | ||
572 | spin_lock(&priv->lock); | |
d95b39c3 MC |
573 | spin_unlock(&priv->lock); |
574 | desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN; | |
575 | desc->skb = skb; | |
576 | desc->data_mapping = dma_map_single(&dev->dev, skb->data, len, | |
577 | DMA_TO_DEVICE); | |
578 | desc->hw_data = (u32)desc->data_mapping; | |
579 | desc->datalen = len; | |
580 | desc->buflen = len; | |
581 | if (unlikely(netif_msg_tx_queued(priv))) | |
f160a2d0 | 582 | netdev_dbg(dev, "sending 0x%p, len=%d\n", skb, skb->len); |
d95b39c3 MC |
583 | if (unlikely(netif_msg_hw(priv))) |
584 | cpmac_dump_desc(dev, desc); | |
585 | if (unlikely(netif_msg_pktdata(priv))) | |
586 | cpmac_dump_skb(dev, skb); | |
587 | cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping); | |
588 | ||
6cd043d9 | 589 | return NETDEV_TX_OK; |
d95b39c3 MC |
590 | } |
591 | ||
592 | static void cpmac_end_xmit(struct net_device *dev, int queue) | |
593 | { | |
594 | struct cpmac_desc *desc; | |
595 | struct cpmac_priv *priv = netdev_priv(dev); | |
596 | ||
597 | desc = &priv->desc_ring[queue]; | |
598 | cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping); | |
599 | if (likely(desc->skb)) { | |
600 | spin_lock(&priv->lock); | |
601 | dev->stats.tx_packets++; | |
602 | dev->stats.tx_bytes += desc->skb->len; | |
603 | spin_unlock(&priv->lock); | |
604 | dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len, | |
605 | DMA_TO_DEVICE); | |
606 | ||
607 | if (unlikely(netif_msg_tx_done(priv))) | |
f160a2d0 VB |
608 | netdev_dbg(dev, "sent 0x%p, len=%d\n", |
609 | desc->skb, desc->skb->len); | |
d95b39c3 MC |
610 | |
611 | dev_kfree_skb_irq(desc->skb); | |
612 | desc->skb = NULL; | |
0220ff7f | 613 | if (__netif_subqueue_stopped(dev, queue)) |
d95b39c3 | 614 | netif_wake_subqueue(dev, queue); |
d95b39c3 MC |
615 | } else { |
616 | if (netif_msg_tx_err(priv) && net_ratelimit()) | |
f160a2d0 | 617 | netdev_warn(dev, "end_xmit: spurious interrupt\n"); |
0220ff7f | 618 | if (__netif_subqueue_stopped(dev, queue)) |
d95b39c3 | 619 | netif_wake_subqueue(dev, queue); |
d95b39c3 MC |
620 | } |
621 | } | |
622 | ||
623 | static void cpmac_hw_stop(struct net_device *dev) | |
624 | { | |
625 | int i; | |
626 | struct cpmac_priv *priv = netdev_priv(dev); | |
a0ea2ac8 | 627 | struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev); |
d95b39c3 MC |
628 | |
629 | ar7_device_reset(pdata->reset_bit); | |
630 | cpmac_write(priv->regs, CPMAC_RX_CONTROL, | |
631 | cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1); | |
632 | cpmac_write(priv->regs, CPMAC_TX_CONTROL, | |
633 | cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1); | |
634 | for (i = 0; i < 8; i++) { | |
635 | cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0); | |
636 | cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0); | |
637 | } | |
638 | cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff); | |
639 | cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff); | |
640 | cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff); | |
641 | cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff); | |
642 | cpmac_write(priv->regs, CPMAC_MAC_CONTROL, | |
643 | cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII); | |
644 | } | |
645 | ||
646 | static void cpmac_hw_start(struct net_device *dev) | |
647 | { | |
648 | int i; | |
649 | struct cpmac_priv *priv = netdev_priv(dev); | |
a0ea2ac8 | 650 | struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev); |
d95b39c3 MC |
651 | |
652 | ar7_device_reset(pdata->reset_bit); | |
653 | for (i = 0; i < 8; i++) { | |
654 | cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0); | |
655 | cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0); | |
656 | } | |
657 | cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping); | |
658 | ||
659 | cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST | | |
660 | MBP_RXMCAST); | |
661 | cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0); | |
662 | for (i = 0; i < 8; i++) | |
663 | cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]); | |
664 | cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]); | |
665 | cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] | | |
666 | (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) | | |
667 | (dev->dev_addr[3] << 24)); | |
668 | cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE); | |
669 | cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff); | |
670 | cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff); | |
671 | cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff); | |
672 | cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff); | |
673 | cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1); | |
674 | cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1); | |
675 | cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff); | |
676 | cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3); | |
677 | ||
678 | cpmac_write(priv->regs, CPMAC_RX_CONTROL, | |
679 | cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1); | |
680 | cpmac_write(priv->regs, CPMAC_TX_CONTROL, | |
681 | cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1); | |
682 | cpmac_write(priv->regs, CPMAC_MAC_CONTROL, | |
683 | cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII | | |
684 | MAC_FDX); | |
685 | } | |
686 | ||
687 | static void cpmac_clear_rx(struct net_device *dev) | |
688 | { | |
689 | struct cpmac_priv *priv = netdev_priv(dev); | |
690 | struct cpmac_desc *desc; | |
691 | int i; | |
59329d8b | 692 | |
d95b39c3 MC |
693 | if (unlikely(!priv->rx_head)) |
694 | return; | |
695 | desc = priv->rx_head; | |
696 | for (i = 0; i < priv->ring_size; i++) { | |
697 | if ((desc->dataflags & CPMAC_OWN) == 0) { | |
698 | if (netif_msg_rx_err(priv) && net_ratelimit()) | |
f160a2d0 | 699 | netdev_warn(dev, "packet dropped\n"); |
d95b39c3 MC |
700 | if (unlikely(netif_msg_hw(priv))) |
701 | cpmac_dump_desc(dev, desc); | |
702 | desc->dataflags = CPMAC_OWN; | |
703 | dev->stats.rx_dropped++; | |
704 | } | |
f917d580 | 705 | desc->hw_next = desc->next->mapping; |
d95b39c3 MC |
706 | desc = desc->next; |
707 | } | |
f917d580 | 708 | priv->rx_head->prev->hw_next = 0; |
d95b39c3 MC |
709 | } |
710 | ||
711 | static void cpmac_clear_tx(struct net_device *dev) | |
712 | { | |
713 | struct cpmac_priv *priv = netdev_priv(dev); | |
714 | int i; | |
59329d8b | 715 | |
d95b39c3 MC |
716 | if (unlikely(!priv->desc_ring)) |
717 | return; | |
6cd043d9 MC |
718 | for (i = 0; i < CPMAC_QUEUES; i++) { |
719 | priv->desc_ring[i].dataflags = 0; | |
d95b39c3 MC |
720 | if (priv->desc_ring[i].skb) { |
721 | dev_kfree_skb_any(priv->desc_ring[i].skb); | |
f917d580 | 722 | priv->desc_ring[i].skb = NULL; |
d95b39c3 | 723 | } |
6cd043d9 | 724 | } |
d95b39c3 MC |
725 | } |
726 | ||
727 | static void cpmac_hw_error(struct work_struct *work) | |
728 | { | |
729 | struct cpmac_priv *priv = | |
730 | container_of(work, struct cpmac_priv, reset_work); | |
731 | ||
732 | spin_lock(&priv->rx_lock); | |
733 | cpmac_clear_rx(priv->dev); | |
734 | spin_unlock(&priv->rx_lock); | |
735 | cpmac_clear_tx(priv->dev); | |
736 | cpmac_hw_start(priv->dev); | |
f917d580 MC |
737 | barrier(); |
738 | atomic_dec(&priv->reset_pending); | |
739 | ||
fd2ea0a7 | 740 | netif_tx_wake_all_queues(priv->dev); |
f917d580 MC |
741 | cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3); |
742 | } | |
743 | ||
744 | static void cpmac_check_status(struct net_device *dev) | |
745 | { | |
746 | struct cpmac_priv *priv = netdev_priv(dev); | |
747 | ||
748 | u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS); | |
749 | int rx_channel = (macstatus >> 8) & 7; | |
750 | int rx_code = (macstatus >> 12) & 15; | |
751 | int tx_channel = (macstatus >> 16) & 7; | |
752 | int tx_code = (macstatus >> 20) & 15; | |
753 | ||
754 | if (rx_code || tx_code) { | |
755 | if (netif_msg_drv(priv) && net_ratelimit()) { | |
756 | /* Can't find any documentation on what these | |
8bcd5c6d | 757 | * error codes actually are. So just log them and hope.. |
f917d580 MC |
758 | */ |
759 | if (rx_code) | |
f160a2d0 VB |
760 | netdev_warn(dev, "host error %d on rx " |
761 | "channel %d (macstatus %08x), resetting\n", | |
762 | rx_code, rx_channel, macstatus); | |
f917d580 | 763 | if (tx_code) |
f160a2d0 VB |
764 | netdev_warn(dev, "host error %d on tx " |
765 | "channel %d (macstatus %08x), resetting\n", | |
766 | tx_code, tx_channel, macstatus); | |
f917d580 MC |
767 | } |
768 | ||
fd2ea0a7 | 769 | netif_tx_stop_all_queues(dev); |
f917d580 MC |
770 | cpmac_hw_stop(dev); |
771 | if (schedule_work(&priv->reset_work)) | |
772 | atomic_inc(&priv->reset_pending); | |
773 | if (unlikely(netif_msg_hw(priv))) | |
774 | cpmac_dump_regs(dev); | |
775 | } | |
776 | cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff); | |
d95b39c3 MC |
777 | } |
778 | ||
779 | static irqreturn_t cpmac_irq(int irq, void *dev_id) | |
780 | { | |
781 | struct net_device *dev = dev_id; | |
782 | struct cpmac_priv *priv; | |
783 | int queue; | |
784 | u32 status; | |
785 | ||
d95b39c3 MC |
786 | priv = netdev_priv(dev); |
787 | ||
788 | status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR); | |
789 | ||
790 | if (unlikely(netif_msg_intr(priv))) | |
f160a2d0 | 791 | netdev_dbg(dev, "interrupt status: 0x%08x\n", status); |
d95b39c3 MC |
792 | |
793 | if (status & MAC_INT_TX) | |
794 | cpmac_end_xmit(dev, (status & 7)); | |
795 | ||
796 | if (status & MAC_INT_RX) { | |
797 | queue = (status >> 8) & 7; | |
288379f0 | 798 | if (napi_schedule_prep(&priv->napi)) { |
67d129d1 | 799 | cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue); |
288379f0 | 800 | __napi_schedule(&priv->napi); |
67d129d1 | 801 | } |
d95b39c3 MC |
802 | } |
803 | ||
804 | cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0); | |
805 | ||
f917d580 MC |
806 | if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS))) |
807 | cpmac_check_status(dev); | |
d95b39c3 MC |
808 | |
809 | return IRQ_HANDLED; | |
810 | } | |
811 | ||
812 | static void cpmac_tx_timeout(struct net_device *dev) | |
813 | { | |
f917d580 | 814 | struct cpmac_priv *priv = netdev_priv(dev); |
d95b39c3 MC |
815 | |
816 | spin_lock(&priv->lock); | |
817 | dev->stats.tx_errors++; | |
818 | spin_unlock(&priv->lock); | |
819 | if (netif_msg_tx_err(priv) && net_ratelimit()) | |
f160a2d0 | 820 | netdev_warn(dev, "transmit timeout\n"); |
f917d580 MC |
821 | |
822 | atomic_inc(&priv->reset_pending); | |
823 | barrier(); | |
824 | cpmac_clear_tx(dev); | |
825 | barrier(); | |
826 | atomic_dec(&priv->reset_pending); | |
827 | ||
fd2ea0a7 | 828 | netif_tx_wake_all_queues(priv->dev); |
d95b39c3 MC |
829 | } |
830 | ||
831 | static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
832 | { | |
d95b39c3 MC |
833 | if (!(netif_running(dev))) |
834 | return -EINVAL; | |
b401a9bc | 835 | if (!dev->phydev) |
d95b39c3 | 836 | return -EINVAL; |
d95b39c3 | 837 | |
b401a9bc | 838 | return phy_mii_ioctl(dev->phydev, ifr, cmd); |
d95b39c3 MC |
839 | } |
840 | ||
559764d1 FF |
841 | static void cpmac_get_ringparam(struct net_device *dev, |
842 | struct ethtool_ringparam *ring) | |
d95b39c3 MC |
843 | { |
844 | struct cpmac_priv *priv = netdev_priv(dev); | |
845 | ||
846 | ring->rx_max_pending = 1024; | |
847 | ring->rx_mini_max_pending = 1; | |
848 | ring->rx_jumbo_max_pending = 1; | |
849 | ring->tx_max_pending = 1; | |
850 | ||
851 | ring->rx_pending = priv->ring_size; | |
852 | ring->rx_mini_pending = 1; | |
853 | ring->rx_jumbo_pending = 1; | |
854 | ring->tx_pending = 1; | |
855 | } | |
856 | ||
559764d1 FF |
857 | static int cpmac_set_ringparam(struct net_device *dev, |
858 | struct ethtool_ringparam *ring) | |
d95b39c3 MC |
859 | { |
860 | struct cpmac_priv *priv = netdev_priv(dev); | |
861 | ||
6cd043d9 | 862 | if (netif_running(dev)) |
d95b39c3 MC |
863 | return -EBUSY; |
864 | priv->ring_size = ring->rx_pending; | |
55064efd | 865 | |
d95b39c3 MC |
866 | return 0; |
867 | } | |
868 | ||
869 | static void cpmac_get_drvinfo(struct net_device *dev, | |
870 | struct ethtool_drvinfo *info) | |
871 | { | |
7826d43f JP |
872 | strlcpy(info->driver, "cpmac", sizeof(info->driver)); |
873 | strlcpy(info->version, CPMAC_VERSION, sizeof(info->version)); | |
874 | snprintf(info->bus_info, sizeof(info->bus_info), "%s", "cpmac"); | |
d95b39c3 MC |
875 | } |
876 | ||
877 | static const struct ethtool_ops cpmac_ethtool_ops = { | |
d95b39c3 MC |
878 | .get_drvinfo = cpmac_get_drvinfo, |
879 | .get_link = ethtool_op_get_link, | |
880 | .get_ringparam = cpmac_get_ringparam, | |
881 | .set_ringparam = cpmac_set_ringparam, | |
7dc09934 PR |
882 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
883 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
d95b39c3 MC |
884 | }; |
885 | ||
886 | static void cpmac_adjust_link(struct net_device *dev) | |
887 | { | |
888 | struct cpmac_priv *priv = netdev_priv(dev); | |
889 | int new_state = 0; | |
890 | ||
891 | spin_lock(&priv->lock); | |
b401a9bc | 892 | if (dev->phydev->link) { |
fd2ea0a7 | 893 | netif_tx_start_all_queues(dev); |
b401a9bc | 894 | if (dev->phydev->duplex != priv->oldduplex) { |
d95b39c3 | 895 | new_state = 1; |
b401a9bc | 896 | priv->oldduplex = dev->phydev->duplex; |
d95b39c3 MC |
897 | } |
898 | ||
b401a9bc | 899 | if (dev->phydev->speed != priv->oldspeed) { |
d95b39c3 | 900 | new_state = 1; |
b401a9bc | 901 | priv->oldspeed = dev->phydev->speed; |
d95b39c3 MC |
902 | } |
903 | ||
904 | if (!priv->oldlink) { | |
905 | new_state = 1; | |
906 | priv->oldlink = 1; | |
d95b39c3 MC |
907 | } |
908 | } else if (priv->oldlink) { | |
d95b39c3 MC |
909 | new_state = 1; |
910 | priv->oldlink = 0; | |
911 | priv->oldspeed = 0; | |
912 | priv->oldduplex = -1; | |
913 | } | |
914 | ||
915 | if (new_state && netif_msg_link(priv) && net_ratelimit()) | |
b401a9bc | 916 | phy_print_status(dev->phydev); |
d95b39c3 MC |
917 | |
918 | spin_unlock(&priv->lock); | |
919 | } | |
920 | ||
921 | static int cpmac_open(struct net_device *dev) | |
922 | { | |
923 | int i, size, res; | |
924 | struct cpmac_priv *priv = netdev_priv(dev); | |
925 | struct resource *mem; | |
926 | struct cpmac_desc *desc; | |
927 | struct sk_buff *skb; | |
928 | ||
d95b39c3 | 929 | mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs"); |
7e307c7a | 930 | if (!request_mem_region(mem->start, resource_size(mem), dev->name)) { |
d95b39c3 | 931 | if (netif_msg_drv(priv)) |
f160a2d0 VB |
932 | netdev_err(dev, "failed to request registers\n"); |
933 | ||
d95b39c3 MC |
934 | res = -ENXIO; |
935 | goto fail_reserve; | |
936 | } | |
937 | ||
7e307c7a | 938 | priv->regs = ioremap(mem->start, resource_size(mem)); |
d95b39c3 MC |
939 | if (!priv->regs) { |
940 | if (netif_msg_drv(priv)) | |
f160a2d0 VB |
941 | netdev_err(dev, "failed to remap registers\n"); |
942 | ||
d95b39c3 MC |
943 | res = -ENXIO; |
944 | goto fail_remap; | |
945 | } | |
946 | ||
947 | size = priv->ring_size + CPMAC_QUEUES; | |
948 | priv->desc_ring = dma_alloc_coherent(&dev->dev, | |
949 | sizeof(struct cpmac_desc) * size, | |
950 | &priv->dma_ring, | |
951 | GFP_KERNEL); | |
952 | if (!priv->desc_ring) { | |
953 | res = -ENOMEM; | |
954 | goto fail_alloc; | |
955 | } | |
956 | ||
957 | for (i = 0; i < size; i++) | |
958 | priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i; | |
959 | ||
960 | priv->rx_head = &priv->desc_ring[CPMAC_QUEUES]; | |
961 | for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) { | |
89d71a66 | 962 | skb = netdev_alloc_skb_ip_align(dev, CPMAC_SKB_SIZE); |
d95b39c3 MC |
963 | if (unlikely(!skb)) { |
964 | res = -ENOMEM; | |
965 | goto fail_desc; | |
966 | } | |
d95b39c3 MC |
967 | desc->skb = skb; |
968 | desc->data_mapping = dma_map_single(&dev->dev, skb->data, | |
969 | CPMAC_SKB_SIZE, | |
970 | DMA_FROM_DEVICE); | |
971 | desc->hw_data = (u32)desc->data_mapping; | |
972 | desc->buflen = CPMAC_SKB_SIZE; | |
973 | desc->dataflags = CPMAC_OWN; | |
974 | desc->next = &priv->rx_head[(i + 1) % priv->ring_size]; | |
f917d580 | 975 | desc->next->prev = desc; |
d95b39c3 MC |
976 | desc->hw_next = (u32)desc->next->mapping; |
977 | } | |
978 | ||
f917d580 MC |
979 | priv->rx_head->prev->hw_next = (u32)0; |
980 | ||
559764d1 FF |
981 | res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED, dev->name, dev); |
982 | if (res) { | |
d95b39c3 | 983 | if (netif_msg_drv(priv)) |
f160a2d0 VB |
984 | netdev_err(dev, "failed to obtain irq\n"); |
985 | ||
d95b39c3 MC |
986 | goto fail_irq; |
987 | } | |
988 | ||
f917d580 | 989 | atomic_set(&priv->reset_pending, 0); |
d95b39c3 MC |
990 | INIT_WORK(&priv->reset_work, cpmac_hw_error); |
991 | cpmac_hw_start(dev); | |
992 | ||
67d129d1 | 993 | napi_enable(&priv->napi); |
b401a9bc PR |
994 | dev->phydev->state = PHY_CHANGELINK; |
995 | phy_start(dev->phydev); | |
d95b39c3 MC |
996 | |
997 | return 0; | |
998 | ||
999 | fail_irq: | |
1000 | fail_desc: | |
1001 | for (i = 0; i < priv->ring_size; i++) { | |
1002 | if (priv->rx_head[i].skb) { | |
1003 | dma_unmap_single(&dev->dev, | |
1004 | priv->rx_head[i].data_mapping, | |
1005 | CPMAC_SKB_SIZE, | |
1006 | DMA_FROM_DEVICE); | |
1007 | kfree_skb(priv->rx_head[i].skb); | |
1008 | } | |
1009 | } | |
731e6f00 CJ |
1010 | dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) * size, |
1011 | priv->desc_ring, priv->dma_ring); | |
1012 | ||
d95b39c3 | 1013 | fail_alloc: |
d95b39c3 MC |
1014 | iounmap(priv->regs); |
1015 | ||
1016 | fail_remap: | |
7e307c7a | 1017 | release_mem_region(mem->start, resource_size(mem)); |
d95b39c3 MC |
1018 | |
1019 | fail_reserve: | |
d95b39c3 MC |
1020 | return res; |
1021 | } | |
1022 | ||
1023 | static int cpmac_stop(struct net_device *dev) | |
1024 | { | |
1025 | int i; | |
1026 | struct cpmac_priv *priv = netdev_priv(dev); | |
1027 | struct resource *mem; | |
1028 | ||
fd2ea0a7 | 1029 | netif_tx_stop_all_queues(dev); |
d95b39c3 MC |
1030 | |
1031 | cancel_work_sync(&priv->reset_work); | |
67d129d1 | 1032 | napi_disable(&priv->napi); |
b401a9bc | 1033 | phy_stop(dev->phydev); |
d95b39c3 MC |
1034 | |
1035 | cpmac_hw_stop(dev); | |
1036 | ||
1037 | for (i = 0; i < 8; i++) | |
1038 | cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0); | |
1039 | cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0); | |
1040 | cpmac_write(priv->regs, CPMAC_MBP, 0); | |
1041 | ||
1042 | free_irq(dev->irq, dev); | |
1043 | iounmap(priv->regs); | |
1044 | mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs"); | |
7e307c7a | 1045 | release_mem_region(mem->start, resource_size(mem)); |
d95b39c3 MC |
1046 | priv->rx_head = &priv->desc_ring[CPMAC_QUEUES]; |
1047 | for (i = 0; i < priv->ring_size; i++) { | |
1048 | if (priv->rx_head[i].skb) { | |
1049 | dma_unmap_single(&dev->dev, | |
1050 | priv->rx_head[i].data_mapping, | |
1051 | CPMAC_SKB_SIZE, | |
1052 | DMA_FROM_DEVICE); | |
1053 | kfree_skb(priv->rx_head[i].skb); | |
1054 | } | |
1055 | } | |
1056 | ||
1057 | dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) * | |
1058 | (CPMAC_QUEUES + priv->ring_size), | |
1059 | priv->desc_ring, priv->dma_ring); | |
55064efd | 1060 | |
d95b39c3 MC |
1061 | return 0; |
1062 | } | |
1063 | ||
63ef7d89 AB |
1064 | static const struct net_device_ops cpmac_netdev_ops = { |
1065 | .ndo_open = cpmac_open, | |
1066 | .ndo_stop = cpmac_stop, | |
1067 | .ndo_start_xmit = cpmac_start_xmit, | |
1068 | .ndo_tx_timeout = cpmac_tx_timeout, | |
afc4b13d | 1069 | .ndo_set_rx_mode = cpmac_set_multicast_list, |
6a9b6546 | 1070 | .ndo_do_ioctl = cpmac_ioctl, |
63ef7d89 AB |
1071 | .ndo_validate_addr = eth_validate_addr, |
1072 | .ndo_set_mac_address = eth_mac_addr, | |
1073 | }; | |
1074 | ||
d95b39c3 MC |
1075 | static int external_switch; |
1076 | ||
f57ae66e | 1077 | static int cpmac_probe(struct platform_device *pdev) |
d95b39c3 | 1078 | { |
69bd4ae5 | 1079 | int rc, phy_id; |
762c6aa1 | 1080 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
d95b39c3 MC |
1081 | struct resource *mem; |
1082 | struct cpmac_priv *priv; | |
1083 | struct net_device *dev; | |
1084 | struct plat_cpmac_data *pdata; | |
b401a9bc | 1085 | struct phy_device *phydev = NULL; |
d95b39c3 | 1086 | |
a0ea2ac8 | 1087 | pdata = dev_get_platdata(&pdev->dev); |
d95b39c3 | 1088 | |
76e61eaa | 1089 | if (external_switch || dumb_switch) { |
a19c5d68 | 1090 | strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */ |
76e61eaa FF |
1091 | phy_id = pdev->id; |
1092 | } else { | |
1093 | for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) { | |
1094 | if (!(pdata->phy_mask & (1 << phy_id))) | |
1095 | continue; | |
3c6396d6 | 1096 | if (!mdiobus_get_phy(cpmac_mii, phy_id)) |
76e61eaa | 1097 | continue; |
762c6aa1 | 1098 | strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE); |
76e61eaa FF |
1099 | break; |
1100 | } | |
d95b39c3 MC |
1101 | } |
1102 | ||
1103 | if (phy_id == PHY_MAX_ADDR) { | |
559764d1 | 1104 | dev_err(&pdev->dev, "no PHY present, falling back " |
f160a2d0 | 1105 | "to switch on MDIO bus 0\n"); |
a19c5d68 | 1106 | strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */ |
9fba1c31 | 1107 | phy_id = pdev->id; |
d95b39c3 | 1108 | } |
9951e048 | 1109 | mdio_bus_id[sizeof(mdio_bus_id) - 1] = '\0'; |
d95b39c3 MC |
1110 | |
1111 | dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES); | |
41de8d4c | 1112 | if (!dev) |
d95b39c3 | 1113 | return -ENOMEM; |
d95b39c3 | 1114 | |
5579f28c | 1115 | SET_NETDEV_DEV(dev, &pdev->dev); |
d95b39c3 MC |
1116 | platform_set_drvdata(pdev, dev); |
1117 | priv = netdev_priv(dev); | |
1118 | ||
1119 | priv->pdev = pdev; | |
1120 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); | |
1121 | if (!mem) { | |
1122 | rc = -ENODEV; | |
09714275 | 1123 | goto fail; |
d95b39c3 MC |
1124 | } |
1125 | ||
1126 | dev->irq = platform_get_irq_byname(pdev, "irq"); | |
1127 | ||
63ef7d89 AB |
1128 | dev->netdev_ops = &cpmac_netdev_ops; |
1129 | dev->ethtool_ops = &cpmac_ethtool_ops; | |
d95b39c3 | 1130 | |
67d129d1 EK |
1131 | netif_napi_add(dev, &priv->napi, cpmac_poll, 64); |
1132 | ||
d95b39c3 MC |
1133 | spin_lock_init(&priv->lock); |
1134 | spin_lock_init(&priv->rx_lock); | |
1135 | priv->dev = dev; | |
1136 | priv->ring_size = 64; | |
1137 | priv->msg_enable = netif_msg_init(debug_level, 0xff); | |
2447f2f3 | 1138 | memcpy(dev->dev_addr, pdata->dev_addr, sizeof(pdata->dev_addr)); |
b88219f8 | 1139 | |
559764d1 FF |
1140 | snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, |
1141 | mdio_bus_id, phy_id); | |
76e61eaa | 1142 | |
b401a9bc PR |
1143 | phydev = phy_connect(dev, priv->phy_name, cpmac_adjust_link, |
1144 | PHY_INTERFACE_MODE_MII); | |
76e61eaa | 1145 | |
b401a9bc | 1146 | if (IS_ERR(phydev)) { |
b88219f8 | 1147 | if (netif_msg_drv(priv)) |
f160a2d0 VB |
1148 | dev_err(&pdev->dev, "Could not attach to PHY\n"); |
1149 | ||
b401a9bc | 1150 | rc = PTR_ERR(phydev); |
09714275 | 1151 | goto fail; |
b88219f8 | 1152 | } |
d95b39c3 | 1153 | |
559764d1 FF |
1154 | rc = register_netdev(dev); |
1155 | if (rc) { | |
f160a2d0 | 1156 | dev_err(&pdev->dev, "Could not register net device\n"); |
d95b39c3 MC |
1157 | goto fail; |
1158 | } | |
1159 | ||
1160 | if (netif_msg_probe(priv)) { | |
f160a2d0 VB |
1161 | dev_info(&pdev->dev, "regs: %p, irq: %d, phy: %s, " |
1162 | "mac: %pM\n", (void *)mem->start, dev->irq, | |
1163 | priv->phy_name, dev->dev_addr); | |
d95b39c3 | 1164 | } |
55064efd | 1165 | |
d95b39c3 MC |
1166 | return 0; |
1167 | ||
1168 | fail: | |
1169 | free_netdev(dev); | |
1170 | return rc; | |
1171 | } | |
1172 | ||
f57ae66e | 1173 | static int cpmac_remove(struct platform_device *pdev) |
d95b39c3 MC |
1174 | { |
1175 | struct net_device *dev = platform_get_drvdata(pdev); | |
59329d8b | 1176 | |
d95b39c3 MC |
1177 | unregister_netdev(dev); |
1178 | free_netdev(dev); | |
55064efd | 1179 | |
d95b39c3 MC |
1180 | return 0; |
1181 | } | |
1182 | ||
1183 | static struct platform_driver cpmac_driver = { | |
96a8d3c1 VB |
1184 | .driver = { |
1185 | .name = "cpmac", | |
96a8d3c1 VB |
1186 | }, |
1187 | .probe = cpmac_probe, | |
f57ae66e | 1188 | .remove = cpmac_remove, |
d95b39c3 MC |
1189 | }; |
1190 | ||
f57ae66e | 1191 | int cpmac_init(void) |
d95b39c3 MC |
1192 | { |
1193 | u32 mask; | |
1194 | int i, res; | |
1195 | ||
298cf9be LB |
1196 | cpmac_mii = mdiobus_alloc(); |
1197 | if (cpmac_mii == NULL) | |
1198 | return -ENOMEM; | |
1199 | ||
1200 | cpmac_mii->name = "cpmac-mii"; | |
1201 | cpmac_mii->read = cpmac_mdio_read; | |
1202 | cpmac_mii->write = cpmac_mdio_write; | |
1203 | cpmac_mii->reset = cpmac_mdio_reset; | |
298cf9be LB |
1204 | |
1205 | cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256); | |
d95b39c3 | 1206 | |
298cf9be | 1207 | if (!cpmac_mii->priv) { |
f160a2d0 | 1208 | pr_err("Can't ioremap mdio registers\n"); |
298cf9be LB |
1209 | res = -ENXIO; |
1210 | goto fail_alloc; | |
d95b39c3 MC |
1211 | } |
1212 | ||
1213 | #warning FIXME: unhardcode gpio&reset bits | |
1214 | ar7_gpio_disable(26); | |
1215 | ar7_gpio_disable(27); | |
1216 | ar7_device_reset(AR7_RESET_BIT_CPMAC_LO); | |
1217 | ar7_device_reset(AR7_RESET_BIT_CPMAC_HI); | |
1218 | ar7_device_reset(AR7_RESET_BIT_EPHY); | |
1219 | ||
298cf9be | 1220 | cpmac_mii->reset(cpmac_mii); |
d95b39c3 | 1221 | |
559764d1 FF |
1222 | for (i = 0; i < 300; i++) { |
1223 | mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE); | |
1224 | if (mask) | |
d95b39c3 MC |
1225 | break; |
1226 | else | |
e4540aa9 | 1227 | msleep(10); |
559764d1 | 1228 | } |
d95b39c3 MC |
1229 | |
1230 | mask &= 0x7fffffff; | |
1231 | if (mask & (mask - 1)) { | |
1232 | external_switch = 1; | |
1233 | mask = 0; | |
1234 | } | |
1235 | ||
298cf9be | 1236 | cpmac_mii->phy_mask = ~(mask | 0x80000000); |
d1733f07 | 1237 | snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "cpmac-1"); |
d95b39c3 | 1238 | |
298cf9be | 1239 | res = mdiobus_register(cpmac_mii); |
d95b39c3 MC |
1240 | if (res) |
1241 | goto fail_mii; | |
1242 | ||
1243 | res = platform_driver_register(&cpmac_driver); | |
1244 | if (res) | |
1245 | goto fail_cpmac; | |
1246 | ||
1247 | return 0; | |
1248 | ||
1249 | fail_cpmac: | |
298cf9be | 1250 | mdiobus_unregister(cpmac_mii); |
d95b39c3 MC |
1251 | |
1252 | fail_mii: | |
298cf9be LB |
1253 | iounmap(cpmac_mii->priv); |
1254 | ||
1255 | fail_alloc: | |
1256 | mdiobus_free(cpmac_mii); | |
d95b39c3 MC |
1257 | |
1258 | return res; | |
1259 | } | |
1260 | ||
f57ae66e | 1261 | void cpmac_exit(void) |
d95b39c3 MC |
1262 | { |
1263 | platform_driver_unregister(&cpmac_driver); | |
298cf9be | 1264 | mdiobus_unregister(cpmac_mii); |
298cf9be | 1265 | iounmap(cpmac_mii->priv); |
48a29516 | 1266 | mdiobus_free(cpmac_mii); |
d95b39c3 MC |
1267 | } |
1268 | ||
1269 | module_init(cpmac_init); | |
1270 | module_exit(cpmac_exit); |