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net: ethernet: ti: Use PTR_ERR_OR_ZERO() to simplify code
[linux-2.6-block.git] / drivers / net / ethernet / ti / am65-cpts.c
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f6bd5952
GS		 1// SPDX-License-Identifier: GPL-2.0
2/* TI K3 AM65x Common Platform Time Sync
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
5 *
6 */
7
8#include <linux/clk.h>
9#include <linux/clk-provider.h>
10#include <linux/err.h>
11#include <linux/if_vlan.h>
12#include <linux/interrupt.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/net_tstamp.h>
16#include <linux/of.h>
17#include <linux/of_irq.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/ptp_classify.h>
21#include <linux/ptp_clock_kernel.h>
22
23#include "am65-cpts.h"
24
25struct am65_genf_regs {
26 u32 comp_lo; /* Comparison Low Value 0:31 */
27 u32 comp_hi; /* Comparison High Value 32:63 */
28 u32 control; /* control */
29 u32 length; /* Length */
30 u32 ppm_low; /* PPM Load Low Value 0:31 */
31 u32 ppm_hi; /* PPM Load High Value 32:63 */
32 u32 ts_nudge; /* Nudge value */
33} __aligned(32) __packed;
34
35#define AM65_CPTS_GENF_MAX_NUM 9
36#define AM65_CPTS_ESTF_MAX_NUM 8
37
38struct am65_cpts_regs {
39 u32 idver; /* Identification and version */
40 u32 control; /* Time sync control */
41 u32 rftclk_sel; /* Reference Clock Select Register */
42 u32 ts_push; /* Time stamp event push */
43 u32 ts_load_val_lo; /* Time Stamp Load Low Value 0:31 */
44 u32 ts_load_en; /* Time stamp load enable */
45 u32 ts_comp_lo; /* Time Stamp Comparison Low Value 0:31 */
46 u32 ts_comp_length; /* Time Stamp Comparison Length */
47 u32 intstat_raw; /* Time sync interrupt status raw */
48 u32 intstat_masked; /* Time sync interrupt status masked */
49 u32 int_enable; /* Time sync interrupt enable */
50 u32 ts_comp_nudge; /* Time Stamp Comparison Nudge Value */
51 u32 event_pop; /* Event interrupt pop */
52 u32 event_0; /* Event Time Stamp lo 0:31 */
53 u32 event_1; /* Event Type Fields */
54 u32 event_2; /* Event Type Fields domain */
55 u32 event_3; /* Event Time Stamp hi 32:63 */
56 u32 ts_load_val_hi; /* Time Stamp Load High Value 32:63 */
57 u32 ts_comp_hi; /* Time Stamp Comparison High Value 32:63 */
58 u32 ts_add_val; /* Time Stamp Add value */
59 u32 ts_ppm_low; /* Time Stamp PPM Load Low Value 0:31 */
60 u32 ts_ppm_hi; /* Time Stamp PPM Load High Value 32:63 */
61 u32 ts_nudge; /* Time Stamp Nudge value */
62 u32 reserv[33];
63 struct am65_genf_regs genf[AM65_CPTS_GENF_MAX_NUM];
64 struct am65_genf_regs estf[AM65_CPTS_ESTF_MAX_NUM];
65};
66
67/* CONTROL_REG */
68#define AM65_CPTS_CONTROL_EN BIT(0)
69#define AM65_CPTS_CONTROL_INT_TEST BIT(1)
70#define AM65_CPTS_CONTROL_TS_COMP_POLARITY BIT(2)
71#define AM65_CPTS_CONTROL_TSTAMP_EN BIT(3)
72#define AM65_CPTS_CONTROL_SEQUENCE_EN BIT(4)
73#define AM65_CPTS_CONTROL_64MODE BIT(5)
74#define AM65_CPTS_CONTROL_TS_COMP_TOG BIT(6)
75#define AM65_CPTS_CONTROL_TS_PPM_DIR BIT(7)
76#define AM65_CPTS_CONTROL_HW1_TS_PUSH_EN BIT(8)
77#define AM65_CPTS_CONTROL_HW2_TS_PUSH_EN BIT(9)
78#define AM65_CPTS_CONTROL_HW3_TS_PUSH_EN BIT(10)
79#define AM65_CPTS_CONTROL_HW4_TS_PUSH_EN BIT(11)
80#define AM65_CPTS_CONTROL_HW5_TS_PUSH_EN BIT(12)
81#define AM65_CPTS_CONTROL_HW6_TS_PUSH_EN BIT(13)
82#define AM65_CPTS_CONTROL_HW7_TS_PUSH_EN BIT(14)
83#define AM65_CPTS_CONTROL_HW8_TS_PUSH_EN BIT(15)
84#define AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET (8)
85
86#define AM65_CPTS_CONTROL_TS_SYNC_SEL_MASK (0xF)
87#define AM65_CPTS_CONTROL_TS_SYNC_SEL_SHIFT (28)
88
89/* RFTCLK_SEL_REG */
90#define AM65_CPTS_RFTCLK_SEL_MASK (0x1F)
91
92/* TS_PUSH_REG */
93#define AM65_CPTS_TS_PUSH BIT(0)
94
95/* TS_LOAD_EN_REG */
96#define AM65_CPTS_TS_LOAD_EN BIT(0)
97
98/* INTSTAT_RAW_REG */
99#define AM65_CPTS_INTSTAT_RAW_TS_PEND BIT(0)
100
101/* INTSTAT_MASKED_REG */
102#define AM65_CPTS_INTSTAT_MASKED_TS_PEND BIT(0)
103
104/* INT_ENABLE_REG */
105#define AM65_CPTS_INT_ENABLE_TS_PEND_EN BIT(0)
106
107/* TS_COMP_NUDGE_REG */
108#define AM65_CPTS_TS_COMP_NUDGE_MASK (0xFF)
109
110/* EVENT_POP_REG */
111#define AM65_CPTS_EVENT_POP BIT(0)
112
113/* EVENT_1_REG */
114#define AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK GENMASK(15, 0)
115
116#define AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK GENMASK(19, 16)
117#define AM65_CPTS_EVENT_1_MESSAGE_TYPE_SHIFT (16)
118
119#define AM65_CPTS_EVENT_1_EVENT_TYPE_MASK GENMASK(23, 20)
120#define AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT (20)
121
122#define AM65_CPTS_EVENT_1_PORT_NUMBER_MASK GENMASK(28, 24)
123#define AM65_CPTS_EVENT_1_PORT_NUMBER_SHIFT (24)
124
125/* EVENT_2_REG */
126#define AM65_CPTS_EVENT_2_REG_DOMAIN_MASK (0xFF)
127#define AM65_CPTS_EVENT_2_REG_DOMAIN_SHIFT (0)
128
129enum {
130 AM65_CPTS_EV_PUSH, /* Time Stamp Push Event */
131 AM65_CPTS_EV_ROLL, /* Time Stamp Rollover Event */
132 AM65_CPTS_EV_HALF, /* Time Stamp Half Rollover Event */
133 AM65_CPTS_EV_HW, /* Hardware Time Stamp Push Event */
134 AM65_CPTS_EV_RX, /* Ethernet Receive Event */
135 AM65_CPTS_EV_TX, /* Ethernet Transmit Event */
136 AM65_CPTS_EV_TS_COMP, /* Time Stamp Compare Event */
137 AM65_CPTS_EV_HOST, /* Host Transmit Event */
138};
139
140struct am65_cpts_event {
141 struct list_head list;
142 unsigned long tmo;
143 u32 event1;
144 u32 event2;
145 u64 timestamp;
146};
147
148#define AM65_CPTS_FIFO_DEPTH (16)
149#define AM65_CPTS_MAX_EVENTS (32)
150#define AM65_CPTS_EVENT_RX_TX_TIMEOUT (20) /* ms */
151#define AM65_CPTS_SKB_TX_WORK_TIMEOUT 1 /* jiffies */
152#define AM65_CPTS_MIN_PPM 0x400
153
154struct am65_cpts {
155 struct device *dev;
156 struct am65_cpts_regs __iomem *reg;
157 struct ptp_clock_info ptp_info;
158 struct ptp_clock *ptp_clock;
159 int phc_index;
160 struct clk_hw *clk_mux_hw;
161 struct device_node *clk_mux_np;
162 struct clk *refclk;
163 u32 refclk_freq;
164 struct list_head events;
165 struct list_head pool;
166 struct am65_cpts_event pool_data[AM65_CPTS_MAX_EVENTS];
167 spinlock_t lock; /* protects events lists*/
168 u32 ext_ts_inputs;
169 u32 genf_num;
170 u32 ts_add_val;
171 int irq;
172 struct mutex ptp_clk_lock; /* PHC access sync */
173 u64 timestamp;
174 u32 genf_enable;
175 u32 hw_ts_enable;
176 struct sk_buff_head txq;
177};
178
179struct am65_cpts_skb_cb_data {
180 unsigned long tmo;
181 u32 skb_mtype_seqid;
182};
183
184#define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r)
185#define am65_cpts_read32(c, r) readl(&(c)->reg->r)
186
187static void am65_cpts_settime(struct am65_cpts *cpts, u64 start_tstamp)
188{
189 u32 val;
190
191 val = upper_32_bits(start_tstamp);
192 am65_cpts_write32(cpts, val, ts_load_val_hi);
193 val = lower_32_bits(start_tstamp);
194 am65_cpts_write32(cpts, val, ts_load_val_lo);
195
196 am65_cpts_write32(cpts, AM65_CPTS_TS_LOAD_EN, ts_load_en);
197}
198
199static void am65_cpts_set_add_val(struct am65_cpts *cpts)
200{
201 /* select coefficient according to the rate */
202 cpts->ts_add_val = (NSEC_PER_SEC / cpts->refclk_freq - 1) & 0x7;
203
204 am65_cpts_write32(cpts, cpts->ts_add_val, ts_add_val);
205}
206
207static void am65_cpts_disable(struct am65_cpts *cpts)
208{
209 am65_cpts_write32(cpts, 0, control);
210 am65_cpts_write32(cpts, 0, int_enable);
211}
212
213static int am65_cpts_event_get_port(struct am65_cpts_event *event)
214{
215 return (event->event1 & AM65_CPTS_EVENT_1_PORT_NUMBER_MASK) >>
216 AM65_CPTS_EVENT_1_PORT_NUMBER_SHIFT;
217}
218
219static int am65_cpts_event_get_type(struct am65_cpts_event *event)
220{
221 return (event->event1 & AM65_CPTS_EVENT_1_EVENT_TYPE_MASK) >>
222 AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT;
223}
224
225static int am65_cpts_cpts_purge_events(struct am65_cpts *cpts)
226{
227 struct list_head *this, *next;
228 struct am65_cpts_event *event;
229 int removed = 0;
230
231 list_for_each_safe(this, next, &cpts->events) {
232 event = list_entry(this, struct am65_cpts_event, list);
233 if (time_after(jiffies, event->tmo)) {
234 list_del_init(&event->list);
235 list_add(&event->list, &cpts->pool);
236 ++removed;
237 }
238 }
239
240 if (removed)
241 dev_dbg(cpts->dev, "event pool cleaned up %d\n", removed);
242 return removed ? 0 : -1;
243}
244
245static bool am65_cpts_fifo_pop_event(struct am65_cpts *cpts,
246 struct am65_cpts_event *event)
247{
248 u32 r = am65_cpts_read32(cpts, intstat_raw);
249
250 if (r & AM65_CPTS_INTSTAT_RAW_TS_PEND) {
251 event->timestamp = am65_cpts_read32(cpts, event_0);
252 event->event1 = am65_cpts_read32(cpts, event_1);
253 event->event2 = am65_cpts_read32(cpts, event_2);
254 event->timestamp |= (u64)am65_cpts_read32(cpts, event_3) << 32;
255 am65_cpts_write32(cpts, AM65_CPTS_EVENT_POP, event_pop);
256 return false;
257 }
258 return true;
259}
260
261static int am65_cpts_fifo_read(struct am65_cpts *cpts)
262{
263 struct ptp_clock_event pevent;
264 struct am65_cpts_event *event;
265 bool schedule = false;
266 int i, type, ret = 0;
267 unsigned long flags;
268
269 spin_lock_irqsave(&cpts->lock, flags);
270 for (i = 0; i < AM65_CPTS_FIFO_DEPTH; i++) {
271 event = list_first_entry_or_null(&cpts->pool,
272 struct am65_cpts_event, list);
273
274 if (!event) {
275 if (am65_cpts_cpts_purge_events(cpts)) {
276 dev_err(cpts->dev, "cpts: event pool empty\n");
277 ret = -1;
278 goto out;
279 }
280 continue;
281 }
282
283 if (am65_cpts_fifo_pop_event(cpts, event))
284 break;
285
286 type = am65_cpts_event_get_type(event);
287 switch (type) {
288 case AM65_CPTS_EV_PUSH:
289 cpts->timestamp = event->timestamp;
290 dev_dbg(cpts->dev, "AM65_CPTS_EV_PUSH t:%llu\n",
291 cpts->timestamp);
292 break;
293 case AM65_CPTS_EV_RX:
294 case AM65_CPTS_EV_TX:
295 event->tmo = jiffies +
296 msecs_to_jiffies(AM65_CPTS_EVENT_RX_TX_TIMEOUT);
297
298 list_del_init(&event->list);
299 list_add_tail(&event->list, &cpts->events);
300
301 dev_dbg(cpts->dev,
302 "AM65_CPTS_EV_TX e1:%08x e2:%08x t:%lld\n",
303 event->event1, event->event2,
304 event->timestamp);
305 schedule = true;
306 break;
307 case AM65_CPTS_EV_HW:
308 pevent.index = am65_cpts_event_get_port(event) - 1;
309 pevent.timestamp = event->timestamp;
310 pevent.type = PTP_CLOCK_EXTTS;
311 dev_dbg(cpts->dev, "AM65_CPTS_EV_HW p:%d t:%llu\n",
312 pevent.index, event->timestamp);
313
314 ptp_clock_event(cpts->ptp_clock, &pevent);
315 break;
316 case AM65_CPTS_EV_HOST:
317 break;
318 case AM65_CPTS_EV_ROLL:
319 case AM65_CPTS_EV_HALF:
320 case AM65_CPTS_EV_TS_COMP:
321 dev_dbg(cpts->dev,
322 "AM65_CPTS_EVT: %d e1:%08x e2:%08x t:%lld\n",
323 type,
324 event->event1, event->event2,
325 event->timestamp);
326 break;
327 default:
328 dev_err(cpts->dev, "cpts: unknown event type\n");
329 ret = -1;
330 goto out;
331 }
332 }
333
334out:
335 spin_unlock_irqrestore(&cpts->lock, flags);
336
337 if (schedule)
338 ptp_schedule_worker(cpts->ptp_clock, 0);
339
340 return ret;
341}
342
343static u64 am65_cpts_gettime(struct am65_cpts *cpts,
344 struct ptp_system_timestamp *sts)
345{
346 unsigned long flags;
347 u64 val = 0;
348
349 /* temporarily disable cpts interrupt to avoid intentional
350 * doubled read. Interrupt can be in-flight - it's Ok.
351 */
352 am65_cpts_write32(cpts, 0, int_enable);
353
354 /* use spin_lock_irqsave() here as it has to run very fast */
355 spin_lock_irqsave(&cpts->lock, flags);
356 ptp_read_system_prets(sts);
357 am65_cpts_write32(cpts, AM65_CPTS_TS_PUSH, ts_push);
358 am65_cpts_read32(cpts, ts_push);
359 ptp_read_system_postts(sts);
360 spin_unlock_irqrestore(&cpts->lock, flags);
361
362 am65_cpts_fifo_read(cpts);
363
364 am65_cpts_write32(cpts, AM65_CPTS_INT_ENABLE_TS_PEND_EN, int_enable);
365
366 val = cpts->timestamp;
367
368 return val;
369}
370
371static irqreturn_t am65_cpts_interrupt(int irq, void *dev_id)
372{
373 struct am65_cpts *cpts = dev_id;
374
375 if (am65_cpts_fifo_read(cpts))
376 dev_dbg(cpts->dev, "cpts: unable to obtain a time stamp\n");
377
378 return IRQ_HANDLED;
379}
380
381/* PTP clock operations */
382static int am65_cpts_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
383{
384 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
385 int neg_adj = 0;
386 u64 adj_period;
387 u32 val;
388
389 if (ppb < 0) {
390 neg_adj = 1;
391 ppb = -ppb;
392 }
393
394 /* base freq = 1GHz = 1 000 000 000
395 * ppb_norm = ppb * base_freq / clock_freq;
396 * ppm_norm = ppb_norm / 1000
397 * adj_period = 1 000 000 / ppm_norm
398 * adj_period = 1 000 000 000 / ppb_norm
399 * adj_period = 1 000 000 000 / (ppb * base_freq / clock_freq)
400 * adj_period = (1 000 000 000 * clock_freq) / (ppb * base_freq)
401 * adj_period = clock_freq / ppb
402 */
403 adj_period = div_u64(cpts->refclk_freq, ppb);
404
405 mutex_lock(&cpts->ptp_clk_lock);
406
407 val = am65_cpts_read32(cpts, control);
408 if (neg_adj)
409 val |= AM65_CPTS_CONTROL_TS_PPM_DIR;
410 else
411 val &= ~AM65_CPTS_CONTROL_TS_PPM_DIR;
412 am65_cpts_write32(cpts, val, control);
413
414 val = upper_32_bits(adj_period) & 0x3FF;
415 am65_cpts_write32(cpts, val, ts_ppm_hi);
416 val = lower_32_bits(adj_period);
417 am65_cpts_write32(cpts, val, ts_ppm_low);
418
419 mutex_unlock(&cpts->ptp_clk_lock);
420
421 return 0;
422}
423
424static int am65_cpts_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
425{
426 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
427 s64 ns;
428
429 mutex_lock(&cpts->ptp_clk_lock);
430 ns = am65_cpts_gettime(cpts, NULL);
431 ns += delta;
432 am65_cpts_settime(cpts, ns);
433 mutex_unlock(&cpts->ptp_clk_lock);
434
435 return 0;
436}
437
438static int am65_cpts_ptp_gettimex(struct ptp_clock_info *ptp,
439 struct timespec64 *ts,
440 struct ptp_system_timestamp *sts)
441{
442 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
443 u64 ns;
444
445 mutex_lock(&cpts->ptp_clk_lock);
446 ns = am65_cpts_gettime(cpts, sts);
447 mutex_unlock(&cpts->ptp_clk_lock);
448 *ts = ns_to_timespec64(ns);
449
450 return 0;
451}
452
453static int am65_cpts_ptp_settime(struct ptp_clock_info *ptp,
454 const struct timespec64 *ts)
455{
456 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
457 u64 ns;
458
459 ns = timespec64_to_ns(ts);
460 mutex_lock(&cpts->ptp_clk_lock);
461 am65_cpts_settime(cpts, ns);
462 mutex_unlock(&cpts->ptp_clk_lock);
463
464 return 0;
465}
466
467static void am65_cpts_extts_enable_hw(struct am65_cpts *cpts, u32 index, int on)
468{
469 u32 v;
470
471 v = am65_cpts_read32(cpts, control);
472 if (on) {
473 v |= BIT(AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET + index);
474 cpts->hw_ts_enable |= BIT(index);
475 } else {
476 v &= ~BIT(AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET + index);
477 cpts->hw_ts_enable &= ~BIT(index);
478 }
479 am65_cpts_write32(cpts, v, control);
480}
481
482static int am65_cpts_extts_enable(struct am65_cpts *cpts, u32 index, int on)
483{
484 if (!!(cpts->hw_ts_enable & BIT(index)) == !!on)
485 return 0;
486
487 mutex_lock(&cpts->ptp_clk_lock);
488 am65_cpts_extts_enable_hw(cpts, index, on);
489 mutex_unlock(&cpts->ptp_clk_lock);
490
491 dev_dbg(cpts->dev, "%s: ExtTS:%u %s\n",
492 __func__, index, on ? "enabled" : "disabled");
493
494 return 0;
495}
496
497static void am65_cpts_perout_enable_hw(struct am65_cpts *cpts,
498 struct ptp_perout_request *req, int on)
499{
500 u64 ns_period, ns_start, cycles;
501 struct timespec64 ts;
502 u32 val;
503
504 if (on) {
505 ts.tv_sec = req->period.sec;
506 ts.tv_nsec = req->period.nsec;
507 ns_period = timespec64_to_ns(&ts);
508
509 cycles = (ns_period * cpts->refclk_freq) / NSEC_PER_SEC;
510
511 ts.tv_sec = req->start.sec;
512 ts.tv_nsec = req->start.nsec;
513 ns_start = timespec64_to_ns(&ts);
514
515 val = upper_32_bits(ns_start);
516 am65_cpts_write32(cpts, val, genf[req->index].comp_hi);
517 val = lower_32_bits(ns_start);
518 am65_cpts_write32(cpts, val, genf[req->index].comp_lo);
519 val = lower_32_bits(cycles);
520 am65_cpts_write32(cpts, val, genf[req->index].length);
521
522 cpts->genf_enable |= BIT(req->index);
523 } else {
524 am65_cpts_write32(cpts, 0, genf[req->index].length);
525
526 cpts->genf_enable &= ~BIT(req->index);
527 }
528}
529
530static int am65_cpts_perout_enable(struct am65_cpts *cpts,
531 struct ptp_perout_request *req, int on)
532{
533 if (!!(cpts->genf_enable & BIT(req->index)) == !!on)
534 return 0;
535
536 mutex_lock(&cpts->ptp_clk_lock);
537 am65_cpts_perout_enable_hw(cpts, req, on);
538 mutex_unlock(&cpts->ptp_clk_lock);
539
540 dev_dbg(cpts->dev, "%s: GenF:%u %s\n",
541 __func__, req->index, on ? "enabled" : "disabled");
542
543 return 0;
544}
545
546static int am65_cpts_ptp_enable(struct ptp_clock_info *ptp,
547 struct ptp_clock_request *rq, int on)
548{
549 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
550
551 switch (rq->type) {
552 case PTP_CLK_REQ_EXTTS:
553 return am65_cpts_extts_enable(cpts, rq->extts.index, on);
554 case PTP_CLK_REQ_PEROUT:
555 return am65_cpts_perout_enable(cpts, &rq->perout, on);
556 default:
557 break;
558 }
559
560 return -EOPNOTSUPP;
561}
562
563static long am65_cpts_ts_work(struct ptp_clock_info *ptp);
564
565static struct ptp_clock_info am65_ptp_info = {
566 .owner = THIS_MODULE,
567 .name = "CTPS timer",
568 .adjfreq = am65_cpts_ptp_adjfreq,
569 .adjtime = am65_cpts_ptp_adjtime,
570 .gettimex64 = am65_cpts_ptp_gettimex,
571 .settime64 = am65_cpts_ptp_settime,
572 .enable = am65_cpts_ptp_enable,
573 .do_aux_work = am65_cpts_ts_work,
574};
575
576static bool am65_cpts_match_tx_ts(struct am65_cpts *cpts,
577 struct am65_cpts_event *event)
578{
579 struct sk_buff_head txq_list;
580 struct sk_buff *skb, *tmp;
581 unsigned long flags;
582 bool found = false;
583 u32 mtype_seqid;
584
585 mtype_seqid = event->event1 &
586 (AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK |
587 AM65_CPTS_EVENT_1_EVENT_TYPE_MASK |
588 AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK);
589
590 __skb_queue_head_init(&txq_list);
591
592 spin_lock_irqsave(&cpts->txq.lock, flags);
593 skb_queue_splice_init(&cpts->txq, &txq_list);
594 spin_unlock_irqrestore(&cpts->txq.lock, flags);
595
596 /* no need to grab txq.lock as access is always done under cpts->lock */
597 skb_queue_walk_safe(&txq_list, skb, tmp) {
598 struct skb_shared_hwtstamps ssh;
599 struct am65_cpts_skb_cb_data *skb_cb =
600 (struct am65_cpts_skb_cb_data *)skb->cb;
601
602 if (mtype_seqid == skb_cb->skb_mtype_seqid) {
603 u64 ns = event->timestamp;
604
605 memset(&ssh, 0, sizeof(ssh));
606 ssh.hwtstamp = ns_to_ktime(ns);
607 skb_tstamp_tx(skb, &ssh);
608 found = true;
609 __skb_unlink(skb, &txq_list);
610 dev_consume_skb_any(skb);
611 dev_dbg(cpts->dev,
612 "match tx timestamp mtype_seqid %08x\n",
613 mtype_seqid);
614 break;
615 }
616
617 if (time_after(jiffies, skb_cb->tmo)) {
618 /* timeout any expired skbs over 100 ms */
619 dev_dbg(cpts->dev,
620 "expiring tx timestamp mtype_seqid %08x\n",
621 mtype_seqid);
622 __skb_unlink(skb, &txq_list);
623 dev_consume_skb_any(skb);
624 }
625 }
626
627 spin_lock_irqsave(&cpts->txq.lock, flags);
628 skb_queue_splice(&txq_list, &cpts->txq);
629 spin_unlock_irqrestore(&cpts->txq.lock, flags);
630
631 return found;
632}
633
634static void am65_cpts_find_ts(struct am65_cpts *cpts)
635{
636 struct am65_cpts_event *event;
637 struct list_head *this, *next;
638 LIST_HEAD(events_free);
639 unsigned long flags;
640 LIST_HEAD(events);
641
642 spin_lock_irqsave(&cpts->lock, flags);
643 list_splice_init(&cpts->events, &events);
644 spin_unlock_irqrestore(&cpts->lock, flags);
645
646 list_for_each_safe(this, next, &events) {
647 event = list_entry(this, struct am65_cpts_event, list);
648 if (am65_cpts_match_tx_ts(cpts, event) ||
649 time_after(jiffies, event->tmo)) {
650 list_del_init(&event->list);
651 list_add(&event->list, &events_free);
652 }
653 }
654
655 spin_lock_irqsave(&cpts->lock, flags);
656 list_splice_tail(&events, &cpts->events);
657 list_splice_tail(&events_free, &cpts->pool);
658 spin_unlock_irqrestore(&cpts->lock, flags);
659}
660
661static long am65_cpts_ts_work(struct ptp_clock_info *ptp)
662{
663 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
664 unsigned long flags;
665 long delay = -1;
666
667 am65_cpts_find_ts(cpts);
668
669 spin_lock_irqsave(&cpts->txq.lock, flags);
670 if (!skb_queue_empty(&cpts->txq))
671 delay = AM65_CPTS_SKB_TX_WORK_TIMEOUT;
672 spin_unlock_irqrestore(&cpts->txq.lock, flags);
673
674 return delay;
675}
676
677/**
678 * am65_cpts_rx_enable - enable rx timestamping
679 * @cpts: cpts handle
680 * @skb: packet
681 *
682 * This functions enables rx packets timestamping. The CPTS can timestamp all
683 * rx packets.
684 */
685void am65_cpts_rx_enable(struct am65_cpts *cpts, bool en)
686{
687 u32 val;
688
689 mutex_lock(&cpts->ptp_clk_lock);
690 val = am65_cpts_read32(cpts, control);
691 if (en)
692 val |= AM65_CPTS_CONTROL_TSTAMP_EN;
693 else
694 val &= ~AM65_CPTS_CONTROL_TSTAMP_EN;
695 am65_cpts_write32(cpts, val, control);
696 mutex_unlock(&cpts->ptp_clk_lock);
697}
698EXPORT_SYMBOL_GPL(am65_cpts_rx_enable);
699
700static int am65_skb_get_mtype_seqid(struct sk_buff *skb, u32 *mtype_seqid)
701{
702 unsigned int ptp_class = ptp_classify_raw(skb);
703 u8 *msgtype, *data = skb->data;
704 unsigned int offset = 0;
705 __be16 *seqid;
706
707 if (ptp_class == PTP_CLASS_NONE)
708 return 0;
709
710 if (ptp_class & PTP_CLASS_VLAN)
711 offset += VLAN_HLEN;
712
713 switch (ptp_class & PTP_CLASS_PMASK) {
714 case PTP_CLASS_IPV4:
715 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
716 break;
717 case PTP_CLASS_IPV6:
718 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
719 break;
720 case PTP_CLASS_L2:
721 offset += ETH_HLEN;
722 break;
723 default:
724 return 0;
725 }
726
727 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
728 return 0;
729
730 if (unlikely(ptp_class & PTP_CLASS_V1))
731 msgtype = data + offset + OFF_PTP_CONTROL;
732 else
733 msgtype = data + offset;
734
735 seqid = (__be16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
736 *mtype_seqid = (*msgtype << AM65_CPTS_EVENT_1_MESSAGE_TYPE_SHIFT) &
737 AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK;
738 *mtype_seqid |= (ntohs(*seqid) & AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK);
739
740 return 1;
741}
742
743/**
744 * am65_cpts_tx_timestamp - save tx packet for timestamping
745 * @cpts: cpts handle
746 * @skb: packet
747 *
748 * This functions saves tx packet for timestamping if packet can be timestamped.
749 * The future processing is done in from PTP auxiliary worker.
750 */
751void am65_cpts_tx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb)
752{
753 struct am65_cpts_skb_cb_data *skb_cb = (void *)skb->cb;
754
755 if (!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
756 return;
757
758 /* add frame to queue for processing later.
759 * The periodic FIFO check will handle this.
760 */
761 skb_get(skb);
762 /* get the timestamp for timeouts */
763 skb_cb->tmo = jiffies + msecs_to_jiffies(100);
764 skb_queue_tail(&cpts->txq, skb);
765 ptp_schedule_worker(cpts->ptp_clock, 0);
766}
767EXPORT_SYMBOL_GPL(am65_cpts_tx_timestamp);
768
769/**
770 * am65_cpts_prep_tx_timestamp - check and prepare tx packet for timestamping
771 * @cpts: cpts handle
772 * @skb: packet
773 *
774 * This functions should be called from .xmit().
775 * It checks if packet can be timestamped, fills internal cpts data
776 * in skb-cb and marks packet as SKBTX_IN_PROGRESS.
777 */
778void am65_cpts_prep_tx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb)
779{
780 struct am65_cpts_skb_cb_data *skb_cb = (void *)skb->cb;
781 int ret;
782
783 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
784 return;
785
786 ret = am65_skb_get_mtype_seqid(skb, &skb_cb->skb_mtype_seqid);
787 if (!ret)
788 return;
789 skb_cb->skb_mtype_seqid |= (AM65_CPTS_EV_TX <<
790 AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT);
791
792 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
793}
794EXPORT_SYMBOL_GPL(am65_cpts_prep_tx_timestamp);
795
796int am65_cpts_phc_index(struct am65_cpts *cpts)
797{
798 return cpts->phc_index;
799}
800EXPORT_SYMBOL_GPL(am65_cpts_phc_index);
801
802static void cpts_free_clk_mux(void *data)
803{
804 struct am65_cpts *cpts = data;
805
806 of_clk_del_provider(cpts->clk_mux_np);
807 clk_hw_unregister_mux(cpts->clk_mux_hw);
808 of_node_put(cpts->clk_mux_np);
809}
810
811static int cpts_of_mux_clk_setup(struct am65_cpts *cpts,
812 struct device_node *node)
813{
814 unsigned int num_parents;
815 const char **parent_names;
816 char *clk_mux_name;
817 void __iomem *reg;
818 int ret = -EINVAL;
819
820 cpts->clk_mux_np = of_get_child_by_name(node, "refclk-mux");
821 if (!cpts->clk_mux_np)
822 return 0;
823
824 num_parents = of_clk_get_parent_count(cpts->clk_mux_np);
825 if (num_parents < 1) {
826 dev_err(cpts->dev, "mux-clock %pOF must have parents\n",
827 cpts->clk_mux_np);
828 goto mux_fail;
829 }
830
831 parent_names = devm_kcalloc(cpts->dev, sizeof(char *), num_parents,
832 GFP_KERNEL);
833 if (!parent_names) {
834 ret = -ENOMEM;
835 goto mux_fail;
836 }
837
838 of_clk_parent_fill(cpts->clk_mux_np, parent_names, num_parents);
839
840 clk_mux_name = devm_kasprintf(cpts->dev, GFP_KERNEL, "%s.%pOFn",
841 dev_name(cpts->dev), cpts->clk_mux_np);
842 if (!clk_mux_name) {
843 ret = -ENOMEM;
844 goto mux_fail;
845 }
846
847 reg = &cpts->reg->rftclk_sel;
848 /* dev must be NULL to avoid recursive incrementing
849 * of module refcnt
850 */
851 cpts->clk_mux_hw = clk_hw_register_mux(NULL, clk_mux_name,
852 parent_names, num_parents,
853 0, reg, 0, 5, 0, NULL);
854 if (IS_ERR(cpts->clk_mux_hw)) {
855 ret = PTR_ERR(cpts->clk_mux_hw);
856 goto mux_fail;
857 }
858
859 ret = of_clk_add_hw_provider(cpts->clk_mux_np, of_clk_hw_simple_get,
860 cpts->clk_mux_hw);
861 if (ret)
862 goto clk_hw_register;
863
864 ret = devm_add_action_or_reset(cpts->dev, cpts_free_clk_mux, cpts);
865 if (ret)
866 dev_err(cpts->dev, "failed to add clkmux reset action %d", ret);
867
868 return ret;
869
870clk_hw_register:
871 clk_hw_unregister_mux(cpts->clk_mux_hw);
872mux_fail:
873 of_node_put(cpts->clk_mux_np);
874 return ret;
875}
876
877static int am65_cpts_of_parse(struct am65_cpts *cpts, struct device_node *node)
878{
879 u32 prop[2];
880
881 if (!of_property_read_u32(node, "ti,cpts-ext-ts-inputs", &prop[0]))
882 cpts->ext_ts_inputs = prop[0];
883
884 if (!of_property_read_u32(node, "ti,cpts-periodic-outputs", &prop[0]))
885 cpts->genf_num = prop[0];
886
887 return cpts_of_mux_clk_setup(cpts, node);
888}
889
890static void am65_cpts_release(void *data)
891{
892 struct am65_cpts *cpts = data;
893
894 ptp_clock_unregister(cpts->ptp_clock);
895 am65_cpts_disable(cpts);
896 clk_disable_unprepare(cpts->refclk);
897}
898
899struct am65_cpts *am65_cpts_create(struct device *dev, void __iomem *regs,
900 struct device_node *node)
901{
902 struct am65_cpts *cpts;
903 int ret, i;
904
905 cpts = devm_kzalloc(dev, sizeof(*cpts), GFP_KERNEL);
906 if (!cpts)
907 return ERR_PTR(-ENOMEM);
908
909 cpts->dev = dev;
910 cpts->reg = (struct am65_cpts_regs __iomem *)regs;
911
912 cpts->irq = of_irq_get_byname(node, "cpts");
913 if (cpts->irq <= 0) {
914 ret = cpts->irq ?: -ENXIO;
915 if (ret != -EPROBE_DEFER)
916 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
917 ret);
918 return ERR_PTR(ret);
919 }
920
921 ret = am65_cpts_of_parse(cpts, node);
922 if (ret)
923 return ERR_PTR(ret);
924
925 mutex_init(&cpts->ptp_clk_lock);
926 INIT_LIST_HEAD(&cpts->events);
927 INIT_LIST_HEAD(&cpts->pool);
928 spin_lock_init(&cpts->lock);
929 skb_queue_head_init(&cpts->txq);
930
931 for (i = 0; i < AM65_CPTS_MAX_EVENTS; i++)
932 list_add(&cpts->pool_data[i].list, &cpts->pool);
933
934 cpts->refclk = devm_get_clk_from_child(dev, node, "cpts");
935 if (IS_ERR(cpts->refclk)) {
936 ret = PTR_ERR(cpts->refclk);
937 if (ret != -EPROBE_DEFER)
938 dev_err(dev, "Failed to get refclk %d\n", ret);
939 return ERR_PTR(ret);
940 }
941
942 ret = clk_prepare_enable(cpts->refclk);
943 if (ret) {
944 dev_err(dev, "Failed to enable refclk %d\n", ret);
945 return ERR_PTR(ret);
946 }
947
948 cpts->refclk_freq = clk_get_rate(cpts->refclk);
949
950 am65_ptp_info.max_adj = cpts->refclk_freq / AM65_CPTS_MIN_PPM;
951 cpts->ptp_info = am65_ptp_info;
952
953 if (cpts->ext_ts_inputs)
954 cpts->ptp_info.n_ext_ts = cpts->ext_ts_inputs;
955 if (cpts->genf_num)
956 cpts->ptp_info.n_per_out = cpts->genf_num;
957
958 am65_cpts_set_add_val(cpts);
959
960 am65_cpts_write32(cpts, AM65_CPTS_CONTROL_EN | AM65_CPTS_CONTROL_64MODE,
961 control);
962 am65_cpts_write32(cpts, AM65_CPTS_INT_ENABLE_TS_PEND_EN, int_enable);
963
964 /* set time to the current system time */
965 am65_cpts_settime(cpts, ktime_to_ns(ktime_get_real()));
966
967 cpts->ptp_clock = ptp_clock_register(&cpts->ptp_info, cpts->dev);
968 if (IS_ERR_OR_NULL(cpts->ptp_clock)) {
969 dev_err(dev, "Failed to register ptp clk %ld\n",
970 PTR_ERR(cpts->ptp_clock));
971 if (!cpts->ptp_clock)
972 ret = -ENODEV;
973 goto refclk_disable;
974 }
975 cpts->phc_index = ptp_clock_index(cpts->ptp_clock);
976
977 ret = devm_add_action_or_reset(dev, am65_cpts_release, cpts);
978 if (ret) {
979 dev_err(dev, "failed to add ptpclk reset action %d", ret);
980 return ERR_PTR(ret);
981 }
982
983 ret = devm_request_threaded_irq(dev, cpts->irq, NULL,
984 am65_cpts_interrupt,
985 IRQF_ONESHOT, dev_name(dev), cpts);
986 if (ret < 0) {
987 dev_err(cpts->dev, "error attaching irq %d\n", ret);
988 return ERR_PTR(ret);
989 }
990
991 dev_info(dev, "CPTS ver 0x%08x, freq:%u, add_val:%u\n",
992 am65_cpts_read32(cpts, idver),
993 cpts->refclk_freq, cpts->ts_add_val);
994
995 return cpts;
996
997refclk_disable:
998 clk_disable_unprepare(cpts->refclk);
999 return ERR_PTR(ret);
1000}
1001EXPORT_SYMBOL_GPL(am65_cpts_create);
1002
1003static int am65_cpts_probe(struct platform_device *pdev)
1004{
1005 struct device_node *node = pdev->dev.of_node;
1006 struct device *dev = &pdev->dev;
1007 struct am65_cpts *cpts;
1008 struct resource *res;
1009 void __iomem *base;
1010
1011 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpts");
1012 base = devm_ioremap_resource(dev, res);
1013 if (IS_ERR(base))
1014 return PTR_ERR(base);
1015
1016 cpts = am65_cpts_create(dev, base, node);
bbae62e3 1017 return PTR_ERR_OR_ZERO(cpts);
f6bd5952
GS		 1018}
1019
1020static const struct of_device_id am65_cpts_of_match[] = {
1021 { .compatible = "ti,am65-cpts", },
1022 { .compatible = "ti,j721e-cpts", },
1023 {},
1024};
1025MODULE_DEVICE_TABLE(of, am65_cpts_of_match);
1026
1027static struct platform_driver am65_cpts_driver = {
1028 .probe = am65_cpts_probe,
1029 .driver = {
1030 .name = "am65-cpts",
1031 .of_match_table = am65_cpts_of_match,
1032 },
1033};
1034module_platform_driver(am65_cpts_driver);
1035
1036MODULE_LICENSE("GPL v2");
1037MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>");
1038MODULE_DESCRIPTION("TI K3 AM65 CPTS driver");
Linux 6.x block layer and io_uring tree(s)