[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_mdio.c

/*******************************************************************************
  STMMAC Ethernet Driver -- MDIO bus implementation
  Provides Bus interface for MII registers

  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Carl Shaw <carl.shaw@st.com>
  Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#include <linux/mii.h>
#include <linux/phy.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/of_mdio.h>
#include <asm/io.h>

#include "stmmac.h"

#define MII_BUSY 0x00000001
#define MII_WRITE 0x00000002

/* GMAC4 defines */
#define MII_GMAC4_GOC_SHIFT		2
#define MII_GMAC4_WRITE			(1 << MII_GMAC4_GOC_SHIFT)
#define MII_GMAC4_READ			(3 << MII_GMAC4_GOC_SHIFT)

#define MII_PHY_ADDR_GMAC4_SHIFT	21
#define MII_PHY_ADDR_GMAC4_MASK		GENMASK(25, 21)
#define MII_PHY_REG_GMAC4_SHIFT		16
#define MII_PHY_REG_GMAC4_MASK		GENMASK(20, 16)
#define MII_CSR_CLK_GMAC4_SHIFT		8
#define MII_CSR_CLK_GMAC4_MASK		GENMASK(11, 8)

static int stmmac_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_addr)
{
	unsigned long curr;
	unsigned long finish = jiffies + 3 * HZ;

	do {
		curr = jiffies;
		if (readl(ioaddr + mii_addr) & MII_BUSY)
			cpu_relax();
		else
			return 0;
	} while (!time_after_eq(curr, finish));

	return -EBUSY;
}

/**
 * stmmac_mdio_read
 * @bus: points to the mii_bus structure
 * @phyaddr: MII addr reg bits 15-11
 * @phyreg: MII addr reg bits 10-6
 * Description: it reads data from the MII register from within the phy device.
 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
 * accessing the PHY registers.
 * Fortunately, it seems this has no drawback for the 7109 MAC.
 */
static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
{
	struct net_device *ndev = bus->priv;
	struct stmmac_priv *priv = netdev_priv(ndev);
	unsigned int mii_address = priv->hw->mii.addr;
	unsigned int mii_data = priv->hw->mii.data;

	int data;
	u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
			((phyreg << 6) & (0x000007C0)));
	regValue |= MII_BUSY | ((priv->clk_csr & 0xF) << 2);

	if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
		return -EBUSY;

	writel(regValue, priv->ioaddr + mii_address);

	if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
		return -EBUSY;

	/* Read the data from the MII data register */
	data = (int)readl(priv->ioaddr + mii_data);

	return data;
}

/**
 * stmmac_mdio_write
 * @bus: points to the mii_bus structure
 * @phyaddr: MII addr reg bits 15-11
 * @phyreg: MII addr reg bits 10-6
 * @phydata: phy data
 * Description: it writes the data into the MII register from within the device.
 */
static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
			     u16 phydata)
{
	struct net_device *ndev = bus->priv;
	struct stmmac_priv *priv = netdev_priv(ndev);
	unsigned int mii_address = priv->hw->mii.addr;
	unsigned int mii_data = priv->hw->mii.data;

	u16 value =
	    (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
	    | MII_WRITE;

	value |= MII_BUSY | ((priv->clk_csr & 0xF) << 2);

	/* Wait until any existing MII operation is complete */
	if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
		return -EBUSY;

	/* Set the MII address register to write */
	writel(phydata, priv->ioaddr + mii_data);
	writel(value, priv->ioaddr + mii_address);

	/* Wait until any existing MII operation is complete */
	return stmmac_mdio_busy_wait(priv->ioaddr, mii_address);
}

/**
 * stmmac_mdio_read_gmac4
 * @bus: points to the mii_bus structure
 * @phyaddr: MII addr reg bits 25-21
 * @phyreg: MII addr reg bits 20-16
 * Description: it reads data from the MII register of GMAC4 from within
 * the phy device.
 */
static int stmmac_mdio_read_gmac4(struct mii_bus *bus, int phyaddr, int phyreg)
{
	struct net_device *ndev = bus->priv;
	struct stmmac_priv *priv = netdev_priv(ndev);
	unsigned int mii_address = priv->hw->mii.addr;
	unsigned int mii_data = priv->hw->mii.data;
	int data;
	u32 value = (((phyaddr << MII_PHY_ADDR_GMAC4_SHIFT) &
		     (MII_PHY_ADDR_GMAC4_MASK)) |
		     ((phyreg << MII_PHY_REG_GMAC4_SHIFT) &
		     (MII_PHY_REG_GMAC4_MASK))) | MII_GMAC4_READ;

	value |= MII_BUSY | ((priv->clk_csr & MII_CSR_CLK_GMAC4_MASK)
		 << MII_CSR_CLK_GMAC4_SHIFT);

	if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
		return -EBUSY;

	writel(value, priv->ioaddr + mii_address);

	if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
		return -EBUSY;

	/* Read the data from the MII data register */
	data = (int)readl(priv->ioaddr + mii_data);

	return data;
}

/**
 * stmmac_mdio_write_gmac4
 * @bus: points to the mii_bus structure
 * @phyaddr: MII addr reg bits 25-21
 * @phyreg: MII addr reg bits 20-16
 * @phydata: phy data
 * Description: it writes the data into the MII register of GMAC4 from within
 * the device.
 */
static int stmmac_mdio_write_gmac4(struct mii_bus *bus, int phyaddr, int phyreg,
				   u16 phydata)
{
	struct net_device *ndev = bus->priv;
	struct stmmac_priv *priv = netdev_priv(ndev);
	unsigned int mii_address = priv->hw->mii.addr;
	unsigned int mii_data = priv->hw->mii.data;

	u32 value = (((phyaddr << MII_PHY_ADDR_GMAC4_SHIFT) &
		     (MII_PHY_ADDR_GMAC4_MASK)) |
		     ((phyreg << MII_PHY_REG_GMAC4_SHIFT) &
		     (MII_PHY_REG_GMAC4_MASK))) | MII_GMAC4_WRITE;

	value |= MII_BUSY | ((priv->clk_csr & MII_CSR_CLK_GMAC4_MASK)
		 << MII_CSR_CLK_GMAC4_SHIFT);

	/* Wait until any existing MII operation is complete */
	if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
		return -EBUSY;

	/* Set the MII address register to write */
	writel(phydata, priv->ioaddr + mii_data);
	writel(value, priv->ioaddr + mii_address);

	/* Wait until any existing MII operation is complete */
	return stmmac_mdio_busy_wait(priv->ioaddr, mii_address);
}

/**
 * stmmac_mdio_reset
 * @bus: points to the mii_bus structure
 * Description: reset the MII bus
 */
int stmmac_mdio_reset(struct mii_bus *bus)
{
#if defined(CONFIG_STMMAC_PLATFORM)
	struct net_device *ndev = bus->priv;
	struct stmmac_priv *priv = netdev_priv(ndev);
	unsigned int mii_address = priv->hw->mii.addr;
	struct stmmac_mdio_bus_data *data = priv->plat->mdio_bus_data;

#ifdef CONFIG_OF
	if (priv->device->of_node) {

		if (data->reset_gpio < 0) {
			struct device_node *np = priv->device->of_node;
			if (!np)
				return 0;

			data->reset_gpio = of_get_named_gpio(np,
						"snps,reset-gpio", 0);
			if (data->reset_gpio < 0)
				return 0;

			data->active_low = of_property_read_bool(np,
						"snps,reset-active-low");
			of_property_read_u32_array(np,
				"snps,reset-delays-us", data->delays, 3);

			if (gpio_request(data->reset_gpio, "mdio-reset"))
				return 0;
		}

		gpio_direction_output(data->reset_gpio,
				      data->active_low ? 1 : 0);
		if (data->delays[0])
			msleep(DIV_ROUND_UP(data->delays[0], 1000));

		gpio_set_value(data->reset_gpio, data->active_low ? 0 : 1);
		if (data->delays[1])
			msleep(DIV_ROUND_UP(data->delays[1], 1000));

		gpio_set_value(data->reset_gpio, data->active_low ? 1 : 0);
		if (data->delays[2])
			msleep(DIV_ROUND_UP(data->delays[2], 1000));
	}
#endif

	if (data->phy_reset) {
		pr_debug("stmmac_mdio_reset: calling phy_reset\n");
		data->phy_reset(priv->plat->bsp_priv);
	}

	/* This is a workaround for problems with the STE101P PHY.
	 * It doesn't complete its reset until at least one clock cycle
	 * on MDC, so perform a dummy mdio read. To be upadted for GMAC4
	 * if needed.
	 */
	if (!priv->plat->has_gmac4)
		writel(0, priv->ioaddr + mii_address);
#endif
	return 0;
}

/**
 * stmmac_mdio_register
 * @ndev: net device structure
 * Description: it registers the MII bus
 */
int stmmac_mdio_register(struct net_device *ndev)
{
	int err = 0;
	struct mii_bus *new_bus;
	struct stmmac_priv *priv = netdev_priv(ndev);
	struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
	struct device_node *mdio_node = priv->plat->mdio_node;
	int addr, found;

	if (!mdio_bus_data)
		return 0;

	new_bus = mdiobus_alloc();
	if (new_bus == NULL)
		return -ENOMEM;

	if (mdio_bus_data->irqs)
		memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq));

#ifdef CONFIG_OF
	if (priv->device->of_node)
		mdio_bus_data->reset_gpio = -1;
#endif

	new_bus->name = "stmmac";
	if (priv->plat->has_gmac4) {
		new_bus->read = &stmmac_mdio_read_gmac4;
		new_bus->write = &stmmac_mdio_write_gmac4;
	} else {
		new_bus->read = &stmmac_mdio_read;
		new_bus->write = &stmmac_mdio_write;
	}

	new_bus->reset = &stmmac_mdio_reset;
	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
		 new_bus->name, priv->plat->bus_id);
	new_bus->priv = ndev;
	new_bus->phy_mask = mdio_bus_data->phy_mask;
	new_bus->parent = priv->device;

	if (mdio_node)
		err = of_mdiobus_register(new_bus, mdio_node);
	else
		err = mdiobus_register(new_bus);
	if (err != 0) {
		pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
		goto bus_register_fail;
	}

	if (priv->plat->phy_node || mdio_node)
		goto bus_register_done;

	found = 0;
	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
		struct phy_device *phydev = mdiobus_get_phy(new_bus, addr);
		if (phydev) {
			int act = 0;
			char irq_num[4];
			char *irq_str;

			/*
			 * If an IRQ was provided to be assigned after
			 * the bus probe, do it here.
			 */
			if ((mdio_bus_data->irqs == NULL) &&
			    (mdio_bus_data->probed_phy_irq > 0)) {
				new_bus->irq[addr] =
					mdio_bus_data->probed_phy_irq;
				phydev->irq = mdio_bus_data->probed_phy_irq;
			}

			/*
			 * If we're going to bind the MAC to this PHY bus,
			 * and no PHY number was provided to the MAC,
			 * use the one probed here.
			 */
			if (priv->plat->phy_addr == -1)
				priv->plat->phy_addr = addr;

			act = (priv->plat->phy_addr == addr);
			switch (phydev->irq) {
			case PHY_POLL:
				irq_str = "POLL";
				break;
			case PHY_IGNORE_INTERRUPT:
				irq_str = "IGNORE";
				break;
			default:
				sprintf(irq_num, "%d", phydev->irq);
				irq_str = irq_num;
				break;
			}
			pr_info("%s: PHY ID %08x at %d IRQ %s (%s)%s\n",
				ndev->name, phydev->phy_id, addr,
				irq_str, phydev_name(phydev),
				act ? " active" : "");
			found = 1;
		}
	}

	if (!found && !mdio_node) {
		pr_warn("%s: No PHY found\n", ndev->name);
		mdiobus_unregister(new_bus);
		mdiobus_free(new_bus);
		return -ENODEV;
	}

bus_register_done:
	priv->mii = new_bus;

	return 0;

bus_register_fail:
	mdiobus_free(new_bus);
	return err;
}

/**
 * stmmac_mdio_unregister
 * @ndev: net device structure
 * Description: it unregisters the MII bus
 */
int stmmac_mdio_unregister(struct net_device *ndev)
{
	struct stmmac_priv *priv = netdev_priv(ndev);

	if (!priv->mii)
		return 0;

	mdiobus_unregister(priv->mii);
	priv->mii->priv = NULL;
	mdiobus_free(priv->mii);
	priv->mii = NULL;

	return 0;
}
Commit	Line	Data
47dd7a54 GC	1	/*******************************************************************************
	2	STMMAC Ethernet Driver -- MDIO bus implementation
	3	Provides Bus interface for MII registers
	4
	5	Copyright (C) 2007-2009 STMicroelectronics Ltd
	6
	7	This program is free software; you can redistribute it and/or modify it
	8	under the terms and conditions of the GNU General Public License,
	9	version 2, as published by the Free Software Foundation.
	10
	11	This program is distributed in the hope it will be useful, but WITHOUT
	12	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	more details.
	15
	16	You should have received a copy of the GNU General Public License along with
	17	this program; if not, write to the Free Software Foundation, Inc.,
	18	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19
	20	The full GNU General Public License is included in this distribution in
	21	the file called "COPYING".
	22
	23	Author: Carl Shaw <carl.shaw@st.com>
	24	Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	25	*******************************************************************************/
	26
47dd7a54 GC	27	#include <linux/mii.h>
47dd7a54 GC	28	#include <linux/phy.h>
5a0e3ad6	29	#include <linux/slab.h>
0e076471 SK	30	#include <linux/of.h>
0e076471 SK	31	#include <linux/of_gpio.h>
e34d6569	32	#include <linux/of_mdio.h>
b7f080cf	33	#include <asm/io.h>
47dd7a54 GC	34
	35	#include "stmmac.h"
	36
	37	#define MII_BUSY 0x00000001
	38	#define MII_WRITE 0x00000002
	39
ac1f74a7 AT	40	/* GMAC4 defines */
	41	#define MII_GMAC4_GOC_SHIFT 2
	42	#define MII_GMAC4_WRITE (1 << MII_GMAC4_GOC_SHIFT)
	43	#define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT)
	44
	45	#define MII_PHY_ADDR_GMAC4_SHIFT 21
	46	#define MII_PHY_ADDR_GMAC4_MASK GENMASK(25, 21)
	47	#define MII_PHY_REG_GMAC4_SHIFT 16
	48	#define MII_PHY_REG_GMAC4_MASK GENMASK(20, 16)
	49	#define MII_CSR_CLK_GMAC4_SHIFT 8
	50	#define MII_CSR_CLK_GMAC4_MASK GENMASK(11, 8)
	51
39b401db DS	52	static int stmmac_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_addr)
	53	{
	54	unsigned long curr;
	55	unsigned long finish = jiffies + 3 * HZ;
	56
	57	do {
	58	curr = jiffies;
	59	if (readl(ioaddr + mii_addr) & MII_BUSY)
	60	cpu_relax();
	61	else
	62	return 0;
	63	} while (!time_after_eq(curr, finish));
	64
	65	return -EBUSY;
	66	}
	67
47dd7a54 GC	68	/**
	69	* stmmac_mdio_read
	70	* @bus: points to the mii_bus structure
	71	* @phyaddr: MII addr reg bits 15-11
	72	* @phyreg: MII addr reg bits 10-6
	73	* Description: it reads data from the MII register from within the phy device.
	74	* For the 7111 GMAC, we must set the bit 0 in the MII address register while
	75	* accessing the PHY registers.
	76	* Fortunately, it seems this has no drawback for the 7109 MAC.
	77	*/
	78	static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
	79	{
	80	struct net_device *ndev = bus->priv;
	81	struct stmmac_priv *priv = netdev_priv(ndev);
db98a0b0 GC	82	unsigned int mii_address = priv->hw->mii.addr;
db98a0b0 GC	83	unsigned int mii_data = priv->hw->mii.data;
47dd7a54 GC	84
	85	int data;
	86	u16 regValue = (((phyaddr << 11) & (0x0000F800)) \|
	87	((phyreg << 6) & (0x000007C0)));
cd7201f4	88	regValue \|= MII_BUSY \| ((priv->clk_csr & 0xF) << 2);
47dd7a54	89
39b401db DS	90	if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
	91	return -EBUSY;
	92
ad01b7d4	93	writel(regValue, priv->ioaddr + mii_address);
39b401db DS	94
	95	if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
	96	return -EBUSY;
47dd7a54 GC	97
47dd7a54 GC	98	/* Read the data from the MII data register */
ad01b7d4	99	data = (int)readl(priv->ioaddr + mii_data);
47dd7a54 GC	100
	101	return data;
	102	}
	103
	104	/**
	105	* stmmac_mdio_write
	106	* @bus: points to the mii_bus structure
	107	* @phyaddr: MII addr reg bits 15-11
	108	* @phyreg: MII addr reg bits 10-6
	109	* @phydata: phy data
	110	* Description: it writes the data into the MII register from within the device.
	111	*/
	112	static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
	113	u16 phydata)
	114	{
	115	struct net_device *ndev = bus->priv;
	116	struct stmmac_priv *priv = netdev_priv(ndev);
db98a0b0 GC	117	unsigned int mii_address = priv->hw->mii.addr;
db98a0b0 GC	118	unsigned int mii_data = priv->hw->mii.data;
47dd7a54 GC	119
	120	u16 value =
	121	(((phyaddr << 11) & (0x0000F800)) \| ((phyreg << 6) & (0x000007C0)))
	122	\| MII_WRITE;
	123
cd7201f4	124	value \|= MII_BUSY \| ((priv->clk_csr & 0xF) << 2);
dfb8fb96	125
47dd7a54	126	/* Wait until any existing MII operation is complete */
39b401db DS	127	if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
39b401db DS	128	return -EBUSY;
47dd7a54 GC	129
47dd7a54 GC	130	/* Set the MII address register to write */
ad01b7d4 GC	131	writel(phydata, priv->ioaddr + mii_data);
ad01b7d4 GC	132	writel(value, priv->ioaddr + mii_address);
47dd7a54 GC	133
47dd7a54 GC	134	/* Wait until any existing MII operation is complete */
39b401db	135	return stmmac_mdio_busy_wait(priv->ioaddr, mii_address);
47dd7a54 GC	136	}
47dd7a54 GC	137
ac1f74a7 AT	138	/**
	139	* stmmac_mdio_read_gmac4
	140	* @bus: points to the mii_bus structure
	141	* @phyaddr: MII addr reg bits 25-21
	142	* @phyreg: MII addr reg bits 20-16
	143	* Description: it reads data from the MII register of GMAC4 from within
	144	* the phy device.
	145	*/
	146	static int stmmac_mdio_read_gmac4(struct mii_bus *bus, int phyaddr, int phyreg)
	147	{
	148	struct net_device *ndev = bus->priv;
	149	struct stmmac_priv *priv = netdev_priv(ndev);
	150	unsigned int mii_address = priv->hw->mii.addr;
	151	unsigned int mii_data = priv->hw->mii.data;
	152	int data;
	153	u32 value = (((phyaddr << MII_PHY_ADDR_GMAC4_SHIFT) &
	154	(MII_PHY_ADDR_GMAC4_MASK)) \|
	155	((phyreg << MII_PHY_REG_GMAC4_SHIFT) &
	156	(MII_PHY_REG_GMAC4_MASK))) \| MII_GMAC4_READ;
	157
	158	value \|= MII_BUSY \| ((priv->clk_csr & MII_CSR_CLK_GMAC4_MASK)
	159	<< MII_CSR_CLK_GMAC4_SHIFT);
	160
	161	if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
	162	return -EBUSY;
	163
	164	writel(value, priv->ioaddr + mii_address);
	165
	166	if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
	167	return -EBUSY;
	168
	169	/* Read the data from the MII data register */
	170	data = (int)readl(priv->ioaddr + mii_data);
	171
	172	return data;
	173	}
	174
	175	/**
	176	* stmmac_mdio_write_gmac4
	177	* @bus: points to the mii_bus structure
	178	* @phyaddr: MII addr reg bits 25-21
	179	* @phyreg: MII addr reg bits 20-16
	180	* @phydata: phy data
	181	* Description: it writes the data into the MII register of GMAC4 from within
	182	* the device.
	183	*/
	184	static int stmmac_mdio_write_gmac4(struct mii_bus *bus, int phyaddr, int phyreg,
	185	u16 phydata)
	186	{
	187	struct net_device *ndev = bus->priv;
	188	struct stmmac_priv *priv = netdev_priv(ndev);
	189	unsigned int mii_address = priv->hw->mii.addr;
	190	unsigned int mii_data = priv->hw->mii.data;
	191
	192	u32 value = (((phyaddr << MII_PHY_ADDR_GMAC4_SHIFT) &
	193	(MII_PHY_ADDR_GMAC4_MASK)) \|
	194	((phyreg << MII_PHY_REG_GMAC4_SHIFT) &
	195	(MII_PHY_REG_GMAC4_MASK))) \| MII_GMAC4_WRITE;
	196
	197	value \|= MII_BUSY \| ((priv->clk_csr & MII_CSR_CLK_GMAC4_MASK)
	198	<< MII_CSR_CLK_GMAC4_SHIFT);
	199
	200	/* Wait until any existing MII operation is complete */
	201	if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
202	return -EBUSY;
203
204	/* Set the MII address register to write */
205	writel(phydata, priv->ioaddr + mii_data);
206	writel(value, priv->ioaddr + mii_address);
207
208	/* Wait until any existing MII operation is complete */
209	return stmmac_mdio_busy_wait(priv->ioaddr, mii_address);
210	}
211
47dd7a54 GC	212	/**
	213	* stmmac_mdio_reset
	214	* @bus: points to the mii_bus structure
	215	* Description: reset the MII bus
	216	*/
073752aa	217	int stmmac_mdio_reset(struct mii_bus *bus)
47dd7a54	218	{
bfab27a1	219	#if defined(CONFIG_STMMAC_PLATFORM)
47dd7a54 GC	220	struct net_device *ndev = bus->priv;
47dd7a54 GC	221	struct stmmac_priv *priv = netdev_priv(ndev);
db98a0b0	222	unsigned int mii_address = priv->hw->mii.addr;
0e076471 SK	223	struct stmmac_mdio_bus_data *data = priv->plat->mdio_bus_data;
	224
	225	#ifdef CONFIG_OF
	226	if (priv->device->of_node) {
0e076471 SK	227
	228	if (data->reset_gpio < 0) {
	229	struct device_node *np = priv->device->of_node;
	230	if (!np)
	231	return 0;
	232
	233	data->reset_gpio = of_get_named_gpio(np,
	234	"snps,reset-gpio", 0);
	235	if (data->reset_gpio < 0)
	236	return 0;
	237
	238	data->active_low = of_property_read_bool(np,
	239	"snps,reset-active-low");
	240	of_property_read_u32_array(np,
	241	"snps,reset-delays-us", data->delays, 3);
0e076471	242
ae26c1c6 GC	243	if (gpio_request(data->reset_gpio, "mdio-reset"))
	244	return 0;
	245	}
0e076471	246
ae26c1c6 GC	247	gpio_direction_output(data->reset_gpio,
	248	data->active_low ? 1 : 0);
	249	if (data->delays[0])
	250	msleep(DIV_ROUND_UP(data->delays[0], 1000));
892aa01d	251
ae26c1c6 GC	252	gpio_set_value(data->reset_gpio, data->active_low ? 0 : 1);
	253	if (data->delays[1])
	254	msleep(DIV_ROUND_UP(data->delays[1], 1000));
892aa01d	255
ae26c1c6 GC	256	gpio_set_value(data->reset_gpio, data->active_low ? 1 : 0);
	257	if (data->delays[2])
	258	msleep(DIV_ROUND_UP(data->delays[2], 1000));
0e076471 SK	259	}
0e076471 SK	260	#endif
47dd7a54	261
0e076471	262	if (data->phy_reset) {
47dd7a54	263	pr_debug("stmmac_mdio_reset: calling phy_reset\n");
0e076471	264	data->phy_reset(priv->plat->bsp_priv);
47dd7a54 GC	265	}
	266
	267	/* This is a workaround for problems with the STE101P PHY.
	268	* It doesn't complete its reset until at least one clock cycle
ac1f74a7 AT	269	* on MDC, so perform a dummy mdio read. To be upadted for GMAC4
ac1f74a7 AT	270	* if needed.
47dd7a54	271	*/
ac1f74a7 AT	272	if (!priv->plat->has_gmac4)
ac1f74a7 AT	273	writel(0, priv->ioaddr + mii_address);
bfab27a1	274	#endif
47dd7a54 GC	275	return 0;
	276	}
	277
	278	/**
	279	* stmmac_mdio_register
	280	* @ndev: net device structure
	281	* Description: it registers the MII bus
	282	*/
	283	int stmmac_mdio_register(struct net_device *ndev)
	284	{
	285	int err = 0;
	286	struct mii_bus *new_bus;
47dd7a54	287	struct stmmac_priv *priv = netdev_priv(ndev);
36bcfe7d	288	struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
a7657f12	289	struct device_node *mdio_node = priv->plat->mdio_node;
47dd7a54 GC	290	int addr, found;
47dd7a54 GC	291
36bcfe7d GC	292	if (!mdio_bus_data)
	293	return 0;
	294
47dd7a54 GC	295	new_bus = mdiobus_alloc();
	296	if (new_bus == NULL)
	297	return -ENOMEM;
	298
e7f4dc35	299	if (mdio_bus_data->irqs)
643d60bf	300	memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq));
47dd7a54	301
0e076471 SK	302	#ifdef CONFIG_OF
	303	if (priv->device->of_node)
	304	mdio_bus_data->reset_gpio = -1;
	305	#endif
	306
90b9a545	307	new_bus->name = "stmmac";
ac1f74a7 AT	308	if (priv->plat->has_gmac4) {
	309	new_bus->read = &stmmac_mdio_read_gmac4;
	310	new_bus->write = &stmmac_mdio_write_gmac4;
	311	} else {
	312	new_bus->read = &stmmac_mdio_read;
	313	new_bus->write = &stmmac_mdio_write;
	314	}
	315
47dd7a54	316	new_bus->reset = &stmmac_mdio_reset;
db8857bf	317	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
ceb69499	318	new_bus->name, priv->plat->bus_id);
47dd7a54	319	new_bus->priv = ndev;
36bcfe7d	320	new_bus->phy_mask = mdio_bus_data->phy_mask;
47dd7a54	321	new_bus->parent = priv->device;
e34d6569	322
6c672c9b RP	323	if (mdio_node)
	324	err = of_mdiobus_register(new_bus, mdio_node);
	325	else
	326	err = mdiobus_register(new_bus);
47dd7a54 GC	327	if (err != 0) {
	328	pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
	329	goto bus_register_fail;
	330	}
	331
cc2fa619 PR	332	if (priv->plat->phy_node \|\| mdio_node)
	333	goto bus_register_done;
	334
47dd7a54	335	found = 0;
36bcfe7d	336	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
7f854420	337	struct phy_device *phydev = mdiobus_get_phy(new_bus, addr);
47dd7a54	338	if (phydev) {
36bcfe7d GC	339	int act = 0;
	340	char irq_num[4];
	341	char *irq_str;
	342
	343	/*
	344	* If an IRQ was provided to be assigned after
	345	* the bus probe, do it here.
	346	*/
	347	if ((mdio_bus_data->irqs == NULL) &&
	348	(mdio_bus_data->probed_phy_irq > 0)) {
e7f4dc35 AL	349	new_bus->irq[addr] =
e7f4dc35 AL	350	mdio_bus_data->probed_phy_irq;
36bcfe7d	351	phydev->irq = mdio_bus_data->probed_phy_irq;
47dd7a54	352	}
36bcfe7d GC	353
36bcfe7d GC	354	/*
a77e4acc	355	* If we're going to bind the MAC to this PHY bus,
36bcfe7d GC	356	* and no PHY number was provided to the MAC,
	357	* use the one probed here.
	358	*/
d56631a6	359	if (priv->plat->phy_addr == -1)
36bcfe7d GC	360	priv->plat->phy_addr = addr;
36bcfe7d GC	361
d56631a6	362	act = (priv->plat->phy_addr == addr);
36bcfe7d GC	363	switch (phydev->irq) {
	364	case PHY_POLL:
	365	irq_str = "POLL";
	366	break;
	367	case PHY_IGNORE_INTERRUPT:
	368	irq_str = "IGNORE";
	369	break;
	370	default:
	371	sprintf(irq_num, "%d", phydev->irq);
	372	irq_str = irq_num;
	373	break;
	374	}
	375	pr_info("%s: PHY ID %08x at %d IRQ %s (%s)%s\n",
	376	ndev->name, phydev->phy_id, addr,
84eff6d1	377	irq_str, phydev_name(phydev),
36bcfe7d	378	act ? " active" : "");
47dd7a54 GC	379	found = 1;
	380	}
	381	}
	382
e34d6569	383	if (!found && !mdio_node) {
fe3881cf	384	pr_warn("%s: No PHY found\n", ndev->name);
3955b22b GC	385	mdiobus_unregister(new_bus);
	386	mdiobus_free(new_bus);
	387	return -ENODEV;
	388	}
	389
cc2fa619	390	bus_register_done:
3955b22b	391	priv->mii = new_bus;
47dd7a54 GC	392
47dd7a54 GC	393	return 0;
36bcfe7d	394
47dd7a54	395	bus_register_fail:
36bcfe7d	396	mdiobus_free(new_bus);
47dd7a54 GC	397	return err;
	398	}
	399
	400	/**
	401	* stmmac_mdio_unregister
	402	* @ndev: net device structure
	403	* Description: it unregisters the MII bus
	404	*/
	405	int stmmac_mdio_unregister(struct net_device *ndev)
	406	{
	407	struct stmmac_priv *priv = netdev_priv(ndev);
	408
a5cf5ce9 SK	409	if (!priv->mii)
	410	return 0;
	411
47dd7a54 GC	412	mdiobus_unregister(priv->mii);
47dd7a54 GC	413	priv->mii->priv = NULL;
36bcfe7d GC	414	mdiobus_free(priv->mii);
36bcfe7d GC	415	priv->mii = NULL;
47dd7a54 GC	416
	417	return 0;
	418	}