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47dd7a54 GC |
1 | /******************************************************************************* |
2 | This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. | |
3 | ST Ethernet IPs are built around a Synopsys IP Core. | |
4 | ||
286a8372 | 5 | Copyright(C) 2007-2011 STMicroelectronics Ltd |
47dd7a54 GC |
6 | |
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
24 | ||
25 | Documentation available at: | |
26 | http://www.stlinux.com | |
27 | Support available at: | |
28 | https://bugzilla.stlinux.com/ | |
29 | *******************************************************************************/ | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/interrupt.h> | |
47dd7a54 GC |
35 | #include <linux/etherdevice.h> |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/ip.h> | |
38 | #include <linux/tcp.h> | |
39 | #include <linux/skbuff.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_ether.h> | |
42 | #include <linux/crc32.h> | |
43 | #include <linux/mii.h> | |
01789349 | 44 | #include <linux/if.h> |
47dd7a54 GC |
45 | #include <linux/if_vlan.h> |
46 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 47 | #include <linux/slab.h> |
70c71606 | 48 | #include <linux/prefetch.h> |
7ac29055 GC |
49 | #ifdef CONFIG_STMMAC_DEBUG_FS |
50 | #include <linux/debugfs.h> | |
51 | #include <linux/seq_file.h> | |
52 | #endif | |
286a8372 | 53 | #include "stmmac.h" |
47dd7a54 GC |
54 | |
55 | #define STMMAC_RESOURCE_NAME "stmmaceth" | |
47dd7a54 GC |
56 | |
57 | #undef STMMAC_DEBUG | |
58 | /*#define STMMAC_DEBUG*/ | |
59 | #ifdef STMMAC_DEBUG | |
60 | #define DBG(nlevel, klevel, fmt, args...) \ | |
61 | ((void)(netif_msg_##nlevel(priv) && \ | |
62 | printk(KERN_##klevel fmt, ## args))) | |
63 | #else | |
64 | #define DBG(nlevel, klevel, fmt, args...) do { } while (0) | |
65 | #endif | |
66 | ||
67 | #undef STMMAC_RX_DEBUG | |
68 | /*#define STMMAC_RX_DEBUG*/ | |
69 | #ifdef STMMAC_RX_DEBUG | |
70 | #define RX_DBG(fmt, args...) printk(fmt, ## args) | |
71 | #else | |
72 | #define RX_DBG(fmt, args...) do { } while (0) | |
73 | #endif | |
74 | ||
75 | #undef STMMAC_XMIT_DEBUG | |
76 | /*#define STMMAC_XMIT_DEBUG*/ | |
77 | #ifdef STMMAC_TX_DEBUG | |
78 | #define TX_DBG(fmt, args...) printk(fmt, ## args) | |
79 | #else | |
80 | #define TX_DBG(fmt, args...) do { } while (0) | |
81 | #endif | |
82 | ||
83 | #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) | |
84 | #define JUMBO_LEN 9000 | |
85 | ||
86 | /* Module parameters */ | |
87 | #define TX_TIMEO 5000 /* default 5 seconds */ | |
88 | static int watchdog = TX_TIMEO; | |
89 | module_param(watchdog, int, S_IRUGO | S_IWUSR); | |
90 | MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds"); | |
91 | ||
92 | static int debug = -1; /* -1: default, 0: no output, 16: all */ | |
93 | module_param(debug, int, S_IRUGO | S_IWUSR); | |
94 | MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)"); | |
95 | ||
96 | static int phyaddr = -1; | |
97 | module_param(phyaddr, int, S_IRUGO); | |
98 | MODULE_PARM_DESC(phyaddr, "Physical device address"); | |
99 | ||
100 | #define DMA_TX_SIZE 256 | |
101 | static int dma_txsize = DMA_TX_SIZE; | |
102 | module_param(dma_txsize, int, S_IRUGO | S_IWUSR); | |
103 | MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); | |
104 | ||
105 | #define DMA_RX_SIZE 256 | |
106 | static int dma_rxsize = DMA_RX_SIZE; | |
107 | module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); | |
108 | MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); | |
109 | ||
110 | static int flow_ctrl = FLOW_OFF; | |
111 | module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); | |
112 | MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); | |
113 | ||
114 | static int pause = PAUSE_TIME; | |
115 | module_param(pause, int, S_IRUGO | S_IWUSR); | |
116 | MODULE_PARM_DESC(pause, "Flow Control Pause Time"); | |
117 | ||
118 | #define TC_DEFAULT 64 | |
119 | static int tc = TC_DEFAULT; | |
120 | module_param(tc, int, S_IRUGO | S_IWUSR); | |
121 | MODULE_PARM_DESC(tc, "DMA threshold control value"); | |
122 | ||
47dd7a54 GC |
123 | /* Pay attention to tune this parameter; take care of both |
124 | * hardware capability and network stabitily/performance impact. | |
125 | * Many tests showed that ~4ms latency seems to be good enough. */ | |
126 | #ifdef CONFIG_STMMAC_TIMER | |
127 | #define DEFAULT_PERIODIC_RATE 256 | |
128 | static int tmrate = DEFAULT_PERIODIC_RATE; | |
129 | module_param(tmrate, int, S_IRUGO | S_IWUSR); | |
130 | MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)"); | |
131 | #endif | |
132 | ||
133 | #define DMA_BUFFER_SIZE BUF_SIZE_2KiB | |
134 | static int buf_sz = DMA_BUFFER_SIZE; | |
135 | module_param(buf_sz, int, S_IRUGO | S_IWUSR); | |
136 | MODULE_PARM_DESC(buf_sz, "DMA buffer size"); | |
137 | ||
47dd7a54 GC |
138 | static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
139 | NETIF_MSG_LINK | NETIF_MSG_IFUP | | |
140 | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); | |
141 | ||
142 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id); | |
47dd7a54 GC |
143 | |
144 | /** | |
145 | * stmmac_verify_args - verify the driver parameters. | |
146 | * Description: it verifies if some wrong parameter is passed to the driver. | |
147 | * Note that wrong parameters are replaced with the default values. | |
148 | */ | |
149 | static void stmmac_verify_args(void) | |
150 | { | |
151 | if (unlikely(watchdog < 0)) | |
152 | watchdog = TX_TIMEO; | |
153 | if (unlikely(dma_rxsize < 0)) | |
154 | dma_rxsize = DMA_RX_SIZE; | |
155 | if (unlikely(dma_txsize < 0)) | |
156 | dma_txsize = DMA_TX_SIZE; | |
157 | if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) | |
158 | buf_sz = DMA_BUFFER_SIZE; | |
159 | if (unlikely(flow_ctrl > 1)) | |
160 | flow_ctrl = FLOW_AUTO; | |
161 | else if (likely(flow_ctrl < 0)) | |
162 | flow_ctrl = FLOW_OFF; | |
163 | if (unlikely((pause < 0) || (pause > 0xffff))) | |
164 | pause = PAUSE_TIME; | |
47dd7a54 GC |
165 | } |
166 | ||
167 | #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG) | |
168 | static void print_pkt(unsigned char *buf, int len) | |
169 | { | |
170 | int j; | |
171 | pr_info("len = %d byte, buf addr: 0x%p", len, buf); | |
172 | for (j = 0; j < len; j++) { | |
173 | if ((j % 16) == 0) | |
174 | pr_info("\n %03x:", j); | |
175 | pr_info(" %02x", buf[j]); | |
176 | } | |
177 | pr_info("\n"); | |
47dd7a54 GC |
178 | } |
179 | #endif | |
180 | ||
181 | /* minimum number of free TX descriptors required to wake up TX process */ | |
182 | #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) | |
183 | ||
184 | static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) | |
185 | { | |
186 | return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; | |
187 | } | |
188 | ||
9dfeb4d9 GC |
189 | /* On some ST platforms, some HW system configuraton registers have to be |
190 | * set according to the link speed negotiated. | |
191 | */ | |
192 | static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) | |
193 | { | |
194 | struct phy_device *phydev = priv->phydev; | |
195 | ||
196 | if (likely(priv->plat->fix_mac_speed)) | |
197 | priv->plat->fix_mac_speed(priv->plat->bsp_priv, | |
198 | phydev->speed); | |
199 | } | |
200 | ||
47dd7a54 GC |
201 | /** |
202 | * stmmac_adjust_link | |
203 | * @dev: net device structure | |
204 | * Description: it adjusts the link parameters. | |
205 | */ | |
206 | static void stmmac_adjust_link(struct net_device *dev) | |
207 | { | |
208 | struct stmmac_priv *priv = netdev_priv(dev); | |
209 | struct phy_device *phydev = priv->phydev; | |
47dd7a54 GC |
210 | unsigned long flags; |
211 | int new_state = 0; | |
212 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; | |
213 | ||
214 | if (phydev == NULL) | |
215 | return; | |
216 | ||
217 | DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n", | |
218 | phydev->addr, phydev->link); | |
219 | ||
220 | spin_lock_irqsave(&priv->lock, flags); | |
221 | if (phydev->link) { | |
ad01b7d4 | 222 | u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
223 | |
224 | /* Now we make sure that we can be in full duplex mode. | |
225 | * If not, we operate in half-duplex mode. */ | |
226 | if (phydev->duplex != priv->oldduplex) { | |
227 | new_state = 1; | |
228 | if (!(phydev->duplex)) | |
db98a0b0 | 229 | ctrl &= ~priv->hw->link.duplex; |
47dd7a54 | 230 | else |
db98a0b0 | 231 | ctrl |= priv->hw->link.duplex; |
47dd7a54 GC |
232 | priv->oldduplex = phydev->duplex; |
233 | } | |
234 | /* Flow Control operation */ | |
235 | if (phydev->pause) | |
ad01b7d4 | 236 | priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex, |
db98a0b0 | 237 | fc, pause_time); |
47dd7a54 GC |
238 | |
239 | if (phydev->speed != priv->speed) { | |
240 | new_state = 1; | |
241 | switch (phydev->speed) { | |
242 | case 1000: | |
9dfeb4d9 | 243 | if (likely(priv->plat->has_gmac)) |
db98a0b0 | 244 | ctrl &= ~priv->hw->link.port; |
9dfeb4d9 | 245 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
246 | break; |
247 | case 100: | |
248 | case 10: | |
9dfeb4d9 | 249 | if (priv->plat->has_gmac) { |
db98a0b0 | 250 | ctrl |= priv->hw->link.port; |
47dd7a54 | 251 | if (phydev->speed == SPEED_100) { |
db98a0b0 | 252 | ctrl |= priv->hw->link.speed; |
47dd7a54 | 253 | } else { |
db98a0b0 | 254 | ctrl &= ~(priv->hw->link.speed); |
47dd7a54 GC |
255 | } |
256 | } else { | |
db98a0b0 | 257 | ctrl &= ~priv->hw->link.port; |
47dd7a54 | 258 | } |
9dfeb4d9 | 259 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
260 | break; |
261 | default: | |
262 | if (netif_msg_link(priv)) | |
263 | pr_warning("%s: Speed (%d) is not 10" | |
264 | " or 100!\n", dev->name, phydev->speed); | |
265 | break; | |
266 | } | |
267 | ||
268 | priv->speed = phydev->speed; | |
269 | } | |
270 | ||
ad01b7d4 | 271 | writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
272 | |
273 | if (!priv->oldlink) { | |
274 | new_state = 1; | |
275 | priv->oldlink = 1; | |
276 | } | |
277 | } else if (priv->oldlink) { | |
278 | new_state = 1; | |
279 | priv->oldlink = 0; | |
280 | priv->speed = 0; | |
281 | priv->oldduplex = -1; | |
282 | } | |
283 | ||
284 | if (new_state && netif_msg_link(priv)) | |
285 | phy_print_status(phydev); | |
286 | ||
287 | spin_unlock_irqrestore(&priv->lock, flags); | |
288 | ||
289 | DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n"); | |
290 | } | |
291 | ||
292 | /** | |
293 | * stmmac_init_phy - PHY initialization | |
294 | * @dev: net device structure | |
295 | * Description: it initializes the driver's PHY state, and attaches the PHY | |
296 | * to the mac driver. | |
297 | * Return value: | |
298 | * 0 on success | |
299 | */ | |
300 | static int stmmac_init_phy(struct net_device *dev) | |
301 | { | |
302 | struct stmmac_priv *priv = netdev_priv(dev); | |
303 | struct phy_device *phydev; | |
109cdd66 GC |
304 | char phy_id[MII_BUS_ID_SIZE + 3]; |
305 | char bus_id[MII_BUS_ID_SIZE]; | |
79ee1dc3 | 306 | int interface = priv->plat->interface; |
47dd7a54 GC |
307 | priv->oldlink = 0; |
308 | priv->speed = 0; | |
309 | priv->oldduplex = -1; | |
310 | ||
9dfeb4d9 | 311 | snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id); |
109cdd66 | 312 | snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, |
36bcfe7d | 313 | priv->plat->phy_addr); |
47dd7a54 GC |
314 | pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id); |
315 | ||
79ee1dc3 | 316 | phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface); |
47dd7a54 GC |
317 | |
318 | if (IS_ERR(phydev)) { | |
319 | pr_err("%s: Could not attach to PHY\n", dev->name); | |
320 | return PTR_ERR(phydev); | |
321 | } | |
322 | ||
79ee1dc3 SK |
323 | /* Stop Advertising 1000BASE Capability if interface is not GMII */ |
324 | if ((interface) && ((interface == PHY_INTERFACE_MODE_MII) || | |
325 | (interface == PHY_INTERFACE_MODE_RMII))) { | |
326 | phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause | | |
327 | SUPPORTED_Asym_Pause); | |
e2c57f83 | 328 | phydev->advertising = phydev->supported; |
79ee1dc3 SK |
329 | } |
330 | ||
47dd7a54 GC |
331 | /* |
332 | * Broken HW is sometimes missing the pull-up resistor on the | |
333 | * MDIO line, which results in reads to non-existent devices returning | |
334 | * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent | |
335 | * device as well. | |
336 | * Note: phydev->phy_id is the result of reading the UID PHY registers. | |
337 | */ | |
338 | if (phydev->phy_id == 0) { | |
339 | phy_disconnect(phydev); | |
340 | return -ENODEV; | |
341 | } | |
342 | pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" | |
36bcfe7d | 343 | " Link = %d\n", dev->name, phydev->phy_id, phydev->link); |
47dd7a54 GC |
344 | |
345 | priv->phydev = phydev; | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
19449bfc | 350 | static inline void stmmac_enable_mac(void __iomem *ioaddr) |
47dd7a54 GC |
351 | { |
352 | u32 value = readl(ioaddr + MAC_CTRL_REG); | |
47dd7a54 | 353 | |
19449bfc | 354 | value |= MAC_RNABLE_RX | MAC_ENABLE_TX; |
47dd7a54 GC |
355 | writel(value, ioaddr + MAC_CTRL_REG); |
356 | } | |
357 | ||
19449bfc | 358 | static inline void stmmac_disable_mac(void __iomem *ioaddr) |
47dd7a54 GC |
359 | { |
360 | u32 value = readl(ioaddr + MAC_CTRL_REG); | |
47dd7a54 | 361 | |
19449bfc | 362 | value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX); |
47dd7a54 GC |
363 | writel(value, ioaddr + MAC_CTRL_REG); |
364 | } | |
365 | ||
366 | /** | |
367 | * display_ring | |
368 | * @p: pointer to the ring. | |
369 | * @size: size of the ring. | |
370 | * Description: display all the descriptors within the ring. | |
371 | */ | |
372 | static void display_ring(struct dma_desc *p, int size) | |
373 | { | |
374 | struct tmp_s { | |
375 | u64 a; | |
376 | unsigned int b; | |
377 | unsigned int c; | |
378 | }; | |
379 | int i; | |
380 | for (i = 0; i < size; i++) { | |
381 | struct tmp_s *x = (struct tmp_s *)(p + i); | |
382 | pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
383 | i, (unsigned int)virt_to_phys(&p[i]), | |
384 | (unsigned int)(x->a), (unsigned int)((x->a) >> 32), | |
385 | x->b, x->c); | |
386 | pr_info("\n"); | |
387 | } | |
388 | } | |
389 | ||
286a8372 GC |
390 | static int stmmac_set_bfsize(int mtu, int bufsize) |
391 | { | |
392 | int ret = bufsize; | |
393 | ||
394 | if (mtu >= BUF_SIZE_4KiB) | |
395 | ret = BUF_SIZE_8KiB; | |
396 | else if (mtu >= BUF_SIZE_2KiB) | |
397 | ret = BUF_SIZE_4KiB; | |
398 | else if (mtu >= DMA_BUFFER_SIZE) | |
399 | ret = BUF_SIZE_2KiB; | |
400 | else | |
401 | ret = DMA_BUFFER_SIZE; | |
402 | ||
403 | return ret; | |
404 | } | |
405 | ||
47dd7a54 GC |
406 | /** |
407 | * init_dma_desc_rings - init the RX/TX descriptor rings | |
408 | * @dev: net device structure | |
409 | * Description: this function initializes the DMA RX/TX descriptors | |
286a8372 GC |
410 | * and allocates the socket buffers. It suppors the chained and ring |
411 | * modes. | |
47dd7a54 GC |
412 | */ |
413 | static void init_dma_desc_rings(struct net_device *dev) | |
414 | { | |
415 | int i; | |
416 | struct stmmac_priv *priv = netdev_priv(dev); | |
417 | struct sk_buff *skb; | |
418 | unsigned int txsize = priv->dma_tx_size; | |
419 | unsigned int rxsize = priv->dma_rx_size; | |
286a8372 GC |
420 | unsigned int bfsize; |
421 | int dis_ic = 0; | |
422 | int des3_as_data_buf = 0; | |
47dd7a54 | 423 | |
286a8372 GC |
424 | /* Set the max buffer size according to the DESC mode |
425 | * and the MTU. Note that RING mode allows 16KiB bsize. */ | |
426 | bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu); | |
427 | ||
428 | if (bfsize == BUF_SIZE_16KiB) | |
429 | des3_as_data_buf = 1; | |
47dd7a54 | 430 | else |
286a8372 | 431 | bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); |
47dd7a54 | 432 | |
73cfe264 GC |
433 | #ifdef CONFIG_STMMAC_TIMER |
434 | /* Disable interrupts on completion for the reception if timer is on */ | |
435 | if (likely(priv->tm->enable)) | |
436 | dis_ic = 1; | |
437 | #endif | |
47dd7a54 GC |
438 | |
439 | DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n", | |
440 | txsize, rxsize, bfsize); | |
441 | ||
442 | priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL); | |
443 | priv->rx_skbuff = | |
444 | kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL); | |
445 | priv->dma_rx = | |
446 | (struct dma_desc *)dma_alloc_coherent(priv->device, | |
447 | rxsize * | |
448 | sizeof(struct dma_desc), | |
449 | &priv->dma_rx_phy, | |
450 | GFP_KERNEL); | |
451 | priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize, | |
452 | GFP_KERNEL); | |
453 | priv->dma_tx = | |
454 | (struct dma_desc *)dma_alloc_coherent(priv->device, | |
455 | txsize * | |
456 | sizeof(struct dma_desc), | |
457 | &priv->dma_tx_phy, | |
458 | GFP_KERNEL); | |
459 | ||
460 | if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) { | |
461 | pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__); | |
462 | return; | |
463 | } | |
464 | ||
286a8372 | 465 | DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, " |
47dd7a54 GC |
466 | "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n", |
467 | dev->name, priv->dma_rx, priv->dma_tx, | |
468 | (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy); | |
469 | ||
470 | /* RX INITIALIZATION */ | |
471 | DBG(probe, INFO, "stmmac: SKB addresses:\n" | |
472 | "skb\t\tskb data\tdma data\n"); | |
473 | ||
474 | for (i = 0; i < rxsize; i++) { | |
475 | struct dma_desc *p = priv->dma_rx + i; | |
476 | ||
45db81e1 GC |
477 | skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN, |
478 | GFP_KERNEL); | |
47dd7a54 GC |
479 | if (unlikely(skb == NULL)) { |
480 | pr_err("%s: Rx init fails; skb is NULL\n", __func__); | |
481 | break; | |
482 | } | |
45db81e1 | 483 | skb_reserve(skb, NET_IP_ALIGN); |
47dd7a54 GC |
484 | priv->rx_skbuff[i] = skb; |
485 | priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, | |
486 | bfsize, DMA_FROM_DEVICE); | |
487 | ||
488 | p->des2 = priv->rx_skbuff_dma[i]; | |
286a8372 GC |
489 | |
490 | priv->hw->ring->init_desc3(des3_as_data_buf, p); | |
491 | ||
47dd7a54 GC |
492 | DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], |
493 | priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]); | |
494 | } | |
495 | priv->cur_rx = 0; | |
496 | priv->dirty_rx = (unsigned int)(i - rxsize); | |
497 | priv->dma_buf_sz = bfsize; | |
498 | buf_sz = bfsize; | |
499 | ||
500 | /* TX INITIALIZATION */ | |
501 | for (i = 0; i < txsize; i++) { | |
502 | priv->tx_skbuff[i] = NULL; | |
503 | priv->dma_tx[i].des2 = 0; | |
504 | } | |
286a8372 GC |
505 | |
506 | /* In case of Chained mode this sets the des3 to the next | |
507 | * element in the chain */ | |
508 | priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize); | |
509 | priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize); | |
510 | ||
47dd7a54 GC |
511 | priv->dirty_tx = 0; |
512 | priv->cur_tx = 0; | |
513 | ||
514 | /* Clear the Rx/Tx descriptors */ | |
db98a0b0 GC |
515 | priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic); |
516 | priv->hw->desc->init_tx_desc(priv->dma_tx, txsize); | |
47dd7a54 GC |
517 | |
518 | if (netif_msg_hw(priv)) { | |
519 | pr_info("RX descriptor ring:\n"); | |
520 | display_ring(priv->dma_rx, rxsize); | |
521 | pr_info("TX descriptor ring:\n"); | |
522 | display_ring(priv->dma_tx, txsize); | |
523 | } | |
47dd7a54 GC |
524 | } |
525 | ||
526 | static void dma_free_rx_skbufs(struct stmmac_priv *priv) | |
527 | { | |
528 | int i; | |
529 | ||
530 | for (i = 0; i < priv->dma_rx_size; i++) { | |
531 | if (priv->rx_skbuff[i]) { | |
532 | dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], | |
533 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
534 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
535 | } | |
536 | priv->rx_skbuff[i] = NULL; | |
537 | } | |
47dd7a54 GC |
538 | } |
539 | ||
540 | static void dma_free_tx_skbufs(struct stmmac_priv *priv) | |
541 | { | |
542 | int i; | |
543 | ||
544 | for (i = 0; i < priv->dma_tx_size; i++) { | |
545 | if (priv->tx_skbuff[i] != NULL) { | |
546 | struct dma_desc *p = priv->dma_tx + i; | |
547 | if (p->des2) | |
548 | dma_unmap_single(priv->device, p->des2, | |
db98a0b0 GC |
549 | priv->hw->desc->get_tx_len(p), |
550 | DMA_TO_DEVICE); | |
47dd7a54 GC |
551 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
552 | priv->tx_skbuff[i] = NULL; | |
553 | } | |
554 | } | |
47dd7a54 GC |
555 | } |
556 | ||
557 | static void free_dma_desc_resources(struct stmmac_priv *priv) | |
558 | { | |
559 | /* Release the DMA TX/RX socket buffers */ | |
560 | dma_free_rx_skbufs(priv); | |
561 | dma_free_tx_skbufs(priv); | |
562 | ||
563 | /* Free the region of consistent memory previously allocated for | |
564 | * the DMA */ | |
565 | dma_free_coherent(priv->device, | |
566 | priv->dma_tx_size * sizeof(struct dma_desc), | |
567 | priv->dma_tx, priv->dma_tx_phy); | |
568 | dma_free_coherent(priv->device, | |
569 | priv->dma_rx_size * sizeof(struct dma_desc), | |
570 | priv->dma_rx, priv->dma_rx_phy); | |
571 | kfree(priv->rx_skbuff_dma); | |
572 | kfree(priv->rx_skbuff); | |
573 | kfree(priv->tx_skbuff); | |
47dd7a54 GC |
574 | } |
575 | ||
47dd7a54 GC |
576 | /** |
577 | * stmmac_dma_operation_mode - HW DMA operation mode | |
578 | * @priv : pointer to the private device structure. | |
579 | * Description: it sets the DMA operation mode: tx/rx DMA thresholds | |
ebbb293f | 580 | * or Store-And-Forward capability. |
47dd7a54 GC |
581 | */ |
582 | static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |
583 | { | |
61b8013a SK |
584 | if (likely(priv->plat->force_sf_dma_mode || |
585 | ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) { | |
586 | /* | |
587 | * In case of GMAC, SF mode can be enabled | |
588 | * to perform the TX COE in HW. This depends on: | |
ebbb293f GC |
589 | * 1) TX COE if actually supported |
590 | * 2) There is no bugged Jumbo frame support | |
591 | * that needs to not insert csum in the TDES. | |
592 | */ | |
593 | priv->hw->dma->dma_mode(priv->ioaddr, | |
594 | SF_DMA_MODE, SF_DMA_MODE); | |
595 | tc = SF_DMA_MODE; | |
596 | } else | |
597 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); | |
47dd7a54 GC |
598 | } |
599 | ||
47dd7a54 GC |
600 | /** |
601 | * stmmac_tx: | |
602 | * @priv: private driver structure | |
603 | * Description: it reclaims resources after transmission completes. | |
604 | */ | |
605 | static void stmmac_tx(struct stmmac_priv *priv) | |
606 | { | |
607 | unsigned int txsize = priv->dma_tx_size; | |
47dd7a54 | 608 | |
a9097a96 GC |
609 | spin_lock(&priv->tx_lock); |
610 | ||
47dd7a54 GC |
611 | while (priv->dirty_tx != priv->cur_tx) { |
612 | int last; | |
613 | unsigned int entry = priv->dirty_tx % txsize; | |
614 | struct sk_buff *skb = priv->tx_skbuff[entry]; | |
615 | struct dma_desc *p = priv->dma_tx + entry; | |
616 | ||
617 | /* Check if the descriptor is owned by the DMA. */ | |
db98a0b0 | 618 | if (priv->hw->desc->get_tx_owner(p)) |
47dd7a54 GC |
619 | break; |
620 | ||
621 | /* Verify tx error by looking at the last segment */ | |
db98a0b0 | 622 | last = priv->hw->desc->get_tx_ls(p); |
47dd7a54 GC |
623 | if (likely(last)) { |
624 | int tx_error = | |
db98a0b0 GC |
625 | priv->hw->desc->tx_status(&priv->dev->stats, |
626 | &priv->xstats, p, | |
ad01b7d4 | 627 | priv->ioaddr); |
47dd7a54 GC |
628 | if (likely(tx_error == 0)) { |
629 | priv->dev->stats.tx_packets++; | |
630 | priv->xstats.tx_pkt_n++; | |
631 | } else | |
632 | priv->dev->stats.tx_errors++; | |
633 | } | |
634 | TX_DBG("%s: curr %d, dirty %d\n", __func__, | |
635 | priv->cur_tx, priv->dirty_tx); | |
636 | ||
637 | if (likely(p->des2)) | |
638 | dma_unmap_single(priv->device, p->des2, | |
db98a0b0 | 639 | priv->hw->desc->get_tx_len(p), |
47dd7a54 | 640 | DMA_TO_DEVICE); |
286a8372 | 641 | priv->hw->ring->clean_desc3(p); |
47dd7a54 GC |
642 | |
643 | if (likely(skb != NULL)) { | |
644 | /* | |
645 | * If there's room in the queue (limit it to size) | |
646 | * we add this skb back into the pool, | |
647 | * if it's the right size. | |
648 | */ | |
649 | if ((skb_queue_len(&priv->rx_recycle) < | |
650 | priv->dma_rx_size) && | |
651 | skb_recycle_check(skb, priv->dma_buf_sz)) | |
652 | __skb_queue_head(&priv->rx_recycle, skb); | |
653 | else | |
654 | dev_kfree_skb(skb); | |
655 | ||
656 | priv->tx_skbuff[entry] = NULL; | |
657 | } | |
658 | ||
db98a0b0 | 659 | priv->hw->desc->release_tx_desc(p); |
47dd7a54 GC |
660 | |
661 | entry = (++priv->dirty_tx) % txsize; | |
662 | } | |
663 | if (unlikely(netif_queue_stopped(priv->dev) && | |
664 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { | |
665 | netif_tx_lock(priv->dev); | |
666 | if (netif_queue_stopped(priv->dev) && | |
667 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { | |
668 | TX_DBG("%s: restart transmit\n", __func__); | |
669 | netif_wake_queue(priv->dev); | |
670 | } | |
671 | netif_tx_unlock(priv->dev); | |
672 | } | |
a9097a96 | 673 | spin_unlock(&priv->tx_lock); |
47dd7a54 GC |
674 | } |
675 | ||
676 | static inline void stmmac_enable_irq(struct stmmac_priv *priv) | |
677 | { | |
73cfe264 GC |
678 | #ifdef CONFIG_STMMAC_TIMER |
679 | if (likely(priv->tm->enable)) | |
680 | priv->tm->timer_start(tmrate); | |
681 | else | |
47dd7a54 | 682 | #endif |
ad01b7d4 | 683 | priv->hw->dma->enable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
684 | } |
685 | ||
686 | static inline void stmmac_disable_irq(struct stmmac_priv *priv) | |
687 | { | |
73cfe264 GC |
688 | #ifdef CONFIG_STMMAC_TIMER |
689 | if (likely(priv->tm->enable)) | |
690 | priv->tm->timer_stop(); | |
691 | else | |
47dd7a54 | 692 | #endif |
ad01b7d4 | 693 | priv->hw->dma->disable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
694 | } |
695 | ||
696 | static int stmmac_has_work(struct stmmac_priv *priv) | |
697 | { | |
698 | unsigned int has_work = 0; | |
699 | int rxret, tx_work = 0; | |
700 | ||
db98a0b0 | 701 | rxret = priv->hw->desc->get_rx_owner(priv->dma_rx + |
47dd7a54 GC |
702 | (priv->cur_rx % priv->dma_rx_size)); |
703 | ||
704 | if (priv->dirty_tx != priv->cur_tx) | |
705 | tx_work = 1; | |
706 | ||
707 | if (likely(!rxret || tx_work)) | |
708 | has_work = 1; | |
709 | ||
710 | return has_work; | |
711 | } | |
712 | ||
713 | static inline void _stmmac_schedule(struct stmmac_priv *priv) | |
714 | { | |
715 | if (likely(stmmac_has_work(priv))) { | |
716 | stmmac_disable_irq(priv); | |
717 | napi_schedule(&priv->napi); | |
718 | } | |
719 | } | |
720 | ||
721 | #ifdef CONFIG_STMMAC_TIMER | |
722 | void stmmac_schedule(struct net_device *dev) | |
723 | { | |
724 | struct stmmac_priv *priv = netdev_priv(dev); | |
725 | ||
726 | priv->xstats.sched_timer_n++; | |
727 | ||
728 | _stmmac_schedule(priv); | |
47dd7a54 GC |
729 | } |
730 | ||
731 | static void stmmac_no_timer_started(unsigned int x) | |
732 | {; | |
733 | }; | |
734 | ||
735 | static void stmmac_no_timer_stopped(void) | |
736 | {; | |
737 | }; | |
738 | #endif | |
739 | ||
740 | /** | |
741 | * stmmac_tx_err: | |
742 | * @priv: pointer to the private device structure | |
743 | * Description: it cleans the descriptors and restarts the transmission | |
744 | * in case of errors. | |
745 | */ | |
746 | static void stmmac_tx_err(struct stmmac_priv *priv) | |
747 | { | |
748 | netif_stop_queue(priv->dev); | |
749 | ||
ad01b7d4 | 750 | priv->hw->dma->stop_tx(priv->ioaddr); |
47dd7a54 | 751 | dma_free_tx_skbufs(priv); |
db98a0b0 | 752 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); |
47dd7a54 GC |
753 | priv->dirty_tx = 0; |
754 | priv->cur_tx = 0; | |
ad01b7d4 | 755 | priv->hw->dma->start_tx(priv->ioaddr); |
47dd7a54 GC |
756 | |
757 | priv->dev->stats.tx_errors++; | |
758 | netif_wake_queue(priv->dev); | |
47dd7a54 GC |
759 | } |
760 | ||
47dd7a54 | 761 | |
aec7ff27 GC |
762 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
763 | { | |
aec7ff27 GC |
764 | int status; |
765 | ||
ad01b7d4 | 766 | status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); |
aec7ff27 GC |
767 | if (likely(status == handle_tx_rx)) |
768 | _stmmac_schedule(priv); | |
769 | ||
770 | else if (unlikely(status == tx_hard_error_bump_tc)) { | |
771 | /* Try to bump up the dma threshold on this failure */ | |
772 | if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { | |
773 | tc += 64; | |
ad01b7d4 | 774 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); |
aec7ff27 | 775 | priv->xstats.threshold = tc; |
47dd7a54 | 776 | } |
aec7ff27 GC |
777 | } else if (unlikely(status == tx_hard_error)) |
778 | stmmac_tx_err(priv); | |
47dd7a54 GC |
779 | } |
780 | ||
1c901a46 GC |
781 | static void stmmac_mmc_setup(struct stmmac_priv *priv) |
782 | { | |
783 | unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | | |
784 | MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; | |
785 | ||
786 | /* Do not manage MMC IRQ (FIXME) */ | |
787 | dwmac_mmc_intr_all_mask(priv->ioaddr); | |
788 | dwmac_mmc_ctrl(priv->ioaddr, mode); | |
789 | memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); | |
790 | } | |
791 | ||
f0b9d786 GC |
792 | static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) |
793 | { | |
794 | u32 hwid = priv->hw->synopsys_uid; | |
795 | ||
796 | /* Only check valid Synopsys Id because old MAC chips | |
797 | * have no HW registers where get the ID */ | |
798 | if (likely(hwid)) { | |
799 | u32 uid = ((hwid & 0x0000ff00) >> 8); | |
800 | u32 synid = (hwid & 0x000000ff); | |
801 | ||
802 | pr_info("STMMAC - user ID: 0x%x, Synopsys ID: 0x%x\n", | |
803 | uid, synid); | |
804 | ||
805 | return synid; | |
806 | } | |
807 | return 0; | |
808 | } | |
e7434821 GC |
809 | |
810 | /* New GMAC chips support a new register to indicate the | |
811 | * presence of the optional feature/functions. | |
812 | */ | |
813 | static int stmmac_get_hw_features(struct stmmac_priv *priv) | |
814 | { | |
5e6efe88 | 815 | u32 hw_cap = 0; |
3c20f72f | 816 | |
5e6efe88 GC |
817 | if (priv->hw->dma->get_hw_feature) { |
818 | hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); | |
e7434821 | 819 | |
1db123fb RK |
820 | priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); |
821 | priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; | |
822 | priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; | |
823 | priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; | |
824 | priv->dma_cap.multi_addr = | |
825 | (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5; | |
826 | priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; | |
827 | priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; | |
828 | priv->dma_cap.pmt_remote_wake_up = | |
829 | (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; | |
830 | priv->dma_cap.pmt_magic_frame = | |
831 | (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; | |
832 | /*MMC*/ | |
833 | priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; | |
e7434821 | 834 | /* IEEE 1588-2002*/ |
1db123fb RK |
835 | priv->dma_cap.time_stamp = |
836 | (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; | |
e7434821 | 837 | /* IEEE 1588-2008*/ |
1db123fb RK |
838 | priv->dma_cap.atime_stamp = |
839 | (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; | |
e7434821 | 840 | /* 802.3az - Energy-Efficient Ethernet (EEE) */ |
1db123fb RK |
841 | priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; |
842 | priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; | |
e7434821 | 843 | /* TX and RX csum */ |
1db123fb RK |
844 | priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; |
845 | priv->dma_cap.rx_coe_type1 = | |
846 | (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; | |
847 | priv->dma_cap.rx_coe_type2 = | |
848 | (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; | |
849 | priv->dma_cap.rxfifo_over_2048 = | |
850 | (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; | |
e7434821 | 851 | /* TX and RX number of channels */ |
1db123fb RK |
852 | priv->dma_cap.number_rx_channel = |
853 | (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; | |
854 | priv->dma_cap.number_tx_channel = | |
855 | (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; | |
e7434821 | 856 | /* Alternate (enhanced) DESC mode*/ |
1db123fb RK |
857 | priv->dma_cap.enh_desc = |
858 | (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; | |
e7434821 GC |
859 | |
860 | } else | |
861 | pr_debug("\tNo HW DMA feature register supported"); | |
862 | ||
863 | return hw_cap; | |
864 | } | |
865 | ||
47dd7a54 GC |
866 | /** |
867 | * stmmac_open - open entry point of the driver | |
868 | * @dev : pointer to the device structure. | |
869 | * Description: | |
870 | * This function is the open entry point of the driver. | |
871 | * Return value: | |
872 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
873 | * file on failure. | |
874 | */ | |
875 | static int stmmac_open(struct net_device *dev) | |
876 | { | |
877 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
878 | int ret; |
879 | ||
880 | /* Check that the MAC address is valid. If its not, refuse | |
881 | * to bring the device up. The user must specify an | |
882 | * address using the following linux command: | |
883 | * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */ | |
884 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
885 | random_ether_addr(dev->dev_addr); | |
886 | pr_warning("%s: generated random MAC address %pM\n", dev->name, | |
887 | dev->dev_addr); | |
888 | } | |
889 | ||
890 | stmmac_verify_args(); | |
891 | ||
47dd7a54 | 892 | #ifdef CONFIG_STMMAC_TIMER |
73cfe264 | 893 | priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL); |
47dd7a54 | 894 | if (unlikely(priv->tm == NULL)) { |
2381a55c | 895 | pr_err("%s: ERROR: timer memory alloc failed\n", __func__); |
47dd7a54 GC |
896 | return -ENOMEM; |
897 | } | |
898 | priv->tm->freq = tmrate; | |
899 | ||
73cfe264 GC |
900 | /* Test if the external timer can be actually used. |
901 | * In case of failure continue without timer. */ | |
47dd7a54 | 902 | if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) { |
73cfe264 | 903 | pr_warning("stmmaceth: cannot attach the external timer.\n"); |
47dd7a54 GC |
904 | priv->tm->freq = 0; |
905 | priv->tm->timer_start = stmmac_no_timer_started; | |
906 | priv->tm->timer_stop = stmmac_no_timer_stopped; | |
73cfe264 GC |
907 | } else |
908 | priv->tm->enable = 1; | |
47dd7a54 | 909 | #endif |
f66ffe28 GC |
910 | ret = stmmac_init_phy(dev); |
911 | if (unlikely(ret)) { | |
912 | pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret); | |
913 | goto open_error; | |
914 | } | |
47dd7a54 GC |
915 | |
916 | /* Create and initialize the TX/RX descriptors chains. */ | |
917 | priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); | |
918 | priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); | |
919 | priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); | |
920 | init_dma_desc_rings(dev); | |
921 | ||
922 | /* DMA initialization and SW reset */ | |
f66ffe28 GC |
923 | ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl, |
924 | priv->dma_tx_phy, priv->dma_rx_phy); | |
925 | if (ret < 0) { | |
47dd7a54 | 926 | pr_err("%s: DMA initialization failed\n", __func__); |
f66ffe28 | 927 | goto open_error; |
47dd7a54 GC |
928 | } |
929 | ||
930 | /* Copy the MAC addr into the HW */ | |
ad01b7d4 | 931 | priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); |
ca5f12c1 | 932 | /* If required, perform hw setup of the bus. */ |
9dfeb4d9 GC |
933 | if (priv->plat->bus_setup) |
934 | priv->plat->bus_setup(priv->ioaddr); | |
47dd7a54 | 935 | /* Initialize the MAC Core */ |
ad01b7d4 | 936 | priv->hw->mac->core_init(priv->ioaddr); |
47dd7a54 | 937 | |
f0b9d786 GC |
938 | stmmac_get_synopsys_id(priv); |
939 | ||
e7434821 GC |
940 | stmmac_get_hw_features(priv); |
941 | ||
3c20f72f | 942 | priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr); |
ebbb293f GC |
943 | if (priv->rx_coe) |
944 | pr_info("stmmac: Rx Checksum Offload Engine supported\n"); | |
9dfeb4d9 | 945 | if (priv->plat->tx_coe) |
ebbb293f | 946 | pr_info("\tTX Checksum insertion supported\n"); |
5e982f3b | 947 | netdev_update_features(dev); |
ebbb293f | 948 | |
f66ffe28 GC |
949 | /* Request the IRQ lines */ |
950 | ret = request_irq(dev->irq, stmmac_interrupt, | |
951 | IRQF_SHARED, dev->name, dev); | |
952 | if (unlikely(ret < 0)) { | |
953 | pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", | |
954 | __func__, dev->irq, ret); | |
955 | goto open_error; | |
956 | } | |
957 | ||
47dd7a54 | 958 | /* Enable the MAC Rx/Tx */ |
19449bfc | 959 | stmmac_enable_mac(priv->ioaddr); |
47dd7a54 GC |
960 | |
961 | /* Set the HW DMA mode and the COE */ | |
962 | stmmac_dma_operation_mode(priv); | |
963 | ||
964 | /* Extra statistics */ | |
965 | memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); | |
966 | priv->xstats.threshold = tc; | |
967 | ||
38fe7a93 GC |
968 | if (priv->dma_cap.rmon) |
969 | stmmac_mmc_setup(priv); | |
1c901a46 | 970 | |
47dd7a54 GC |
971 | /* Start the ball rolling... */ |
972 | DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); | |
ad01b7d4 GC |
973 | priv->hw->dma->start_tx(priv->ioaddr); |
974 | priv->hw->dma->start_rx(priv->ioaddr); | |
47dd7a54 GC |
975 | |
976 | #ifdef CONFIG_STMMAC_TIMER | |
977 | priv->tm->timer_start(tmrate); | |
978 | #endif | |
979 | /* Dump DMA/MAC registers */ | |
980 | if (netif_msg_hw(priv)) { | |
ad01b7d4 GC |
981 | priv->hw->mac->dump_regs(priv->ioaddr); |
982 | priv->hw->dma->dump_regs(priv->ioaddr); | |
47dd7a54 GC |
983 | } |
984 | ||
985 | if (priv->phydev) | |
986 | phy_start(priv->phydev); | |
987 | ||
988 | napi_enable(&priv->napi); | |
989 | skb_queue_head_init(&priv->rx_recycle); | |
990 | netif_start_queue(dev); | |
f66ffe28 | 991 | |
47dd7a54 | 992 | return 0; |
f66ffe28 GC |
993 | |
994 | open_error: | |
995 | #ifdef CONFIG_STMMAC_TIMER | |
996 | kfree(priv->tm); | |
997 | #endif | |
998 | if (priv->phydev) | |
999 | phy_disconnect(priv->phydev); | |
1000 | ||
1001 | return ret; | |
47dd7a54 GC |
1002 | } |
1003 | ||
1004 | /** | |
1005 | * stmmac_release - close entry point of the driver | |
1006 | * @dev : device pointer. | |
1007 | * Description: | |
1008 | * This is the stop entry point of the driver. | |
1009 | */ | |
1010 | static int stmmac_release(struct net_device *dev) | |
1011 | { | |
1012 | struct stmmac_priv *priv = netdev_priv(dev); | |
1013 | ||
1014 | /* Stop and disconnect the PHY */ | |
1015 | if (priv->phydev) { | |
1016 | phy_stop(priv->phydev); | |
1017 | phy_disconnect(priv->phydev); | |
1018 | priv->phydev = NULL; | |
1019 | } | |
1020 | ||
1021 | netif_stop_queue(dev); | |
1022 | ||
1023 | #ifdef CONFIG_STMMAC_TIMER | |
1024 | /* Stop and release the timer */ | |
1025 | stmmac_close_ext_timer(); | |
1026 | if (priv->tm != NULL) | |
1027 | kfree(priv->tm); | |
1028 | #endif | |
1029 | napi_disable(&priv->napi); | |
1030 | skb_queue_purge(&priv->rx_recycle); | |
1031 | ||
1032 | /* Free the IRQ lines */ | |
1033 | free_irq(dev->irq, dev); | |
1034 | ||
1035 | /* Stop TX/RX DMA and clear the descriptors */ | |
ad01b7d4 GC |
1036 | priv->hw->dma->stop_tx(priv->ioaddr); |
1037 | priv->hw->dma->stop_rx(priv->ioaddr); | |
47dd7a54 GC |
1038 | |
1039 | /* Release and free the Rx/Tx resources */ | |
1040 | free_dma_desc_resources(priv); | |
1041 | ||
19449bfc | 1042 | /* Disable the MAC Rx/Tx */ |
1043 | stmmac_disable_mac(priv->ioaddr); | |
47dd7a54 GC |
1044 | |
1045 | netif_carrier_off(dev); | |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
47dd7a54 GC |
1050 | /** |
1051 | * stmmac_xmit: | |
1052 | * @skb : the socket buffer | |
1053 | * @dev : device pointer | |
1054 | * Description : Tx entry point of the driver. | |
1055 | */ | |
1056 | static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) | |
1057 | { | |
1058 | struct stmmac_priv *priv = netdev_priv(dev); | |
1059 | unsigned int txsize = priv->dma_tx_size; | |
1060 | unsigned int entry; | |
1061 | int i, csum_insertion = 0; | |
1062 | int nfrags = skb_shinfo(skb)->nr_frags; | |
1063 | struct dma_desc *desc, *first; | |
286a8372 | 1064 | unsigned int nopaged_len = skb_headlen(skb); |
47dd7a54 GC |
1065 | |
1066 | if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { | |
1067 | if (!netif_queue_stopped(dev)) { | |
1068 | netif_stop_queue(dev); | |
1069 | /* This is a hard error, log it. */ | |
1070 | pr_err("%s: BUG! Tx Ring full when queue awake\n", | |
1071 | __func__); | |
1072 | } | |
1073 | return NETDEV_TX_BUSY; | |
1074 | } | |
1075 | ||
a9097a96 GC |
1076 | spin_lock(&priv->tx_lock); |
1077 | ||
47dd7a54 GC |
1078 | entry = priv->cur_tx % txsize; |
1079 | ||
1080 | #ifdef STMMAC_XMIT_DEBUG | |
1081 | if ((skb->len > ETH_FRAME_LEN) || nfrags) | |
1082 | pr_info("stmmac xmit:\n" | |
1083 | "\tskb addr %p - len: %d - nopaged_len: %d\n" | |
1084 | "\tn_frags: %d - ip_summed: %d - %s gso\n", | |
286a8372 | 1085 | skb, skb->len, nopaged_len, nfrags, skb->ip_summed, |
47dd7a54 GC |
1086 | !skb_is_gso(skb) ? "isn't" : "is"); |
1087 | #endif | |
1088 | ||
5e982f3b | 1089 | csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); |
47dd7a54 GC |
1090 | |
1091 | desc = priv->dma_tx + entry; | |
1092 | first = desc; | |
1093 | ||
1094 | #ifdef STMMAC_XMIT_DEBUG | |
1095 | if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN)) | |
1096 | pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n" | |
1097 | "\t\tn_frags: %d, ip_summed: %d\n", | |
286a8372 | 1098 | skb->len, nopaged_len, nfrags, skb->ip_summed); |
47dd7a54 GC |
1099 | #endif |
1100 | priv->tx_skbuff[entry] = skb; | |
286a8372 GC |
1101 | |
1102 | if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) { | |
1103 | entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion); | |
47dd7a54 GC |
1104 | desc = priv->dma_tx + entry; |
1105 | } else { | |
47dd7a54 GC |
1106 | desc->des2 = dma_map_single(priv->device, skb->data, |
1107 | nopaged_len, DMA_TO_DEVICE); | |
db98a0b0 GC |
1108 | priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, |
1109 | csum_insertion); | |
47dd7a54 GC |
1110 | } |
1111 | ||
1112 | for (i = 0; i < nfrags; i++) { | |
9e903e08 ED |
1113 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
1114 | int len = skb_frag_size(frag); | |
47dd7a54 GC |
1115 | |
1116 | entry = (++priv->cur_tx) % txsize; | |
1117 | desc = priv->dma_tx + entry; | |
1118 | ||
1119 | TX_DBG("\t[entry %d] segment len: %d\n", entry, len); | |
f722380d IC |
1120 | desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, |
1121 | DMA_TO_DEVICE); | |
47dd7a54 | 1122 | priv->tx_skbuff[entry] = NULL; |
db98a0b0 | 1123 | priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion); |
eb0dc4bb | 1124 | wmb(); |
db98a0b0 | 1125 | priv->hw->desc->set_tx_owner(desc); |
47dd7a54 GC |
1126 | } |
1127 | ||
1128 | /* Interrupt on completition only for the latest segment */ | |
db98a0b0 | 1129 | priv->hw->desc->close_tx_desc(desc); |
73cfe264 | 1130 | |
47dd7a54 | 1131 | #ifdef CONFIG_STMMAC_TIMER |
73cfe264 GC |
1132 | /* Clean IC while using timer */ |
1133 | if (likely(priv->tm->enable)) | |
db98a0b0 | 1134 | priv->hw->desc->clear_tx_ic(desc); |
47dd7a54 | 1135 | #endif |
eb0dc4bb SH |
1136 | |
1137 | wmb(); | |
1138 | ||
47dd7a54 | 1139 | /* To avoid raise condition */ |
db98a0b0 | 1140 | priv->hw->desc->set_tx_owner(first); |
47dd7a54 GC |
1141 | |
1142 | priv->cur_tx++; | |
1143 | ||
1144 | #ifdef STMMAC_XMIT_DEBUG | |
1145 | if (netif_msg_pktdata(priv)) { | |
1146 | pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, " | |
1147 | "first=%p, nfrags=%d\n", | |
1148 | (priv->cur_tx % txsize), (priv->dirty_tx % txsize), | |
1149 | entry, first, nfrags); | |
1150 | display_ring(priv->dma_tx, txsize); | |
1151 | pr_info(">>> frame to be transmitted: "); | |
1152 | print_pkt(skb->data, skb->len); | |
1153 | } | |
1154 | #endif | |
1155 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { | |
1156 | TX_DBG("%s: stop transmitted packets\n", __func__); | |
1157 | netif_stop_queue(dev); | |
1158 | } | |
1159 | ||
1160 | dev->stats.tx_bytes += skb->len; | |
1161 | ||
3e82ce12 RC |
1162 | skb_tx_timestamp(skb); |
1163 | ||
52f64fae RC |
1164 | priv->hw->dma->enable_dma_transmission(priv->ioaddr); |
1165 | ||
a9097a96 GC |
1166 | spin_unlock(&priv->tx_lock); |
1167 | ||
47dd7a54 GC |
1168 | return NETDEV_TX_OK; |
1169 | } | |
1170 | ||
1171 | static inline void stmmac_rx_refill(struct stmmac_priv *priv) | |
1172 | { | |
1173 | unsigned int rxsize = priv->dma_rx_size; | |
1174 | int bfsize = priv->dma_buf_sz; | |
1175 | struct dma_desc *p = priv->dma_rx; | |
1176 | ||
1177 | for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { | |
1178 | unsigned int entry = priv->dirty_rx % rxsize; | |
1179 | if (likely(priv->rx_skbuff[entry] == NULL)) { | |
1180 | struct sk_buff *skb; | |
1181 | ||
1182 | skb = __skb_dequeue(&priv->rx_recycle); | |
1183 | if (skb == NULL) | |
1184 | skb = netdev_alloc_skb_ip_align(priv->dev, | |
1185 | bfsize); | |
1186 | ||
1187 | if (unlikely(skb == NULL)) | |
1188 | break; | |
1189 | ||
1190 | priv->rx_skbuff[entry] = skb; | |
1191 | priv->rx_skbuff_dma[entry] = | |
1192 | dma_map_single(priv->device, skb->data, bfsize, | |
1193 | DMA_FROM_DEVICE); | |
1194 | ||
1195 | (p + entry)->des2 = priv->rx_skbuff_dma[entry]; | |
286a8372 GC |
1196 | |
1197 | if (unlikely(priv->plat->has_gmac)) | |
1198 | priv->hw->ring->refill_desc3(bfsize, p + entry); | |
1199 | ||
47dd7a54 GC |
1200 | RX_DBG(KERN_INFO "\trefill entry #%d\n", entry); |
1201 | } | |
eb0dc4bb | 1202 | wmb(); |
db98a0b0 | 1203 | priv->hw->desc->set_rx_owner(p + entry); |
47dd7a54 | 1204 | } |
47dd7a54 GC |
1205 | } |
1206 | ||
1207 | static int stmmac_rx(struct stmmac_priv *priv, int limit) | |
1208 | { | |
1209 | unsigned int rxsize = priv->dma_rx_size; | |
1210 | unsigned int entry = priv->cur_rx % rxsize; | |
1211 | unsigned int next_entry; | |
1212 | unsigned int count = 0; | |
1213 | struct dma_desc *p = priv->dma_rx + entry; | |
1214 | struct dma_desc *p_next; | |
1215 | ||
1216 | #ifdef STMMAC_RX_DEBUG | |
1217 | if (netif_msg_hw(priv)) { | |
1218 | pr_debug(">>> stmmac_rx: descriptor ring:\n"); | |
1219 | display_ring(priv->dma_rx, rxsize); | |
1220 | } | |
1221 | #endif | |
1222 | count = 0; | |
db98a0b0 | 1223 | while (!priv->hw->desc->get_rx_owner(p)) { |
47dd7a54 GC |
1224 | int status; |
1225 | ||
1226 | if (count >= limit) | |
1227 | break; | |
1228 | ||
1229 | count++; | |
1230 | ||
1231 | next_entry = (++priv->cur_rx) % rxsize; | |
1232 | p_next = priv->dma_rx + next_entry; | |
1233 | prefetch(p_next); | |
1234 | ||
1235 | /* read the status of the incoming frame */ | |
db98a0b0 GC |
1236 | status = (priv->hw->desc->rx_status(&priv->dev->stats, |
1237 | &priv->xstats, p)); | |
47dd7a54 GC |
1238 | if (unlikely(status == discard_frame)) |
1239 | priv->dev->stats.rx_errors++; | |
1240 | else { | |
1241 | struct sk_buff *skb; | |
3eeb2997 | 1242 | int frame_len; |
47dd7a54 | 1243 | |
3eeb2997 GC |
1244 | frame_len = priv->hw->desc->get_rx_frame_len(p); |
1245 | /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 | |
1246 | * Type frames (LLC/LLC-SNAP) */ | |
1247 | if (unlikely(status != llc_snap)) | |
1248 | frame_len -= ETH_FCS_LEN; | |
47dd7a54 GC |
1249 | #ifdef STMMAC_RX_DEBUG |
1250 | if (frame_len > ETH_FRAME_LEN) | |
1251 | pr_debug("\tRX frame size %d, COE status: %d\n", | |
1252 | frame_len, status); | |
1253 | ||
1254 | if (netif_msg_hw(priv)) | |
1255 | pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", | |
1256 | p, entry, p->des2); | |
1257 | #endif | |
1258 | skb = priv->rx_skbuff[entry]; | |
1259 | if (unlikely(!skb)) { | |
1260 | pr_err("%s: Inconsistent Rx descriptor chain\n", | |
1261 | priv->dev->name); | |
1262 | priv->dev->stats.rx_dropped++; | |
1263 | break; | |
1264 | } | |
1265 | prefetch(skb->data - NET_IP_ALIGN); | |
1266 | priv->rx_skbuff[entry] = NULL; | |
1267 | ||
1268 | skb_put(skb, frame_len); | |
1269 | dma_unmap_single(priv->device, | |
1270 | priv->rx_skbuff_dma[entry], | |
1271 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
1272 | #ifdef STMMAC_RX_DEBUG | |
1273 | if (netif_msg_pktdata(priv)) { | |
1274 | pr_info(" frame received (%dbytes)", frame_len); | |
1275 | print_pkt(skb->data, frame_len); | |
1276 | } | |
1277 | #endif | |
1278 | skb->protocol = eth_type_trans(skb, priv->dev); | |
1279 | ||
3c20f72f GC |
1280 | if (unlikely(!priv->rx_coe)) { |
1281 | /* No RX COE for old mac10/100 devices */ | |
bc8acf2c | 1282 | skb_checksum_none_assert(skb); |
47dd7a54 GC |
1283 | netif_receive_skb(skb); |
1284 | } else { | |
1285 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1286 | napi_gro_receive(&priv->napi, skb); | |
1287 | } | |
1288 | ||
1289 | priv->dev->stats.rx_packets++; | |
1290 | priv->dev->stats.rx_bytes += frame_len; | |
47dd7a54 GC |
1291 | } |
1292 | entry = next_entry; | |
1293 | p = p_next; /* use prefetched values */ | |
1294 | } | |
1295 | ||
1296 | stmmac_rx_refill(priv); | |
1297 | ||
1298 | priv->xstats.rx_pkt_n += count; | |
1299 | ||
1300 | return count; | |
1301 | } | |
1302 | ||
1303 | /** | |
1304 | * stmmac_poll - stmmac poll method (NAPI) | |
1305 | * @napi : pointer to the napi structure. | |
1306 | * @budget : maximum number of packets that the current CPU can receive from | |
1307 | * all interfaces. | |
1308 | * Description : | |
1309 | * This function implements the the reception process. | |
1310 | * Also it runs the TX completion thread | |
1311 | */ | |
1312 | static int stmmac_poll(struct napi_struct *napi, int budget) | |
1313 | { | |
1314 | struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); | |
1315 | int work_done = 0; | |
1316 | ||
1317 | priv->xstats.poll_n++; | |
1318 | stmmac_tx(priv); | |
1319 | work_done = stmmac_rx(priv, budget); | |
1320 | ||
1321 | if (work_done < budget) { | |
1322 | napi_complete(napi); | |
1323 | stmmac_enable_irq(priv); | |
1324 | } | |
1325 | return work_done; | |
1326 | } | |
1327 | ||
1328 | /** | |
1329 | * stmmac_tx_timeout | |
1330 | * @dev : Pointer to net device structure | |
1331 | * Description: this function is called when a packet transmission fails to | |
1332 | * complete within a reasonable tmrate. The driver will mark the error in the | |
1333 | * netdev structure and arrange for the device to be reset to a sane state | |
1334 | * in order to transmit a new packet. | |
1335 | */ | |
1336 | static void stmmac_tx_timeout(struct net_device *dev) | |
1337 | { | |
1338 | struct stmmac_priv *priv = netdev_priv(dev); | |
1339 | ||
1340 | /* Clear Tx resources and restart transmitting again */ | |
1341 | stmmac_tx_err(priv); | |
47dd7a54 GC |
1342 | } |
1343 | ||
1344 | /* Configuration changes (passed on by ifconfig) */ | |
1345 | static int stmmac_config(struct net_device *dev, struct ifmap *map) | |
1346 | { | |
1347 | if (dev->flags & IFF_UP) /* can't act on a running interface */ | |
1348 | return -EBUSY; | |
1349 | ||
1350 | /* Don't allow changing the I/O address */ | |
1351 | if (map->base_addr != dev->base_addr) { | |
1352 | pr_warning("%s: can't change I/O address\n", dev->name); | |
1353 | return -EOPNOTSUPP; | |
1354 | } | |
1355 | ||
1356 | /* Don't allow changing the IRQ */ | |
1357 | if (map->irq != dev->irq) { | |
1358 | pr_warning("%s: can't change IRQ number %d\n", | |
1359 | dev->name, dev->irq); | |
1360 | return -EOPNOTSUPP; | |
1361 | } | |
1362 | ||
1363 | /* ignore other fields */ | |
1364 | return 0; | |
1365 | } | |
1366 | ||
1367 | /** | |
01789349 | 1368 | * stmmac_set_rx_mode - entry point for multicast addressing |
47dd7a54 GC |
1369 | * @dev : pointer to the device structure |
1370 | * Description: | |
1371 | * This function is a driver entry point which gets called by the kernel | |
1372 | * whenever multicast addresses must be enabled/disabled. | |
1373 | * Return value: | |
1374 | * void. | |
1375 | */ | |
01789349 | 1376 | static void stmmac_set_rx_mode(struct net_device *dev) |
47dd7a54 GC |
1377 | { |
1378 | struct stmmac_priv *priv = netdev_priv(dev); | |
1379 | ||
1380 | spin_lock(&priv->lock); | |
db98a0b0 | 1381 | priv->hw->mac->set_filter(dev); |
47dd7a54 | 1382 | spin_unlock(&priv->lock); |
47dd7a54 GC |
1383 | } |
1384 | ||
1385 | /** | |
1386 | * stmmac_change_mtu - entry point to change MTU size for the device. | |
1387 | * @dev : device pointer. | |
1388 | * @new_mtu : the new MTU size for the device. | |
1389 | * Description: the Maximum Transfer Unit (MTU) is used by the network layer | |
1390 | * to drive packet transmission. Ethernet has an MTU of 1500 octets | |
1391 | * (ETH_DATA_LEN). This value can be changed with ifconfig. | |
1392 | * Return value: | |
1393 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1394 | * file on failure. | |
1395 | */ | |
1396 | static int stmmac_change_mtu(struct net_device *dev, int new_mtu) | |
1397 | { | |
1398 | struct stmmac_priv *priv = netdev_priv(dev); | |
1399 | int max_mtu; | |
1400 | ||
1401 | if (netif_running(dev)) { | |
1402 | pr_err("%s: must be stopped to change its MTU\n", dev->name); | |
1403 | return -EBUSY; | |
1404 | } | |
1405 | ||
48febf7e | 1406 | if (priv->plat->enh_desc) |
47dd7a54 GC |
1407 | max_mtu = JUMBO_LEN; |
1408 | else | |
45db81e1 | 1409 | max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); |
47dd7a54 GC |
1410 | |
1411 | if ((new_mtu < 46) || (new_mtu > max_mtu)) { | |
1412 | pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); | |
1413 | return -EINVAL; | |
1414 | } | |
1415 | ||
5e982f3b MM |
1416 | dev->mtu = new_mtu; |
1417 | netdev_update_features(dev); | |
1418 | ||
1419 | return 0; | |
1420 | } | |
1421 | ||
c8f44aff MM |
1422 | static netdev_features_t stmmac_fix_features(struct net_device *dev, |
1423 | netdev_features_t features) | |
5e982f3b MM |
1424 | { |
1425 | struct stmmac_priv *priv = netdev_priv(dev); | |
1426 | ||
1427 | if (!priv->rx_coe) | |
1428 | features &= ~NETIF_F_RXCSUM; | |
1429 | if (!priv->plat->tx_coe) | |
1430 | features &= ~NETIF_F_ALL_CSUM; | |
1431 | ||
ebbb293f GC |
1432 | /* Some GMAC devices have a bugged Jumbo frame support that |
1433 | * needs to have the Tx COE disabled for oversized frames | |
1434 | * (due to limited buffer sizes). In this case we disable | |
1435 | * the TX csum insertionin the TDES and not use SF. */ | |
5e982f3b MM |
1436 | if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) |
1437 | features &= ~NETIF_F_ALL_CSUM; | |
ebbb293f | 1438 | |
5e982f3b | 1439 | return features; |
47dd7a54 GC |
1440 | } |
1441 | ||
1442 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id) | |
1443 | { | |
1444 | struct net_device *dev = (struct net_device *)dev_id; | |
1445 | struct stmmac_priv *priv = netdev_priv(dev); | |
1446 | ||
1447 | if (unlikely(!dev)) { | |
1448 | pr_err("%s: invalid dev pointer\n", __func__); | |
1449 | return IRQ_NONE; | |
1450 | } | |
1451 | ||
9dfeb4d9 | 1452 | if (priv->plat->has_gmac) |
47dd7a54 | 1453 | /* To handle GMAC own interrupts */ |
ad01b7d4 | 1454 | priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr); |
aec7ff27 GC |
1455 | |
1456 | stmmac_dma_interrupt(priv); | |
47dd7a54 GC |
1457 | |
1458 | return IRQ_HANDLED; | |
1459 | } | |
1460 | ||
1461 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1462 | /* Polling receive - used by NETCONSOLE and other diagnostic tools | |
1463 | * to allow network I/O with interrupts disabled. */ | |
1464 | static void stmmac_poll_controller(struct net_device *dev) | |
1465 | { | |
1466 | disable_irq(dev->irq); | |
1467 | stmmac_interrupt(dev->irq, dev); | |
1468 | enable_irq(dev->irq); | |
1469 | } | |
1470 | #endif | |
1471 | ||
1472 | /** | |
1473 | * stmmac_ioctl - Entry point for the Ioctl | |
1474 | * @dev: Device pointer. | |
1475 | * @rq: An IOCTL specefic structure, that can contain a pointer to | |
1476 | * a proprietary structure used to pass information to the driver. | |
1477 | * @cmd: IOCTL command | |
1478 | * Description: | |
1479 | * Currently there are no special functionality supported in IOCTL, just the | |
1480 | * phy_mii_ioctl(...) can be invoked. | |
1481 | */ | |
1482 | static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1483 | { | |
1484 | struct stmmac_priv *priv = netdev_priv(dev); | |
28b04113 | 1485 | int ret; |
47dd7a54 GC |
1486 | |
1487 | if (!netif_running(dev)) | |
1488 | return -EINVAL; | |
1489 | ||
28b04113 RC |
1490 | if (!priv->phydev) |
1491 | return -EINVAL; | |
1492 | ||
1493 | spin_lock(&priv->lock); | |
1494 | ret = phy_mii_ioctl(priv->phydev, rq, cmd); | |
1495 | spin_unlock(&priv->lock); | |
1496 | ||
47dd7a54 GC |
1497 | return ret; |
1498 | } | |
1499 | ||
7ac29055 GC |
1500 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1501 | static struct dentry *stmmac_fs_dir; | |
1502 | static struct dentry *stmmac_rings_status; | |
e7434821 | 1503 | static struct dentry *stmmac_dma_cap; |
7ac29055 GC |
1504 | |
1505 | static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) | |
1506 | { | |
1507 | struct tmp_s { | |
1508 | u64 a; | |
1509 | unsigned int b; | |
1510 | unsigned int c; | |
1511 | }; | |
1512 | int i; | |
1513 | struct net_device *dev = seq->private; | |
1514 | struct stmmac_priv *priv = netdev_priv(dev); | |
1515 | ||
1516 | seq_printf(seq, "=======================\n"); | |
1517 | seq_printf(seq, " RX descriptor ring\n"); | |
1518 | seq_printf(seq, "=======================\n"); | |
1519 | ||
1520 | for (i = 0; i < priv->dma_rx_size; i++) { | |
1521 | struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i); | |
1522 | seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
1523 | i, (unsigned int)(x->a), | |
1524 | (unsigned int)((x->a) >> 32), x->b, x->c); | |
1525 | seq_printf(seq, "\n"); | |
1526 | } | |
1527 | ||
1528 | seq_printf(seq, "\n"); | |
1529 | seq_printf(seq, "=======================\n"); | |
1530 | seq_printf(seq, " TX descriptor ring\n"); | |
1531 | seq_printf(seq, "=======================\n"); | |
1532 | ||
1533 | for (i = 0; i < priv->dma_tx_size; i++) { | |
1534 | struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i); | |
1535 | seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", | |
1536 | i, (unsigned int)(x->a), | |
1537 | (unsigned int)((x->a) >> 32), x->b, x->c); | |
1538 | seq_printf(seq, "\n"); | |
1539 | } | |
1540 | ||
1541 | return 0; | |
1542 | } | |
1543 | ||
1544 | static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) | |
1545 | { | |
1546 | return single_open(file, stmmac_sysfs_ring_read, inode->i_private); | |
1547 | } | |
1548 | ||
1549 | static const struct file_operations stmmac_rings_status_fops = { | |
1550 | .owner = THIS_MODULE, | |
1551 | .open = stmmac_sysfs_ring_open, | |
1552 | .read = seq_read, | |
1553 | .llseek = seq_lseek, | |
1554 | .release = seq_release, | |
1555 | }; | |
1556 | ||
e7434821 GC |
1557 | static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) |
1558 | { | |
1559 | struct net_device *dev = seq->private; | |
1560 | struct stmmac_priv *priv = netdev_priv(dev); | |
1561 | ||
1562 | if (!stmmac_get_hw_features(priv)) { | |
1563 | seq_printf(seq, "DMA HW features not supported\n"); | |
1564 | return 0; | |
1565 | } | |
1566 | ||
1567 | seq_printf(seq, "==============================\n"); | |
1568 | seq_printf(seq, "\tDMA HW features\n"); | |
1569 | seq_printf(seq, "==============================\n"); | |
1570 | ||
1571 | seq_printf(seq, "\t10/100 Mbps %s\n", | |
1572 | (priv->dma_cap.mbps_10_100) ? "Y" : "N"); | |
1573 | seq_printf(seq, "\t1000 Mbps %s\n", | |
1574 | (priv->dma_cap.mbps_1000) ? "Y" : "N"); | |
1575 | seq_printf(seq, "\tHalf duple %s\n", | |
1576 | (priv->dma_cap.half_duplex) ? "Y" : "N"); | |
1577 | seq_printf(seq, "\tHash Filter: %s\n", | |
1578 | (priv->dma_cap.hash_filter) ? "Y" : "N"); | |
1579 | seq_printf(seq, "\tMultiple MAC address registers: %s\n", | |
1580 | (priv->dma_cap.multi_addr) ? "Y" : "N"); | |
1581 | seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", | |
1582 | (priv->dma_cap.pcs) ? "Y" : "N"); | |
1583 | seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", | |
1584 | (priv->dma_cap.sma_mdio) ? "Y" : "N"); | |
1585 | seq_printf(seq, "\tPMT Remote wake up: %s\n", | |
1586 | (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); | |
1587 | seq_printf(seq, "\tPMT Magic Frame: %s\n", | |
1588 | (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); | |
1589 | seq_printf(seq, "\tRMON module: %s\n", | |
1590 | (priv->dma_cap.rmon) ? "Y" : "N"); | |
1591 | seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", | |
1592 | (priv->dma_cap.time_stamp) ? "Y" : "N"); | |
1593 | seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", | |
1594 | (priv->dma_cap.atime_stamp) ? "Y" : "N"); | |
1595 | seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", | |
1596 | (priv->dma_cap.eee) ? "Y" : "N"); | |
1597 | seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); | |
1598 | seq_printf(seq, "\tChecksum Offload in TX: %s\n", | |
1599 | (priv->dma_cap.tx_coe) ? "Y" : "N"); | |
1600 | seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", | |
1601 | (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); | |
1602 | seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", | |
1603 | (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); | |
1604 | seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", | |
1605 | (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); | |
1606 | seq_printf(seq, "\tNumber of Additional RX channel: %d\n", | |
1607 | priv->dma_cap.number_rx_channel); | |
1608 | seq_printf(seq, "\tNumber of Additional TX channel: %d\n", | |
1609 | priv->dma_cap.number_tx_channel); | |
1610 | seq_printf(seq, "\tEnhanced descriptors: %s\n", | |
1611 | (priv->dma_cap.enh_desc) ? "Y" : "N"); | |
1612 | ||
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) | |
1617 | { | |
1618 | return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); | |
1619 | } | |
1620 | ||
1621 | static const struct file_operations stmmac_dma_cap_fops = { | |
1622 | .owner = THIS_MODULE, | |
1623 | .open = stmmac_sysfs_dma_cap_open, | |
1624 | .read = seq_read, | |
1625 | .llseek = seq_lseek, | |
1626 | .release = seq_release, | |
1627 | }; | |
1628 | ||
7ac29055 GC |
1629 | static int stmmac_init_fs(struct net_device *dev) |
1630 | { | |
1631 | /* Create debugfs entries */ | |
1632 | stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); | |
1633 | ||
1634 | if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { | |
1635 | pr_err("ERROR %s, debugfs create directory failed\n", | |
1636 | STMMAC_RESOURCE_NAME); | |
1637 | ||
1638 | return -ENOMEM; | |
1639 | } | |
1640 | ||
1641 | /* Entry to report DMA RX/TX rings */ | |
1642 | stmmac_rings_status = debugfs_create_file("descriptors_status", | |
1643 | S_IRUGO, stmmac_fs_dir, dev, | |
1644 | &stmmac_rings_status_fops); | |
1645 | ||
1646 | if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { | |
1647 | pr_info("ERROR creating stmmac ring debugfs file\n"); | |
1648 | debugfs_remove(stmmac_fs_dir); | |
1649 | ||
1650 | return -ENOMEM; | |
1651 | } | |
1652 | ||
e7434821 GC |
1653 | /* Entry to report the DMA HW features */ |
1654 | stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, | |
1655 | dev, &stmmac_dma_cap_fops); | |
1656 | ||
1657 | if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { | |
1658 | pr_info("ERROR creating stmmac MMC debugfs file\n"); | |
1659 | debugfs_remove(stmmac_rings_status); | |
1660 | debugfs_remove(stmmac_fs_dir); | |
1661 | ||
1662 | return -ENOMEM; | |
1663 | } | |
1664 | ||
7ac29055 GC |
1665 | return 0; |
1666 | } | |
1667 | ||
1668 | static void stmmac_exit_fs(void) | |
1669 | { | |
1670 | debugfs_remove(stmmac_rings_status); | |
e7434821 | 1671 | debugfs_remove(stmmac_dma_cap); |
7ac29055 GC |
1672 | debugfs_remove(stmmac_fs_dir); |
1673 | } | |
1674 | #endif /* CONFIG_STMMAC_DEBUG_FS */ | |
1675 | ||
47dd7a54 GC |
1676 | static const struct net_device_ops stmmac_netdev_ops = { |
1677 | .ndo_open = stmmac_open, | |
1678 | .ndo_start_xmit = stmmac_xmit, | |
1679 | .ndo_stop = stmmac_release, | |
1680 | .ndo_change_mtu = stmmac_change_mtu, | |
5e982f3b | 1681 | .ndo_fix_features = stmmac_fix_features, |
01789349 | 1682 | .ndo_set_rx_mode = stmmac_set_rx_mode, |
47dd7a54 GC |
1683 | .ndo_tx_timeout = stmmac_tx_timeout, |
1684 | .ndo_do_ioctl = stmmac_ioctl, | |
1685 | .ndo_set_config = stmmac_config, | |
47dd7a54 GC |
1686 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1687 | .ndo_poll_controller = stmmac_poll_controller, | |
1688 | #endif | |
1689 | .ndo_set_mac_address = eth_mac_addr, | |
1690 | }; | |
1691 | ||
1692 | /** | |
1693 | * stmmac_probe - Initialization of the adapter . | |
1694 | * @dev : device pointer | |
1695 | * Description: The function initializes the network device structure for | |
1696 | * the STMMAC driver. It also calls the low level routines | |
1697 | * in order to init the HW (i.e. the DMA engine) | |
1698 | */ | |
1699 | static int stmmac_probe(struct net_device *dev) | |
1700 | { | |
1701 | int ret = 0; | |
1702 | struct stmmac_priv *priv = netdev_priv(dev); | |
1703 | ||
1704 | ether_setup(dev); | |
1705 | ||
1706 | dev->netdev_ops = &stmmac_netdev_ops; | |
1707 | stmmac_set_ethtool_ops(dev); | |
1708 | ||
5e982f3b MM |
1709 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; |
1710 | dev->features |= dev->hw_features | NETIF_F_HIGHDMA; | |
47dd7a54 GC |
1711 | dev->watchdog_timeo = msecs_to_jiffies(watchdog); |
1712 | #ifdef STMMAC_VLAN_TAG_USED | |
1713 | /* Both mac100 and gmac support receive VLAN tag detection */ | |
1714 | dev->features |= NETIF_F_HW_VLAN_RX; | |
1715 | #endif | |
1716 | priv->msg_enable = netif_msg_init(debug, default_msg_level); | |
1717 | ||
47dd7a54 GC |
1718 | if (flow_ctrl) |
1719 | priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ | |
1720 | ||
1721 | priv->pause = pause; | |
1722 | netif_napi_add(dev, &priv->napi, stmmac_poll, 64); | |
1723 | ||
1724 | /* Get the MAC address */ | |
ad01b7d4 GC |
1725 | priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr, |
1726 | dev->dev_addr, 0); | |
47dd7a54 GC |
1727 | |
1728 | if (!is_valid_ether_addr(dev->dev_addr)) | |
1729 | pr_warning("\tno valid MAC address;" | |
1730 | "please, use ifconfig or nwhwconfig!\n"); | |
1731 | ||
f8e96161 | 1732 | spin_lock_init(&priv->lock); |
a9097a96 | 1733 | spin_lock_init(&priv->tx_lock); |
f8e96161 | 1734 | |
47dd7a54 GC |
1735 | ret = register_netdev(dev); |
1736 | if (ret) { | |
1737 | pr_err("%s: ERROR %i registering the device\n", | |
1738 | __func__, ret); | |
1739 | return -ENODEV; | |
1740 | } | |
1741 | ||
1742 | DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n", | |
1743 | dev->name, (dev->features & NETIF_F_SG) ? "on" : "off", | |
79032644 | 1744 | (dev->features & NETIF_F_IP_CSUM) ? "on" : "off"); |
47dd7a54 | 1745 | |
47dd7a54 GC |
1746 | return ret; |
1747 | } | |
1748 | ||
1749 | /** | |
1750 | * stmmac_mac_device_setup | |
1751 | * @dev : device pointer | |
1752 | * Description: select and initialise the mac device (mac100 or Gmac). | |
1753 | */ | |
1754 | static int stmmac_mac_device_setup(struct net_device *dev) | |
1755 | { | |
1756 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
1757 | |
1758 | struct mac_device_info *device; | |
1759 | ||
01789349 JP |
1760 | if (priv->plat->has_gmac) { |
1761 | dev->priv_flags |= IFF_UNICAST_FLT; | |
ad01b7d4 | 1762 | device = dwmac1000_setup(priv->ioaddr); |
01789349 | 1763 | } else { |
ad01b7d4 | 1764 | device = dwmac100_setup(priv->ioaddr); |
01789349 | 1765 | } |
3d90c508 | 1766 | |
1ff21906 DC |
1767 | if (!device) |
1768 | return -ENOMEM; | |
1769 | ||
9dfeb4d9 | 1770 | if (priv->plat->enh_desc) { |
3d90c508 GC |
1771 | device->desc = &enh_desc_ops; |
1772 | pr_info("\tEnhanced descriptor structure\n"); | |
1773 | } else | |
56b106ae | 1774 | device->desc = &ndesc_ops; |
47dd7a54 | 1775 | |
db98a0b0 | 1776 | priv->hw = device; |
286a8372 | 1777 | priv->hw->ring = &ring_mode_ops; |
47dd7a54 | 1778 | |
539c9aa5 | 1779 | if (device_can_wakeup(priv->device)) { |
543876c9 | 1780 | priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */ |
3172d3af | 1781 | enable_irq_wake(priv->wol_irq); |
539c9aa5 | 1782 | } |
47dd7a54 GC |
1783 | |
1784 | return 0; | |
1785 | } | |
1786 | ||
47dd7a54 GC |
1787 | /** |
1788 | * stmmac_dvr_probe | |
1789 | * @pdev: platform device pointer | |
1790 | * Description: the driver is initialized through platform_device. | |
1791 | */ | |
1792 | static int stmmac_dvr_probe(struct platform_device *pdev) | |
1793 | { | |
1794 | int ret = 0; | |
1795 | struct resource *res; | |
ad01b7d4 | 1796 | void __iomem *addr = NULL; |
47dd7a54 | 1797 | struct net_device *ndev = NULL; |
293bb1c4 | 1798 | struct stmmac_priv *priv = NULL; |
47dd7a54 GC |
1799 | struct plat_stmmacenet_data *plat_dat; |
1800 | ||
1801 | pr_info("STMMAC driver:\n\tplatform registration... "); | |
1802 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
34a52f36 DC |
1803 | if (!res) |
1804 | return -ENODEV; | |
ebbb293f | 1805 | pr_info("\tdone!\n"); |
47dd7a54 | 1806 | |
b6222682 | 1807 | if (!request_mem_region(res->start, resource_size(res), |
47dd7a54 GC |
1808 | pdev->name)) { |
1809 | pr_err("%s: ERROR: memory allocation failed" | |
1810 | "cannot get the I/O addr 0x%x\n", | |
1811 | __func__, (unsigned int)res->start); | |
34a52f36 | 1812 | return -EBUSY; |
47dd7a54 GC |
1813 | } |
1814 | ||
7c5365bc | 1815 | addr = ioremap(res->start, resource_size(res)); |
47dd7a54 | 1816 | if (!addr) { |
7c5365bc | 1817 | pr_err("%s: ERROR: memory mapping failed\n", __func__); |
47dd7a54 | 1818 | ret = -ENOMEM; |
34a52f36 | 1819 | goto out_release_region; |
47dd7a54 GC |
1820 | } |
1821 | ||
1822 | ndev = alloc_etherdev(sizeof(struct stmmac_priv)); | |
1823 | if (!ndev) { | |
1824 | pr_err("%s: ERROR: allocating the device\n", __func__); | |
1825 | ret = -ENOMEM; | |
34a52f36 | 1826 | goto out_unmap; |
47dd7a54 GC |
1827 | } |
1828 | ||
1829 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1830 | ||
1831 | /* Get the MAC information */ | |
1832 | ndev->irq = platform_get_irq_byname(pdev, "macirq"); | |
1833 | if (ndev->irq == -ENXIO) { | |
1834 | pr_err("%s: ERROR: MAC IRQ configuration " | |
1835 | "information not found\n", __func__); | |
34a52f36 DC |
1836 | ret = -ENXIO; |
1837 | goto out_free_ndev; | |
47dd7a54 GC |
1838 | } |
1839 | ||
1840 | priv = netdev_priv(ndev); | |
1841 | priv->device = &(pdev->dev); | |
1842 | priv->dev = ndev; | |
ee7946a7 | 1843 | plat_dat = pdev->dev.platform_data; |
9dfeb4d9 GC |
1844 | |
1845 | priv->plat = plat_dat; | |
1846 | ||
ad01b7d4 | 1847 | priv->ioaddr = addr; |
47dd7a54 | 1848 | |
543876c9 GC |
1849 | /* PMT module is not integrated in all the MAC devices. */ |
1850 | if (plat_dat->pmt) { | |
1851 | pr_info("\tPMT module supported\n"); | |
1852 | device_set_wakeup_capable(&pdev->dev, 1); | |
1853 | } | |
3172d3af DS |
1854 | /* |
1855 | * On some platforms e.g. SPEAr the wake up irq differs from the mac irq | |
1856 | * The external wake up irq can be passed through the platform code | |
1857 | * named as "eth_wake_irq" | |
1858 | * | |
1859 | * In case the wake up interrupt is not passed from the platform | |
1860 | * so the driver will continue to use the mac irq (ndev->irq) | |
1861 | */ | |
1862 | priv->wol_irq = platform_get_irq_byname(pdev, "eth_wake_irq"); | |
1863 | if (priv->wol_irq == -ENXIO) | |
1864 | priv->wol_irq = ndev->irq; | |
1865 | ||
543876c9 | 1866 | |
47dd7a54 GC |
1867 | platform_set_drvdata(pdev, ndev); |
1868 | ||
1869 | /* Set the I/O base addr */ | |
1870 | ndev->base_addr = (unsigned long)addr; | |
1871 | ||
293bb1c4 GC |
1872 | /* Custom initialisation */ |
1873 | if (priv->plat->init) { | |
1874 | ret = priv->plat->init(pdev); | |
1875 | if (unlikely(ret)) | |
34a52f36 | 1876 | goto out_free_ndev; |
293bb1c4 | 1877 | } |
ee7946a7 | 1878 | |
47dd7a54 GC |
1879 | /* MAC HW revice detection */ |
1880 | ret = stmmac_mac_device_setup(ndev); | |
1881 | if (ret < 0) | |
34a52f36 | 1882 | goto out_plat_exit; |
47dd7a54 GC |
1883 | |
1884 | /* Network Device Registration */ | |
1885 | ret = stmmac_probe(ndev); | |
1886 | if (ret < 0) | |
34a52f36 | 1887 | goto out_plat_exit; |
47dd7a54 | 1888 | |
36bcfe7d GC |
1889 | /* Override with kernel parameters if supplied XXX CRS XXX |
1890 | * this needs to have multiple instances */ | |
1891 | if ((phyaddr >= 0) && (phyaddr <= 31)) | |
1892 | priv->plat->phy_addr = phyaddr; | |
47dd7a54 | 1893 | |
47dd7a54 | 1894 | pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n" |
1f0f6388 DM |
1895 | "\tIO base addr: 0x%p)\n", ndev->name, pdev->name, |
1896 | pdev->id, ndev->irq, addr); | |
47dd7a54 GC |
1897 | |
1898 | /* MDIO bus Registration */ | |
9dfeb4d9 | 1899 | pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id); |
47dd7a54 GC |
1900 | ret = stmmac_mdio_register(ndev); |
1901 | if (ret < 0) | |
34a52f36 | 1902 | goto out_unregister; |
47dd7a54 | 1903 | pr_debug("registered!\n"); |
7ac29055 GC |
1904 | |
1905 | #ifdef CONFIG_STMMAC_DEBUG_FS | |
1906 | ret = stmmac_init_fs(ndev); | |
1907 | if (ret < 0) | |
1908 | pr_warning("\tFailed debugFS registration"); | |
1909 | #endif | |
1910 | ||
34a52f36 | 1911 | return 0; |
47dd7a54 | 1912 | |
34a52f36 DC |
1913 | out_unregister: |
1914 | unregister_netdev(ndev); | |
1915 | out_plat_exit: | |
1916 | if (priv->plat->exit) | |
1917 | priv->plat->exit(pdev); | |
1918 | out_free_ndev: | |
1919 | free_netdev(ndev); | |
1920 | platform_set_drvdata(pdev, NULL); | |
1921 | out_unmap: | |
1922 | iounmap(addr); | |
1923 | out_release_region: | |
1924 | release_mem_region(res->start, resource_size(res)); | |
47dd7a54 GC |
1925 | |
1926 | return ret; | |
1927 | } | |
1928 | ||
1929 | /** | |
1930 | * stmmac_dvr_remove | |
1931 | * @pdev: platform device pointer | |
1932 | * Description: this function resets the TX/RX processes, disables the MAC RX/TX | |
1933 | * changes the link status, releases the DMA descriptor rings, | |
1934 | * unregisters the MDIO bus and unmaps the allocated memory. | |
1935 | */ | |
1936 | static int stmmac_dvr_remove(struct platform_device *pdev) | |
1937 | { | |
1938 | struct net_device *ndev = platform_get_drvdata(pdev); | |
aec7ff27 | 1939 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 GC |
1940 | struct resource *res; |
1941 | ||
1942 | pr_info("%s:\n\tremoving driver", __func__); | |
1943 | ||
ad01b7d4 GC |
1944 | priv->hw->dma->stop_rx(priv->ioaddr); |
1945 | priv->hw->dma->stop_tx(priv->ioaddr); | |
47dd7a54 | 1946 | |
19449bfc | 1947 | stmmac_disable_mac(priv->ioaddr); |
47dd7a54 GC |
1948 | |
1949 | netif_carrier_off(ndev); | |
1950 | ||
1951 | stmmac_mdio_unregister(ndev); | |
1952 | ||
293bb1c4 GC |
1953 | if (priv->plat->exit) |
1954 | priv->plat->exit(pdev); | |
1955 | ||
47dd7a54 GC |
1956 | platform_set_drvdata(pdev, NULL); |
1957 | unregister_netdev(ndev); | |
1958 | ||
ad01b7d4 | 1959 | iounmap((void *)priv->ioaddr); |
47dd7a54 | 1960 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
7c5365bc | 1961 | release_mem_region(res->start, resource_size(res)); |
47dd7a54 | 1962 | |
7ac29055 GC |
1963 | #ifdef CONFIG_STMMAC_DEBUG_FS |
1964 | stmmac_exit_fs(); | |
1965 | #endif | |
1966 | ||
47dd7a54 GC |
1967 | free_netdev(ndev); |
1968 | ||
1969 | return 0; | |
1970 | } | |
1971 | ||
1972 | #ifdef CONFIG_PM | |
874bd42d | 1973 | static int stmmac_suspend(struct device *dev) |
47dd7a54 | 1974 | { |
874bd42d GC |
1975 | struct net_device *ndev = dev_get_drvdata(dev); |
1976 | struct stmmac_priv *priv = netdev_priv(ndev); | |
47dd7a54 GC |
1977 | int dis_ic = 0; |
1978 | ||
874bd42d | 1979 | if (!ndev || !netif_running(ndev)) |
47dd7a54 GC |
1980 | return 0; |
1981 | ||
1982 | spin_lock(&priv->lock); | |
1983 | ||
874bd42d GC |
1984 | netif_device_detach(ndev); |
1985 | netif_stop_queue(ndev); | |
1986 | if (priv->phydev) | |
1987 | phy_stop(priv->phydev); | |
47dd7a54 GC |
1988 | |
1989 | #ifdef CONFIG_STMMAC_TIMER | |
874bd42d GC |
1990 | priv->tm->timer_stop(); |
1991 | if (likely(priv->tm->enable)) | |
1992 | dis_ic = 1; | |
47dd7a54 | 1993 | #endif |
874bd42d GC |
1994 | napi_disable(&priv->napi); |
1995 | ||
1996 | /* Stop TX/RX DMA */ | |
1997 | priv->hw->dma->stop_tx(priv->ioaddr); | |
1998 | priv->hw->dma->stop_rx(priv->ioaddr); | |
1999 | /* Clear the Rx/Tx descriptors */ | |
2000 | priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size, | |
2001 | dis_ic); | |
2002 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); | |
2003 | ||
2004 | /* Enable Power down mode by programming the PMT regs */ | |
2005 | if (device_may_wakeup(priv->device)) | |
2006 | priv->hw->mac->pmt(priv->ioaddr, priv->wolopts); | |
2007 | else | |
2008 | stmmac_disable_mac(priv->ioaddr); | |
47dd7a54 GC |
2009 | |
2010 | spin_unlock(&priv->lock); | |
2011 | return 0; | |
2012 | } | |
2013 | ||
874bd42d | 2014 | static int stmmac_resume(struct device *dev) |
47dd7a54 | 2015 | { |
874bd42d GC |
2016 | struct net_device *ndev = dev_get_drvdata(dev); |
2017 | struct stmmac_priv *priv = netdev_priv(ndev); | |
47dd7a54 | 2018 | |
874bd42d | 2019 | if (!netif_running(ndev)) |
47dd7a54 GC |
2020 | return 0; |
2021 | ||
c4433be6 GC |
2022 | spin_lock(&priv->lock); |
2023 | ||
47dd7a54 GC |
2024 | /* Power Down bit, into the PM register, is cleared |
2025 | * automatically as soon as a magic packet or a Wake-up frame | |
2026 | * is received. Anyway, it's better to manually clear | |
2027 | * this bit because it can generate problems while resuming | |
2028 | * from another devices (e.g. serial console). */ | |
874bd42d | 2029 | if (device_may_wakeup(priv->device)) |
543876c9 | 2030 | priv->hw->mac->pmt(priv->ioaddr, 0); |
47dd7a54 | 2031 | |
874bd42d | 2032 | netif_device_attach(ndev); |
47dd7a54 GC |
2033 | |
2034 | /* Enable the MAC and DMA */ | |
19449bfc | 2035 | stmmac_enable_mac(priv->ioaddr); |
ad01b7d4 GC |
2036 | priv->hw->dma->start_tx(priv->ioaddr); |
2037 | priv->hw->dma->start_rx(priv->ioaddr); | |
47dd7a54 GC |
2038 | |
2039 | #ifdef CONFIG_STMMAC_TIMER | |
874bd42d GC |
2040 | if (likely(priv->tm->enable)) |
2041 | priv->tm->timer_start(tmrate); | |
47dd7a54 GC |
2042 | #endif |
2043 | napi_enable(&priv->napi); | |
2044 | ||
2045 | if (priv->phydev) | |
2046 | phy_start(priv->phydev); | |
2047 | ||
874bd42d | 2048 | netif_start_queue(ndev); |
47dd7a54 | 2049 | |
47dd7a54 GC |
2050 | spin_unlock(&priv->lock); |
2051 | return 0; | |
2052 | } | |
47dd7a54 | 2053 | |
874bd42d GC |
2054 | static int stmmac_freeze(struct device *dev) |
2055 | { | |
2056 | struct net_device *ndev = dev_get_drvdata(dev); | |
2057 | ||
2058 | if (!ndev || !netif_running(ndev)) | |
2059 | return 0; | |
2060 | ||
2061 | return stmmac_release(ndev); | |
2062 | } | |
2063 | ||
2064 | static int stmmac_restore(struct device *dev) | |
2065 | { | |
2066 | struct net_device *ndev = dev_get_drvdata(dev); | |
2067 | ||
2068 | if (!ndev || !netif_running(ndev)) | |
2069 | return 0; | |
2070 | ||
2071 | return stmmac_open(ndev); | |
2072 | } | |
2073 | ||
2074 | static const struct dev_pm_ops stmmac_pm_ops = { | |
47dd7a54 GC |
2075 | .suspend = stmmac_suspend, |
2076 | .resume = stmmac_resume, | |
874bd42d GC |
2077 | .freeze = stmmac_freeze, |
2078 | .thaw = stmmac_restore, | |
2079 | .restore = stmmac_restore, | |
2080 | }; | |
2081 | #else | |
2082 | static const struct dev_pm_ops stmmac_pm_ops; | |
2083 | #endif /* CONFIG_PM */ | |
47dd7a54 | 2084 | |
874bd42d GC |
2085 | static struct platform_driver stmmac_driver = { |
2086 | .probe = stmmac_dvr_probe, | |
2087 | .remove = stmmac_dvr_remove, | |
2088 | .driver = { | |
2089 | .name = STMMAC_RESOURCE_NAME, | |
2090 | .owner = THIS_MODULE, | |
2091 | .pm = &stmmac_pm_ops, | |
2092 | }, | |
47dd7a54 GC |
2093 | }; |
2094 | ||
2095 | /** | |
2096 | * stmmac_init_module - Entry point for the driver | |
2097 | * Description: This function is the entry point for the driver. | |
2098 | */ | |
2099 | static int __init stmmac_init_module(void) | |
2100 | { | |
2101 | int ret; | |
2102 | ||
47dd7a54 GC |
2103 | ret = platform_driver_register(&stmmac_driver); |
2104 | return ret; | |
2105 | } | |
2106 | ||
2107 | /** | |
2108 | * stmmac_cleanup_module - Cleanup routine for the driver | |
2109 | * Description: This function is the cleanup routine for the driver. | |
2110 | */ | |
2111 | static void __exit stmmac_cleanup_module(void) | |
2112 | { | |
47dd7a54 GC |
2113 | platform_driver_unregister(&stmmac_driver); |
2114 | } | |
2115 | ||
2116 | #ifndef MODULE | |
2117 | static int __init stmmac_cmdline_opt(char *str) | |
2118 | { | |
2119 | char *opt; | |
2120 | ||
2121 | if (!str || !*str) | |
2122 | return -EINVAL; | |
2123 | while ((opt = strsep(&str, ",")) != NULL) { | |
f3240e28 GC |
2124 | if (!strncmp(opt, "debug:", 6)) { |
2125 | if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug)) | |
2126 | goto err; | |
2127 | } else if (!strncmp(opt, "phyaddr:", 8)) { | |
2128 | if (strict_strtoul(opt + 8, 0, | |
2129 | (unsigned long *)&phyaddr)) | |
2130 | goto err; | |
2131 | } else if (!strncmp(opt, "dma_txsize:", 11)) { | |
2132 | if (strict_strtoul(opt + 11, 0, | |
2133 | (unsigned long *)&dma_txsize)) | |
2134 | goto err; | |
2135 | } else if (!strncmp(opt, "dma_rxsize:", 11)) { | |
2136 | if (strict_strtoul(opt + 11, 0, | |
2137 | (unsigned long *)&dma_rxsize)) | |
2138 | goto err; | |
2139 | } else if (!strncmp(opt, "buf_sz:", 7)) { | |
2140 | if (strict_strtoul(opt + 7, 0, | |
2141 | (unsigned long *)&buf_sz)) | |
2142 | goto err; | |
2143 | } else if (!strncmp(opt, "tc:", 3)) { | |
2144 | if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc)) | |
2145 | goto err; | |
2146 | } else if (!strncmp(opt, "watchdog:", 9)) { | |
2147 | if (strict_strtoul(opt + 9, 0, | |
2148 | (unsigned long *)&watchdog)) | |
2149 | goto err; | |
2150 | } else if (!strncmp(opt, "flow_ctrl:", 10)) { | |
2151 | if (strict_strtoul(opt + 10, 0, | |
2152 | (unsigned long *)&flow_ctrl)) | |
2153 | goto err; | |
2154 | } else if (!strncmp(opt, "pause:", 6)) { | |
2155 | if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause)) | |
2156 | goto err; | |
47dd7a54 | 2157 | #ifdef CONFIG_STMMAC_TIMER |
f3240e28 GC |
2158 | } else if (!strncmp(opt, "tmrate:", 7)) { |
2159 | if (strict_strtoul(opt + 7, 0, | |
2160 | (unsigned long *)&tmrate)) | |
2161 | goto err; | |
47dd7a54 | 2162 | #endif |
f3240e28 | 2163 | } |
47dd7a54 GC |
2164 | } |
2165 | return 0; | |
f3240e28 GC |
2166 | |
2167 | err: | |
2168 | pr_err("%s: ERROR broken module parameter conversion", __func__); | |
2169 | return -EINVAL; | |
47dd7a54 GC |
2170 | } |
2171 | ||
2172 | __setup("stmmaceth=", stmmac_cmdline_opt); | |
2173 | #endif | |
2174 | ||
2175 | module_init(stmmac_init_module); | |
2176 | module_exit(stmmac_cleanup_module); | |
2177 | ||
2178 | MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver"); | |
2179 | MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); | |
2180 | MODULE_LICENSE("GPL"); |