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47dd7a54 GC |
1 | /******************************************************************************* |
2 | This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. | |
3 | ST Ethernet IPs are built around a Synopsys IP Core. | |
4 | ||
286a8372 | 5 | Copyright(C) 2007-2011 STMicroelectronics Ltd |
47dd7a54 GC |
6 | |
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
24 | ||
25 | Documentation available at: | |
26 | http://www.stlinux.com | |
27 | Support available at: | |
28 | https://bugzilla.stlinux.com/ | |
29 | *******************************************************************************/ | |
30 | ||
6a81c26f | 31 | #include <linux/clk.h> |
47dd7a54 GC |
32 | #include <linux/kernel.h> |
33 | #include <linux/interrupt.h> | |
47dd7a54 GC |
34 | #include <linux/ip.h> |
35 | #include <linux/tcp.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/ethtool.h> | |
38 | #include <linux/if_ether.h> | |
39 | #include <linux/crc32.h> | |
40 | #include <linux/mii.h> | |
01789349 | 41 | #include <linux/if.h> |
47dd7a54 GC |
42 | #include <linux/if_vlan.h> |
43 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 44 | #include <linux/slab.h> |
70c71606 | 45 | #include <linux/prefetch.h> |
db88f10a | 46 | #include <linux/pinctrl/consumer.h> |
50fb4f74 | 47 | #ifdef CONFIG_DEBUG_FS |
7ac29055 GC |
48 | #include <linux/debugfs.h> |
49 | #include <linux/seq_file.h> | |
50fb4f74 | 50 | #endif /* CONFIG_DEBUG_FS */ |
891434b1 RK |
51 | #include <linux/net_tstamp.h> |
52 | #include "stmmac_ptp.h" | |
286a8372 | 53 | #include "stmmac.h" |
c5e4ddbd | 54 | #include <linux/reset.h> |
5790cf3c | 55 | #include <linux/of_mdio.h> |
19d857c9 | 56 | #include "dwmac1000.h" |
47dd7a54 | 57 | |
47dd7a54 | 58 | #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) |
f748be53 | 59 | #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) |
47dd7a54 GC |
60 | |
61 | /* Module parameters */ | |
32ceabca | 62 | #define TX_TIMEO 5000 |
47dd7a54 GC |
63 | static int watchdog = TX_TIMEO; |
64 | module_param(watchdog, int, S_IRUGO | S_IWUSR); | |
32ceabca | 65 | MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); |
47dd7a54 | 66 | |
32ceabca | 67 | static int debug = -1; |
47dd7a54 | 68 | module_param(debug, int, S_IRUGO | S_IWUSR); |
32ceabca | 69 | MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); |
47dd7a54 | 70 | |
47d1f71f | 71 | static int phyaddr = -1; |
47dd7a54 GC |
72 | module_param(phyaddr, int, S_IRUGO); |
73 | MODULE_PARM_DESC(phyaddr, "Physical device address"); | |
74 | ||
e3ad57c9 | 75 | #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) |
120e87f9 | 76 | #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) |
47dd7a54 GC |
77 | |
78 | static int flow_ctrl = FLOW_OFF; | |
79 | module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); | |
80 | MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); | |
81 | ||
82 | static int pause = PAUSE_TIME; | |
83 | module_param(pause, int, S_IRUGO | S_IWUSR); | |
84 | MODULE_PARM_DESC(pause, "Flow Control Pause Time"); | |
85 | ||
86 | #define TC_DEFAULT 64 | |
87 | static int tc = TC_DEFAULT; | |
88 | module_param(tc, int, S_IRUGO | S_IWUSR); | |
89 | MODULE_PARM_DESC(tc, "DMA threshold control value"); | |
90 | ||
d916701c GC |
91 | #define DEFAULT_BUFSIZE 1536 |
92 | static int buf_sz = DEFAULT_BUFSIZE; | |
47dd7a54 GC |
93 | module_param(buf_sz, int, S_IRUGO | S_IWUSR); |
94 | MODULE_PARM_DESC(buf_sz, "DMA buffer size"); | |
95 | ||
22ad3838 GC |
96 | #define STMMAC_RX_COPYBREAK 256 |
97 | ||
47dd7a54 GC |
98 | static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
99 | NETIF_MSG_LINK | NETIF_MSG_IFUP | | |
100 | NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); | |
101 | ||
d765955d GC |
102 | #define STMMAC_DEFAULT_LPI_TIMER 1000 |
103 | static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; | |
104 | module_param(eee_timer, int, S_IRUGO | S_IWUSR); | |
105 | MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); | |
f5351ef7 | 106 | #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) |
d765955d | 107 | |
22d3efe5 PM |
108 | /* By default the driver will use the ring mode to manage tx and rx descriptors, |
109 | * but allow user to force to use the chain instead of the ring | |
4a7d666a GC |
110 | */ |
111 | static unsigned int chain_mode; | |
112 | module_param(chain_mode, int, S_IRUGO); | |
113 | MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); | |
114 | ||
47dd7a54 | 115 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id); |
47dd7a54 | 116 | |
50fb4f74 | 117 | #ifdef CONFIG_DEBUG_FS |
bfab27a1 | 118 | static int stmmac_init_fs(struct net_device *dev); |
466c5ac8 | 119 | static void stmmac_exit_fs(struct net_device *dev); |
bfab27a1 GC |
120 | #endif |
121 | ||
9125cdd1 GC |
122 | #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) |
123 | ||
47dd7a54 GC |
124 | /** |
125 | * stmmac_verify_args - verify the driver parameters. | |
732fdf0e GC |
126 | * Description: it checks the driver parameters and set a default in case of |
127 | * errors. | |
47dd7a54 GC |
128 | */ |
129 | static void stmmac_verify_args(void) | |
130 | { | |
131 | if (unlikely(watchdog < 0)) | |
132 | watchdog = TX_TIMEO; | |
d916701c GC |
133 | if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) |
134 | buf_sz = DEFAULT_BUFSIZE; | |
47dd7a54 GC |
135 | if (unlikely(flow_ctrl > 1)) |
136 | flow_ctrl = FLOW_AUTO; | |
137 | else if (likely(flow_ctrl < 0)) | |
138 | flow_ctrl = FLOW_OFF; | |
139 | if (unlikely((pause < 0) || (pause > 0xffff))) | |
140 | pause = PAUSE_TIME; | |
d765955d GC |
141 | if (eee_timer < 0) |
142 | eee_timer = STMMAC_DEFAULT_LPI_TIMER; | |
47dd7a54 GC |
143 | } |
144 | ||
32ceabca GC |
145 | /** |
146 | * stmmac_clk_csr_set - dynamically set the MDC clock | |
147 | * @priv: driver private structure | |
148 | * Description: this is to dynamically set the MDC clock according to the csr | |
149 | * clock input. | |
150 | * Note: | |
151 | * If a specific clk_csr value is passed from the platform | |
152 | * this means that the CSR Clock Range selection cannot be | |
153 | * changed at run-time and it is fixed (as reported in the driver | |
154 | * documentation). Viceversa the driver will try to set the MDC | |
155 | * clock dynamically according to the actual clock input. | |
156 | */ | |
cd7201f4 GC |
157 | static void stmmac_clk_csr_set(struct stmmac_priv *priv) |
158 | { | |
cd7201f4 GC |
159 | u32 clk_rate; |
160 | ||
161 | clk_rate = clk_get_rate(priv->stmmac_clk); | |
162 | ||
163 | /* Platform provided default clk_csr would be assumed valid | |
ceb69499 GC |
164 | * for all other cases except for the below mentioned ones. |
165 | * For values higher than the IEEE 802.3 specified frequency | |
166 | * we can not estimate the proper divider as it is not known | |
167 | * the frequency of clk_csr_i. So we do not change the default | |
168 | * divider. | |
169 | */ | |
cd7201f4 GC |
170 | if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { |
171 | if (clk_rate < CSR_F_35M) | |
172 | priv->clk_csr = STMMAC_CSR_20_35M; | |
173 | else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) | |
174 | priv->clk_csr = STMMAC_CSR_35_60M; | |
175 | else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) | |
176 | priv->clk_csr = STMMAC_CSR_60_100M; | |
177 | else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) | |
178 | priv->clk_csr = STMMAC_CSR_100_150M; | |
179 | else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) | |
180 | priv->clk_csr = STMMAC_CSR_150_250M; | |
19d857c9 | 181 | else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) |
cd7201f4 | 182 | priv->clk_csr = STMMAC_CSR_250_300M; |
ceb69499 | 183 | } |
cd7201f4 GC |
184 | } |
185 | ||
47dd7a54 GC |
186 | static void print_pkt(unsigned char *buf, int len) |
187 | { | |
424c4f78 AS |
188 | pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); |
189 | print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); | |
47dd7a54 | 190 | } |
47dd7a54 | 191 | |
47dd7a54 GC |
192 | static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) |
193 | { | |
e3ad57c9 GC |
194 | unsigned avail; |
195 | ||
196 | if (priv->dirty_tx > priv->cur_tx) | |
197 | avail = priv->dirty_tx - priv->cur_tx - 1; | |
198 | else | |
199 | avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1; | |
200 | ||
201 | return avail; | |
202 | } | |
203 | ||
204 | static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv) | |
205 | { | |
206 | unsigned dirty; | |
207 | ||
208 | if (priv->dirty_rx <= priv->cur_rx) | |
209 | dirty = priv->cur_rx - priv->dirty_rx; | |
210 | else | |
211 | dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx; | |
212 | ||
213 | return dirty; | |
47dd7a54 GC |
214 | } |
215 | ||
32ceabca | 216 | /** |
732fdf0e | 217 | * stmmac_hw_fix_mac_speed - callback for speed selection |
32ceabca GC |
218 | * @priv: driver private structure |
219 | * Description: on some platforms (e.g. ST), some HW system configuraton | |
220 | * registers have to be set according to the link speed negotiated. | |
9dfeb4d9 GC |
221 | */ |
222 | static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) | |
223 | { | |
d6d50c7e PR |
224 | struct net_device *ndev = priv->dev; |
225 | struct phy_device *phydev = ndev->phydev; | |
9dfeb4d9 GC |
226 | |
227 | if (likely(priv->plat->fix_mac_speed)) | |
ceb69499 | 228 | priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); |
9dfeb4d9 GC |
229 | } |
230 | ||
32ceabca | 231 | /** |
732fdf0e | 232 | * stmmac_enable_eee_mode - check and enter in LPI mode |
32ceabca | 233 | * @priv: driver private structure |
732fdf0e GC |
234 | * Description: this function is to verify and enter in LPI mode in case of |
235 | * EEE. | |
32ceabca | 236 | */ |
d765955d GC |
237 | static void stmmac_enable_eee_mode(struct stmmac_priv *priv) |
238 | { | |
239 | /* Check and enter in LPI mode */ | |
240 | if ((priv->dirty_tx == priv->cur_tx) && | |
241 | (priv->tx_path_in_lpi_mode == false)) | |
7ed24bbe | 242 | priv->hw->mac->set_eee_mode(priv->hw); |
d765955d GC |
243 | } |
244 | ||
32ceabca | 245 | /** |
732fdf0e | 246 | * stmmac_disable_eee_mode - disable and exit from LPI mode |
32ceabca GC |
247 | * @priv: driver private structure |
248 | * Description: this function is to exit and disable EEE in case of | |
249 | * LPI state is true. This is called by the xmit. | |
250 | */ | |
d765955d GC |
251 | void stmmac_disable_eee_mode(struct stmmac_priv *priv) |
252 | { | |
7ed24bbe | 253 | priv->hw->mac->reset_eee_mode(priv->hw); |
d765955d GC |
254 | del_timer_sync(&priv->eee_ctrl_timer); |
255 | priv->tx_path_in_lpi_mode = false; | |
256 | } | |
257 | ||
258 | /** | |
732fdf0e | 259 | * stmmac_eee_ctrl_timer - EEE TX SW timer. |
d765955d GC |
260 | * @arg : data hook |
261 | * Description: | |
32ceabca | 262 | * if there is no data transfer and if we are not in LPI state, |
d765955d GC |
263 | * then MAC Transmitter can be moved to LPI state. |
264 | */ | |
265 | static void stmmac_eee_ctrl_timer(unsigned long arg) | |
266 | { | |
267 | struct stmmac_priv *priv = (struct stmmac_priv *)arg; | |
268 | ||
269 | stmmac_enable_eee_mode(priv); | |
f5351ef7 | 270 | mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
d765955d GC |
271 | } |
272 | ||
273 | /** | |
732fdf0e | 274 | * stmmac_eee_init - init EEE |
32ceabca | 275 | * @priv: driver private structure |
d765955d | 276 | * Description: |
732fdf0e GC |
277 | * if the GMAC supports the EEE (from the HW cap reg) and the phy device |
278 | * can also manage EEE, this function enable the LPI state and start related | |
279 | * timer. | |
d765955d GC |
280 | */ |
281 | bool stmmac_eee_init(struct stmmac_priv *priv) | |
282 | { | |
d6d50c7e | 283 | struct net_device *ndev = priv->dev; |
4741cf9c | 284 | unsigned long flags; |
d765955d GC |
285 | bool ret = false; |
286 | ||
f5351ef7 GC |
287 | /* Using PCS we cannot dial with the phy registers at this stage |
288 | * so we do not support extra feature like EEE. | |
289 | */ | |
3fe5cadb GC |
290 | if ((priv->hw->pcs == STMMAC_PCS_RGMII) || |
291 | (priv->hw->pcs == STMMAC_PCS_TBI) || | |
292 | (priv->hw->pcs == STMMAC_PCS_RTBI)) | |
f5351ef7 GC |
293 | goto out; |
294 | ||
d765955d GC |
295 | /* MAC core supports the EEE feature. */ |
296 | if (priv->dma_cap.eee) { | |
83bf79b6 GC |
297 | int tx_lpi_timer = priv->tx_lpi_timer; |
298 | ||
d765955d | 299 | /* Check if the PHY supports EEE */ |
d6d50c7e | 300 | if (phy_init_eee(ndev->phydev, 1)) { |
83bf79b6 GC |
301 | /* To manage at run-time if the EEE cannot be supported |
302 | * anymore (for example because the lp caps have been | |
303 | * changed). | |
304 | * In that case the driver disable own timers. | |
305 | */ | |
4741cf9c | 306 | spin_lock_irqsave(&priv->lock, flags); |
83bf79b6 | 307 | if (priv->eee_active) { |
38ddc59d | 308 | netdev_dbg(priv->dev, "disable EEE\n"); |
83bf79b6 | 309 | del_timer_sync(&priv->eee_ctrl_timer); |
7ed24bbe | 310 | priv->hw->mac->set_eee_timer(priv->hw, 0, |
83bf79b6 GC |
311 | tx_lpi_timer); |
312 | } | |
313 | priv->eee_active = 0; | |
4741cf9c | 314 | spin_unlock_irqrestore(&priv->lock, flags); |
d765955d | 315 | goto out; |
83bf79b6 GC |
316 | } |
317 | /* Activate the EEE and start timers */ | |
4741cf9c | 318 | spin_lock_irqsave(&priv->lock, flags); |
f5351ef7 GC |
319 | if (!priv->eee_active) { |
320 | priv->eee_active = 1; | |
ccb36da1 VT |
321 | setup_timer(&priv->eee_ctrl_timer, |
322 | stmmac_eee_ctrl_timer, | |
323 | (unsigned long)priv); | |
324 | mod_timer(&priv->eee_ctrl_timer, | |
325 | STMMAC_LPI_T(eee_timer)); | |
f5351ef7 | 326 | |
7ed24bbe | 327 | priv->hw->mac->set_eee_timer(priv->hw, |
f5351ef7 | 328 | STMMAC_DEFAULT_LIT_LS, |
83bf79b6 | 329 | tx_lpi_timer); |
71965352 GC |
330 | } |
331 | /* Set HW EEE according to the speed */ | |
d6d50c7e | 332 | priv->hw->mac->set_eee_pls(priv->hw, ndev->phydev->link); |
d765955d | 333 | |
d765955d | 334 | ret = true; |
4741cf9c GC |
335 | spin_unlock_irqrestore(&priv->lock, flags); |
336 | ||
38ddc59d | 337 | netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); |
d765955d GC |
338 | } |
339 | out: | |
340 | return ret; | |
341 | } | |
342 | ||
732fdf0e | 343 | /* stmmac_get_tx_hwtstamp - get HW TX timestamps |
32ceabca | 344 | * @priv: driver private structure |
ba1ffd74 | 345 | * @p : descriptor pointer |
891434b1 RK |
346 | * @skb : the socket buffer |
347 | * Description : | |
348 | * This function will read timestamp from the descriptor & pass it to stack. | |
349 | * and also perform some sanity checks. | |
350 | */ | |
351 | static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, | |
ba1ffd74 | 352 | struct dma_desc *p, struct sk_buff *skb) |
891434b1 RK |
353 | { |
354 | struct skb_shared_hwtstamps shhwtstamp; | |
355 | u64 ns; | |
891434b1 RK |
356 | |
357 | if (!priv->hwts_tx_en) | |
358 | return; | |
359 | ||
ceb69499 | 360 | /* exit if skb doesn't support hw tstamp */ |
75e4364f | 361 | if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) |
891434b1 RK |
362 | return; |
363 | ||
891434b1 | 364 | /* check tx tstamp status */ |
ba1ffd74 GC |
365 | if (!priv->hw->desc->get_tx_timestamp_status(p)) { |
366 | /* get the valid tstamp */ | |
367 | ns = priv->hw->desc->get_timestamp(p, priv->adv_ts); | |
891434b1 | 368 | |
ba1ffd74 GC |
369 | memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); |
370 | shhwtstamp.hwtstamp = ns_to_ktime(ns); | |
891434b1 | 371 | |
ba1ffd74 GC |
372 | netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns); |
373 | /* pass tstamp to stack */ | |
374 | skb_tstamp_tx(skb, &shhwtstamp); | |
375 | } | |
891434b1 RK |
376 | |
377 | return; | |
378 | } | |
379 | ||
732fdf0e | 380 | /* stmmac_get_rx_hwtstamp - get HW RX timestamps |
32ceabca | 381 | * @priv: driver private structure |
ba1ffd74 GC |
382 | * @p : descriptor pointer |
383 | * @np : next descriptor pointer | |
891434b1 RK |
384 | * @skb : the socket buffer |
385 | * Description : | |
386 | * This function will read received packet's timestamp from the descriptor | |
387 | * and pass it to stack. It also perform some sanity checks. | |
388 | */ | |
ba1ffd74 GC |
389 | static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, |
390 | struct dma_desc *np, struct sk_buff *skb) | |
891434b1 RK |
391 | { |
392 | struct skb_shared_hwtstamps *shhwtstamp = NULL; | |
393 | u64 ns; | |
891434b1 RK |
394 | |
395 | if (!priv->hwts_rx_en) | |
396 | return; | |
397 | ||
ba1ffd74 GC |
398 | /* Check if timestamp is available */ |
399 | if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) { | |
400 | /* For GMAC4, the valid timestamp is from CTX next desc. */ | |
401 | if (priv->plat->has_gmac4) | |
402 | ns = priv->hw->desc->get_timestamp(np, priv->adv_ts); | |
403 | else | |
404 | ns = priv->hw->desc->get_timestamp(p, priv->adv_ts); | |
891434b1 | 405 | |
ba1ffd74 GC |
406 | netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns); |
407 | shhwtstamp = skb_hwtstamps(skb); | |
408 | memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); | |
409 | shhwtstamp->hwtstamp = ns_to_ktime(ns); | |
410 | } else { | |
411 | netdev_err(priv->dev, "cannot get RX hw timestamp\n"); | |
412 | } | |
891434b1 RK |
413 | } |
414 | ||
415 | /** | |
416 | * stmmac_hwtstamp_ioctl - control hardware timestamping. | |
417 | * @dev: device pointer. | |
418 | * @ifr: An IOCTL specefic structure, that can contain a pointer to | |
419 | * a proprietary structure used to pass information to the driver. | |
420 | * Description: | |
421 | * This function configures the MAC to enable/disable both outgoing(TX) | |
422 | * and incoming(RX) packets time stamping based on user input. | |
423 | * Return Value: | |
424 | * 0 on success and an appropriate -ve integer on failure. | |
425 | */ | |
426 | static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) | |
427 | { | |
428 | struct stmmac_priv *priv = netdev_priv(dev); | |
429 | struct hwtstamp_config config; | |
0a624155 | 430 | struct timespec64 now; |
891434b1 RK |
431 | u64 temp = 0; |
432 | u32 ptp_v2 = 0; | |
433 | u32 tstamp_all = 0; | |
434 | u32 ptp_over_ipv4_udp = 0; | |
435 | u32 ptp_over_ipv6_udp = 0; | |
436 | u32 ptp_over_ethernet = 0; | |
437 | u32 snap_type_sel = 0; | |
438 | u32 ts_master_en = 0; | |
439 | u32 ts_event_en = 0; | |
440 | u32 value = 0; | |
19d857c9 | 441 | u32 sec_inc; |
891434b1 RK |
442 | |
443 | if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { | |
444 | netdev_alert(priv->dev, "No support for HW time stamping\n"); | |
445 | priv->hwts_tx_en = 0; | |
446 | priv->hwts_rx_en = 0; | |
447 | ||
448 | return -EOPNOTSUPP; | |
449 | } | |
450 | ||
451 | if (copy_from_user(&config, ifr->ifr_data, | |
ceb69499 | 452 | sizeof(struct hwtstamp_config))) |
891434b1 RK |
453 | return -EFAULT; |
454 | ||
38ddc59d LC |
455 | netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", |
456 | __func__, config.flags, config.tx_type, config.rx_filter); | |
891434b1 RK |
457 | |
458 | /* reserved for future extensions */ | |
459 | if (config.flags) | |
460 | return -EINVAL; | |
461 | ||
5f3da328 BH |
462 | if (config.tx_type != HWTSTAMP_TX_OFF && |
463 | config.tx_type != HWTSTAMP_TX_ON) | |
891434b1 | 464 | return -ERANGE; |
891434b1 RK |
465 | |
466 | if (priv->adv_ts) { | |
467 | switch (config.rx_filter) { | |
891434b1 | 468 | case HWTSTAMP_FILTER_NONE: |
ceb69499 | 469 | /* time stamp no incoming packet at all */ |
891434b1 RK |
470 | config.rx_filter = HWTSTAMP_FILTER_NONE; |
471 | break; | |
472 | ||
891434b1 | 473 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: |
ceb69499 | 474 | /* PTP v1, UDP, any kind of event packet */ |
891434b1 RK |
475 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; |
476 | /* take time stamp for all event messages */ | |
477 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
478 | ||
479 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
480 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
481 | break; | |
482 | ||
891434b1 | 483 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
ceb69499 | 484 | /* PTP v1, UDP, Sync packet */ |
891434b1 RK |
485 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; |
486 | /* take time stamp for SYNC messages only */ | |
487 | ts_event_en = PTP_TCR_TSEVNTENA; | |
488 | ||
489 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
490 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
491 | break; | |
492 | ||
891434b1 | 493 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
ceb69499 | 494 | /* PTP v1, UDP, Delay_req packet */ |
891434b1 RK |
495 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; |
496 | /* take time stamp for Delay_Req messages only */ | |
497 | ts_master_en = PTP_TCR_TSMSTRENA; | |
498 | ts_event_en = PTP_TCR_TSEVNTENA; | |
499 | ||
500 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
501 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
502 | break; | |
503 | ||
891434b1 | 504 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: |
ceb69499 | 505 | /* PTP v2, UDP, any kind of event packet */ |
891434b1 RK |
506 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; |
507 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
508 | /* take time stamp for all event messages */ | |
509 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
510 | ||
511 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
512 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
513 | break; | |
514 | ||
891434b1 | 515 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: |
ceb69499 | 516 | /* PTP v2, UDP, Sync packet */ |
891434b1 RK |
517 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; |
518 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
519 | /* take time stamp for SYNC messages only */ | |
520 | ts_event_en = PTP_TCR_TSEVNTENA; | |
521 | ||
522 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
523 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
524 | break; | |
525 | ||
891434b1 | 526 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: |
ceb69499 | 527 | /* PTP v2, UDP, Delay_req packet */ |
891434b1 RK |
528 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; |
529 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
530 | /* take time stamp for Delay_Req messages only */ | |
531 | ts_master_en = PTP_TCR_TSMSTRENA; | |
532 | ts_event_en = PTP_TCR_TSEVNTENA; | |
533 | ||
534 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
535 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
536 | break; | |
537 | ||
891434b1 | 538 | case HWTSTAMP_FILTER_PTP_V2_EVENT: |
ceb69499 | 539 | /* PTP v2/802.AS1 any layer, any kind of event packet */ |
891434b1 RK |
540 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
541 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
542 | /* take time stamp for all event messages */ | |
543 | snap_type_sel = PTP_TCR_SNAPTYPSEL_1; | |
544 | ||
545 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
546 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
547 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
548 | break; | |
549 | ||
891434b1 | 550 | case HWTSTAMP_FILTER_PTP_V2_SYNC: |
ceb69499 | 551 | /* PTP v2/802.AS1, any layer, Sync packet */ |
891434b1 RK |
552 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; |
553 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
554 | /* take time stamp for SYNC messages only */ | |
555 | ts_event_en = PTP_TCR_TSEVNTENA; | |
556 | ||
557 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
558 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
559 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
560 | break; | |
561 | ||
891434b1 | 562 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: |
ceb69499 | 563 | /* PTP v2/802.AS1, any layer, Delay_req packet */ |
891434b1 RK |
564 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; |
565 | ptp_v2 = PTP_TCR_TSVER2ENA; | |
566 | /* take time stamp for Delay_Req messages only */ | |
567 | ts_master_en = PTP_TCR_TSMSTRENA; | |
568 | ts_event_en = PTP_TCR_TSEVNTENA; | |
569 | ||
570 | ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; | |
571 | ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; | |
572 | ptp_over_ethernet = PTP_TCR_TSIPENA; | |
573 | break; | |
574 | ||
891434b1 | 575 | case HWTSTAMP_FILTER_ALL: |
ceb69499 | 576 | /* time stamp any incoming packet */ |
891434b1 RK |
577 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
578 | tstamp_all = PTP_TCR_TSENALL; | |
579 | break; | |
580 | ||
581 | default: | |
582 | return -ERANGE; | |
583 | } | |
584 | } else { | |
585 | switch (config.rx_filter) { | |
586 | case HWTSTAMP_FILTER_NONE: | |
587 | config.rx_filter = HWTSTAMP_FILTER_NONE; | |
588 | break; | |
589 | default: | |
590 | /* PTP v1, UDP, any kind of event packet */ | |
591 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; | |
592 | break; | |
593 | } | |
594 | } | |
595 | priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); | |
5f3da328 | 596 | priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; |
891434b1 RK |
597 | |
598 | if (!priv->hwts_tx_en && !priv->hwts_rx_en) | |
ba1ffd74 | 599 | priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0); |
891434b1 RK |
600 | else { |
601 | value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | | |
ceb69499 GC |
602 | tstamp_all | ptp_v2 | ptp_over_ethernet | |
603 | ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | | |
604 | ts_master_en | snap_type_sel); | |
ba1ffd74 | 605 | priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value); |
891434b1 RK |
606 | |
607 | /* program Sub Second Increment reg */ | |
19d857c9 | 608 | sec_inc = priv->hw->ptp->config_sub_second_increment( |
ba1ffd74 GC |
609 | priv->ptpaddr, priv->clk_ptp_rate, |
610 | priv->plat->has_gmac4); | |
19d857c9 | 611 | temp = div_u64(1000000000ULL, sec_inc); |
891434b1 RK |
612 | |
613 | /* calculate default added value: | |
614 | * formula is : | |
615 | * addend = (2^32)/freq_div_ratio; | |
19d857c9 | 616 | * where, freq_div_ratio = 1e9ns/sec_inc |
891434b1 | 617 | */ |
19d857c9 | 618 | temp = (u64)(temp << 32); |
5566401f | 619 | priv->default_addend = div_u64(temp, priv->clk_ptp_rate); |
ba1ffd74 | 620 | priv->hw->ptp->config_addend(priv->ptpaddr, |
891434b1 RK |
621 | priv->default_addend); |
622 | ||
623 | /* initialize system time */ | |
0a624155 AB |
624 | ktime_get_real_ts64(&now); |
625 | ||
626 | /* lower 32 bits of tv_sec are safe until y2106 */ | |
ba1ffd74 | 627 | priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec, |
891434b1 RK |
628 | now.tv_nsec); |
629 | } | |
630 | ||
631 | return copy_to_user(ifr->ifr_data, &config, | |
632 | sizeof(struct hwtstamp_config)) ? -EFAULT : 0; | |
633 | } | |
634 | ||
32ceabca | 635 | /** |
732fdf0e | 636 | * stmmac_init_ptp - init PTP |
32ceabca | 637 | * @priv: driver private structure |
732fdf0e | 638 | * Description: this is to verify if the HW supports the PTPv1 or PTPv2. |
32ceabca | 639 | * This is done by looking at the HW cap. register. |
732fdf0e | 640 | * This function also registers the ptp driver. |
32ceabca | 641 | */ |
92ba6888 | 642 | static int stmmac_init_ptp(struct stmmac_priv *priv) |
891434b1 | 643 | { |
92ba6888 RK |
644 | if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) |
645 | return -EOPNOTSUPP; | |
646 | ||
5566401f GC |
647 | /* Fall-back to main clock in case of no PTP ref is passed */ |
648 | priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref"); | |
649 | if (IS_ERR(priv->clk_ptp_ref)) { | |
650 | priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk); | |
651 | priv->clk_ptp_ref = NULL; | |
be9b3174 | 652 | netdev_dbg(priv->dev, "PTP uses main clock\n"); |
5566401f GC |
653 | } else { |
654 | clk_prepare_enable(priv->clk_ptp_ref); | |
655 | priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref); | |
be9b3174 | 656 | netdev_dbg(priv->dev, "PTP rate %d\n", priv->clk_ptp_rate); |
5566401f GC |
657 | } |
658 | ||
7cd01399 | 659 | priv->adv_ts = 0; |
be9b3174 GC |
660 | /* Check if adv_ts can be enabled for dwmac 4.x core */ |
661 | if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp) | |
662 | priv->adv_ts = 1; | |
663 | /* Dwmac 3.x core with extend_desc can support adv_ts */ | |
664 | else if (priv->extend_desc && priv->dma_cap.atime_stamp) | |
7cd01399 VB |
665 | priv->adv_ts = 1; |
666 | ||
be9b3174 GC |
667 | if (priv->dma_cap.time_stamp) |
668 | netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); | |
7cd01399 | 669 | |
be9b3174 GC |
670 | if (priv->adv_ts) |
671 | netdev_info(priv->dev, | |
672 | "IEEE 1588-2008 Advanced Timestamp supported\n"); | |
891434b1 RK |
673 | |
674 | priv->hw->ptp = &stmmac_ptp; | |
675 | priv->hwts_tx_en = 0; | |
676 | priv->hwts_rx_en = 0; | |
92ba6888 | 677 | |
c30a70d3 GC |
678 | stmmac_ptp_register(priv); |
679 | ||
680 | return 0; | |
92ba6888 RK |
681 | } |
682 | ||
683 | static void stmmac_release_ptp(struct stmmac_priv *priv) | |
684 | { | |
5566401f GC |
685 | if (priv->clk_ptp_ref) |
686 | clk_disable_unprepare(priv->clk_ptp_ref); | |
92ba6888 | 687 | stmmac_ptp_unregister(priv); |
891434b1 RK |
688 | } |
689 | ||
47dd7a54 | 690 | /** |
732fdf0e | 691 | * stmmac_adjust_link - adjusts the link parameters |
47dd7a54 | 692 | * @dev: net device structure |
732fdf0e GC |
693 | * Description: this is the helper called by the physical abstraction layer |
694 | * drivers to communicate the phy link status. According the speed and duplex | |
695 | * this driver can invoke registered glue-logic as well. | |
696 | * It also invoke the eee initialization because it could happen when switch | |
697 | * on different networks (that are eee capable). | |
47dd7a54 GC |
698 | */ |
699 | static void stmmac_adjust_link(struct net_device *dev) | |
700 | { | |
701 | struct stmmac_priv *priv = netdev_priv(dev); | |
d6d50c7e | 702 | struct phy_device *phydev = dev->phydev; |
47dd7a54 GC |
703 | unsigned long flags; |
704 | int new_state = 0; | |
705 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; | |
706 | ||
707 | if (phydev == NULL) | |
708 | return; | |
709 | ||
47dd7a54 | 710 | spin_lock_irqsave(&priv->lock, flags); |
d765955d | 711 | |
47dd7a54 | 712 | if (phydev->link) { |
ad01b7d4 | 713 | u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
714 | |
715 | /* Now we make sure that we can be in full duplex mode. | |
716 | * If not, we operate in half-duplex mode. */ | |
717 | if (phydev->duplex != priv->oldduplex) { | |
718 | new_state = 1; | |
719 | if (!(phydev->duplex)) | |
db98a0b0 | 720 | ctrl &= ~priv->hw->link.duplex; |
47dd7a54 | 721 | else |
db98a0b0 | 722 | ctrl |= priv->hw->link.duplex; |
47dd7a54 GC |
723 | priv->oldduplex = phydev->duplex; |
724 | } | |
725 | /* Flow Control operation */ | |
726 | if (phydev->pause) | |
7ed24bbe | 727 | priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, |
db98a0b0 | 728 | fc, pause_time); |
47dd7a54 GC |
729 | |
730 | if (phydev->speed != priv->speed) { | |
731 | new_state = 1; | |
732 | switch (phydev->speed) { | |
733 | case 1000: | |
f748be53 AT |
734 | if (likely((priv->plat->has_gmac) || |
735 | (priv->plat->has_gmac4))) | |
db98a0b0 | 736 | ctrl &= ~priv->hw->link.port; |
ceb69499 | 737 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
738 | break; |
739 | case 100: | |
740 | case 10: | |
f748be53 AT |
741 | if (likely((priv->plat->has_gmac) || |
742 | (priv->plat->has_gmac4))) { | |
db98a0b0 | 743 | ctrl |= priv->hw->link.port; |
47dd7a54 | 744 | if (phydev->speed == SPEED_100) { |
db98a0b0 | 745 | ctrl |= priv->hw->link.speed; |
47dd7a54 | 746 | } else { |
db98a0b0 | 747 | ctrl &= ~(priv->hw->link.speed); |
47dd7a54 GC |
748 | } |
749 | } else { | |
db98a0b0 | 750 | ctrl &= ~priv->hw->link.port; |
47dd7a54 | 751 | } |
9dfeb4d9 | 752 | stmmac_hw_fix_mac_speed(priv); |
47dd7a54 GC |
753 | break; |
754 | default: | |
b3e51069 LC |
755 | netif_warn(priv, link, priv->dev, |
756 | "Speed (%d) not 10/100\n", | |
757 | phydev->speed); | |
47dd7a54 GC |
758 | break; |
759 | } | |
760 | ||
761 | priv->speed = phydev->speed; | |
762 | } | |
763 | ||
ad01b7d4 | 764 | writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
47dd7a54 GC |
765 | |
766 | if (!priv->oldlink) { | |
767 | new_state = 1; | |
768 | priv->oldlink = 1; | |
769 | } | |
770 | } else if (priv->oldlink) { | |
771 | new_state = 1; | |
772 | priv->oldlink = 0; | |
773 | priv->speed = 0; | |
774 | priv->oldduplex = -1; | |
775 | } | |
776 | ||
777 | if (new_state && netif_msg_link(priv)) | |
778 | phy_print_status(phydev); | |
779 | ||
4741cf9c GC |
780 | spin_unlock_irqrestore(&priv->lock, flags); |
781 | ||
52f95bbf GC |
782 | if (phydev->is_pseudo_fixed_link) |
783 | /* Stop PHY layer to call the hook to adjust the link in case | |
784 | * of a switch is attached to the stmmac driver. | |
785 | */ | |
786 | phydev->irq = PHY_IGNORE_INTERRUPT; | |
787 | else | |
788 | /* At this stage, init the EEE if supported. | |
789 | * Never called in case of fixed_link. | |
790 | */ | |
791 | priv->eee_enabled = stmmac_eee_init(priv); | |
47dd7a54 GC |
792 | } |
793 | ||
32ceabca | 794 | /** |
732fdf0e | 795 | * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported |
32ceabca GC |
796 | * @priv: driver private structure |
797 | * Description: this is to verify if the HW supports the PCS. | |
798 | * Physical Coding Sublayer (PCS) interface that can be used when the MAC is | |
799 | * configured for the TBI, RTBI, or SGMII PHY interface. | |
800 | */ | |
e58bb43f GC |
801 | static void stmmac_check_pcs_mode(struct stmmac_priv *priv) |
802 | { | |
803 | int interface = priv->plat->interface; | |
804 | ||
805 | if (priv->dma_cap.pcs) { | |
0d909dcd BA |
806 | if ((interface == PHY_INTERFACE_MODE_RGMII) || |
807 | (interface == PHY_INTERFACE_MODE_RGMII_ID) || | |
808 | (interface == PHY_INTERFACE_MODE_RGMII_RXID) || | |
809 | (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { | |
38ddc59d | 810 | netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); |
3fe5cadb | 811 | priv->hw->pcs = STMMAC_PCS_RGMII; |
0d909dcd | 812 | } else if (interface == PHY_INTERFACE_MODE_SGMII) { |
38ddc59d | 813 | netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); |
3fe5cadb | 814 | priv->hw->pcs = STMMAC_PCS_SGMII; |
e58bb43f GC |
815 | } |
816 | } | |
817 | } | |
818 | ||
47dd7a54 GC |
819 | /** |
820 | * stmmac_init_phy - PHY initialization | |
821 | * @dev: net device structure | |
822 | * Description: it initializes the driver's PHY state, and attaches the PHY | |
823 | * to the mac driver. | |
824 | * Return value: | |
825 | * 0 on success | |
826 | */ | |
827 | static int stmmac_init_phy(struct net_device *dev) | |
828 | { | |
829 | struct stmmac_priv *priv = netdev_priv(dev); | |
830 | struct phy_device *phydev; | |
d765955d | 831 | char phy_id_fmt[MII_BUS_ID_SIZE + 3]; |
109cdd66 | 832 | char bus_id[MII_BUS_ID_SIZE]; |
79ee1dc3 | 833 | int interface = priv->plat->interface; |
9cbadf09 | 834 | int max_speed = priv->plat->max_speed; |
47dd7a54 GC |
835 | priv->oldlink = 0; |
836 | priv->speed = 0; | |
837 | priv->oldduplex = -1; | |
838 | ||
5790cf3c MO |
839 | if (priv->plat->phy_node) { |
840 | phydev = of_phy_connect(dev, priv->plat->phy_node, | |
841 | &stmmac_adjust_link, 0, interface); | |
842 | } else { | |
a7657f12 GC |
843 | snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", |
844 | priv->plat->bus_id); | |
5790cf3c MO |
845 | |
846 | snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, | |
847 | priv->plat->phy_addr); | |
de9a2165 | 848 | netdev_dbg(priv->dev, "%s: trying to attach to %s\n", __func__, |
38ddc59d | 849 | phy_id_fmt); |
5790cf3c MO |
850 | |
851 | phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, | |
852 | interface); | |
853 | } | |
47dd7a54 | 854 | |
dfc50fca | 855 | if (IS_ERR_OR_NULL(phydev)) { |
38ddc59d | 856 | netdev_err(priv->dev, "Could not attach to PHY\n"); |
dfc50fca AB |
857 | if (!phydev) |
858 | return -ENODEV; | |
859 | ||
47dd7a54 GC |
860 | return PTR_ERR(phydev); |
861 | } | |
862 | ||
79ee1dc3 | 863 | /* Stop Advertising 1000BASE Capability if interface is not GMII */ |
c5b9b4e4 | 864 | if ((interface == PHY_INTERFACE_MODE_MII) || |
9cbadf09 | 865 | (interface == PHY_INTERFACE_MODE_RMII) || |
a77e4acc | 866 | (max_speed < 1000 && max_speed > 0)) |
c5b9b4e4 SK |
867 | phydev->advertising &= ~(SUPPORTED_1000baseT_Half | |
868 | SUPPORTED_1000baseT_Full); | |
79ee1dc3 | 869 | |
47dd7a54 GC |
870 | /* |
871 | * Broken HW is sometimes missing the pull-up resistor on the | |
872 | * MDIO line, which results in reads to non-existent devices returning | |
873 | * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent | |
874 | * device as well. | |
875 | * Note: phydev->phy_id is the result of reading the UID PHY registers. | |
876 | */ | |
27732381 | 877 | if (!priv->plat->phy_node && phydev->phy_id == 0) { |
47dd7a54 GC |
878 | phy_disconnect(phydev); |
879 | return -ENODEV; | |
880 | } | |
8e99fc5f | 881 | |
c51e424d FF |
882 | /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid |
883 | * subsequent PHY polling, make sure we force a link transition if | |
884 | * we have a UP/DOWN/UP transition | |
885 | */ | |
886 | if (phydev->is_pseudo_fixed_link) | |
887 | phydev->irq = PHY_POLL; | |
888 | ||
de9a2165 LC |
889 | netdev_dbg(priv->dev, "%s: attached to PHY (UID 0x%x) Link = %d\n", |
890 | __func__, phydev->phy_id, phydev->link); | |
47dd7a54 | 891 | |
47dd7a54 GC |
892 | return 0; |
893 | } | |
894 | ||
c24602ef GC |
895 | static void stmmac_display_rings(struct stmmac_priv *priv) |
896 | { | |
d0225e7d AT |
897 | void *head_rx, *head_tx; |
898 | ||
c24602ef | 899 | if (priv->extend_desc) { |
d0225e7d AT |
900 | head_rx = (void *)priv->dma_erx; |
901 | head_tx = (void *)priv->dma_etx; | |
c24602ef | 902 | } else { |
d0225e7d AT |
903 | head_rx = (void *)priv->dma_rx; |
904 | head_tx = (void *)priv->dma_tx; | |
c24602ef | 905 | } |
d0225e7d AT |
906 | |
907 | /* Display Rx ring */ | |
908 | priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true); | |
909 | /* Display Tx ring */ | |
910 | priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false); | |
c24602ef GC |
911 | } |
912 | ||
286a8372 GC |
913 | static int stmmac_set_bfsize(int mtu, int bufsize) |
914 | { | |
915 | int ret = bufsize; | |
916 | ||
917 | if (mtu >= BUF_SIZE_4KiB) | |
918 | ret = BUF_SIZE_8KiB; | |
919 | else if (mtu >= BUF_SIZE_2KiB) | |
920 | ret = BUF_SIZE_4KiB; | |
d916701c | 921 | else if (mtu > DEFAULT_BUFSIZE) |
286a8372 GC |
922 | ret = BUF_SIZE_2KiB; |
923 | else | |
d916701c | 924 | ret = DEFAULT_BUFSIZE; |
286a8372 GC |
925 | |
926 | return ret; | |
927 | } | |
928 | ||
32ceabca | 929 | /** |
732fdf0e | 930 | * stmmac_clear_descriptors - clear descriptors |
32ceabca GC |
931 | * @priv: driver private structure |
932 | * Description: this function is called to clear the tx and rx descriptors | |
933 | * in case of both basic and extended descriptors are used. | |
934 | */ | |
c24602ef GC |
935 | static void stmmac_clear_descriptors(struct stmmac_priv *priv) |
936 | { | |
937 | int i; | |
c24602ef GC |
938 | |
939 | /* Clear the Rx/Tx descriptors */ | |
e3ad57c9 | 940 | for (i = 0; i < DMA_RX_SIZE; i++) |
c24602ef GC |
941 | if (priv->extend_desc) |
942 | priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, | |
943 | priv->use_riwt, priv->mode, | |
e3ad57c9 | 944 | (i == DMA_RX_SIZE - 1)); |
c24602ef GC |
945 | else |
946 | priv->hw->desc->init_rx_desc(&priv->dma_rx[i], | |
947 | priv->use_riwt, priv->mode, | |
e3ad57c9 GC |
948 | (i == DMA_RX_SIZE - 1)); |
949 | for (i = 0; i < DMA_TX_SIZE; i++) | |
c24602ef GC |
950 | if (priv->extend_desc) |
951 | priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, | |
952 | priv->mode, | |
e3ad57c9 | 953 | (i == DMA_TX_SIZE - 1)); |
c24602ef GC |
954 | else |
955 | priv->hw->desc->init_tx_desc(&priv->dma_tx[i], | |
956 | priv->mode, | |
e3ad57c9 | 957 | (i == DMA_TX_SIZE - 1)); |
c24602ef GC |
958 | } |
959 | ||
732fdf0e GC |
960 | /** |
961 | * stmmac_init_rx_buffers - init the RX descriptor buffer. | |
962 | * @priv: driver private structure | |
963 | * @p: descriptor pointer | |
964 | * @i: descriptor index | |
965 | * @flags: gfp flag. | |
966 | * Description: this function is called to allocate a receive buffer, perform | |
967 | * the DMA mapping and init the descriptor. | |
968 | */ | |
c24602ef | 969 | static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, |
777da230 | 970 | int i, gfp_t flags) |
c24602ef GC |
971 | { |
972 | struct sk_buff *skb; | |
973 | ||
4ec49a37 | 974 | skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags); |
56329137 | 975 | if (!skb) { |
38ddc59d LC |
976 | netdev_err(priv->dev, |
977 | "%s: Rx init fails; skb is NULL\n", __func__); | |
56329137 | 978 | return -ENOMEM; |
c24602ef | 979 | } |
c24602ef GC |
980 | priv->rx_skbuff[i] = skb; |
981 | priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, | |
982 | priv->dma_buf_sz, | |
983 | DMA_FROM_DEVICE); | |
56329137 | 984 | if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { |
38ddc59d | 985 | netdev_err(priv->dev, "%s: DMA mapping error\n", __func__); |
56329137 BZ |
986 | dev_kfree_skb_any(skb); |
987 | return -EINVAL; | |
988 | } | |
c24602ef | 989 | |
f748be53 | 990 | if (priv->synopsys_id >= DWMAC_CORE_4_00) |
f8be0d78 | 991 | p->des0 = cpu_to_le32(priv->rx_skbuff_dma[i]); |
f748be53 | 992 | else |
f8be0d78 | 993 | p->des2 = cpu_to_le32(priv->rx_skbuff_dma[i]); |
c24602ef | 994 | |
29896a67 | 995 | if ((priv->hw->mode->init_desc3) && |
c24602ef | 996 | (priv->dma_buf_sz == BUF_SIZE_16KiB)) |
29896a67 | 997 | priv->hw->mode->init_desc3(p); |
c24602ef GC |
998 | |
999 | return 0; | |
1000 | } | |
1001 | ||
56329137 BZ |
1002 | static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) |
1003 | { | |
1004 | if (priv->rx_skbuff[i]) { | |
1005 | dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], | |
1006 | priv->dma_buf_sz, DMA_FROM_DEVICE); | |
1007 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
1008 | } | |
1009 | priv->rx_skbuff[i] = NULL; | |
1010 | } | |
1011 | ||
47dd7a54 GC |
1012 | /** |
1013 | * init_dma_desc_rings - init the RX/TX descriptor rings | |
1014 | * @dev: net device structure | |
732fdf0e GC |
1015 | * @flags: gfp flag. |
1016 | * Description: this function initializes the DMA RX/TX descriptors | |
286a8372 GC |
1017 | * and allocates the socket buffers. It suppors the chained and ring |
1018 | * modes. | |
47dd7a54 | 1019 | */ |
777da230 | 1020 | static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) |
47dd7a54 GC |
1021 | { |
1022 | int i; | |
1023 | struct stmmac_priv *priv = netdev_priv(dev); | |
4a7d666a | 1024 | unsigned int bfsize = 0; |
56329137 | 1025 | int ret = -ENOMEM; |
47dd7a54 | 1026 | |
29896a67 GC |
1027 | if (priv->hw->mode->set_16kib_bfsize) |
1028 | bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); | |
286a8372 | 1029 | |
4a7d666a | 1030 | if (bfsize < BUF_SIZE_16KiB) |
286a8372 | 1031 | bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); |
47dd7a54 | 1032 | |
2618abb7 VB |
1033 | priv->dma_buf_sz = bfsize; |
1034 | ||
b3e51069 LC |
1035 | netif_dbg(priv, probe, priv->dev, |
1036 | "(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", | |
1037 | __func__, (u32)priv->dma_rx_phy, (u32)priv->dma_tx_phy); | |
1038 | ||
1039 | /* RX INITIALIZATION */ | |
1040 | netif_dbg(priv, probe, priv->dev, | |
1041 | "SKB addresses:\nskb\t\tskb data\tdma data\n"); | |
47dd7a54 | 1042 | |
e3ad57c9 | 1043 | for (i = 0; i < DMA_RX_SIZE; i++) { |
c24602ef GC |
1044 | struct dma_desc *p; |
1045 | if (priv->extend_desc) | |
1046 | p = &((priv->dma_erx + i)->basic); | |
1047 | else | |
1048 | p = priv->dma_rx + i; | |
47dd7a54 | 1049 | |
777da230 | 1050 | ret = stmmac_init_rx_buffers(priv, p, i, flags); |
56329137 BZ |
1051 | if (ret) |
1052 | goto err_init_rx_buffers; | |
286a8372 | 1053 | |
b3e51069 LC |
1054 | netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n", |
1055 | priv->rx_skbuff[i], priv->rx_skbuff[i]->data, | |
1056 | (unsigned int)priv->rx_skbuff_dma[i]); | |
47dd7a54 GC |
1057 | } |
1058 | priv->cur_rx = 0; | |
e3ad57c9 | 1059 | priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); |
47dd7a54 GC |
1060 | buf_sz = bfsize; |
1061 | ||
c24602ef GC |
1062 | /* Setup the chained descriptor addresses */ |
1063 | if (priv->mode == STMMAC_CHAIN_MODE) { | |
1064 | if (priv->extend_desc) { | |
29896a67 | 1065 | priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, |
e3ad57c9 | 1066 | DMA_RX_SIZE, 1); |
29896a67 | 1067 | priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, |
e3ad57c9 | 1068 | DMA_TX_SIZE, 1); |
c24602ef | 1069 | } else { |
29896a67 | 1070 | priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, |
e3ad57c9 | 1071 | DMA_RX_SIZE, 0); |
29896a67 | 1072 | priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, |
e3ad57c9 | 1073 | DMA_TX_SIZE, 0); |
c24602ef GC |
1074 | } |
1075 | } | |
1076 | ||
47dd7a54 | 1077 | /* TX INITIALIZATION */ |
e3ad57c9 | 1078 | for (i = 0; i < DMA_TX_SIZE; i++) { |
c24602ef GC |
1079 | struct dma_desc *p; |
1080 | if (priv->extend_desc) | |
1081 | p = &((priv->dma_etx + i)->basic); | |
1082 | else | |
1083 | p = priv->dma_tx + i; | |
f748be53 AT |
1084 | |
1085 | if (priv->synopsys_id >= DWMAC_CORE_4_00) { | |
1086 | p->des0 = 0; | |
1087 | p->des1 = 0; | |
1088 | p->des2 = 0; | |
1089 | p->des3 = 0; | |
1090 | } else { | |
1091 | p->des2 = 0; | |
1092 | } | |
1093 | ||
362b37be GC |
1094 | priv->tx_skbuff_dma[i].buf = 0; |
1095 | priv->tx_skbuff_dma[i].map_as_page = false; | |
553e2ab3 | 1096 | priv->tx_skbuff_dma[i].len = 0; |
2a6d8e17 | 1097 | priv->tx_skbuff_dma[i].last_segment = false; |
47dd7a54 | 1098 | priv->tx_skbuff[i] = NULL; |
47dd7a54 | 1099 | } |
286a8372 | 1100 | |
47dd7a54 GC |
1101 | priv->dirty_tx = 0; |
1102 | priv->cur_tx = 0; | |
38979574 | 1103 | netdev_reset_queue(priv->dev); |
47dd7a54 | 1104 | |
c24602ef | 1105 | stmmac_clear_descriptors(priv); |
47dd7a54 | 1106 | |
c24602ef GC |
1107 | if (netif_msg_hw(priv)) |
1108 | stmmac_display_rings(priv); | |
56329137 BZ |
1109 | |
1110 | return 0; | |
1111 | err_init_rx_buffers: | |
1112 | while (--i >= 0) | |
1113 | stmmac_free_rx_buffers(priv, i); | |
56329137 | 1114 | return ret; |
47dd7a54 GC |
1115 | } |
1116 | ||
1117 | static void dma_free_rx_skbufs(struct stmmac_priv *priv) | |
1118 | { | |
1119 | int i; | |
1120 | ||
e3ad57c9 | 1121 | for (i = 0; i < DMA_RX_SIZE; i++) |
56329137 | 1122 | stmmac_free_rx_buffers(priv, i); |
47dd7a54 GC |
1123 | } |
1124 | ||
1125 | static void dma_free_tx_skbufs(struct stmmac_priv *priv) | |
1126 | { | |
1127 | int i; | |
1128 | ||
e3ad57c9 | 1129 | for (i = 0; i < DMA_TX_SIZE; i++) { |
75e4364f | 1130 | struct dma_desc *p; |
1131 | ||
1132 | if (priv->extend_desc) | |
1133 | p = &((priv->dma_etx + i)->basic); | |
1134 | else | |
1135 | p = priv->dma_tx + i; | |
1136 | ||
362b37be GC |
1137 | if (priv->tx_skbuff_dma[i].buf) { |
1138 | if (priv->tx_skbuff_dma[i].map_as_page) | |
1139 | dma_unmap_page(priv->device, | |
1140 | priv->tx_skbuff_dma[i].buf, | |
553e2ab3 | 1141 | priv->tx_skbuff_dma[i].len, |
362b37be GC |
1142 | DMA_TO_DEVICE); |
1143 | else | |
1144 | dma_unmap_single(priv->device, | |
1145 | priv->tx_skbuff_dma[i].buf, | |
553e2ab3 | 1146 | priv->tx_skbuff_dma[i].len, |
362b37be | 1147 | DMA_TO_DEVICE); |
75e4364f | 1148 | } |
c24602ef | 1149 | |
75e4364f | 1150 | if (priv->tx_skbuff[i] != NULL) { |
47dd7a54 GC |
1151 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
1152 | priv->tx_skbuff[i] = NULL; | |
362b37be GC |
1153 | priv->tx_skbuff_dma[i].buf = 0; |
1154 | priv->tx_skbuff_dma[i].map_as_page = false; | |
47dd7a54 GC |
1155 | } |
1156 | } | |
47dd7a54 GC |
1157 | } |
1158 | ||
732fdf0e GC |
1159 | /** |
1160 | * alloc_dma_desc_resources - alloc TX/RX resources. | |
1161 | * @priv: private structure | |
1162 | * Description: according to which descriptor can be used (extend or basic) | |
1163 | * this function allocates the resources for TX and RX paths. In case of | |
1164 | * reception, for example, it pre-allocated the RX socket buffer in order to | |
1165 | * allow zero-copy mechanism. | |
1166 | */ | |
09f8d696 SK |
1167 | static int alloc_dma_desc_resources(struct stmmac_priv *priv) |
1168 | { | |
09f8d696 SK |
1169 | int ret = -ENOMEM; |
1170 | ||
e3ad57c9 | 1171 | priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t), |
09f8d696 SK |
1172 | GFP_KERNEL); |
1173 | if (!priv->rx_skbuff_dma) | |
1174 | return -ENOMEM; | |
1175 | ||
e3ad57c9 | 1176 | priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *), |
09f8d696 SK |
1177 | GFP_KERNEL); |
1178 | if (!priv->rx_skbuff) | |
1179 | goto err_rx_skbuff; | |
1180 | ||
e3ad57c9 | 1181 | priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE, |
362b37be | 1182 | sizeof(*priv->tx_skbuff_dma), |
09f8d696 SK |
1183 | GFP_KERNEL); |
1184 | if (!priv->tx_skbuff_dma) | |
1185 | goto err_tx_skbuff_dma; | |
1186 | ||
e3ad57c9 | 1187 | priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *), |
09f8d696 SK |
1188 | GFP_KERNEL); |
1189 | if (!priv->tx_skbuff) | |
1190 | goto err_tx_skbuff; | |
1191 | ||
1192 | if (priv->extend_desc) { | |
e3ad57c9 | 1193 | priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * |
f1590670 AB |
1194 | sizeof(struct |
1195 | dma_extended_desc), | |
1196 | &priv->dma_rx_phy, | |
1197 | GFP_KERNEL); | |
09f8d696 SK |
1198 | if (!priv->dma_erx) |
1199 | goto err_dma; | |
1200 | ||
e3ad57c9 | 1201 | priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * |
f1590670 AB |
1202 | sizeof(struct |
1203 | dma_extended_desc), | |
1204 | &priv->dma_tx_phy, | |
1205 | GFP_KERNEL); | |
09f8d696 | 1206 | if (!priv->dma_etx) { |
e3ad57c9 | 1207 | dma_free_coherent(priv->device, DMA_RX_SIZE * |
f1590670 AB |
1208 | sizeof(struct dma_extended_desc), |
1209 | priv->dma_erx, priv->dma_rx_phy); | |
09f8d696 SK |
1210 | goto err_dma; |
1211 | } | |
1212 | } else { | |
e3ad57c9 | 1213 | priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * |
f1590670 AB |
1214 | sizeof(struct dma_desc), |
1215 | &priv->dma_rx_phy, | |
1216 | GFP_KERNEL); | |
09f8d696 SK |
1217 | if (!priv->dma_rx) |
1218 | goto err_dma; | |
1219 | ||
e3ad57c9 | 1220 | priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * |
f1590670 AB |
1221 | sizeof(struct dma_desc), |
1222 | &priv->dma_tx_phy, | |
1223 | GFP_KERNEL); | |
09f8d696 | 1224 | if (!priv->dma_tx) { |
e3ad57c9 | 1225 | dma_free_coherent(priv->device, DMA_RX_SIZE * |
f1590670 AB |
1226 | sizeof(struct dma_desc), |
1227 | priv->dma_rx, priv->dma_rx_phy); | |
09f8d696 SK |
1228 | goto err_dma; |
1229 | } | |
1230 | } | |
1231 | ||
1232 | return 0; | |
1233 | ||
1234 | err_dma: | |
1235 | kfree(priv->tx_skbuff); | |
1236 | err_tx_skbuff: | |
1237 | kfree(priv->tx_skbuff_dma); | |
1238 | err_tx_skbuff_dma: | |
1239 | kfree(priv->rx_skbuff); | |
1240 | err_rx_skbuff: | |
1241 | kfree(priv->rx_skbuff_dma); | |
1242 | return ret; | |
1243 | } | |
1244 | ||
47dd7a54 GC |
1245 | static void free_dma_desc_resources(struct stmmac_priv *priv) |
1246 | { | |
1247 | /* Release the DMA TX/RX socket buffers */ | |
1248 | dma_free_rx_skbufs(priv); | |
1249 | dma_free_tx_skbufs(priv); | |
1250 | ||
ceb69499 | 1251 | /* Free DMA regions of consistent memory previously allocated */ |
c24602ef GC |
1252 | if (!priv->extend_desc) { |
1253 | dma_free_coherent(priv->device, | |
e3ad57c9 | 1254 | DMA_TX_SIZE * sizeof(struct dma_desc), |
c24602ef GC |
1255 | priv->dma_tx, priv->dma_tx_phy); |
1256 | dma_free_coherent(priv->device, | |
e3ad57c9 | 1257 | DMA_RX_SIZE * sizeof(struct dma_desc), |
c24602ef GC |
1258 | priv->dma_rx, priv->dma_rx_phy); |
1259 | } else { | |
e3ad57c9 | 1260 | dma_free_coherent(priv->device, DMA_TX_SIZE * |
c24602ef GC |
1261 | sizeof(struct dma_extended_desc), |
1262 | priv->dma_etx, priv->dma_tx_phy); | |
e3ad57c9 | 1263 | dma_free_coherent(priv->device, DMA_RX_SIZE * |
c24602ef GC |
1264 | sizeof(struct dma_extended_desc), |
1265 | priv->dma_erx, priv->dma_rx_phy); | |
1266 | } | |
47dd7a54 GC |
1267 | kfree(priv->rx_skbuff_dma); |
1268 | kfree(priv->rx_skbuff); | |
cf32deec | 1269 | kfree(priv->tx_skbuff_dma); |
47dd7a54 | 1270 | kfree(priv->tx_skbuff); |
47dd7a54 GC |
1271 | } |
1272 | ||
47dd7a54 GC |
1273 | /** |
1274 | * stmmac_dma_operation_mode - HW DMA operation mode | |
32ceabca | 1275 | * @priv: driver private structure |
732fdf0e GC |
1276 | * Description: it is used for configuring the DMA operation mode register in |
1277 | * order to program the tx/rx DMA thresholds or Store-And-Forward mode. | |
47dd7a54 GC |
1278 | */ |
1279 | static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |
1280 | { | |
f88203a2 VB |
1281 | int rxfifosz = priv->plat->rx_fifo_size; |
1282 | ||
e2a240c7 | 1283 | if (priv->plat->force_thresh_dma_mode) |
f88203a2 | 1284 | priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz); |
e2a240c7 | 1285 | else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { |
61b8013a SK |
1286 | /* |
1287 | * In case of GMAC, SF mode can be enabled | |
1288 | * to perform the TX COE in HW. This depends on: | |
ebbb293f GC |
1289 | * 1) TX COE if actually supported |
1290 | * 2) There is no bugged Jumbo frame support | |
1291 | * that needs to not insert csum in the TDES. | |
1292 | */ | |
f88203a2 VB |
1293 | priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE, |
1294 | rxfifosz); | |
b2dec116 | 1295 | priv->xstats.threshold = SF_DMA_MODE; |
ebbb293f | 1296 | } else |
f88203a2 VB |
1297 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE, |
1298 | rxfifosz); | |
47dd7a54 GC |
1299 | } |
1300 | ||
47dd7a54 | 1301 | /** |
732fdf0e | 1302 | * stmmac_tx_clean - to manage the transmission completion |
32ceabca | 1303 | * @priv: driver private structure |
732fdf0e | 1304 | * Description: it reclaims the transmit resources after transmission completes. |
47dd7a54 | 1305 | */ |
9125cdd1 | 1306 | static void stmmac_tx_clean(struct stmmac_priv *priv) |
47dd7a54 | 1307 | { |
38979574 | 1308 | unsigned int bytes_compl = 0, pkts_compl = 0; |
e3ad57c9 | 1309 | unsigned int entry = priv->dirty_tx; |
47dd7a54 | 1310 | |
739c8e14 | 1311 | netif_tx_lock(priv->dev); |
a9097a96 | 1312 | |
9125cdd1 GC |
1313 | priv->xstats.tx_clean++; |
1314 | ||
e3ad57c9 | 1315 | while (entry != priv->cur_tx) { |
47dd7a54 | 1316 | struct sk_buff *skb = priv->tx_skbuff[entry]; |
c24602ef | 1317 | struct dma_desc *p; |
c363b658 | 1318 | int status; |
c24602ef GC |
1319 | |
1320 | if (priv->extend_desc) | |
ceb69499 | 1321 | p = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
1322 | else |
1323 | p = priv->dma_tx + entry; | |
47dd7a54 | 1324 | |
c363b658 | 1325 | status = priv->hw->desc->tx_status(&priv->dev->stats, |
ceb69499 GC |
1326 | &priv->xstats, p, |
1327 | priv->ioaddr); | |
c363b658 FG |
1328 | /* Check if the descriptor is owned by the DMA */ |
1329 | if (unlikely(status & tx_dma_own)) | |
1330 | break; | |
1331 | ||
1332 | /* Just consider the last segment and ...*/ | |
1333 | if (likely(!(status & tx_not_ls))) { | |
1334 | /* ... verify the status error condition */ | |
1335 | if (unlikely(status & tx_err)) { | |
1336 | priv->dev->stats.tx_errors++; | |
1337 | } else { | |
47dd7a54 GC |
1338 | priv->dev->stats.tx_packets++; |
1339 | priv->xstats.tx_pkt_n++; | |
c363b658 | 1340 | } |
ba1ffd74 | 1341 | stmmac_get_tx_hwtstamp(priv, p, skb); |
47dd7a54 | 1342 | } |
47dd7a54 | 1343 | |
362b37be GC |
1344 | if (likely(priv->tx_skbuff_dma[entry].buf)) { |
1345 | if (priv->tx_skbuff_dma[entry].map_as_page) | |
1346 | dma_unmap_page(priv->device, | |
1347 | priv->tx_skbuff_dma[entry].buf, | |
553e2ab3 | 1348 | priv->tx_skbuff_dma[entry].len, |
362b37be GC |
1349 | DMA_TO_DEVICE); |
1350 | else | |
1351 | dma_unmap_single(priv->device, | |
1352 | priv->tx_skbuff_dma[entry].buf, | |
553e2ab3 | 1353 | priv->tx_skbuff_dma[entry].len, |
362b37be GC |
1354 | DMA_TO_DEVICE); |
1355 | priv->tx_skbuff_dma[entry].buf = 0; | |
f748be53 | 1356 | priv->tx_skbuff_dma[entry].len = 0; |
362b37be | 1357 | priv->tx_skbuff_dma[entry].map_as_page = false; |
cf32deec | 1358 | } |
f748be53 AT |
1359 | |
1360 | if (priv->hw->mode->clean_desc3) | |
1361 | priv->hw->mode->clean_desc3(priv, p); | |
1362 | ||
2a6d8e17 | 1363 | priv->tx_skbuff_dma[entry].last_segment = false; |
96951366 | 1364 | priv->tx_skbuff_dma[entry].is_jumbo = false; |
47dd7a54 GC |
1365 | |
1366 | if (likely(skb != NULL)) { | |
38979574 BG |
1367 | pkts_compl++; |
1368 | bytes_compl += skb->len; | |
7c565c33 | 1369 | dev_consume_skb_any(skb); |
47dd7a54 GC |
1370 | priv->tx_skbuff[entry] = NULL; |
1371 | } | |
1372 | ||
4a7d666a | 1373 | priv->hw->desc->release_tx_desc(p, priv->mode); |
47dd7a54 | 1374 | |
e3ad57c9 | 1375 | entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); |
47dd7a54 | 1376 | } |
fbc80823 | 1377 | priv->dirty_tx = entry; |
38979574 BG |
1378 | |
1379 | netdev_completed_queue(priv->dev, pkts_compl, bytes_compl); | |
1380 | ||
47dd7a54 | 1381 | if (unlikely(netif_queue_stopped(priv->dev) && |
739c8e14 LS |
1382 | stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) { |
1383 | netif_dbg(priv, tx_done, priv->dev, | |
1384 | "%s: restart transmit\n", __func__); | |
1385 | netif_wake_queue(priv->dev); | |
47dd7a54 | 1386 | } |
d765955d GC |
1387 | |
1388 | if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { | |
1389 | stmmac_enable_eee_mode(priv); | |
f5351ef7 | 1390 | mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); |
d765955d | 1391 | } |
739c8e14 | 1392 | netif_tx_unlock(priv->dev); |
47dd7a54 GC |
1393 | } |
1394 | ||
9125cdd1 | 1395 | static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) |
47dd7a54 | 1396 | { |
7284a3f1 | 1397 | priv->hw->dma->enable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
1398 | } |
1399 | ||
9125cdd1 | 1400 | static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) |
47dd7a54 | 1401 | { |
7284a3f1 | 1402 | priv->hw->dma->disable_dma_irq(priv->ioaddr); |
47dd7a54 GC |
1403 | } |
1404 | ||
47dd7a54 | 1405 | /** |
732fdf0e | 1406 | * stmmac_tx_err - to manage the tx error |
32ceabca | 1407 | * @priv: driver private structure |
47dd7a54 | 1408 | * Description: it cleans the descriptors and restarts the transmission |
732fdf0e | 1409 | * in case of transmission errors. |
47dd7a54 GC |
1410 | */ |
1411 | static void stmmac_tx_err(struct stmmac_priv *priv) | |
1412 | { | |
c24602ef | 1413 | int i; |
47dd7a54 GC |
1414 | netif_stop_queue(priv->dev); |
1415 | ||
ad01b7d4 | 1416 | priv->hw->dma->stop_tx(priv->ioaddr); |
47dd7a54 | 1417 | dma_free_tx_skbufs(priv); |
e3ad57c9 | 1418 | for (i = 0; i < DMA_TX_SIZE; i++) |
c24602ef GC |
1419 | if (priv->extend_desc) |
1420 | priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, | |
1421 | priv->mode, | |
e3ad57c9 | 1422 | (i == DMA_TX_SIZE - 1)); |
c24602ef GC |
1423 | else |
1424 | priv->hw->desc->init_tx_desc(&priv->dma_tx[i], | |
1425 | priv->mode, | |
e3ad57c9 | 1426 | (i == DMA_TX_SIZE - 1)); |
47dd7a54 GC |
1427 | priv->dirty_tx = 0; |
1428 | priv->cur_tx = 0; | |
38979574 | 1429 | netdev_reset_queue(priv->dev); |
ad01b7d4 | 1430 | priv->hw->dma->start_tx(priv->ioaddr); |
47dd7a54 GC |
1431 | |
1432 | priv->dev->stats.tx_errors++; | |
1433 | netif_wake_queue(priv->dev); | |
47dd7a54 GC |
1434 | } |
1435 | ||
32ceabca | 1436 | /** |
732fdf0e | 1437 | * stmmac_dma_interrupt - DMA ISR |
32ceabca GC |
1438 | * @priv: driver private structure |
1439 | * Description: this is the DMA ISR. It is called by the main ISR. | |
732fdf0e GC |
1440 | * It calls the dwmac dma routine and schedule poll method in case of some |
1441 | * work can be done. | |
32ceabca | 1442 | */ |
aec7ff27 GC |
1443 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
1444 | { | |
aec7ff27 | 1445 | int status; |
f88203a2 | 1446 | int rxfifosz = priv->plat->rx_fifo_size; |
aec7ff27 | 1447 | |
ad01b7d4 | 1448 | status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); |
9125cdd1 GC |
1449 | if (likely((status & handle_rx)) || (status & handle_tx)) { |
1450 | if (likely(napi_schedule_prep(&priv->napi))) { | |
1451 | stmmac_disable_dma_irq(priv); | |
1452 | __napi_schedule(&priv->napi); | |
1453 | } | |
1454 | } | |
1455 | if (unlikely(status & tx_hard_error_bump_tc)) { | |
aec7ff27 | 1456 | /* Try to bump up the dma threshold on this failure */ |
b2dec116 SZ |
1457 | if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && |
1458 | (tc <= 256)) { | |
aec7ff27 | 1459 | tc += 64; |
c405abe2 | 1460 | if (priv->plat->force_thresh_dma_mode) |
f88203a2 VB |
1461 | priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, |
1462 | rxfifosz); | |
c405abe2 SZ |
1463 | else |
1464 | priv->hw->dma->dma_mode(priv->ioaddr, tc, | |
f88203a2 | 1465 | SF_DMA_MODE, rxfifosz); |
aec7ff27 | 1466 | priv->xstats.threshold = tc; |
47dd7a54 | 1467 | } |
aec7ff27 GC |
1468 | } else if (unlikely(status == tx_hard_error)) |
1469 | stmmac_tx_err(priv); | |
47dd7a54 GC |
1470 | } |
1471 | ||
32ceabca GC |
1472 | /** |
1473 | * stmmac_mmc_setup: setup the Mac Management Counters (MMC) | |
1474 | * @priv: driver private structure | |
1475 | * Description: this masks the MMC irq, in fact, the counters are managed in SW. | |
1476 | */ | |
1c901a46 GC |
1477 | static void stmmac_mmc_setup(struct stmmac_priv *priv) |
1478 | { | |
1479 | unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | | |
36ff7c1e | 1480 | MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; |
1c901a46 | 1481 | |
ba1ffd74 GC |
1482 | if (priv->synopsys_id >= DWMAC_CORE_4_00) { |
1483 | priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET; | |
f748be53 | 1484 | priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET; |
ba1ffd74 GC |
1485 | } else { |
1486 | priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET; | |
f748be53 | 1487 | priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET; |
ba1ffd74 | 1488 | } |
36ff7c1e AT |
1489 | |
1490 | dwmac_mmc_intr_all_mask(priv->mmcaddr); | |
4f795b25 GC |
1491 | |
1492 | if (priv->dma_cap.rmon) { | |
36ff7c1e | 1493 | dwmac_mmc_ctrl(priv->mmcaddr, mode); |
4f795b25 GC |
1494 | memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); |
1495 | } else | |
38ddc59d | 1496 | netdev_info(priv->dev, "No MAC Management Counters available\n"); |
1c901a46 GC |
1497 | } |
1498 | ||
19e30c14 | 1499 | /** |
732fdf0e | 1500 | * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors |
32ceabca GC |
1501 | * @priv: driver private structure |
1502 | * Description: select the Enhanced/Alternate or Normal descriptors. | |
732fdf0e GC |
1503 | * In case of Enhanced/Alternate, it checks if the extended descriptors are |
1504 | * supported by the HW capability register. | |
ff3dd78c | 1505 | */ |
19e30c14 GC |
1506 | static void stmmac_selec_desc_mode(struct stmmac_priv *priv) |
1507 | { | |
1508 | if (priv->plat->enh_desc) { | |
38ddc59d | 1509 | dev_info(priv->device, "Enhanced/Alternate descriptors\n"); |
c24602ef GC |
1510 | |
1511 | /* GMAC older than 3.50 has no extended descriptors */ | |
1512 | if (priv->synopsys_id >= DWMAC_CORE_3_50) { | |
38ddc59d | 1513 | dev_info(priv->device, "Enabled extended descriptors\n"); |
c24602ef GC |
1514 | priv->extend_desc = 1; |
1515 | } else | |
38ddc59d | 1516 | dev_warn(priv->device, "Extended descriptors not supported\n"); |
c24602ef | 1517 | |
19e30c14 GC |
1518 | priv->hw->desc = &enh_desc_ops; |
1519 | } else { | |
38ddc59d | 1520 | dev_info(priv->device, "Normal descriptors\n"); |
19e30c14 GC |
1521 | priv->hw->desc = &ndesc_ops; |
1522 | } | |
1523 | } | |
1524 | ||
1525 | /** | |
732fdf0e | 1526 | * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. |
32ceabca | 1527 | * @priv: driver private structure |
19e30c14 GC |
1528 | * Description: |
1529 | * new GMAC chip generations have a new register to indicate the | |
1530 | * presence of the optional feature/functions. | |
1531 | * This can be also used to override the value passed through the | |
1532 | * platform and necessary for old MAC10/100 and GMAC chips. | |
e7434821 GC |
1533 | */ |
1534 | static int stmmac_get_hw_features(struct stmmac_priv *priv) | |
1535 | { | |
f10a6a35 | 1536 | u32 ret = 0; |
3c20f72f | 1537 | |
5e6efe88 | 1538 | if (priv->hw->dma->get_hw_feature) { |
f10a6a35 AT |
1539 | priv->hw->dma->get_hw_feature(priv->ioaddr, |
1540 | &priv->dma_cap); | |
1541 | ret = 1; | |
19e30c14 | 1542 | } |
e7434821 | 1543 | |
f10a6a35 | 1544 | return ret; |
e7434821 GC |
1545 | } |
1546 | ||
32ceabca | 1547 | /** |
732fdf0e | 1548 | * stmmac_check_ether_addr - check if the MAC addr is valid |
32ceabca GC |
1549 | * @priv: driver private structure |
1550 | * Description: | |
1551 | * it is to verify if the MAC address is valid, in case of failures it | |
1552 | * generates a random MAC address | |
1553 | */ | |
bfab27a1 GC |
1554 | static void stmmac_check_ether_addr(struct stmmac_priv *priv) |
1555 | { | |
bfab27a1 | 1556 | if (!is_valid_ether_addr(priv->dev->dev_addr)) { |
7ed24bbe | 1557 | priv->hw->mac->get_umac_addr(priv->hw, |
bfab27a1 | 1558 | priv->dev->dev_addr, 0); |
ceb69499 | 1559 | if (!is_valid_ether_addr(priv->dev->dev_addr)) |
f2cedb63 | 1560 | eth_hw_addr_random(priv->dev); |
38ddc59d LC |
1561 | netdev_info(priv->dev, "device MAC address %pM\n", |
1562 | priv->dev->dev_addr); | |
bfab27a1 | 1563 | } |
bfab27a1 GC |
1564 | } |
1565 | ||
32ceabca | 1566 | /** |
732fdf0e | 1567 | * stmmac_init_dma_engine - DMA init. |
32ceabca GC |
1568 | * @priv: driver private structure |
1569 | * Description: | |
1570 | * It inits the DMA invoking the specific MAC/GMAC callback. | |
1571 | * Some DMA parameters can be passed from the platform; | |
1572 | * in case of these are not passed a default is kept for the MAC or GMAC. | |
1573 | */ | |
0f1f88a8 GC |
1574 | static int stmmac_init_dma_engine(struct stmmac_priv *priv) |
1575 | { | |
c24602ef | 1576 | int atds = 0; |
495db273 | 1577 | int ret = 0; |
0f1f88a8 | 1578 | |
a332e2fa NC |
1579 | if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { |
1580 | dev_err(priv->device, "Invalid DMA configuration\n"); | |
89ab75bf | 1581 | return -EINVAL; |
0f1f88a8 GC |
1582 | } |
1583 | ||
c24602ef GC |
1584 | if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) |
1585 | atds = 1; | |
1586 | ||
495db273 GC |
1587 | ret = priv->hw->dma->reset(priv->ioaddr); |
1588 | if (ret) { | |
1589 | dev_err(priv->device, "Failed to reset the dma\n"); | |
1590 | return ret; | |
1591 | } | |
1592 | ||
50ca903a | 1593 | priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg, |
89ab75bf | 1594 | priv->dma_tx_phy, priv->dma_rx_phy, atds); |
afea0365 | 1595 | |
f748be53 AT |
1596 | if (priv->synopsys_id >= DWMAC_CORE_4_00) { |
1597 | priv->rx_tail_addr = priv->dma_rx_phy + | |
1598 | (DMA_RX_SIZE * sizeof(struct dma_desc)); | |
1599 | priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, priv->rx_tail_addr, | |
1600 | STMMAC_CHAN0); | |
1601 | ||
1602 | priv->tx_tail_addr = priv->dma_tx_phy + | |
1603 | (DMA_TX_SIZE * sizeof(struct dma_desc)); | |
1604 | priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, | |
1605 | STMMAC_CHAN0); | |
1606 | } | |
1607 | ||
1608 | if (priv->plat->axi && priv->hw->dma->axi) | |
afea0365 GC |
1609 | priv->hw->dma->axi(priv->ioaddr, priv->plat->axi); |
1610 | ||
495db273 | 1611 | return ret; |
0f1f88a8 GC |
1612 | } |
1613 | ||
9125cdd1 | 1614 | /** |
732fdf0e | 1615 | * stmmac_tx_timer - mitigation sw timer for tx. |
9125cdd1 GC |
1616 | * @data: data pointer |
1617 | * Description: | |
1618 | * This is the timer handler to directly invoke the stmmac_tx_clean. | |
1619 | */ | |
1620 | static void stmmac_tx_timer(unsigned long data) | |
1621 | { | |
1622 | struct stmmac_priv *priv = (struct stmmac_priv *)data; | |
1623 | ||
1624 | stmmac_tx_clean(priv); | |
1625 | } | |
1626 | ||
1627 | /** | |
732fdf0e | 1628 | * stmmac_init_tx_coalesce - init tx mitigation options. |
32ceabca | 1629 | * @priv: driver private structure |
9125cdd1 GC |
1630 | * Description: |
1631 | * This inits the transmit coalesce parameters: i.e. timer rate, | |
1632 | * timer handler and default threshold used for enabling the | |
1633 | * interrupt on completion bit. | |
1634 | */ | |
1635 | static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) | |
1636 | { | |
1637 | priv->tx_coal_frames = STMMAC_TX_FRAMES; | |
1638 | priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; | |
1639 | init_timer(&priv->txtimer); | |
1640 | priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); | |
1641 | priv->txtimer.data = (unsigned long)priv; | |
1642 | priv->txtimer.function = stmmac_tx_timer; | |
1643 | add_timer(&priv->txtimer); | |
1644 | } | |
1645 | ||
523f11b5 | 1646 | /** |
732fdf0e | 1647 | * stmmac_hw_setup - setup mac in a usable state. |
523f11b5 SK |
1648 | * @dev : pointer to the device structure. |
1649 | * Description: | |
732fdf0e GC |
1650 | * this is the main function to setup the HW in a usable state because the |
1651 | * dma engine is reset, the core registers are configured (e.g. AXI, | |
1652 | * Checksum features, timers). The DMA is ready to start receiving and | |
1653 | * transmitting. | |
523f11b5 SK |
1654 | * Return value: |
1655 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1656 | * file on failure. | |
1657 | */ | |
fe131929 | 1658 | static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) |
523f11b5 SK |
1659 | { |
1660 | struct stmmac_priv *priv = netdev_priv(dev); | |
1661 | int ret; | |
1662 | ||
523f11b5 SK |
1663 | /* DMA initialization and SW reset */ |
1664 | ret = stmmac_init_dma_engine(priv); | |
1665 | if (ret < 0) { | |
38ddc59d LC |
1666 | netdev_err(priv->dev, "%s: DMA engine initialization failed\n", |
1667 | __func__); | |
523f11b5 SK |
1668 | return ret; |
1669 | } | |
1670 | ||
1671 | /* Copy the MAC addr into the HW */ | |
7ed24bbe | 1672 | priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); |
523f11b5 SK |
1673 | |
1674 | /* If required, perform hw setup of the bus. */ | |
1675 | if (priv->plat->bus_setup) | |
1676 | priv->plat->bus_setup(priv->ioaddr); | |
1677 | ||
02e57b9d GC |
1678 | /* PS and related bits will be programmed according to the speed */ |
1679 | if (priv->hw->pcs) { | |
1680 | int speed = priv->plat->mac_port_sel_speed; | |
1681 | ||
1682 | if ((speed == SPEED_10) || (speed == SPEED_100) || | |
1683 | (speed == SPEED_1000)) { | |
1684 | priv->hw->ps = speed; | |
1685 | } else { | |
1686 | dev_warn(priv->device, "invalid port speed\n"); | |
1687 | priv->hw->ps = 0; | |
1688 | } | |
1689 | } | |
1690 | ||
523f11b5 | 1691 | /* Initialize the MAC Core */ |
7ed24bbe | 1692 | priv->hw->mac->core_init(priv->hw, dev->mtu); |
523f11b5 | 1693 | |
978aded4 GC |
1694 | ret = priv->hw->mac->rx_ipc(priv->hw); |
1695 | if (!ret) { | |
38ddc59d | 1696 | netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); |
978aded4 | 1697 | priv->plat->rx_coe = STMMAC_RX_COE_NONE; |
d2afb5bd | 1698 | priv->hw->rx_csum = 0; |
978aded4 GC |
1699 | } |
1700 | ||
523f11b5 | 1701 | /* Enable the MAC Rx/Tx */ |
f748be53 AT |
1702 | if (priv->synopsys_id >= DWMAC_CORE_4_00) |
1703 | stmmac_dwmac4_set_mac(priv->ioaddr, true); | |
1704 | else | |
1705 | stmmac_set_mac(priv->ioaddr, true); | |
523f11b5 SK |
1706 | |
1707 | /* Set the HW DMA mode and the COE */ | |
1708 | stmmac_dma_operation_mode(priv); | |
1709 | ||
1710 | stmmac_mmc_setup(priv); | |
1711 | ||
fe131929 HC |
1712 | if (init_ptp) { |
1713 | ret = stmmac_init_ptp(priv); | |
7086605a | 1714 | if (ret) |
c30a70d3 | 1715 | netdev_warn(priv->dev, "fail to init PTP.\n"); |
fe131929 | 1716 | } |
523f11b5 | 1717 | |
50fb4f74 | 1718 | #ifdef CONFIG_DEBUG_FS |
523f11b5 SK |
1719 | ret = stmmac_init_fs(dev); |
1720 | if (ret < 0) | |
38ddc59d LC |
1721 | netdev_warn(priv->dev, "%s: failed debugFS registration\n", |
1722 | __func__); | |
523f11b5 SK |
1723 | #endif |
1724 | /* Start the ball rolling... */ | |
38ddc59d | 1725 | netdev_dbg(priv->dev, "DMA RX/TX processes started...\n"); |
523f11b5 SK |
1726 | priv->hw->dma->start_tx(priv->ioaddr); |
1727 | priv->hw->dma->start_rx(priv->ioaddr); | |
1728 | ||
1729 | /* Dump DMA/MAC registers */ | |
1730 | if (netif_msg_hw(priv)) { | |
7ed24bbe | 1731 | priv->hw->mac->dump_regs(priv->hw); |
523f11b5 SK |
1732 | priv->hw->dma->dump_regs(priv->ioaddr); |
1733 | } | |
1734 | priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; | |
1735 | ||
523f11b5 SK |
1736 | if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { |
1737 | priv->rx_riwt = MAX_DMA_RIWT; | |
1738 | priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); | |
1739 | } | |
1740 | ||
3fe5cadb | 1741 | if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane) |
02e57b9d | 1742 | priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0); |
523f11b5 | 1743 | |
f748be53 AT |
1744 | /* set TX ring length */ |
1745 | if (priv->hw->dma->set_tx_ring_len) | |
1746 | priv->hw->dma->set_tx_ring_len(priv->ioaddr, | |
1747 | (DMA_TX_SIZE - 1)); | |
1748 | /* set RX ring length */ | |
1749 | if (priv->hw->dma->set_rx_ring_len) | |
1750 | priv->hw->dma->set_rx_ring_len(priv->ioaddr, | |
1751 | (DMA_RX_SIZE - 1)); | |
1752 | /* Enable TSO */ | |
1753 | if (priv->tso) | |
1754 | priv->hw->dma->enable_tso(priv->ioaddr, 1, STMMAC_CHAN0); | |
1755 | ||
523f11b5 SK |
1756 | return 0; |
1757 | } | |
1758 | ||
47dd7a54 GC |
1759 | /** |
1760 | * stmmac_open - open entry point of the driver | |
1761 | * @dev : pointer to the device structure. | |
1762 | * Description: | |
1763 | * This function is the open entry point of the driver. | |
1764 | * Return value: | |
1765 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
1766 | * file on failure. | |
1767 | */ | |
1768 | static int stmmac_open(struct net_device *dev) | |
1769 | { | |
1770 | struct stmmac_priv *priv = netdev_priv(dev); | |
47dd7a54 GC |
1771 | int ret; |
1772 | ||
4bfcbd7a FV |
1773 | stmmac_check_ether_addr(priv); |
1774 | ||
3fe5cadb GC |
1775 | if (priv->hw->pcs != STMMAC_PCS_RGMII && |
1776 | priv->hw->pcs != STMMAC_PCS_TBI && | |
1777 | priv->hw->pcs != STMMAC_PCS_RTBI) { | |
e58bb43f GC |
1778 | ret = stmmac_init_phy(dev); |
1779 | if (ret) { | |
38ddc59d LC |
1780 | netdev_err(priv->dev, |
1781 | "%s: Cannot attach to PHY (error: %d)\n", | |
1782 | __func__, ret); | |
89df20d9 | 1783 | return ret; |
e58bb43f | 1784 | } |
f66ffe28 | 1785 | } |
47dd7a54 | 1786 | |
523f11b5 SK |
1787 | /* Extra statistics */ |
1788 | memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); | |
1789 | priv->xstats.threshold = tc; | |
1790 | ||
47dd7a54 | 1791 | priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); |
22ad3838 | 1792 | priv->rx_copybreak = STMMAC_RX_COPYBREAK; |
56329137 | 1793 | |
7262b7b2 | 1794 | ret = alloc_dma_desc_resources(priv); |
09f8d696 | 1795 | if (ret < 0) { |
38ddc59d LC |
1796 | netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", |
1797 | __func__); | |
09f8d696 SK |
1798 | goto dma_desc_error; |
1799 | } | |
1800 | ||
777da230 GC |
1801 | ret = init_dma_desc_rings(dev, GFP_KERNEL); |
1802 | if (ret < 0) { | |
38ddc59d LC |
1803 | netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", |
1804 | __func__); | |
777da230 GC |
1805 | goto init_error; |
1806 | } | |
1807 | ||
fe131929 | 1808 | ret = stmmac_hw_setup(dev, true); |
56329137 | 1809 | if (ret < 0) { |
38ddc59d | 1810 | netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); |
c9324d18 | 1811 | goto init_error; |
47dd7a54 GC |
1812 | } |
1813 | ||
777da230 GC |
1814 | stmmac_init_tx_coalesce(priv); |
1815 | ||
d6d50c7e PR |
1816 | if (dev->phydev) |
1817 | phy_start(dev->phydev); | |
47dd7a54 | 1818 | |
f66ffe28 GC |
1819 | /* Request the IRQ lines */ |
1820 | ret = request_irq(dev->irq, stmmac_interrupt, | |
ceb69499 | 1821 | IRQF_SHARED, dev->name, dev); |
f66ffe28 | 1822 | if (unlikely(ret < 0)) { |
38ddc59d LC |
1823 | netdev_err(priv->dev, |
1824 | "%s: ERROR: allocating the IRQ %d (error: %d)\n", | |
1825 | __func__, dev->irq, ret); | |
c9324d18 | 1826 | goto init_error; |
f66ffe28 GC |
1827 | } |
1828 | ||
7a13f8f5 FV |
1829 | /* Request the Wake IRQ in case of another line is used for WoL */ |
1830 | if (priv->wol_irq != dev->irq) { | |
1831 | ret = request_irq(priv->wol_irq, stmmac_interrupt, | |
1832 | IRQF_SHARED, dev->name, dev); | |
1833 | if (unlikely(ret < 0)) { | |
38ddc59d LC |
1834 | netdev_err(priv->dev, |
1835 | "%s: ERROR: allocating the WoL IRQ %d (%d)\n", | |
1836 | __func__, priv->wol_irq, ret); | |
c9324d18 | 1837 | goto wolirq_error; |
7a13f8f5 FV |
1838 | } |
1839 | } | |
1840 | ||
d765955d | 1841 | /* Request the IRQ lines */ |
d7ec8584 | 1842 | if (priv->lpi_irq > 0) { |
d765955d GC |
1843 | ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, |
1844 | dev->name, dev); | |
1845 | if (unlikely(ret < 0)) { | |
38ddc59d LC |
1846 | netdev_err(priv->dev, |
1847 | "%s: ERROR: allocating the LPI IRQ %d (%d)\n", | |
1848 | __func__, priv->lpi_irq, ret); | |
c9324d18 | 1849 | goto lpiirq_error; |
d765955d GC |
1850 | } |
1851 | } | |
1852 | ||
47dd7a54 | 1853 | napi_enable(&priv->napi); |
47dd7a54 | 1854 | netif_start_queue(dev); |
f66ffe28 | 1855 | |
47dd7a54 | 1856 | return 0; |
f66ffe28 | 1857 | |
c9324d18 | 1858 | lpiirq_error: |
d765955d GC |
1859 | if (priv->wol_irq != dev->irq) |
1860 | free_irq(priv->wol_irq, dev); | |
c9324d18 | 1861 | wolirq_error: |
7a13f8f5 FV |
1862 | free_irq(dev->irq, dev); |
1863 | ||
c9324d18 GC |
1864 | init_error: |
1865 | free_dma_desc_resources(priv); | |
56329137 | 1866 | dma_desc_error: |
d6d50c7e PR |
1867 | if (dev->phydev) |
1868 | phy_disconnect(dev->phydev); | |
4bfcbd7a | 1869 | |
f66ffe28 | 1870 | return ret; |
47dd7a54 GC |
1871 | } |
1872 | ||
1873 | /** | |
1874 | * stmmac_release - close entry point of the driver | |
1875 | * @dev : device pointer. | |
1876 | * Description: | |
1877 | * This is the stop entry point of the driver. | |
1878 | */ | |
1879 | static int stmmac_release(struct net_device *dev) | |
1880 | { | |
1881 | struct stmmac_priv *priv = netdev_priv(dev); | |
1882 | ||
d765955d GC |
1883 | if (priv->eee_enabled) |
1884 | del_timer_sync(&priv->eee_ctrl_timer); | |
1885 | ||
47dd7a54 | 1886 | /* Stop and disconnect the PHY */ |
d6d50c7e PR |
1887 | if (dev->phydev) { |
1888 | phy_stop(dev->phydev); | |
1889 | phy_disconnect(dev->phydev); | |
47dd7a54 GC |
1890 | } |
1891 | ||
1892 | netif_stop_queue(dev); | |
1893 | ||
47dd7a54 | 1894 | napi_disable(&priv->napi); |
47dd7a54 | 1895 | |
9125cdd1 GC |
1896 | del_timer_sync(&priv->txtimer); |
1897 | ||
47dd7a54 GC |
1898 | /* Free the IRQ lines */ |
1899 | free_irq(dev->irq, dev); | |
7a13f8f5 FV |
1900 | if (priv->wol_irq != dev->irq) |
1901 | free_irq(priv->wol_irq, dev); | |
d7ec8584 | 1902 | if (priv->lpi_irq > 0) |
d765955d | 1903 | free_irq(priv->lpi_irq, dev); |
47dd7a54 GC |
1904 | |
1905 | /* Stop TX/RX DMA and clear the descriptors */ | |
ad01b7d4 GC |
1906 | priv->hw->dma->stop_tx(priv->ioaddr); |
1907 | priv->hw->dma->stop_rx(priv->ioaddr); | |
47dd7a54 GC |
1908 | |
1909 | /* Release and free the Rx/Tx resources */ | |
1910 | free_dma_desc_resources(priv); | |
1911 | ||
19449bfc | 1912 | /* Disable the MAC Rx/Tx */ |
bfab27a1 | 1913 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 GC |
1914 | |
1915 | netif_carrier_off(dev); | |
1916 | ||
50fb4f74 | 1917 | #ifdef CONFIG_DEBUG_FS |
466c5ac8 | 1918 | stmmac_exit_fs(dev); |
bfab27a1 | 1919 | #endif |
bfab27a1 | 1920 | |
92ba6888 RK |
1921 | stmmac_release_ptp(priv); |
1922 | ||
47dd7a54 GC |
1923 | return 0; |
1924 | } | |
1925 | ||
f748be53 AT |
1926 | /** |
1927 | * stmmac_tso_allocator - close entry point of the driver | |
1928 | * @priv: driver private structure | |
1929 | * @des: buffer start address | |
1930 | * @total_len: total length to fill in descriptors | |
1931 | * @last_segmant: condition for the last descriptor | |
1932 | * Description: | |
1933 | * This function fills descriptor and request new descriptors according to | |
1934 | * buffer length to fill | |
1935 | */ | |
1936 | static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des, | |
1937 | int total_len, bool last_segment) | |
1938 | { | |
1939 | struct dma_desc *desc; | |
1940 | int tmp_len; | |
1941 | u32 buff_size; | |
1942 | ||
1943 | tmp_len = total_len; | |
1944 | ||
1945 | while (tmp_len > 0) { | |
1946 | priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); | |
1947 | desc = priv->dma_tx + priv->cur_tx; | |
1948 | ||
f8be0d78 | 1949 | desc->des0 = cpu_to_le32(des + (total_len - tmp_len)); |
f748be53 AT |
1950 | buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? |
1951 | TSO_MAX_BUFF_SIZE : tmp_len; | |
1952 | ||
1953 | priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size, | |
1954 | 0, 1, | |
1955 | (last_segment) && (buff_size < TSO_MAX_BUFF_SIZE), | |
1956 | 0, 0); | |
1957 | ||
1958 | tmp_len -= TSO_MAX_BUFF_SIZE; | |
1959 | } | |
1960 | } | |
1961 | ||
1962 | /** | |
1963 | * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) | |
1964 | * @skb : the socket buffer | |
1965 | * @dev : device pointer | |
1966 | * Description: this is the transmit function that is called on TSO frames | |
1967 | * (support available on GMAC4 and newer chips). | |
1968 | * Diagram below show the ring programming in case of TSO frames: | |
1969 | * | |
1970 | * First Descriptor | |
1971 | * -------- | |
1972 | * | DES0 |---> buffer1 = L2/L3/L4 header | |
1973 | * | DES1 |---> TCP Payload (can continue on next descr...) | |
1974 | * | DES2 |---> buffer 1 and 2 len | |
1975 | * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] | |
1976 | * -------- | |
1977 | * | | |
1978 | * ... | |
1979 | * | | |
1980 | * -------- | |
1981 | * | DES0 | --| Split TCP Payload on Buffers 1 and 2 | |
1982 | * | DES1 | --| | |
1983 | * | DES2 | --> buffer 1 and 2 len | |
1984 | * | DES3 | | |
1985 | * -------- | |
1986 | * | |
1987 | * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. | |
1988 | */ | |
1989 | static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) | |
1990 | { | |
1991 | u32 pay_len, mss; | |
1992 | int tmp_pay_len = 0; | |
1993 | struct stmmac_priv *priv = netdev_priv(dev); | |
1994 | int nfrags = skb_shinfo(skb)->nr_frags; | |
1995 | unsigned int first_entry, des; | |
1996 | struct dma_desc *desc, *first, *mss_desc = NULL; | |
1997 | u8 proto_hdr_len; | |
1998 | int i; | |
1999 | ||
f748be53 AT |
2000 | /* Compute header lengths */ |
2001 | proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
2002 | ||
2003 | /* Desc availability based on threshold should be enough safe */ | |
2004 | if (unlikely(stmmac_tx_avail(priv) < | |
2005 | (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { | |
2006 | if (!netif_queue_stopped(dev)) { | |
2007 | netif_stop_queue(dev); | |
2008 | /* This is a hard error, log it. */ | |
38ddc59d LC |
2009 | netdev_err(priv->dev, |
2010 | "%s: Tx Ring full when queue awake\n", | |
2011 | __func__); | |
f748be53 | 2012 | } |
f748be53 AT |
2013 | return NETDEV_TX_BUSY; |
2014 | } | |
2015 | ||
2016 | pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ | |
2017 | ||
2018 | mss = skb_shinfo(skb)->gso_size; | |
2019 | ||
2020 | /* set new MSS value if needed */ | |
2021 | if (mss != priv->mss) { | |
2022 | mss_desc = priv->dma_tx + priv->cur_tx; | |
2023 | priv->hw->desc->set_mss(mss_desc, mss); | |
2024 | priv->mss = mss; | |
2025 | priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); | |
2026 | } | |
2027 | ||
2028 | if (netif_msg_tx_queued(priv)) { | |
2029 | pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n", | |
2030 | __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss); | |
2031 | pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, | |
2032 | skb->data_len); | |
2033 | } | |
2034 | ||
2035 | first_entry = priv->cur_tx; | |
2036 | ||
2037 | desc = priv->dma_tx + first_entry; | |
2038 | first = desc; | |
2039 | ||
2040 | /* first descriptor: fill Headers on Buf1 */ | |
2041 | des = dma_map_single(priv->device, skb->data, skb_headlen(skb), | |
2042 | DMA_TO_DEVICE); | |
2043 | if (dma_mapping_error(priv->device, des)) | |
2044 | goto dma_map_err; | |
2045 | ||
2046 | priv->tx_skbuff_dma[first_entry].buf = des; | |
2047 | priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb); | |
2048 | priv->tx_skbuff[first_entry] = skb; | |
2049 | ||
f8be0d78 | 2050 | first->des0 = cpu_to_le32(des); |
f748be53 AT |
2051 | |
2052 | /* Fill start of payload in buff2 of first descriptor */ | |
2053 | if (pay_len) | |
f8be0d78 | 2054 | first->des1 = cpu_to_le32(des + proto_hdr_len); |
f748be53 AT |
2055 | |
2056 | /* If needed take extra descriptors to fill the remaining payload */ | |
2057 | tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; | |
2058 | ||
2059 | stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0)); | |
2060 | ||
2061 | /* Prepare fragments */ | |
2062 | for (i = 0; i < nfrags; i++) { | |
2063 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2064 | ||
2065 | des = skb_frag_dma_map(priv->device, frag, 0, | |
2066 | skb_frag_size(frag), | |
2067 | DMA_TO_DEVICE); | |
2068 | ||
2069 | stmmac_tso_allocator(priv, des, skb_frag_size(frag), | |
2070 | (i == nfrags - 1)); | |
2071 | ||
2072 | priv->tx_skbuff_dma[priv->cur_tx].buf = des; | |
2073 | priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag); | |
2074 | priv->tx_skbuff[priv->cur_tx] = NULL; | |
2075 | priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true; | |
2076 | } | |
2077 | ||
2078 | priv->tx_skbuff_dma[priv->cur_tx].last_segment = true; | |
2079 | ||
2080 | priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE); | |
2081 | ||
2082 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { | |
b3e51069 LC |
2083 | netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", |
2084 | __func__); | |
f748be53 AT |
2085 | netif_stop_queue(dev); |
2086 | } | |
2087 | ||
2088 | dev->stats.tx_bytes += skb->len; | |
2089 | priv->xstats.tx_tso_frames++; | |
2090 | priv->xstats.tx_tso_nfrags += nfrags; | |
2091 | ||
2092 | /* Manage tx mitigation */ | |
2093 | priv->tx_count_frames += nfrags + 1; | |
2094 | if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { | |
2095 | mod_timer(&priv->txtimer, | |
2096 | STMMAC_COAL_TIMER(priv->tx_coal_timer)); | |
2097 | } else { | |
2098 | priv->tx_count_frames = 0; | |
2099 | priv->hw->desc->set_tx_ic(desc); | |
2100 | priv->xstats.tx_set_ic_bit++; | |
2101 | } | |
2102 | ||
2103 | if (!priv->hwts_tx_en) | |
2104 | skb_tx_timestamp(skb); | |
2105 | ||
2106 | if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && | |
2107 | priv->hwts_tx_en)) { | |
2108 | /* declare that device is doing timestamping */ | |
2109 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
2110 | priv->hw->desc->enable_tx_timestamp(first); | |
2111 | } | |
2112 | ||
2113 | /* Complete the first descriptor before granting the DMA */ | |
2114 | priv->hw->desc->prepare_tso_tx_desc(first, 1, | |
2115 | proto_hdr_len, | |
2116 | pay_len, | |
2117 | 1, priv->tx_skbuff_dma[first_entry].last_segment, | |
2118 | tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len)); | |
2119 | ||
2120 | /* If context desc is used to change MSS */ | |
2121 | if (mss_desc) | |
2122 | priv->hw->desc->set_tx_owner(mss_desc); | |
2123 | ||
2124 | /* The own bit must be the latest setting done when prepare the | |
2125 | * descriptor and then barrier is needed to make sure that | |
2126 | * all is coherent before granting the DMA engine. | |
2127 | */ | |
2128 | smp_wmb(); | |
2129 | ||
2130 | if (netif_msg_pktdata(priv)) { | |
2131 | pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", | |
2132 | __func__, priv->cur_tx, priv->dirty_tx, first_entry, | |
2133 | priv->cur_tx, first, nfrags); | |
2134 | ||
2135 | priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE, | |
2136 | 0); | |
2137 | ||
2138 | pr_info(">>> frame to be transmitted: "); | |
2139 | print_pkt(skb->data, skb_headlen(skb)); | |
2140 | } | |
2141 | ||
2142 | netdev_sent_queue(dev, skb->len); | |
2143 | ||
2144 | priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, | |
2145 | STMMAC_CHAN0); | |
2146 | ||
f748be53 AT |
2147 | return NETDEV_TX_OK; |
2148 | ||
2149 | dma_map_err: | |
f748be53 AT |
2150 | dev_err(priv->device, "Tx dma map failed\n"); |
2151 | dev_kfree_skb(skb); | |
2152 | priv->dev->stats.tx_dropped++; | |
2153 | return NETDEV_TX_OK; | |
2154 | } | |
2155 | ||
47dd7a54 | 2156 | /** |
732fdf0e | 2157 | * stmmac_xmit - Tx entry point of the driver |
47dd7a54 GC |
2158 | * @skb : the socket buffer |
2159 | * @dev : device pointer | |
32ceabca GC |
2160 | * Description : this is the tx entry point of the driver. |
2161 | * It programs the chain or the ring and supports oversized frames | |
2162 | * and SG feature. | |
47dd7a54 GC |
2163 | */ |
2164 | static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) | |
2165 | { | |
2166 | struct stmmac_priv *priv = netdev_priv(dev); | |
0e80bdc9 | 2167 | unsigned int nopaged_len = skb_headlen(skb); |
4a7d666a | 2168 | int i, csum_insertion = 0, is_jumbo = 0; |
47dd7a54 | 2169 | int nfrags = skb_shinfo(skb)->nr_frags; |
0e80bdc9 | 2170 | unsigned int entry, first_entry; |
47dd7a54 | 2171 | struct dma_desc *desc, *first; |
0e80bdc9 | 2172 | unsigned int enh_desc; |
f748be53 AT |
2173 | unsigned int des; |
2174 | ||
2175 | /* Manage oversized TCP frames for GMAC4 device */ | |
2176 | if (skb_is_gso(skb) && priv->tso) { | |
2177 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) | |
2178 | return stmmac_tso_xmit(skb, dev); | |
2179 | } | |
47dd7a54 GC |
2180 | |
2181 | if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { | |
2182 | if (!netif_queue_stopped(dev)) { | |
2183 | netif_stop_queue(dev); | |
2184 | /* This is a hard error, log it. */ | |
38ddc59d LC |
2185 | netdev_err(priv->dev, |
2186 | "%s: Tx Ring full when queue awake\n", | |
2187 | __func__); | |
47dd7a54 GC |
2188 | } |
2189 | return NETDEV_TX_BUSY; | |
2190 | } | |
2191 | ||
d765955d GC |
2192 | if (priv->tx_path_in_lpi_mode) |
2193 | stmmac_disable_eee_mode(priv); | |
2194 | ||
e3ad57c9 | 2195 | entry = priv->cur_tx; |
0e80bdc9 | 2196 | first_entry = entry; |
47dd7a54 | 2197 | |
5e982f3b | 2198 | csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); |
47dd7a54 | 2199 | |
0e80bdc9 | 2200 | if (likely(priv->extend_desc)) |
ceb69499 | 2201 | desc = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
2202 | else |
2203 | desc = priv->dma_tx + entry; | |
2204 | ||
47dd7a54 GC |
2205 | first = desc; |
2206 | ||
0e80bdc9 GC |
2207 | priv->tx_skbuff[first_entry] = skb; |
2208 | ||
2209 | enh_desc = priv->plat->enh_desc; | |
4a7d666a | 2210 | /* To program the descriptors according to the size of the frame */ |
29896a67 GC |
2211 | if (enh_desc) |
2212 | is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); | |
2213 | ||
f748be53 AT |
2214 | if (unlikely(is_jumbo) && likely(priv->synopsys_id < |
2215 | DWMAC_CORE_4_00)) { | |
29896a67 | 2216 | entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); |
362b37be GC |
2217 | if (unlikely(entry < 0)) |
2218 | goto dma_map_err; | |
29896a67 | 2219 | } |
47dd7a54 GC |
2220 | |
2221 | for (i = 0; i < nfrags; i++) { | |
9e903e08 ED |
2222 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
2223 | int len = skb_frag_size(frag); | |
be434d50 | 2224 | bool last_segment = (i == (nfrags - 1)); |
47dd7a54 | 2225 | |
e3ad57c9 GC |
2226 | entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); |
2227 | ||
0e80bdc9 | 2228 | if (likely(priv->extend_desc)) |
ceb69499 | 2229 | desc = (struct dma_desc *)(priv->dma_etx + entry); |
c24602ef GC |
2230 | else |
2231 | desc = priv->dma_tx + entry; | |
47dd7a54 | 2232 | |
f748be53 AT |
2233 | des = skb_frag_dma_map(priv->device, frag, 0, len, |
2234 | DMA_TO_DEVICE); | |
2235 | if (dma_mapping_error(priv->device, des)) | |
362b37be GC |
2236 | goto dma_map_err; /* should reuse desc w/o issues */ |
2237 | ||
0e80bdc9 | 2238 | priv->tx_skbuff[entry] = NULL; |
f748be53 | 2239 | |
f8be0d78 MW |
2240 | priv->tx_skbuff_dma[entry].buf = des; |
2241 | if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) | |
2242 | desc->des0 = cpu_to_le32(des); | |
2243 | else | |
2244 | desc->des2 = cpu_to_le32(des); | |
f748be53 | 2245 | |
362b37be | 2246 | priv->tx_skbuff_dma[entry].map_as_page = true; |
553e2ab3 | 2247 | priv->tx_skbuff_dma[entry].len = len; |
0e80bdc9 GC |
2248 | priv->tx_skbuff_dma[entry].last_segment = last_segment; |
2249 | ||
2250 | /* Prepare the descriptor and set the own bit too */ | |
4a7d666a | 2251 | priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, |
be434d50 | 2252 | priv->mode, 1, last_segment); |
47dd7a54 GC |
2253 | } |
2254 | ||
e3ad57c9 GC |
2255 | entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); |
2256 | ||
2257 | priv->cur_tx = entry; | |
47dd7a54 | 2258 | |
47dd7a54 | 2259 | if (netif_msg_pktdata(priv)) { |
d0225e7d AT |
2260 | void *tx_head; |
2261 | ||
38ddc59d LC |
2262 | netdev_dbg(priv->dev, |
2263 | "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", | |
2264 | __func__, priv->cur_tx, priv->dirty_tx, first_entry, | |
2265 | entry, first, nfrags); | |
83d7af64 | 2266 | |
c24602ef | 2267 | if (priv->extend_desc) |
d0225e7d | 2268 | tx_head = (void *)priv->dma_etx; |
c24602ef | 2269 | else |
d0225e7d AT |
2270 | tx_head = (void *)priv->dma_tx; |
2271 | ||
2272 | priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false); | |
c24602ef | 2273 | |
38ddc59d | 2274 | netdev_dbg(priv->dev, ">>> frame to be transmitted: "); |
47dd7a54 GC |
2275 | print_pkt(skb->data, skb->len); |
2276 | } | |
0e80bdc9 | 2277 | |
47dd7a54 | 2278 | if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { |
b3e51069 LC |
2279 | netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", |
2280 | __func__); | |
47dd7a54 GC |
2281 | netif_stop_queue(dev); |
2282 | } | |
2283 | ||
2284 | dev->stats.tx_bytes += skb->len; | |
2285 | ||
0e80bdc9 GC |
2286 | /* According to the coalesce parameter the IC bit for the latest |
2287 | * segment is reset and the timer re-started to clean the tx status. | |
2288 | * This approach takes care about the fragments: desc is the first | |
2289 | * element in case of no SG. | |
2290 | */ | |
2291 | priv->tx_count_frames += nfrags + 1; | |
2292 | if (likely(priv->tx_coal_frames > priv->tx_count_frames)) { | |
2293 | mod_timer(&priv->txtimer, | |
2294 | STMMAC_COAL_TIMER(priv->tx_coal_timer)); | |
2295 | } else { | |
2296 | priv->tx_count_frames = 0; | |
2297 | priv->hw->desc->set_tx_ic(desc); | |
2298 | priv->xstats.tx_set_ic_bit++; | |
891434b1 RK |
2299 | } |
2300 | ||
2301 | if (!priv->hwts_tx_en) | |
2302 | skb_tx_timestamp(skb); | |
3e82ce12 | 2303 | |
0e80bdc9 GC |
2304 | /* Ready to fill the first descriptor and set the OWN bit w/o any |
2305 | * problems because all the descriptors are actually ready to be | |
2306 | * passed to the DMA engine. | |
2307 | */ | |
2308 | if (likely(!is_jumbo)) { | |
2309 | bool last_segment = (nfrags == 0); | |
2310 | ||
f748be53 AT |
2311 | des = dma_map_single(priv->device, skb->data, |
2312 | nopaged_len, DMA_TO_DEVICE); | |
2313 | if (dma_mapping_error(priv->device, des)) | |
0e80bdc9 GC |
2314 | goto dma_map_err; |
2315 | ||
f8be0d78 MW |
2316 | priv->tx_skbuff_dma[first_entry].buf = des; |
2317 | if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) | |
2318 | first->des0 = cpu_to_le32(des); | |
2319 | else | |
2320 | first->des2 = cpu_to_le32(des); | |
f748be53 | 2321 | |
0e80bdc9 GC |
2322 | priv->tx_skbuff_dma[first_entry].len = nopaged_len; |
2323 | priv->tx_skbuff_dma[first_entry].last_segment = last_segment; | |
2324 | ||
2325 | if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && | |
2326 | priv->hwts_tx_en)) { | |
2327 | /* declare that device is doing timestamping */ | |
2328 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
2329 | priv->hw->desc->enable_tx_timestamp(first); | |
2330 | } | |
2331 | ||
2332 | /* Prepare the first descriptor setting the OWN bit too */ | |
2333 | priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len, | |
2334 | csum_insertion, priv->mode, 1, | |
2335 | last_segment); | |
2336 | ||
2337 | /* The own bit must be the latest setting done when prepare the | |
2338 | * descriptor and then barrier is needed to make sure that | |
2339 | * all is coherent before granting the DMA engine. | |
2340 | */ | |
2341 | smp_wmb(); | |
2342 | } | |
2343 | ||
38979574 | 2344 | netdev_sent_queue(dev, skb->len); |
f748be53 AT |
2345 | |
2346 | if (priv->synopsys_id < DWMAC_CORE_4_00) | |
2347 | priv->hw->dma->enable_dma_transmission(priv->ioaddr); | |
2348 | else | |
2349 | priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr, | |
2350 | STMMAC_CHAN0); | |
52f64fae | 2351 | |
362b37be | 2352 | return NETDEV_TX_OK; |
a9097a96 | 2353 | |
362b37be | 2354 | dma_map_err: |
38ddc59d | 2355 | netdev_err(priv->dev, "Tx DMA map failed\n"); |
362b37be GC |
2356 | dev_kfree_skb(skb); |
2357 | priv->dev->stats.tx_dropped++; | |
47dd7a54 GC |
2358 | return NETDEV_TX_OK; |
2359 | } | |
2360 | ||
b9381985 VB |
2361 | static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) |
2362 | { | |
2363 | struct ethhdr *ehdr; | |
2364 | u16 vlanid; | |
2365 | ||
2366 | if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == | |
2367 | NETIF_F_HW_VLAN_CTAG_RX && | |
2368 | !__vlan_get_tag(skb, &vlanid)) { | |
2369 | /* pop the vlan tag */ | |
2370 | ehdr = (struct ethhdr *)skb->data; | |
2371 | memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); | |
2372 | skb_pull(skb, VLAN_HLEN); | |
2373 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); | |
2374 | } | |
2375 | } | |
2376 | ||
2377 | ||
120e87f9 GC |
2378 | static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv) |
2379 | { | |
2380 | if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH) | |
2381 | return 0; | |
2382 | ||
2383 | return 1; | |
2384 | } | |
2385 | ||
32ceabca | 2386 | /** |
732fdf0e | 2387 | * stmmac_rx_refill - refill used skb preallocated buffers |
32ceabca GC |
2388 | * @priv: driver private structure |
2389 | * Description : this is to reallocate the skb for the reception process | |
2390 | * that is based on zero-copy. | |
2391 | */ | |
47dd7a54 GC |
2392 | static inline void stmmac_rx_refill(struct stmmac_priv *priv) |
2393 | { | |
47dd7a54 | 2394 | int bfsize = priv->dma_buf_sz; |
e3ad57c9 GC |
2395 | unsigned int entry = priv->dirty_rx; |
2396 | int dirty = stmmac_rx_dirty(priv); | |
47dd7a54 | 2397 | |
e3ad57c9 | 2398 | while (dirty-- > 0) { |
c24602ef GC |
2399 | struct dma_desc *p; |
2400 | ||
2401 | if (priv->extend_desc) | |
ceb69499 | 2402 | p = (struct dma_desc *)(priv->dma_erx + entry); |
c24602ef GC |
2403 | else |
2404 | p = priv->dma_rx + entry; | |
2405 | ||
47dd7a54 GC |
2406 | if (likely(priv->rx_skbuff[entry] == NULL)) { |
2407 | struct sk_buff *skb; | |
2408 | ||
acb600de | 2409 | skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); |
120e87f9 GC |
2410 | if (unlikely(!skb)) { |
2411 | /* so for a while no zero-copy! */ | |
2412 | priv->rx_zeroc_thresh = STMMAC_RX_THRESH; | |
2413 | if (unlikely(net_ratelimit())) | |
2414 | dev_err(priv->device, | |
2415 | "fail to alloc skb entry %d\n", | |
2416 | entry); | |
47dd7a54 | 2417 | break; |
120e87f9 | 2418 | } |
47dd7a54 GC |
2419 | |
2420 | priv->rx_skbuff[entry] = skb; | |
2421 | priv->rx_skbuff_dma[entry] = | |
2422 | dma_map_single(priv->device, skb->data, bfsize, | |
2423 | DMA_FROM_DEVICE); | |
362b37be GC |
2424 | if (dma_mapping_error(priv->device, |
2425 | priv->rx_skbuff_dma[entry])) { | |
38ddc59d | 2426 | netdev_err(priv->dev, "Rx DMA map failed\n"); |
362b37be GC |
2427 | dev_kfree_skb(skb); |
2428 | break; | |
2429 | } | |
286a8372 | 2430 | |
f748be53 | 2431 | if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) { |
f8be0d78 | 2432 | p->des0 = cpu_to_le32(priv->rx_skbuff_dma[entry]); |
f748be53 AT |
2433 | p->des1 = 0; |
2434 | } else { | |
f8be0d78 | 2435 | p->des2 = cpu_to_le32(priv->rx_skbuff_dma[entry]); |
f748be53 AT |
2436 | } |
2437 | if (priv->hw->mode->refill_desc3) | |
2438 | priv->hw->mode->refill_desc3(priv, p); | |
286a8372 | 2439 | |
120e87f9 GC |
2440 | if (priv->rx_zeroc_thresh > 0) |
2441 | priv->rx_zeroc_thresh--; | |
2442 | ||
b3e51069 LC |
2443 | netif_dbg(priv, rx_status, priv->dev, |
2444 | "refill entry #%d\n", entry); | |
47dd7a54 | 2445 | } |
eb0dc4bb | 2446 | wmb(); |
f748be53 AT |
2447 | |
2448 | if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) | |
2449 | priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0); | |
2450 | else | |
2451 | priv->hw->desc->set_rx_owner(p); | |
2452 | ||
8e839891 | 2453 | wmb(); |
e3ad57c9 GC |
2454 | |
2455 | entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); | |
47dd7a54 | 2456 | } |
e3ad57c9 | 2457 | priv->dirty_rx = entry; |
47dd7a54 GC |
2458 | } |
2459 | ||
32ceabca | 2460 | /** |
732fdf0e | 2461 | * stmmac_rx - manage the receive process |
32ceabca GC |
2462 | * @priv: driver private structure |
2463 | * @limit: napi bugget. | |
2464 | * Description : this the function called by the napi poll method. | |
2465 | * It gets all the frames inside the ring. | |
2466 | */ | |
47dd7a54 GC |
2467 | static int stmmac_rx(struct stmmac_priv *priv, int limit) |
2468 | { | |
e3ad57c9 | 2469 | unsigned int entry = priv->cur_rx; |
47dd7a54 GC |
2470 | unsigned int next_entry; |
2471 | unsigned int count = 0; | |
d2afb5bd | 2472 | int coe = priv->hw->rx_csum; |
47dd7a54 | 2473 | |
83d7af64 | 2474 | if (netif_msg_rx_status(priv)) { |
d0225e7d AT |
2475 | void *rx_head; |
2476 | ||
38ddc59d | 2477 | netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); |
c24602ef | 2478 | if (priv->extend_desc) |
d0225e7d | 2479 | rx_head = (void *)priv->dma_erx; |
c24602ef | 2480 | else |
d0225e7d AT |
2481 | rx_head = (void *)priv->dma_rx; |
2482 | ||
2483 | priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true); | |
47dd7a54 | 2484 | } |
c24602ef | 2485 | while (count < limit) { |
47dd7a54 | 2486 | int status; |
9401bb5c | 2487 | struct dma_desc *p; |
ba1ffd74 | 2488 | struct dma_desc *np; |
47dd7a54 | 2489 | |
c24602ef | 2490 | if (priv->extend_desc) |
ceb69499 | 2491 | p = (struct dma_desc *)(priv->dma_erx + entry); |
c24602ef | 2492 | else |
ceb69499 | 2493 | p = priv->dma_rx + entry; |
c24602ef | 2494 | |
c1fa3212 FG |
2495 | /* read the status of the incoming frame */ |
2496 | status = priv->hw->desc->rx_status(&priv->dev->stats, | |
2497 | &priv->xstats, p); | |
2498 | /* check if managed by the DMA otherwise go ahead */ | |
2499 | if (unlikely(status & dma_own)) | |
47dd7a54 GC |
2500 | break; |
2501 | ||
2502 | count++; | |
2503 | ||
e3ad57c9 GC |
2504 | priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE); |
2505 | next_entry = priv->cur_rx; | |
2506 | ||
c24602ef | 2507 | if (priv->extend_desc) |
ba1ffd74 | 2508 | np = (struct dma_desc *)(priv->dma_erx + next_entry); |
c24602ef | 2509 | else |
ba1ffd74 GC |
2510 | np = priv->dma_rx + next_entry; |
2511 | ||
2512 | prefetch(np); | |
47dd7a54 | 2513 | |
c24602ef GC |
2514 | if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) |
2515 | priv->hw->desc->rx_extended_status(&priv->dev->stats, | |
2516 | &priv->xstats, | |
2517 | priv->dma_erx + | |
2518 | entry); | |
891434b1 | 2519 | if (unlikely(status == discard_frame)) { |
47dd7a54 | 2520 | priv->dev->stats.rx_errors++; |
891434b1 RK |
2521 | if (priv->hwts_rx_en && !priv->extend_desc) { |
2522 | /* DESC2 & DESC3 will be overwitten by device | |
2523 | * with timestamp value, hence reinitialize | |
2524 | * them in stmmac_rx_refill() function so that | |
2525 | * device can reuse it. | |
2526 | */ | |
2527 | priv->rx_skbuff[entry] = NULL; | |
2528 | dma_unmap_single(priv->device, | |
ceb69499 GC |
2529 | priv->rx_skbuff_dma[entry], |
2530 | priv->dma_buf_sz, | |
2531 | DMA_FROM_DEVICE); | |
891434b1 RK |
2532 | } |
2533 | } else { | |
47dd7a54 | 2534 | struct sk_buff *skb; |
3eeb2997 | 2535 | int frame_len; |
f748be53 AT |
2536 | unsigned int des; |
2537 | ||
2538 | if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) | |
f8be0d78 | 2539 | des = le32_to_cpu(p->des0); |
f748be53 | 2540 | else |
f8be0d78 | 2541 | des = le32_to_cpu(p->des2); |
47dd7a54 | 2542 | |
ceb69499 GC |
2543 | frame_len = priv->hw->desc->get_rx_frame_len(p, coe); |
2544 | ||
f748be53 AT |
2545 | /* If frame length is greather than skb buffer size |
2546 | * (preallocated during init) then the packet is | |
2547 | * ignored | |
2548 | */ | |
e527c4a7 | 2549 | if (frame_len > priv->dma_buf_sz) { |
38ddc59d LC |
2550 | netdev_err(priv->dev, |
2551 | "len %d larger than size (%d)\n", | |
2552 | frame_len, priv->dma_buf_sz); | |
e527c4a7 GC |
2553 | priv->dev->stats.rx_length_errors++; |
2554 | break; | |
2555 | } | |
2556 | ||
3eeb2997 | 2557 | /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 |
ceb69499 GC |
2558 | * Type frames (LLC/LLC-SNAP) |
2559 | */ | |
3eeb2997 GC |
2560 | if (unlikely(status != llc_snap)) |
2561 | frame_len -= ETH_FCS_LEN; | |
47dd7a54 | 2562 | |
83d7af64 | 2563 | if (netif_msg_rx_status(priv)) { |
38ddc59d LC |
2564 | netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n", |
2565 | p, entry, des); | |
83d7af64 | 2566 | if (frame_len > ETH_FRAME_LEN) |
38ddc59d LC |
2567 | netdev_dbg(priv->dev, "frame size %d, COE: %d\n", |
2568 | frame_len, status); | |
83d7af64 | 2569 | } |
22ad3838 | 2570 | |
f748be53 AT |
2571 | /* The zero-copy is always used for all the sizes |
2572 | * in case of GMAC4 because it needs | |
2573 | * to refill the used descriptors, always. | |
2574 | */ | |
2575 | if (unlikely(!priv->plat->has_gmac4 && | |
2576 | ((frame_len < priv->rx_copybreak) || | |
2577 | stmmac_rx_threshold_count(priv)))) { | |
22ad3838 GC |
2578 | skb = netdev_alloc_skb_ip_align(priv->dev, |
2579 | frame_len); | |
2580 | if (unlikely(!skb)) { | |
2581 | if (net_ratelimit()) | |
2582 | dev_warn(priv->device, | |
2583 | "packet dropped\n"); | |
2584 | priv->dev->stats.rx_dropped++; | |
2585 | break; | |
2586 | } | |
2587 | ||
2588 | dma_sync_single_for_cpu(priv->device, | |
2589 | priv->rx_skbuff_dma | |
2590 | [entry], frame_len, | |
2591 | DMA_FROM_DEVICE); | |
2592 | skb_copy_to_linear_data(skb, | |
2593 | priv-> | |
2594 | rx_skbuff[entry]->data, | |
2595 | frame_len); | |
2596 | ||
2597 | skb_put(skb, frame_len); | |
2598 | dma_sync_single_for_device(priv->device, | |
2599 | priv->rx_skbuff_dma | |
2600 | [entry], frame_len, | |
2601 | DMA_FROM_DEVICE); | |
2602 | } else { | |
2603 | skb = priv->rx_skbuff[entry]; | |
2604 | if (unlikely(!skb)) { | |
38ddc59d LC |
2605 | netdev_err(priv->dev, |
2606 | "%s: Inconsistent Rx chain\n", | |
2607 | priv->dev->name); | |
22ad3838 GC |
2608 | priv->dev->stats.rx_dropped++; |
2609 | break; | |
2610 | } | |
2611 | prefetch(skb->data - NET_IP_ALIGN); | |
2612 | priv->rx_skbuff[entry] = NULL; | |
120e87f9 | 2613 | priv->rx_zeroc_thresh++; |
22ad3838 GC |
2614 | |
2615 | skb_put(skb, frame_len); | |
2616 | dma_unmap_single(priv->device, | |
2617 | priv->rx_skbuff_dma[entry], | |
2618 | priv->dma_buf_sz, | |
2619 | DMA_FROM_DEVICE); | |
47dd7a54 | 2620 | } |
47dd7a54 | 2621 | |
47dd7a54 | 2622 | if (netif_msg_pktdata(priv)) { |
38ddc59d LC |
2623 | netdev_dbg(priv->dev, "frame received (%dbytes)", |
2624 | frame_len); | |
47dd7a54 GC |
2625 | print_pkt(skb->data, frame_len); |
2626 | } | |
83d7af64 | 2627 | |
ba1ffd74 GC |
2628 | stmmac_get_rx_hwtstamp(priv, p, np, skb); |
2629 | ||
b9381985 VB |
2630 | stmmac_rx_vlan(priv->dev, skb); |
2631 | ||
47dd7a54 GC |
2632 | skb->protocol = eth_type_trans(skb, priv->dev); |
2633 | ||
ceb69499 | 2634 | if (unlikely(!coe)) |
bc8acf2c | 2635 | skb_checksum_none_assert(skb); |
62a2ab93 | 2636 | else |
47dd7a54 | 2637 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
62a2ab93 GC |
2638 | |
2639 | napi_gro_receive(&priv->napi, skb); | |
47dd7a54 GC |
2640 | |
2641 | priv->dev->stats.rx_packets++; | |
2642 | priv->dev->stats.rx_bytes += frame_len; | |
47dd7a54 GC |
2643 | } |
2644 | entry = next_entry; | |
47dd7a54 GC |
2645 | } |
2646 | ||
2647 | stmmac_rx_refill(priv); | |
2648 | ||
2649 | priv->xstats.rx_pkt_n += count; | |
2650 | ||
2651 | return count; | |
2652 | } | |
2653 | ||
2654 | /** | |
2655 | * stmmac_poll - stmmac poll method (NAPI) | |
2656 | * @napi : pointer to the napi structure. | |
2657 | * @budget : maximum number of packets that the current CPU can receive from | |
2658 | * all interfaces. | |
2659 | * Description : | |
9125cdd1 | 2660 | * To look at the incoming frames and clear the tx resources. |
47dd7a54 GC |
2661 | */ |
2662 | static int stmmac_poll(struct napi_struct *napi, int budget) | |
2663 | { | |
2664 | struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); | |
2665 | int work_done = 0; | |
2666 | ||
9125cdd1 GC |
2667 | priv->xstats.napi_poll++; |
2668 | stmmac_tx_clean(priv); | |
47dd7a54 | 2669 | |
9125cdd1 | 2670 | work_done = stmmac_rx(priv, budget); |
47dd7a54 GC |
2671 | if (work_done < budget) { |
2672 | napi_complete(napi); | |
9125cdd1 | 2673 | stmmac_enable_dma_irq(priv); |
47dd7a54 GC |
2674 | } |
2675 | return work_done; | |
2676 | } | |
2677 | ||
2678 | /** | |
2679 | * stmmac_tx_timeout | |
2680 | * @dev : Pointer to net device structure | |
2681 | * Description: this function is called when a packet transmission fails to | |
7284a3f1 | 2682 | * complete within a reasonable time. The driver will mark the error in the |
47dd7a54 GC |
2683 | * netdev structure and arrange for the device to be reset to a sane state |
2684 | * in order to transmit a new packet. | |
2685 | */ | |
2686 | static void stmmac_tx_timeout(struct net_device *dev) | |
2687 | { | |
2688 | struct stmmac_priv *priv = netdev_priv(dev); | |
2689 | ||
2690 | /* Clear Tx resources and restart transmitting again */ | |
2691 | stmmac_tx_err(priv); | |
47dd7a54 GC |
2692 | } |
2693 | ||
47dd7a54 | 2694 | /** |
01789349 | 2695 | * stmmac_set_rx_mode - entry point for multicast addressing |
47dd7a54 GC |
2696 | * @dev : pointer to the device structure |
2697 | * Description: | |
2698 | * This function is a driver entry point which gets called by the kernel | |
2699 | * whenever multicast addresses must be enabled/disabled. | |
2700 | * Return value: | |
2701 | * void. | |
2702 | */ | |
01789349 | 2703 | static void stmmac_set_rx_mode(struct net_device *dev) |
47dd7a54 GC |
2704 | { |
2705 | struct stmmac_priv *priv = netdev_priv(dev); | |
2706 | ||
3b57de95 | 2707 | priv->hw->mac->set_filter(priv->hw, dev); |
47dd7a54 GC |
2708 | } |
2709 | ||
2710 | /** | |
2711 | * stmmac_change_mtu - entry point to change MTU size for the device. | |
2712 | * @dev : device pointer. | |
2713 | * @new_mtu : the new MTU size for the device. | |
2714 | * Description: the Maximum Transfer Unit (MTU) is used by the network layer | |
2715 | * to drive packet transmission. Ethernet has an MTU of 1500 octets | |
2716 | * (ETH_DATA_LEN). This value can be changed with ifconfig. | |
2717 | * Return value: | |
2718 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
2719 | * file on failure. | |
2720 | */ | |
2721 | static int stmmac_change_mtu(struct net_device *dev, int new_mtu) | |
2722 | { | |
38ddc59d LC |
2723 | struct stmmac_priv *priv = netdev_priv(dev); |
2724 | ||
47dd7a54 | 2725 | if (netif_running(dev)) { |
38ddc59d | 2726 | netdev_err(priv->dev, "must be stopped to change its MTU\n"); |
47dd7a54 GC |
2727 | return -EBUSY; |
2728 | } | |
2729 | ||
5e982f3b | 2730 | dev->mtu = new_mtu; |
f748be53 | 2731 | |
5e982f3b MM |
2732 | netdev_update_features(dev); |
2733 | ||
2734 | return 0; | |
2735 | } | |
2736 | ||
c8f44aff | 2737 | static netdev_features_t stmmac_fix_features(struct net_device *dev, |
ceb69499 | 2738 | netdev_features_t features) |
5e982f3b MM |
2739 | { |
2740 | struct stmmac_priv *priv = netdev_priv(dev); | |
2741 | ||
38912bdb | 2742 | if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) |
5e982f3b | 2743 | features &= ~NETIF_F_RXCSUM; |
d2afb5bd | 2744 | |
5e982f3b | 2745 | if (!priv->plat->tx_coe) |
a188222b | 2746 | features &= ~NETIF_F_CSUM_MASK; |
5e982f3b | 2747 | |
ebbb293f GC |
2748 | /* Some GMAC devices have a bugged Jumbo frame support that |
2749 | * needs to have the Tx COE disabled for oversized frames | |
2750 | * (due to limited buffer sizes). In this case we disable | |
ceb69499 GC |
2751 | * the TX csum insertionin the TDES and not use SF. |
2752 | */ | |
5e982f3b | 2753 | if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) |
a188222b | 2754 | features &= ~NETIF_F_CSUM_MASK; |
ebbb293f | 2755 | |
f748be53 AT |
2756 | /* Disable tso if asked by ethtool */ |
2757 | if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { | |
2758 | if (features & NETIF_F_TSO) | |
2759 | priv->tso = true; | |
2760 | else | |
2761 | priv->tso = false; | |
2762 | } | |
2763 | ||
5e982f3b | 2764 | return features; |
47dd7a54 GC |
2765 | } |
2766 | ||
d2afb5bd GC |
2767 | static int stmmac_set_features(struct net_device *netdev, |
2768 | netdev_features_t features) | |
2769 | { | |
2770 | struct stmmac_priv *priv = netdev_priv(netdev); | |
2771 | ||
2772 | /* Keep the COE Type in case of csum is supporting */ | |
2773 | if (features & NETIF_F_RXCSUM) | |
2774 | priv->hw->rx_csum = priv->plat->rx_coe; | |
2775 | else | |
2776 | priv->hw->rx_csum = 0; | |
2777 | /* No check needed because rx_coe has been set before and it will be | |
2778 | * fixed in case of issue. | |
2779 | */ | |
2780 | priv->hw->mac->rx_ipc(priv->hw); | |
2781 | ||
2782 | return 0; | |
2783 | } | |
2784 | ||
32ceabca GC |
2785 | /** |
2786 | * stmmac_interrupt - main ISR | |
2787 | * @irq: interrupt number. | |
2788 | * @dev_id: to pass the net device pointer. | |
2789 | * Description: this is the main driver interrupt service routine. | |
732fdf0e GC |
2790 | * It can call: |
2791 | * o DMA service routine (to manage incoming frame reception and transmission | |
2792 | * status) | |
2793 | * o Core interrupts to manage: remote wake-up, management counter, LPI | |
2794 | * interrupts. | |
32ceabca | 2795 | */ |
47dd7a54 GC |
2796 | static irqreturn_t stmmac_interrupt(int irq, void *dev_id) |
2797 | { | |
2798 | struct net_device *dev = (struct net_device *)dev_id; | |
2799 | struct stmmac_priv *priv = netdev_priv(dev); | |
2800 | ||
89f7f2cf SK |
2801 | if (priv->irq_wake) |
2802 | pm_wakeup_event(priv->device, 0); | |
2803 | ||
47dd7a54 | 2804 | if (unlikely(!dev)) { |
38ddc59d | 2805 | netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); |
47dd7a54 GC |
2806 | return IRQ_NONE; |
2807 | } | |
2808 | ||
d765955d | 2809 | /* To handle GMAC own interrupts */ |
f748be53 | 2810 | if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) { |
7ed24bbe | 2811 | int status = priv->hw->mac->host_irq_status(priv->hw, |
0982a0f6 | 2812 | &priv->xstats); |
d765955d | 2813 | if (unlikely(status)) { |
d765955d | 2814 | /* For LPI we need to save the tx status */ |
0982a0f6 | 2815 | if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) |
d765955d | 2816 | priv->tx_path_in_lpi_mode = true; |
0982a0f6 | 2817 | if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) |
d765955d | 2818 | priv->tx_path_in_lpi_mode = false; |
a8b7d770 | 2819 | if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr) |
f748be53 AT |
2820 | priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, |
2821 | priv->rx_tail_addr, | |
2822 | STMMAC_CHAN0); | |
d765955d | 2823 | } |
70523e63 GC |
2824 | |
2825 | /* PCS link status */ | |
3fe5cadb | 2826 | if (priv->hw->pcs) { |
70523e63 GC |
2827 | if (priv->xstats.pcs_link) |
2828 | netif_carrier_on(dev); | |
2829 | else | |
2830 | netif_carrier_off(dev); | |
2831 | } | |
d765955d | 2832 | } |
aec7ff27 | 2833 | |
d765955d | 2834 | /* To handle DMA interrupts */ |
aec7ff27 | 2835 | stmmac_dma_interrupt(priv); |
47dd7a54 GC |
2836 | |
2837 | return IRQ_HANDLED; | |
2838 | } | |
2839 | ||
2840 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2841 | /* Polling receive - used by NETCONSOLE and other diagnostic tools | |
ceb69499 GC |
2842 | * to allow network I/O with interrupts disabled. |
2843 | */ | |
47dd7a54 GC |
2844 | static void stmmac_poll_controller(struct net_device *dev) |
2845 | { | |
2846 | disable_irq(dev->irq); | |
2847 | stmmac_interrupt(dev->irq, dev); | |
2848 | enable_irq(dev->irq); | |
2849 | } | |
2850 | #endif | |
2851 | ||
2852 | /** | |
2853 | * stmmac_ioctl - Entry point for the Ioctl | |
2854 | * @dev: Device pointer. | |
2855 | * @rq: An IOCTL specefic structure, that can contain a pointer to | |
2856 | * a proprietary structure used to pass information to the driver. | |
2857 | * @cmd: IOCTL command | |
2858 | * Description: | |
32ceabca | 2859 | * Currently it supports the phy_mii_ioctl(...) and HW time stamping. |
47dd7a54 GC |
2860 | */ |
2861 | static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2862 | { | |
891434b1 | 2863 | int ret = -EOPNOTSUPP; |
47dd7a54 GC |
2864 | |
2865 | if (!netif_running(dev)) | |
2866 | return -EINVAL; | |
2867 | ||
891434b1 RK |
2868 | switch (cmd) { |
2869 | case SIOCGMIIPHY: | |
2870 | case SIOCGMIIREG: | |
2871 | case SIOCSMIIREG: | |
d6d50c7e | 2872 | if (!dev->phydev) |
891434b1 | 2873 | return -EINVAL; |
d6d50c7e | 2874 | ret = phy_mii_ioctl(dev->phydev, rq, cmd); |
891434b1 RK |
2875 | break; |
2876 | case SIOCSHWTSTAMP: | |
2877 | ret = stmmac_hwtstamp_ioctl(dev, rq); | |
2878 | break; | |
2879 | default: | |
2880 | break; | |
2881 | } | |
28b04113 | 2882 | |
47dd7a54 GC |
2883 | return ret; |
2884 | } | |
2885 | ||
50fb4f74 | 2886 | #ifdef CONFIG_DEBUG_FS |
7ac29055 | 2887 | static struct dentry *stmmac_fs_dir; |
7ac29055 | 2888 | |
c24602ef | 2889 | static void sysfs_display_ring(void *head, int size, int extend_desc, |
ceb69499 | 2890 | struct seq_file *seq) |
7ac29055 | 2891 | { |
7ac29055 | 2892 | int i; |
ceb69499 GC |
2893 | struct dma_extended_desc *ep = (struct dma_extended_desc *)head; |
2894 | struct dma_desc *p = (struct dma_desc *)head; | |
7ac29055 | 2895 | |
c24602ef GC |
2896 | for (i = 0; i < size; i++) { |
2897 | u64 x; | |
2898 | if (extend_desc) { | |
2899 | x = *(u64 *) ep; | |
2900 | seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 | 2901 | i, (unsigned int)virt_to_phys(ep), |
f8be0d78 MW |
2902 | le32_to_cpu(ep->basic.des0), |
2903 | le32_to_cpu(ep->basic.des1), | |
2904 | le32_to_cpu(ep->basic.des2), | |
2905 | le32_to_cpu(ep->basic.des3)); | |
c24602ef GC |
2906 | ep++; |
2907 | } else { | |
2908 | x = *(u64 *) p; | |
2909 | seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", | |
ceb69499 | 2910 | i, (unsigned int)virt_to_phys(ep), |
f8be0d78 MW |
2911 | le32_to_cpu(p->des0), le32_to_cpu(p->des1), |
2912 | le32_to_cpu(p->des2), le32_to_cpu(p->des3)); | |
c24602ef GC |
2913 | p++; |
2914 | } | |
7ac29055 GC |
2915 | seq_printf(seq, "\n"); |
2916 | } | |
c24602ef | 2917 | } |
7ac29055 | 2918 | |
c24602ef GC |
2919 | static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) |
2920 | { | |
2921 | struct net_device *dev = seq->private; | |
2922 | struct stmmac_priv *priv = netdev_priv(dev); | |
7ac29055 | 2923 | |
c24602ef GC |
2924 | if (priv->extend_desc) { |
2925 | seq_printf(seq, "Extended RX descriptor ring:\n"); | |
e3ad57c9 | 2926 | sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq); |
c24602ef | 2927 | seq_printf(seq, "Extended TX descriptor ring:\n"); |
e3ad57c9 | 2928 | sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq); |
c24602ef GC |
2929 | } else { |
2930 | seq_printf(seq, "RX descriptor ring:\n"); | |
e3ad57c9 | 2931 | sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq); |
c24602ef | 2932 | seq_printf(seq, "TX descriptor ring:\n"); |
e3ad57c9 | 2933 | sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq); |
7ac29055 GC |
2934 | } |
2935 | ||
2936 | return 0; | |
2937 | } | |
2938 | ||
2939 | static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) | |
2940 | { | |
2941 | return single_open(file, stmmac_sysfs_ring_read, inode->i_private); | |
2942 | } | |
2943 | ||
22d3efe5 PM |
2944 | /* Debugfs files, should appear in /sys/kernel/debug/stmmaceth/eth0 */ |
2945 | ||
7ac29055 GC |
2946 | static const struct file_operations stmmac_rings_status_fops = { |
2947 | .owner = THIS_MODULE, | |
2948 | .open = stmmac_sysfs_ring_open, | |
2949 | .read = seq_read, | |
2950 | .llseek = seq_lseek, | |
74863948 | 2951 | .release = single_release, |
7ac29055 GC |
2952 | }; |
2953 | ||
e7434821 GC |
2954 | static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) |
2955 | { | |
2956 | struct net_device *dev = seq->private; | |
2957 | struct stmmac_priv *priv = netdev_priv(dev); | |
2958 | ||
19e30c14 | 2959 | if (!priv->hw_cap_support) { |
e7434821 GC |
2960 | seq_printf(seq, "DMA HW features not supported\n"); |
2961 | return 0; | |
2962 | } | |
2963 | ||
2964 | seq_printf(seq, "==============================\n"); | |
2965 | seq_printf(seq, "\tDMA HW features\n"); | |
2966 | seq_printf(seq, "==============================\n"); | |
2967 | ||
22d3efe5 | 2968 | seq_printf(seq, "\t10/100 Mbps: %s\n", |
e7434821 | 2969 | (priv->dma_cap.mbps_10_100) ? "Y" : "N"); |
22d3efe5 | 2970 | seq_printf(seq, "\t1000 Mbps: %s\n", |
e7434821 | 2971 | (priv->dma_cap.mbps_1000) ? "Y" : "N"); |
22d3efe5 | 2972 | seq_printf(seq, "\tHalf duplex: %s\n", |
e7434821 GC |
2973 | (priv->dma_cap.half_duplex) ? "Y" : "N"); |
2974 | seq_printf(seq, "\tHash Filter: %s\n", | |
2975 | (priv->dma_cap.hash_filter) ? "Y" : "N"); | |
2976 | seq_printf(seq, "\tMultiple MAC address registers: %s\n", | |
2977 | (priv->dma_cap.multi_addr) ? "Y" : "N"); | |
2978 | seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", | |
2979 | (priv->dma_cap.pcs) ? "Y" : "N"); | |
2980 | seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", | |
2981 | (priv->dma_cap.sma_mdio) ? "Y" : "N"); | |
2982 | seq_printf(seq, "\tPMT Remote wake up: %s\n", | |
2983 | (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); | |
2984 | seq_printf(seq, "\tPMT Magic Frame: %s\n", | |
2985 | (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); | |
2986 | seq_printf(seq, "\tRMON module: %s\n", | |
2987 | (priv->dma_cap.rmon) ? "Y" : "N"); | |
2988 | seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", | |
2989 | (priv->dma_cap.time_stamp) ? "Y" : "N"); | |
22d3efe5 | 2990 | seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", |
e7434821 | 2991 | (priv->dma_cap.atime_stamp) ? "Y" : "N"); |
22d3efe5 | 2992 | seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", |
e7434821 GC |
2993 | (priv->dma_cap.eee) ? "Y" : "N"); |
2994 | seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); | |
2995 | seq_printf(seq, "\tChecksum Offload in TX: %s\n", | |
2996 | (priv->dma_cap.tx_coe) ? "Y" : "N"); | |
f748be53 AT |
2997 | if (priv->synopsys_id >= DWMAC_CORE_4_00) { |
2998 | seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", | |
2999 | (priv->dma_cap.rx_coe) ? "Y" : "N"); | |
3000 | } else { | |
3001 | seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", | |
3002 | (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); | |
3003 | seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", | |
3004 | (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); | |
3005 | } | |
e7434821 GC |
3006 | seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", |
3007 | (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); | |
3008 | seq_printf(seq, "\tNumber of Additional RX channel: %d\n", | |
3009 | priv->dma_cap.number_rx_channel); | |
3010 | seq_printf(seq, "\tNumber of Additional TX channel: %d\n", | |
3011 | priv->dma_cap.number_tx_channel); | |
3012 | seq_printf(seq, "\tEnhanced descriptors: %s\n", | |
3013 | (priv->dma_cap.enh_desc) ? "Y" : "N"); | |
3014 | ||
3015 | return 0; | |
3016 | } | |
3017 | ||
3018 | static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) | |
3019 | { | |
3020 | return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); | |
3021 | } | |
3022 | ||
3023 | static const struct file_operations stmmac_dma_cap_fops = { | |
3024 | .owner = THIS_MODULE, | |
3025 | .open = stmmac_sysfs_dma_cap_open, | |
3026 | .read = seq_read, | |
3027 | .llseek = seq_lseek, | |
74863948 | 3028 | .release = single_release, |
e7434821 GC |
3029 | }; |
3030 | ||
7ac29055 GC |
3031 | static int stmmac_init_fs(struct net_device *dev) |
3032 | { | |
466c5ac8 MO |
3033 | struct stmmac_priv *priv = netdev_priv(dev); |
3034 | ||
3035 | /* Create per netdev entries */ | |
3036 | priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); | |
7ac29055 | 3037 | |
466c5ac8 | 3038 | if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) { |
38ddc59d | 3039 | netdev_err(priv->dev, "ERROR failed to create debugfs directory\n"); |
7ac29055 GC |
3040 | |
3041 | return -ENOMEM; | |
3042 | } | |
3043 | ||
3044 | /* Entry to report DMA RX/TX rings */ | |
466c5ac8 MO |
3045 | priv->dbgfs_rings_status = |
3046 | debugfs_create_file("descriptors_status", S_IRUGO, | |
3047 | priv->dbgfs_dir, dev, | |
3048 | &stmmac_rings_status_fops); | |
7ac29055 | 3049 | |
466c5ac8 | 3050 | if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) { |
38ddc59d | 3051 | netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n"); |
466c5ac8 | 3052 | debugfs_remove_recursive(priv->dbgfs_dir); |
7ac29055 GC |
3053 | |
3054 | return -ENOMEM; | |
3055 | } | |
3056 | ||
e7434821 | 3057 | /* Entry to report the DMA HW features */ |
466c5ac8 MO |
3058 | priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, |
3059 | priv->dbgfs_dir, | |
3060 | dev, &stmmac_dma_cap_fops); | |
e7434821 | 3061 | |
466c5ac8 | 3062 | if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) { |
38ddc59d | 3063 | netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n"); |
466c5ac8 | 3064 | debugfs_remove_recursive(priv->dbgfs_dir); |
e7434821 GC |
3065 | |
3066 | return -ENOMEM; | |
3067 | } | |
3068 | ||
7ac29055 GC |
3069 | return 0; |
3070 | } | |
3071 | ||
466c5ac8 | 3072 | static void stmmac_exit_fs(struct net_device *dev) |
7ac29055 | 3073 | { |
466c5ac8 MO |
3074 | struct stmmac_priv *priv = netdev_priv(dev); |
3075 | ||
3076 | debugfs_remove_recursive(priv->dbgfs_dir); | |
7ac29055 | 3077 | } |
50fb4f74 | 3078 | #endif /* CONFIG_DEBUG_FS */ |
7ac29055 | 3079 | |
47dd7a54 GC |
3080 | static const struct net_device_ops stmmac_netdev_ops = { |
3081 | .ndo_open = stmmac_open, | |
3082 | .ndo_start_xmit = stmmac_xmit, | |
3083 | .ndo_stop = stmmac_release, | |
3084 | .ndo_change_mtu = stmmac_change_mtu, | |
5e982f3b | 3085 | .ndo_fix_features = stmmac_fix_features, |
d2afb5bd | 3086 | .ndo_set_features = stmmac_set_features, |
01789349 | 3087 | .ndo_set_rx_mode = stmmac_set_rx_mode, |
47dd7a54 GC |
3088 | .ndo_tx_timeout = stmmac_tx_timeout, |
3089 | .ndo_do_ioctl = stmmac_ioctl, | |
47dd7a54 GC |
3090 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3091 | .ndo_poll_controller = stmmac_poll_controller, | |
3092 | #endif | |
3093 | .ndo_set_mac_address = eth_mac_addr, | |
3094 | }; | |
3095 | ||
cf3f047b GC |
3096 | /** |
3097 | * stmmac_hw_init - Init the MAC device | |
32ceabca | 3098 | * @priv: driver private structure |
732fdf0e GC |
3099 | * Description: this function is to configure the MAC device according to |
3100 | * some platform parameters or the HW capability register. It prepares the | |
3101 | * driver to use either ring or chain modes and to setup either enhanced or | |
3102 | * normal descriptors. | |
cf3f047b GC |
3103 | */ |
3104 | static int stmmac_hw_init(struct stmmac_priv *priv) | |
3105 | { | |
cf3f047b GC |
3106 | struct mac_device_info *mac; |
3107 | ||
3108 | /* Identify the MAC HW device */ | |
03f2eecd MKB |
3109 | if (priv->plat->has_gmac) { |
3110 | priv->dev->priv_flags |= IFF_UNICAST_FLT; | |
3b57de95 VB |
3111 | mac = dwmac1000_setup(priv->ioaddr, |
3112 | priv->plat->multicast_filter_bins, | |
c623d149 AT |
3113 | priv->plat->unicast_filter_entries, |
3114 | &priv->synopsys_id); | |
f748be53 AT |
3115 | } else if (priv->plat->has_gmac4) { |
3116 | priv->dev->priv_flags |= IFF_UNICAST_FLT; | |
3117 | mac = dwmac4_setup(priv->ioaddr, | |
3118 | priv->plat->multicast_filter_bins, | |
3119 | priv->plat->unicast_filter_entries, | |
3120 | &priv->synopsys_id); | |
03f2eecd | 3121 | } else { |
c623d149 | 3122 | mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id); |
03f2eecd | 3123 | } |
cf3f047b GC |
3124 | if (!mac) |
3125 | return -ENOMEM; | |
3126 | ||
3127 | priv->hw = mac; | |
3128 | ||
4a7d666a | 3129 | /* To use the chained or ring mode */ |
f748be53 AT |
3130 | if (priv->synopsys_id >= DWMAC_CORE_4_00) { |
3131 | priv->hw->mode = &dwmac4_ring_mode_ops; | |
4a7d666a | 3132 | } else { |
f748be53 AT |
3133 | if (chain_mode) { |
3134 | priv->hw->mode = &chain_mode_ops; | |
38ddc59d | 3135 | dev_info(priv->device, "Chain mode enabled\n"); |
f748be53 AT |
3136 | priv->mode = STMMAC_CHAIN_MODE; |
3137 | } else { | |
3138 | priv->hw->mode = &ring_mode_ops; | |
38ddc59d | 3139 | dev_info(priv->device, "Ring mode enabled\n"); |
f748be53 AT |
3140 | priv->mode = STMMAC_RING_MODE; |
3141 | } | |
4a7d666a GC |
3142 | } |
3143 | ||
cf3f047b GC |
3144 | /* Get the HW capability (new GMAC newer than 3.50a) */ |
3145 | priv->hw_cap_support = stmmac_get_hw_features(priv); | |
3146 | if (priv->hw_cap_support) { | |
38ddc59d | 3147 | dev_info(priv->device, "DMA HW capability register supported\n"); |
cf3f047b GC |
3148 | |
3149 | /* We can override some gmac/dma configuration fields: e.g. | |
3150 | * enh_desc, tx_coe (e.g. that are passed through the | |
3151 | * platform) with the values from the HW capability | |
3152 | * register (if supported). | |
3153 | */ | |
3154 | priv->plat->enh_desc = priv->dma_cap.enh_desc; | |
cf3f047b | 3155 | priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; |
3fe5cadb | 3156 | priv->hw->pmt = priv->plat->pmt; |
38912bdb | 3157 | |
a8df35d4 EG |
3158 | /* TXCOE doesn't work in thresh DMA mode */ |
3159 | if (priv->plat->force_thresh_dma_mode) | |
3160 | priv->plat->tx_coe = 0; | |
3161 | else | |
3162 | priv->plat->tx_coe = priv->dma_cap.tx_coe; | |
3163 | ||
f748be53 AT |
3164 | /* In case of GMAC4 rx_coe is from HW cap register. */ |
3165 | priv->plat->rx_coe = priv->dma_cap.rx_coe; | |
38912bdb DS |
3166 | |
3167 | if (priv->dma_cap.rx_coe_type2) | |
3168 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; | |
3169 | else if (priv->dma_cap.rx_coe_type1) | |
3170 | priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; | |
3171 | ||
38ddc59d LC |
3172 | } else { |
3173 | dev_info(priv->device, "No HW DMA feature register supported\n"); | |
3174 | } | |
cf3f047b | 3175 | |
f748be53 AT |
3176 | /* To use alternate (extended), normal or GMAC4 descriptor structures */ |
3177 | if (priv->synopsys_id >= DWMAC_CORE_4_00) | |
3178 | priv->hw->desc = &dwmac4_desc_ops; | |
3179 | else | |
3180 | stmmac_selec_desc_mode(priv); | |
61369d02 | 3181 | |
d2afb5bd GC |
3182 | if (priv->plat->rx_coe) { |
3183 | priv->hw->rx_csum = priv->plat->rx_coe; | |
38ddc59d | 3184 | dev_info(priv->device, "RX Checksum Offload Engine supported\n"); |
f748be53 | 3185 | if (priv->synopsys_id < DWMAC_CORE_4_00) |
38ddc59d | 3186 | dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); |
d2afb5bd | 3187 | } |
cf3f047b | 3188 | if (priv->plat->tx_coe) |
38ddc59d | 3189 | dev_info(priv->device, "TX Checksum insertion supported\n"); |
cf3f047b GC |
3190 | |
3191 | if (priv->plat->pmt) { | |
38ddc59d | 3192 | dev_info(priv->device, "Wake-Up On Lan supported\n"); |
cf3f047b GC |
3193 | device_set_wakeup_capable(priv->device, 1); |
3194 | } | |
3195 | ||
f748be53 | 3196 | if (priv->dma_cap.tsoen) |
38ddc59d | 3197 | dev_info(priv->device, "TSO supported\n"); |
f748be53 | 3198 | |
c24602ef | 3199 | return 0; |
cf3f047b GC |
3200 | } |
3201 | ||
47dd7a54 | 3202 | /** |
bfab27a1 GC |
3203 | * stmmac_dvr_probe |
3204 | * @device: device pointer | |
ff3dd78c | 3205 | * @plat_dat: platform data pointer |
e56788cf | 3206 | * @res: stmmac resource pointer |
bfab27a1 GC |
3207 | * Description: this is the main probe function used to |
3208 | * call the alloc_etherdev, allocate the priv structure. | |
9afec6ef | 3209 | * Return: |
15ffac73 | 3210 | * returns 0 on success, otherwise errno. |
47dd7a54 | 3211 | */ |
15ffac73 JE |
3212 | int stmmac_dvr_probe(struct device *device, |
3213 | struct plat_stmmacenet_data *plat_dat, | |
3214 | struct stmmac_resources *res) | |
47dd7a54 GC |
3215 | { |
3216 | int ret = 0; | |
bfab27a1 GC |
3217 | struct net_device *ndev = NULL; |
3218 | struct stmmac_priv *priv; | |
47dd7a54 | 3219 | |
bfab27a1 | 3220 | ndev = alloc_etherdev(sizeof(struct stmmac_priv)); |
41de8d4c | 3221 | if (!ndev) |
15ffac73 | 3222 | return -ENOMEM; |
bfab27a1 GC |
3223 | |
3224 | SET_NETDEV_DEV(ndev, device); | |
3225 | ||
3226 | priv = netdev_priv(ndev); | |
3227 | priv->device = device; | |
3228 | priv->dev = ndev; | |
47dd7a54 | 3229 | |
bfab27a1 | 3230 | stmmac_set_ethtool_ops(ndev); |
cf3f047b GC |
3231 | priv->pause = pause; |
3232 | priv->plat = plat_dat; | |
e56788cf JE |
3233 | priv->ioaddr = res->addr; |
3234 | priv->dev->base_addr = (unsigned long)res->addr; | |
3235 | ||
3236 | priv->dev->irq = res->irq; | |
3237 | priv->wol_irq = res->wol_irq; | |
3238 | priv->lpi_irq = res->lpi_irq; | |
3239 | ||
3240 | if (res->mac) | |
3241 | memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); | |
cf3f047b | 3242 | |
a7a62685 | 3243 | dev_set_drvdata(device, priv->dev); |
803f8fc4 | 3244 | |
cf3f047b GC |
3245 | /* Verify driver arguments */ |
3246 | stmmac_verify_args(); | |
bfab27a1 | 3247 | |
cf3f047b | 3248 | /* Override with kernel parameters if supplied XXX CRS XXX |
ceb69499 GC |
3249 | * this needs to have multiple instances |
3250 | */ | |
cf3f047b GC |
3251 | if ((phyaddr >= 0) && (phyaddr <= 31)) |
3252 | priv->plat->phy_addr = phyaddr; | |
3253 | ||
62866e98 CYT |
3254 | priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); |
3255 | if (IS_ERR(priv->stmmac_clk)) { | |
38ddc59d LC |
3256 | netdev_warn(priv->dev, "%s: warning: cannot get CSR clock\n", |
3257 | __func__); | |
c5bb86c3 KHL |
3258 | /* If failed to obtain stmmac_clk and specific clk_csr value |
3259 | * is NOT passed from the platform, probe fail. | |
3260 | */ | |
3261 | if (!priv->plat->clk_csr) { | |
3262 | ret = PTR_ERR(priv->stmmac_clk); | |
3263 | goto error_clk_get; | |
3264 | } else { | |
3265 | priv->stmmac_clk = NULL; | |
3266 | } | |
62866e98 CYT |
3267 | } |
3268 | clk_prepare_enable(priv->stmmac_clk); | |
3269 | ||
5f9755d2 AB |
3270 | priv->pclk = devm_clk_get(priv->device, "pclk"); |
3271 | if (IS_ERR(priv->pclk)) { | |
3272 | if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) { | |
3273 | ret = -EPROBE_DEFER; | |
3274 | goto error_pclk_get; | |
3275 | } | |
3276 | priv->pclk = NULL; | |
3277 | } | |
3278 | clk_prepare_enable(priv->pclk); | |
3279 | ||
c5e4ddbd CYT |
3280 | priv->stmmac_rst = devm_reset_control_get(priv->device, |
3281 | STMMAC_RESOURCE_NAME); | |
3282 | if (IS_ERR(priv->stmmac_rst)) { | |
3283 | if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { | |
3284 | ret = -EPROBE_DEFER; | |
3285 | goto error_hw_init; | |
3286 | } | |
3287 | dev_info(priv->device, "no reset control found\n"); | |
3288 | priv->stmmac_rst = NULL; | |
3289 | } | |
3290 | if (priv->stmmac_rst) | |
3291 | reset_control_deassert(priv->stmmac_rst); | |
3292 | ||
cf3f047b | 3293 | /* Init MAC and get the capabilities */ |
c24602ef GC |
3294 | ret = stmmac_hw_init(priv); |
3295 | if (ret) | |
62866e98 | 3296 | goto error_hw_init; |
cf3f047b GC |
3297 | |
3298 | ndev->netdev_ops = &stmmac_netdev_ops; | |
bfab27a1 | 3299 | |
cf3f047b GC |
3300 | ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
3301 | NETIF_F_RXCSUM; | |
f748be53 AT |
3302 | |
3303 | if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { | |
3304 | ndev->hw_features |= NETIF_F_TSO; | |
3305 | priv->tso = true; | |
38ddc59d | 3306 | dev_info(priv->device, "TSO feature enabled\n"); |
f748be53 | 3307 | } |
bfab27a1 GC |
3308 | ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; |
3309 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
47dd7a54 GC |
3310 | #ifdef STMMAC_VLAN_TAG_USED |
3311 | /* Both mac100 and gmac support receive VLAN tag detection */ | |
f646968f | 3312 | ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; |
47dd7a54 GC |
3313 | #endif |
3314 | priv->msg_enable = netif_msg_init(debug, default_msg_level); | |
3315 | ||
44770e11 JW |
3316 | /* MTU range: 46 - hw-specific max */ |
3317 | ndev->min_mtu = ETH_ZLEN - ETH_HLEN; | |
3318 | if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) | |
3319 | ndev->max_mtu = JUMBO_LEN; | |
3320 | else | |
3321 | ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); | |
3322 | if (priv->plat->maxmtu < ndev->max_mtu) | |
3323 | ndev->max_mtu = priv->plat->maxmtu; | |
3324 | ||
47dd7a54 GC |
3325 | if (flow_ctrl) |
3326 | priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ | |
3327 | ||
62a2ab93 GC |
3328 | /* Rx Watchdog is available in the COREs newer than the 3.40. |
3329 | * In some case, for example on bugged HW this feature | |
3330 | * has to be disable and this can be done by passing the | |
3331 | * riwt_off field from the platform. | |
3332 | */ | |
3333 | if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { | |
3334 | priv->use_riwt = 1; | |
38ddc59d | 3335 | netdev_info(priv->dev, "Enable RX Mitigation via HW Watchdog Timer\n"); |
62a2ab93 GC |
3336 | } |
3337 | ||
bfab27a1 | 3338 | netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); |
47dd7a54 | 3339 | |
f8e96161 VL |
3340 | spin_lock_init(&priv->lock); |
3341 | ||
bfab27a1 | 3342 | ret = register_netdev(ndev); |
47dd7a54 | 3343 | if (ret) { |
38ddc59d LC |
3344 | netdev_err(priv->dev, "%s: ERROR %i registering the device\n", |
3345 | __func__, ret); | |
6a81c26f | 3346 | goto error_netdev_register; |
47dd7a54 GC |
3347 | } |
3348 | ||
cd7201f4 GC |
3349 | /* If a specific clk_csr value is passed from the platform |
3350 | * this means that the CSR Clock Range selection cannot be | |
3351 | * changed at run-time and it is fixed. Viceversa the driver'll try to | |
3352 | * set the MDC clock dynamically according to the csr actual | |
3353 | * clock input. | |
3354 | */ | |
3355 | if (!priv->plat->clk_csr) | |
3356 | stmmac_clk_csr_set(priv); | |
3357 | else | |
3358 | priv->clk_csr = priv->plat->clk_csr; | |
3359 | ||
e58bb43f GC |
3360 | stmmac_check_pcs_mode(priv); |
3361 | ||
3fe5cadb GC |
3362 | if (priv->hw->pcs != STMMAC_PCS_RGMII && |
3363 | priv->hw->pcs != STMMAC_PCS_TBI && | |
3364 | priv->hw->pcs != STMMAC_PCS_RTBI) { | |
e58bb43f GC |
3365 | /* MDIO bus Registration */ |
3366 | ret = stmmac_mdio_register(ndev); | |
3367 | if (ret < 0) { | |
38ddc59d LC |
3368 | netdev_err(priv->dev, |
3369 | "%s: MDIO bus (id: %d) registration failed", | |
3370 | __func__, priv->plat->bus_id); | |
e58bb43f GC |
3371 | goto error_mdio_register; |
3372 | } | |
4bfcbd7a FV |
3373 | } |
3374 | ||
15ffac73 | 3375 | return 0; |
47dd7a54 | 3376 | |
6a81c26f | 3377 | error_mdio_register: |
34a52f36 | 3378 | unregister_netdev(ndev); |
6a81c26f VK |
3379 | error_netdev_register: |
3380 | netif_napi_del(&priv->napi); | |
62866e98 | 3381 | error_hw_init: |
5f9755d2 AB |
3382 | clk_disable_unprepare(priv->pclk); |
3383 | error_pclk_get: | |
62866e98 CYT |
3384 | clk_disable_unprepare(priv->stmmac_clk); |
3385 | error_clk_get: | |
34a52f36 | 3386 | free_netdev(ndev); |
47dd7a54 | 3387 | |
15ffac73 | 3388 | return ret; |
47dd7a54 | 3389 | } |
b2e2f0c7 | 3390 | EXPORT_SYMBOL_GPL(stmmac_dvr_probe); |
47dd7a54 GC |
3391 | |
3392 | /** | |
3393 | * stmmac_dvr_remove | |
f4e7bd81 | 3394 | * @dev: device pointer |
47dd7a54 | 3395 | * Description: this function resets the TX/RX processes, disables the MAC RX/TX |
bfab27a1 | 3396 | * changes the link status, releases the DMA descriptor rings. |
47dd7a54 | 3397 | */ |
f4e7bd81 | 3398 | int stmmac_dvr_remove(struct device *dev) |
47dd7a54 | 3399 | { |
f4e7bd81 | 3400 | struct net_device *ndev = dev_get_drvdata(dev); |
aec7ff27 | 3401 | struct stmmac_priv *priv = netdev_priv(ndev); |
47dd7a54 | 3402 | |
38ddc59d | 3403 | netdev_info(priv->dev, "%s: removing driver", __func__); |
47dd7a54 | 3404 | |
ad01b7d4 GC |
3405 | priv->hw->dma->stop_rx(priv->ioaddr); |
3406 | priv->hw->dma->stop_tx(priv->ioaddr); | |
47dd7a54 | 3407 | |
bfab27a1 | 3408 | stmmac_set_mac(priv->ioaddr, false); |
47dd7a54 | 3409 | netif_carrier_off(ndev); |
47dd7a54 | 3410 | unregister_netdev(ndev); |
c5e4ddbd CYT |
3411 | if (priv->stmmac_rst) |
3412 | reset_control_assert(priv->stmmac_rst); | |
5f9755d2 | 3413 | clk_disable_unprepare(priv->pclk); |
62866e98 | 3414 | clk_disable_unprepare(priv->stmmac_clk); |
3fe5cadb GC |
3415 | if (priv->hw->pcs != STMMAC_PCS_RGMII && |
3416 | priv->hw->pcs != STMMAC_PCS_TBI && | |
3417 | priv->hw->pcs != STMMAC_PCS_RTBI) | |
e743471f | 3418 | stmmac_mdio_unregister(ndev); |
47dd7a54 GC |
3419 | free_netdev(ndev); |
3420 | ||
3421 | return 0; | |
3422 | } | |
b2e2f0c7 | 3423 | EXPORT_SYMBOL_GPL(stmmac_dvr_remove); |
47dd7a54 | 3424 | |
732fdf0e GC |
3425 | /** |
3426 | * stmmac_suspend - suspend callback | |
f4e7bd81 | 3427 | * @dev: device pointer |
732fdf0e GC |
3428 | * Description: this is the function to suspend the device and it is called |
3429 | * by the platform driver to stop the network queue, release the resources, | |
3430 | * program the PMT register (for WoL), clean and release driver resources. | |
3431 | */ | |
f4e7bd81 | 3432 | int stmmac_suspend(struct device *dev) |
47dd7a54 | 3433 | { |
f4e7bd81 | 3434 | struct net_device *ndev = dev_get_drvdata(dev); |
874bd42d | 3435 | struct stmmac_priv *priv = netdev_priv(ndev); |
f8c5a875 | 3436 | unsigned long flags; |
47dd7a54 | 3437 | |
874bd42d | 3438 | if (!ndev || !netif_running(ndev)) |
47dd7a54 GC |
3439 | return 0; |
3440 | ||
d6d50c7e PR |
3441 | if (ndev->phydev) |
3442 | phy_stop(ndev->phydev); | |
102463b1 | 3443 | |
f8c5a875 | 3444 | spin_lock_irqsave(&priv->lock, flags); |
47dd7a54 | 3445 | |
874bd42d GC |
3446 | netif_device_detach(ndev); |
3447 | netif_stop_queue(ndev); | |
47dd7a54 | 3448 | |
874bd42d GC |
3449 | napi_disable(&priv->napi); |
3450 | ||
3451 | /* Stop TX/RX DMA */ | |
3452 | priv->hw->dma->stop_tx(priv->ioaddr); | |
3453 | priv->hw->dma->stop_rx(priv->ioaddr); | |
c24602ef | 3454 | |
874bd42d | 3455 | /* Enable Power down mode by programming the PMT regs */ |
89f7f2cf | 3456 | if (device_may_wakeup(priv->device)) { |
7ed24bbe | 3457 | priv->hw->mac->pmt(priv->hw, priv->wolopts); |
89f7f2cf SK |
3458 | priv->irq_wake = 1; |
3459 | } else { | |
bfab27a1 | 3460 | stmmac_set_mac(priv->ioaddr, false); |
db88f10a | 3461 | pinctrl_pm_select_sleep_state(priv->device); |
ba1377ff | 3462 | /* Disable clock in case of PWM is off */ |
5f9755d2 | 3463 | clk_disable(priv->pclk); |
777da230 | 3464 | clk_disable(priv->stmmac_clk); |
ba1377ff | 3465 | } |
f8c5a875 | 3466 | spin_unlock_irqrestore(&priv->lock, flags); |
2d871aa0 VB |
3467 | |
3468 | priv->oldlink = 0; | |
3469 | priv->speed = 0; | |
3470 | priv->oldduplex = -1; | |
47dd7a54 GC |
3471 | return 0; |
3472 | } | |
b2e2f0c7 | 3473 | EXPORT_SYMBOL_GPL(stmmac_suspend); |
47dd7a54 | 3474 | |
732fdf0e GC |
3475 | /** |
3476 | * stmmac_resume - resume callback | |
f4e7bd81 | 3477 | * @dev: device pointer |
732fdf0e GC |
3478 | * Description: when resume this function is invoked to setup the DMA and CORE |
3479 | * in a usable state. | |
3480 | */ | |
f4e7bd81 | 3481 | int stmmac_resume(struct device *dev) |
47dd7a54 | 3482 | { |
f4e7bd81 | 3483 | struct net_device *ndev = dev_get_drvdata(dev); |
874bd42d | 3484 | struct stmmac_priv *priv = netdev_priv(ndev); |
f8c5a875 | 3485 | unsigned long flags; |
47dd7a54 | 3486 | |
874bd42d | 3487 | if (!netif_running(ndev)) |
47dd7a54 GC |
3488 | return 0; |
3489 | ||
47dd7a54 GC |
3490 | /* Power Down bit, into the PM register, is cleared |
3491 | * automatically as soon as a magic packet or a Wake-up frame | |
3492 | * is received. Anyway, it's better to manually clear | |
3493 | * this bit because it can generate problems while resuming | |
ceb69499 GC |
3494 | * from another devices (e.g. serial console). |
3495 | */ | |
623997fb | 3496 | if (device_may_wakeup(priv->device)) { |
f55d84b0 | 3497 | spin_lock_irqsave(&priv->lock, flags); |
7ed24bbe | 3498 | priv->hw->mac->pmt(priv->hw, 0); |
f55d84b0 | 3499 | spin_unlock_irqrestore(&priv->lock, flags); |
89f7f2cf | 3500 | priv->irq_wake = 0; |
623997fb | 3501 | } else { |
db88f10a | 3502 | pinctrl_pm_select_default_state(priv->device); |
ba1377ff | 3503 | /* enable the clk prevously disabled */ |
777da230 | 3504 | clk_enable(priv->stmmac_clk); |
5f9755d2 | 3505 | clk_enable(priv->pclk); |
623997fb SK |
3506 | /* reset the phy so that it's ready */ |
3507 | if (priv->mii) | |
3508 | stmmac_mdio_reset(priv->mii); | |
3509 | } | |
47dd7a54 | 3510 | |
874bd42d | 3511 | netif_device_attach(ndev); |
47dd7a54 | 3512 | |
f55d84b0 VP |
3513 | spin_lock_irqsave(&priv->lock, flags); |
3514 | ||
ae79a639 GC |
3515 | priv->cur_rx = 0; |
3516 | priv->dirty_rx = 0; | |
3517 | priv->dirty_tx = 0; | |
3518 | priv->cur_tx = 0; | |
f748be53 AT |
3519 | /* reset private mss value to force mss context settings at |
3520 | * next tso xmit (only used for gmac4). | |
3521 | */ | |
3522 | priv->mss = 0; | |
3523 | ||
ae79a639 GC |
3524 | stmmac_clear_descriptors(priv); |
3525 | ||
fe131929 | 3526 | stmmac_hw_setup(ndev, false); |
777da230 | 3527 | stmmac_init_tx_coalesce(priv); |
ac316c78 | 3528 | stmmac_set_rx_mode(ndev); |
47dd7a54 | 3529 | |
47dd7a54 GC |
3530 | napi_enable(&priv->napi); |
3531 | ||
874bd42d | 3532 | netif_start_queue(ndev); |
47dd7a54 | 3533 | |
f8c5a875 | 3534 | spin_unlock_irqrestore(&priv->lock, flags); |
102463b1 | 3535 | |
d6d50c7e PR |
3536 | if (ndev->phydev) |
3537 | phy_start(ndev->phydev); | |
102463b1 | 3538 | |
47dd7a54 GC |
3539 | return 0; |
3540 | } | |
b2e2f0c7 | 3541 | EXPORT_SYMBOL_GPL(stmmac_resume); |
ba27ec66 | 3542 | |
47dd7a54 GC |
3543 | #ifndef MODULE |
3544 | static int __init stmmac_cmdline_opt(char *str) | |
3545 | { | |
3546 | char *opt; | |
3547 | ||
3548 | if (!str || !*str) | |
3549 | return -EINVAL; | |
3550 | while ((opt = strsep(&str, ",")) != NULL) { | |
f3240e28 | 3551 | if (!strncmp(opt, "debug:", 6)) { |
ea2ab871 | 3552 | if (kstrtoint(opt + 6, 0, &debug)) |
f3240e28 GC |
3553 | goto err; |
3554 | } else if (!strncmp(opt, "phyaddr:", 8)) { | |
ea2ab871 | 3555 | if (kstrtoint(opt + 8, 0, &phyaddr)) |
f3240e28 | 3556 | goto err; |
f3240e28 | 3557 | } else if (!strncmp(opt, "buf_sz:", 7)) { |
ea2ab871 | 3558 | if (kstrtoint(opt + 7, 0, &buf_sz)) |
f3240e28 GC |
3559 | goto err; |
3560 | } else if (!strncmp(opt, "tc:", 3)) { | |
ea2ab871 | 3561 | if (kstrtoint(opt + 3, 0, &tc)) |
f3240e28 GC |
3562 | goto err; |
3563 | } else if (!strncmp(opt, "watchdog:", 9)) { | |
ea2ab871 | 3564 | if (kstrtoint(opt + 9, 0, &watchdog)) |
f3240e28 GC |
3565 | goto err; |
3566 | } else if (!strncmp(opt, "flow_ctrl:", 10)) { | |
ea2ab871 | 3567 | if (kstrtoint(opt + 10, 0, &flow_ctrl)) |
f3240e28 GC |
3568 | goto err; |
3569 | } else if (!strncmp(opt, "pause:", 6)) { | |
ea2ab871 | 3570 | if (kstrtoint(opt + 6, 0, &pause)) |
f3240e28 | 3571 | goto err; |
506f669c | 3572 | } else if (!strncmp(opt, "eee_timer:", 10)) { |
d765955d GC |
3573 | if (kstrtoint(opt + 10, 0, &eee_timer)) |
3574 | goto err; | |
4a7d666a GC |
3575 | } else if (!strncmp(opt, "chain_mode:", 11)) { |
3576 | if (kstrtoint(opt + 11, 0, &chain_mode)) | |
3577 | goto err; | |
f3240e28 | 3578 | } |
47dd7a54 GC |
3579 | } |
3580 | return 0; | |
f3240e28 GC |
3581 | |
3582 | err: | |
3583 | pr_err("%s: ERROR broken module parameter conversion", __func__); | |
3584 | return -EINVAL; | |
47dd7a54 GC |
3585 | } |
3586 | ||
3587 | __setup("stmmaceth=", stmmac_cmdline_opt); | |
ceb69499 | 3588 | #endif /* MODULE */ |
6fc0d0f2 | 3589 | |
466c5ac8 MO |
3590 | static int __init stmmac_init(void) |
3591 | { | |
3592 | #ifdef CONFIG_DEBUG_FS | |
3593 | /* Create debugfs main directory if it doesn't exist yet */ | |
3594 | if (!stmmac_fs_dir) { | |
3595 | stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); | |
3596 | ||
3597 | if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { | |
3598 | pr_err("ERROR %s, debugfs create directory failed\n", | |
3599 | STMMAC_RESOURCE_NAME); | |
3600 | ||
3601 | return -ENOMEM; | |
3602 | } | |
3603 | } | |
3604 | #endif | |
3605 | ||
3606 | return 0; | |
3607 | } | |
3608 | ||
3609 | static void __exit stmmac_exit(void) | |
3610 | { | |
3611 | #ifdef CONFIG_DEBUG_FS | |
3612 | debugfs_remove_recursive(stmmac_fs_dir); | |
3613 | #endif | |
3614 | } | |
3615 | ||
3616 | module_init(stmmac_init) | |
3617 | module_exit(stmmac_exit) | |
3618 | ||
6fc0d0f2 GC |
3619 | MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); |
3620 | MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); | |
3621 | MODULE_LICENSE("GPL"); |