[linux-block.git] / drivers / net / ethernet / stmicro / stmmac / stmmac.h

/*******************************************************************************
  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#ifndef __STMMAC_H__
#define __STMMAC_H__

#define STMMAC_RESOURCE_NAME   "stmmaceth"
#define DRV_MODULE_VERSION	"Jan_2016"

#include <linux/clk.h>
#include <linux/stmmac.h>
#include <linux/phy.h>
#include <linux/pci.h>
#include "common.h"
#include <linux/ptp_clock_kernel.h>
#include <linux/net_tstamp.h>
#include <linux/reset.h>

struct stmmac_resources {
	void __iomem *addr;
	const char *mac;
	int wol_irq;
	int lpi_irq;
	int irq;
};

struct stmmac_tx_info {
	dma_addr_t buf;
	bool map_as_page;
	unsigned len;
	bool last_segment;
	bool is_jumbo;
};

/* Frequently used values are kept adjacent for cache effect */
struct stmmac_tx_queue {
	u32 tx_count_frames;
	struct timer_list txtimer;
	u32 queue_index;
	struct stmmac_priv *priv_data;
	struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
	struct dma_desc *dma_tx;
	struct sk_buff **tx_skbuff;
	struct stmmac_tx_info *tx_skbuff_dma;
	unsigned int cur_tx;
	unsigned int dirty_tx;
	dma_addr_t dma_tx_phy;
	u32 tx_tail_addr;
	u32 mss;
};

struct stmmac_rx_queue {
	u32 queue_index;
	struct stmmac_priv *priv_data;
	struct dma_extended_desc *dma_erx;
	struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
	struct sk_buff **rx_skbuff;
	dma_addr_t *rx_skbuff_dma;
	unsigned int cur_rx;
	unsigned int dirty_rx;
	u32 rx_zeroc_thresh;
	dma_addr_t dma_rx_phy;
	u32 rx_tail_addr;
};

struct stmmac_channel {
	struct napi_struct rx_napi ____cacheline_aligned_in_smp;
	struct napi_struct tx_napi ____cacheline_aligned_in_smp;
	struct stmmac_priv *priv_data;
	u32 index;
};

struct stmmac_tc_entry {
	bool in_use;
	bool in_hw;
	bool is_last;
	bool is_frag;
	void *frag_ptr;
	unsigned int table_pos;
	u32 handle;
	u32 prio;
	struct {
		u32 match_data;
		u32 match_en;
		u8 af:1;
		u8 rf:1;
		u8 im:1;
		u8 nc:1;
		u8 res1:4;
		u8 frame_offset;
		u8 ok_index;
		u8 dma_ch_no;
		u32 res2;
	} __packed val;
};

#define STMMAC_PPS_MAX		4
struct stmmac_pps_cfg {
	bool available;
	struct timespec64 start;
	struct timespec64 period;
};

struct stmmac_priv {
	/* Frequently used values are kept adjacent for cache effect */
	u32 tx_coal_frames;
	u32 tx_coal_timer;

	int tx_coalesce;
	int hwts_tx_en;
	bool tx_path_in_lpi_mode;
	bool tso;

	unsigned int dma_buf_sz;
	unsigned int rx_copybreak;
	u32 rx_riwt;
	int hwts_rx_en;

	void __iomem *ioaddr;
	struct net_device *dev;
	struct device *device;
	struct mac_device_info *hw;
	int (*hwif_quirks)(struct stmmac_priv *priv);
	struct mutex lock;

	/* RX Queue */
	struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];

	/* TX Queue */
	struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];

	/* Generic channel for NAPI */
	struct stmmac_channel channel[STMMAC_CH_MAX];

	bool oldlink;
	int speed;
	int oldduplex;
	unsigned int flow_ctrl;
	unsigned int pause;
	struct mii_bus *mii;
	int mii_irq[PHY_MAX_ADDR];

	struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
	struct stmmac_safety_stats sstats;
	struct plat_stmmacenet_data *plat;
	struct dma_features dma_cap;
	struct stmmac_counters mmc;
	int hw_cap_support;
	int synopsys_id;
	u32 msg_enable;
	int wolopts;
	int wol_irq;
	int clk_csr;
	struct timer_list eee_ctrl_timer;
	int lpi_irq;
	int eee_enabled;
	int eee_active;
	int tx_lpi_timer;
	unsigned int mode;
	unsigned int chain_mode;
	int extend_desc;
	struct hwtstamp_config tstamp_config;
	struct ptp_clock *ptp_clock;
	struct ptp_clock_info ptp_clock_ops;
	unsigned int default_addend;
	u32 sub_second_inc;
	u32 systime_flags;
	u32 adv_ts;
	int use_riwt;
	int irq_wake;
	spinlock_t ptp_lock;
	void __iomem *mmcaddr;
	void __iomem *ptpaddr;

#ifdef CONFIG_DEBUG_FS
	struct dentry *dbgfs_dir;
	struct dentry *dbgfs_rings_status;
	struct dentry *dbgfs_dma_cap;
#endif

	unsigned long state;
	struct workqueue_struct *wq;
	struct work_struct service_task;

	/* TC Handling */
	unsigned int tc_entries_max;
	unsigned int tc_off_max;
	struct stmmac_tc_entry *tc_entries;

	/* Pulse Per Second output */
	struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
};

enum stmmac_state {
	STMMAC_DOWN,
	STMMAC_RESET_REQUESTED,
	STMMAC_RESETING,
	STMMAC_SERVICE_SCHED,
};

int stmmac_mdio_unregister(struct net_device *ndev);
int stmmac_mdio_register(struct net_device *ndev);
int stmmac_mdio_reset(struct mii_bus *mii);
void stmmac_set_ethtool_ops(struct net_device *netdev);

void stmmac_ptp_register(struct stmmac_priv *priv);
void stmmac_ptp_unregister(struct stmmac_priv *priv);
int stmmac_resume(struct device *dev);
int stmmac_suspend(struct device *dev);
int stmmac_dvr_remove(struct device *dev);
int stmmac_dvr_probe(struct device *device,
		     struct plat_stmmacenet_data *plat_dat,
		     struct stmmac_resources *res);
void stmmac_disable_eee_mode(struct stmmac_priv *priv);
bool stmmac_eee_init(struct stmmac_priv *priv);

#endif /* __STMMAC_H__ */
Commit	Line	Data
47dd7a54 GC	1	/*******************************************************************************
	2	Copyright (C) 2007-2009 STMicroelectronics Ltd
	3
	4	This program is free software; you can redistribute it and/or modify it
	5	under the terms and conditions of the GNU General Public License,
	6	version 2, as published by the Free Software Foundation.
	7
	8	This program is distributed in the hope it will be useful, but WITHOUT
	9	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	more details.
	12
47dd7a54 GC	13	The full GNU General Public License is included in this distribution in
	14	the file called "COPYING".
	15
	16	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	17	*******************************************************************************/
	18
bd4242df RK	19	#ifndef __STMMAC_H__
	20	#define __STMMAC_H__
	21
bfab27a1	22	#define STMMAC_RESOURCE_NAME "stmmaceth"
06bce7dd	23	#define DRV_MODULE_VERSION "Jan_2016"
ba1377ff GC	24
ba1377ff GC	25	#include <linux/clk.h>
ee7946a7	26	#include <linux/stmmac.h>
286a8372	27	#include <linux/phy.h>
33d5e332	28	#include <linux/pci.h>
47dd7a54	29	#include "common.h"
92ba6888	30	#include <linux/ptp_clock_kernel.h>
d6228b7c	31	#include <linux/net_tstamp.h>
c5e4ddbd	32	#include <linux/reset.h>
47dd7a54	33
e56788cf JE	34	struct stmmac_resources {
	35	void __iomem *addr;
	36	const char *mac;
	37	int wol_irq;
	38	int lpi_irq;
	39	int irq;
	40	};
	41
362b37be GC	42	struct stmmac_tx_info {
	43	dma_addr_t buf;
	44	bool map_as_page;
553e2ab3	45	unsigned len;
2a6d8e17	46	bool last_segment;
96951366	47	bool is_jumbo;
362b37be GC	48	};
362b37be GC	49
ce736788 JP	50	/* Frequently used values are kept adjacent for cache effect */
ce736788 JP	51	struct stmmac_tx_queue {
8fce3331 JA	52	u32 tx_count_frames;
8fce3331 JA	53	struct timer_list txtimer;
ce736788 JP	54	u32 queue_index;
	55	struct stmmac_priv *priv_data;
	56	struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
	57	struct dma_desc *dma_tx;
	58	struct sk_buff **tx_skbuff;
	59	struct stmmac_tx_info *tx_skbuff_dma;
	60	unsigned int cur_tx;
	61	unsigned int dirty_tx;
	62	dma_addr_t dma_tx_phy;
	63	u32 tx_tail_addr;
8d212a9e	64	u32 mss;
ce736788 JP	65	};
ce736788 JP	66
54139cf3 JP	67	struct stmmac_rx_queue {
	68	u32 queue_index;
	69	struct stmmac_priv *priv_data;
	70	struct dma_extended_desc *dma_erx;
	71	struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
	72	struct sk_buff **rx_skbuff;
	73	dma_addr_t *rx_skbuff_dma;
	74	unsigned int cur_rx;
	75	unsigned int dirty_rx;
	76	u32 rx_zeroc_thresh;
	77	dma_addr_t dma_rx_phy;
	78	u32 rx_tail_addr;
8fce3331 JA	79	};
	80
	81	struct stmmac_channel {
4ccb4585 JA	82	struct napi_struct rx_napi ____cacheline_aligned_in_smp;
4ccb4585 JA	83	struct napi_struct tx_napi ____cacheline_aligned_in_smp;
8fce3331 JA	84	struct stmmac_priv *priv_data;
8fce3331 JA	85	u32 index;
54139cf3 JP	86	};
54139cf3 JP	87
4dbbe8dd JA	88	struct stmmac_tc_entry {
	89	bool in_use;
	90	bool in_hw;
	91	bool is_last;
	92	bool is_frag;
	93	void *frag_ptr;
	94	unsigned int table_pos;
	95	u32 handle;
	96	u32 prio;
	97	struct {
	98	u32 match_data;
	99	u32 match_en;
	100	u8 af:1;
	101	u8 rf:1;
	102	u8 im:1;
	103	u8 nc:1;
	104	u8 res1:4;
	105	u8 frame_offset;
	106	u8 ok_index;
	107	u8 dma_ch_no;
	108	u32 res2;
	109	} __packed val;
	110	};
	111
9a8a02c9 JA	112	#define STMMAC_PPS_MAX 4
	113	struct stmmac_pps_cfg {
	114	bool available;
	115	struct timespec64 start;
	116	struct timespec64 period;
	117	};
	118
47dd7a54 GC	119	struct stmmac_priv {
47dd7a54 GC	120	/* Frequently used values are kept adjacent for cache effect */
1bb6dea8 GC	121	u32 tx_coal_frames;
1bb6dea8 GC	122	u32 tx_coal_timer;
ce736788	123
47dd7a54	124	int tx_coalesce;
1bb6dea8	125	int hwts_tx_en;
1bb6dea8	126	bool tx_path_in_lpi_mode;
f748be53	127	bool tso;
47dd7a54	128
1bb6dea8	129	unsigned int dma_buf_sz;
22ad3838	130	unsigned int rx_copybreak;
1bb6dea8 GC	131	u32 rx_riwt;
1bb6dea8 GC	132	int hwts_rx_en;
5bacd778	133
1bb6dea8	134	void __iomem *ioaddr;
47dd7a54	135	struct net_device *dev;
47dd7a54	136	struct device *device;
db98a0b0	137	struct mac_device_info *hw;
7cfde0af	138	int (hwif_quirks)(struct stmmac_priv priv);
29555fa3	139	struct mutex lock;
47dd7a54	140
54139cf3 JP	141	/* RX Queue */
	142	struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];
	143
ce736788 JP	144	/* TX Queue */
	145	struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
	146
8fce3331 JA	147	/* Generic channel for NAPI */
	148	struct stmmac_channel channel[STMMAC_CH_MAX];
	149
4d869b03	150	bool oldlink;
47dd7a54 GC	151	int speed;
	152	int oldduplex;
	153	unsigned int flow_ctrl;
	154	unsigned int pause;
	155	struct mii_bus *mii;
36bcfe7d	156	int mii_irq[PHY_MAX_ADDR];
47dd7a54	157
1bb6dea8	158	struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
8bf993a5	159	struct stmmac_safety_stats sstats;
9dfeb4d9	160	struct plat_stmmacenet_data *plat;
e7434821	161	struct dma_features dma_cap;
1bb6dea8	162	struct stmmac_counters mmc;
19e30c14	163	int hw_cap_support;
1bb6dea8 GC	164	int synopsys_id;
	165	u32 msg_enable;
	166	int wolopts;
	167	int wol_irq;
cd7201f4	168	int clk_csr;
d765955d	169	struct timer_list eee_ctrl_timer;
d765955d GC	170	int lpi_irq;
	171	int eee_enabled;
	172	int eee_active;
	173	int tx_lpi_timer;
4a7d666a	174	unsigned int mode;
5f0456b4	175	unsigned int chain_mode;
c24602ef	176	int extend_desc;
d6228b7c	177	struct hwtstamp_config tstamp_config;
92ba6888 RK	178	struct ptp_clock *ptp_clock;
92ba6888 RK	179	struct ptp_clock_info ptp_clock_ops;
1bb6dea8	180	unsigned int default_addend;
9a8a02c9 JA	181	u32 sub_second_inc;
9a8a02c9 JA	182	u32 systime_flags;
1bb6dea8 GC	183	u32 adv_ts;
1bb6dea8 GC	184	int use_riwt;
89f7f2cf	185	int irq_wake;
92ba6888	186	spinlock_t ptp_lock;
36ff7c1e	187	void __iomem *mmcaddr;
ba1ffd74	188	void __iomem *ptpaddr;
466c5ac8 MO	189
	190	#ifdef CONFIG_DEBUG_FS
	191	struct dentry *dbgfs_dir;
	192	struct dentry *dbgfs_rings_status;
	193	struct dentry *dbgfs_dma_cap;
	194	#endif
34877a15 JA	195
	196	unsigned long state;
	197	struct workqueue_struct *wq;
	198	struct work_struct service_task;
4dbbe8dd JA	199
	200	/* TC Handling */
	201	unsigned int tc_entries_max;
	202	unsigned int tc_off_max;
	203	struct stmmac_tc_entry *tc_entries;
9a8a02c9 JA	204
	205	/* Pulse Per Second output */
	206	struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
34877a15 JA	207	};
	208
	209	enum stmmac_state {
	210	STMMAC_DOWN,
	211	STMMAC_RESET_REQUESTED,
	212	STMMAC_RESETING,
	213	STMMAC_SERVICE_SCHED,
47dd7a54 GC	214	};
47dd7a54 GC	215
d6cc64ef JP	216	int stmmac_mdio_unregister(struct net_device *ndev);
d6cc64ef JP	217	int stmmac_mdio_register(struct net_device *ndev);
073752aa	218	int stmmac_mdio_reset(struct mii_bus *mii);
d6cc64ef	219	void stmmac_set_ethtool_ops(struct net_device *netdev);
915af656	220
c30a70d3	221	void stmmac_ptp_register(struct stmmac_priv *priv);
d6cc64ef	222	void stmmac_ptp_unregister(struct stmmac_priv *priv);
f4e7bd81 JE	223	int stmmac_resume(struct device *dev);
	224	int stmmac_suspend(struct device *dev);
	225	int stmmac_dvr_remove(struct device *dev);
15ffac73 JE	226	int stmmac_dvr_probe(struct device *device,
	227	struct plat_stmmacenet_data *plat_dat,
	228	struct stmmac_resources *res);
d765955d GC	229	void stmmac_disable_eee_mode(struct stmmac_priv *priv);
d765955d GC	230	bool stmmac_eee_init(struct stmmac_priv *priv);
ba1377ff	231
bd4242df	232	#endif /* __STMMAC_H__ */