[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / hwif.c

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
 * stmmac HW Interface Handling
 */

#include "common.h"
#include "stmmac.h"
#include "stmmac_ptp.h"
#include "stmmac_est.h"

static u32 stmmac_get_id(struct stmmac_priv *priv, u32 id_reg)
{
	u32 reg = readl(priv->ioaddr + id_reg);

	if (!reg) {
		dev_info(priv->device, "Version ID not available\n");
		return 0x0;
	}

	dev_info(priv->device, "User ID: 0x%x, Synopsys ID: 0x%x\n",
			(unsigned int)(reg & GENMASK(15, 8)) >> 8,
			(unsigned int)(reg & GENMASK(7, 0)));
	return reg & GENMASK(7, 0);
}

static u32 stmmac_get_dev_id(struct stmmac_priv *priv, u32 id_reg)
{
	u32 reg = readl(priv->ioaddr + id_reg);

	if (!reg) {
		dev_info(priv->device, "Version ID not available\n");
		return 0x0;
	}

	return (reg & GENMASK(15, 8)) >> 8;
}

static void stmmac_dwmac_mode_quirk(struct stmmac_priv *priv)
{
	struct mac_device_info *mac = priv->hw;

	if (priv->chain_mode) {
		dev_info(priv->device, "Chain mode enabled\n");
		priv->mode = STMMAC_CHAIN_MODE;
		mac->mode = &chain_mode_ops;
	} else {
		dev_info(priv->device, "Ring mode enabled\n");
		priv->mode = STMMAC_RING_MODE;
		mac->mode = &ring_mode_ops;
	}
}

static int stmmac_dwmac1_quirks(struct stmmac_priv *priv)
{
	struct mac_device_info *mac = priv->hw;

	if (priv->plat->enh_desc) {
		dev_info(priv->device, "Enhanced/Alternate descriptors\n");

		/* GMAC older than 3.50 has no extended descriptors */
		if (priv->synopsys_id >= DWMAC_CORE_3_50) {
			dev_info(priv->device, "Enabled extended descriptors\n");
			priv->extend_desc = 1;
		} else {
			dev_warn(priv->device, "Extended descriptors not supported\n");
		}

		mac->desc = &enh_desc_ops;
	} else {
		dev_info(priv->device, "Normal descriptors\n");
		mac->desc = &ndesc_ops;
	}

	stmmac_dwmac_mode_quirk(priv);
	return 0;
}

static int stmmac_dwmac4_quirks(struct stmmac_priv *priv)
{
	stmmac_dwmac_mode_quirk(priv);
	return 0;
}

static int stmmac_dwxlgmac_quirks(struct stmmac_priv *priv)
{
	priv->hw->xlgmac = true;
	return 0;
}

int stmmac_reset(struct stmmac_priv *priv, void __iomem *ioaddr)
{
	struct plat_stmmacenet_data *plat = priv ? priv->plat : NULL;

	if (!priv)
		return -EINVAL;

	if (plat && plat->fix_soc_reset)
		return plat->fix_soc_reset(plat, ioaddr);

	return stmmac_do_callback(priv, dma, reset, ioaddr);
}

static const struct stmmac_hwif_entry {
	bool gmac;
	bool gmac4;
	bool xgmac;
	u32 min_id;
	u32 dev_id;
	const struct stmmac_regs_off regs;
	const void *desc;
	const void *dma;
	const void *mac;
	const void *hwtimestamp;
	const void *mode;
	const void *tc;
	const void *mmc;
	const void *est;
	int (*setup)(struct stmmac_priv *priv);
	int (*quirks)(struct stmmac_priv *priv);
} stmmac_hw[] = {
	/* NOTE: New HW versions shall go to the end of this table */
	{
		.gmac = false,
		.gmac4 = false,
		.xgmac = false,
		.min_id = 0,
		.regs = {
			.ptp_off = PTP_GMAC3_X_OFFSET,
			.mmc_off = MMC_GMAC3_X_OFFSET,
		},
		.desc = NULL,
		.dma = &dwmac100_dma_ops,
		.mac = &dwmac100_ops,
		.hwtimestamp = &stmmac_ptp,
		.mode = NULL,
		.tc = NULL,
		.mmc = &dwmac_mmc_ops,
		.setup = dwmac100_setup,
		.quirks = stmmac_dwmac1_quirks,
	}, {
		.gmac = true,
		.gmac4 = false,
		.xgmac = false,
		.min_id = 0,
		.regs = {
			.ptp_off = PTP_GMAC3_X_OFFSET,
			.mmc_off = MMC_GMAC3_X_OFFSET,
		},
		.desc = NULL,
		.dma = &dwmac1000_dma_ops,
		.mac = &dwmac1000_ops,
		.hwtimestamp = &stmmac_ptp,
		.mode = NULL,
		.tc = NULL,
		.mmc = &dwmac_mmc_ops,
		.setup = dwmac1000_setup,
		.quirks = stmmac_dwmac1_quirks,
	}, {
		.gmac = false,
		.gmac4 = true,
		.xgmac = false,
		.min_id = 0,
		.regs = {
			.ptp_off = PTP_GMAC4_OFFSET,
			.mmc_off = MMC_GMAC4_OFFSET,
			.est_off = EST_GMAC4_OFFSET,
		},
		.desc = &dwmac4_desc_ops,
		.dma = &dwmac4_dma_ops,
		.mac = &dwmac4_ops,
		.hwtimestamp = &stmmac_ptp,
		.mode = NULL,
		.tc = &dwmac510_tc_ops,
		.mmc = &dwmac_mmc_ops,
		.est = &dwmac510_est_ops,
		.setup = dwmac4_setup,
		.quirks = stmmac_dwmac4_quirks,
	}, {
		.gmac = false,
		.gmac4 = true,
		.xgmac = false,
		.min_id = DWMAC_CORE_4_00,
		.regs = {
			.ptp_off = PTP_GMAC4_OFFSET,
			.mmc_off = MMC_GMAC4_OFFSET,
			.est_off = EST_GMAC4_OFFSET,
		},
		.desc = &dwmac4_desc_ops,
		.dma = &dwmac4_dma_ops,
		.mac = &dwmac410_ops,
		.hwtimestamp = &stmmac_ptp,
		.mode = &dwmac4_ring_mode_ops,
		.tc = &dwmac510_tc_ops,
		.mmc = &dwmac_mmc_ops,
		.est = &dwmac510_est_ops,
		.setup = dwmac4_setup,
		.quirks = NULL,
	}, {
		.gmac = false,
		.gmac4 = true,
		.xgmac = false,
		.min_id = DWMAC_CORE_4_10,
		.regs = {
			.ptp_off = PTP_GMAC4_OFFSET,
			.mmc_off = MMC_GMAC4_OFFSET,
			.est_off = EST_GMAC4_OFFSET,
		},
		.desc = &dwmac4_desc_ops,
		.dma = &dwmac410_dma_ops,
		.mac = &dwmac410_ops,
		.hwtimestamp = &stmmac_ptp,
		.mode = &dwmac4_ring_mode_ops,
		.tc = &dwmac510_tc_ops,
		.mmc = &dwmac_mmc_ops,
		.est = &dwmac510_est_ops,
		.setup = dwmac4_setup,
		.quirks = NULL,
	}, {
		.gmac = false,
		.gmac4 = true,
		.xgmac = false,
		.min_id = DWMAC_CORE_5_10,
		.regs = {
			.ptp_off = PTP_GMAC4_OFFSET,
			.mmc_off = MMC_GMAC4_OFFSET,
			.est_off = EST_GMAC4_OFFSET,
		},
		.desc = &dwmac4_desc_ops,
		.dma = &dwmac410_dma_ops,
		.mac = &dwmac510_ops,
		.hwtimestamp = &stmmac_ptp,
		.mode = &dwmac4_ring_mode_ops,
		.tc = &dwmac510_tc_ops,
		.mmc = &dwmac_mmc_ops,
		.est = &dwmac510_est_ops,
		.setup = dwmac4_setup,
		.quirks = NULL,
	}, {
		.gmac = false,
		.gmac4 = false,
		.xgmac = true,
		.min_id = DWXGMAC_CORE_2_10,
		.dev_id = DWXGMAC_ID,
		.regs = {
			.ptp_off = PTP_XGMAC_OFFSET,
			.mmc_off = MMC_XGMAC_OFFSET,
			.est_off = EST_XGMAC_OFFSET,
		},
		.desc = &dwxgmac210_desc_ops,
		.dma = &dwxgmac210_dma_ops,
		.mac = &dwxgmac210_ops,
		.hwtimestamp = &stmmac_ptp,
		.mode = NULL,
		.tc = &dwmac510_tc_ops,
		.mmc = &dwxgmac_mmc_ops,
		.est = &dwmac510_est_ops,
		.setup = dwxgmac2_setup,
		.quirks = NULL,
	}, {
		.gmac = false,
		.gmac4 = false,
		.xgmac = true,
		.min_id = DWXLGMAC_CORE_2_00,
		.dev_id = DWXLGMAC_ID,
		.regs = {
			.ptp_off = PTP_XGMAC_OFFSET,
			.mmc_off = MMC_XGMAC_OFFSET,
			.est_off = EST_XGMAC_OFFSET,
		},
		.desc = &dwxgmac210_desc_ops,
		.dma = &dwxgmac210_dma_ops,
		.mac = &dwxlgmac2_ops,
		.hwtimestamp = &stmmac_ptp,
		.mode = NULL,
		.tc = &dwmac510_tc_ops,
		.mmc = &dwxgmac_mmc_ops,
		.est = &dwmac510_est_ops,
		.setup = dwxlgmac2_setup,
		.quirks = stmmac_dwxlgmac_quirks,
	},
};

int stmmac_hwif_init(struct stmmac_priv *priv)
{
	bool needs_xgmac = priv->plat->has_xgmac;
	bool needs_gmac4 = priv->plat->has_gmac4;
	bool needs_gmac = priv->plat->has_gmac;
	const struct stmmac_hwif_entry *entry;
	struct mac_device_info *mac;
	bool needs_setup = true;
	u32 id, dev_id = 0;
	int i, ret;

	if (needs_gmac) {
		id = stmmac_get_id(priv, GMAC_VERSION);
	} else if (needs_gmac4 || needs_xgmac) {
		id = stmmac_get_id(priv, GMAC4_VERSION);
		if (needs_xgmac)
			dev_id = stmmac_get_dev_id(priv, GMAC4_VERSION);
	} else {
		id = 0;
	}

	/* Save ID for later use */
	priv->synopsys_id = id;

	/* Lets assume some safe values first */
	priv->ptpaddr = priv->ioaddr +
		(needs_gmac4 ? PTP_GMAC4_OFFSET : PTP_GMAC3_X_OFFSET);
	priv->mmcaddr = priv->ioaddr +
		(needs_gmac4 ? MMC_GMAC4_OFFSET : MMC_GMAC3_X_OFFSET);
	if (needs_gmac4)
		priv->estaddr = priv->ioaddr + EST_GMAC4_OFFSET;
	else if (needs_xgmac)
		priv->estaddr = priv->ioaddr + EST_XGMAC_OFFSET;

	/* Check for HW specific setup first */
	if (priv->plat->setup) {
		mac = priv->plat->setup(priv);
		needs_setup = false;
	} else {
		mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
	}

	if (!mac)
		return -ENOMEM;

	/* Fallback to generic HW */
	for (i = ARRAY_SIZE(stmmac_hw) - 1; i >= 0; i--) {
		entry = &stmmac_hw[i];

		if (needs_gmac ^ entry->gmac)
			continue;
		if (needs_gmac4 ^ entry->gmac4)
			continue;
		if (needs_xgmac ^ entry->xgmac)
			continue;
		/* Use synopsys_id var because some setups can override this */
		if (priv->synopsys_id < entry->min_id)
			continue;
		if (needs_xgmac && (dev_id ^ entry->dev_id))
			continue;

		/* Only use generic HW helpers if needed */
		mac->desc = mac->desc ? : entry->desc;
		mac->dma = mac->dma ? : entry->dma;
		mac->mac = mac->mac ? : entry->mac;
		mac->ptp = mac->ptp ? : entry->hwtimestamp;
		mac->mode = mac->mode ? : entry->mode;
		mac->tc = mac->tc ? : entry->tc;
		mac->mmc = mac->mmc ? : entry->mmc;
		mac->est = mac->est ? : entry->est;

		priv->hw = mac;
		priv->ptpaddr = priv->ioaddr + entry->regs.ptp_off;
		priv->mmcaddr = priv->ioaddr + entry->regs.mmc_off;
		if (entry->est)
			priv->estaddr = priv->ioaddr + entry->regs.est_off;

		/* Entry found */
		if (needs_setup) {
			ret = entry->setup(priv);
			if (ret)
				return ret;
		}

		/* Save quirks, if needed for posterior use */
		priv->hwif_quirks = entry->quirks;
		return 0;
	}

	dev_err(priv->device, "Failed to find HW IF (id=0x%x, gmac=%d/%d)\n",
			id, needs_gmac, needs_gmac4);
	return -EINVAL;
}
Commit	Line	Data
5f0456b4 JA	1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	2	/*
	3	* Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
	4	* stmmac HW Interface Handling
	5	*/
	6
	7	#include "common.h"
	8	#include "stmmac.h"
758d5c73	9	#include "stmmac_ptp.h"
c3f3b972	10	#include "stmmac_est.h"
5f0456b4 JA	11
	12	static u32 stmmac_get_id(struct stmmac_priv *priv, u32 id_reg)
	13	{
	14	u32 reg = readl(priv->ioaddr + id_reg);
	15
	16	if (!reg) {
	17	dev_info(priv->device, "Version ID not available\n");
	18	return 0x0;
	19	}
	20
	21	dev_info(priv->device, "User ID: 0x%x, Synopsys ID: 0x%x\n",
	22	(unsigned int)(reg & GENMASK(15, 8)) >> 8,
	23	(unsigned int)(reg & GENMASK(7, 0)));
	24	return reg & GENMASK(7, 0);
	25	}
	26
4a4ccde0 JA	27	static u32 stmmac_get_dev_id(struct stmmac_priv *priv, u32 id_reg)
	28	{
	29	u32 reg = readl(priv->ioaddr + id_reg);
	30
	31	if (!reg) {
	32	dev_info(priv->device, "Version ID not available\n");
	33	return 0x0;
	34	}
	35
	36	return (reg & GENMASK(15, 8)) >> 8;
	37	}
	38
5f0456b4 JA	39	static void stmmac_dwmac_mode_quirk(struct stmmac_priv *priv)
	40	{
	41	struct mac_device_info *mac = priv->hw;
	42
	43	if (priv->chain_mode) {
	44	dev_info(priv->device, "Chain mode enabled\n");
	45	priv->mode = STMMAC_CHAIN_MODE;
	46	mac->mode = &chain_mode_ops;
	47	} else {
	48	dev_info(priv->device, "Ring mode enabled\n");
	49	priv->mode = STMMAC_RING_MODE;
	50	mac->mode = &ring_mode_ops;
	51	}
	52	}
	53
	54	static int stmmac_dwmac1_quirks(struct stmmac_priv *priv)
	55	{
	56	struct mac_device_info *mac = priv->hw;
	57
	58	if (priv->plat->enh_desc) {
	59	dev_info(priv->device, "Enhanced/Alternate descriptors\n");
	60
	61	/* GMAC older than 3.50 has no extended descriptors */
	62	if (priv->synopsys_id >= DWMAC_CORE_3_50) {
	63	dev_info(priv->device, "Enabled extended descriptors\n");
	64	priv->extend_desc = 1;
	65	} else {
	66	dev_warn(priv->device, "Extended descriptors not supported\n");
	67	}
	68
	69	mac->desc = &enh_desc_ops;
	70	} else {
	71	dev_info(priv->device, "Normal descriptors\n");
	72	mac->desc = &ndesc_ops;
	73	}
	74
	75	stmmac_dwmac_mode_quirk(priv);
	76	return 0;
	77	}
	78
	79	static int stmmac_dwmac4_quirks(struct stmmac_priv *priv)
	80	{
	81	stmmac_dwmac_mode_quirk(priv);
	82	return 0;
	83	}
	84
4a4ccde0 JA	85	static int stmmac_dwxlgmac_quirks(struct stmmac_priv *priv)
	86	{
	87	priv->hw->xlgmac = true;
	88	return 0;
	89	}
	90
10739ea3 SW	91	int stmmac_reset(struct stmmac_priv priv, void __iomem ioaddr)
	92	{
	93	struct plat_stmmacenet_data *plat = priv ? priv->plat : NULL;
	94
	95	if (!priv)
	96	return -EINVAL;
	97
	98	if (plat && plat->fix_soc_reset)
	99	return plat->fix_soc_reset(plat, ioaddr);
	100
	101	return stmmac_do_callback(priv, dma, reset, ioaddr);
	102	}
	103
5f0456b4 JA	104	static const struct stmmac_hwif_entry {
	105	bool gmac;
	106	bool gmac4;
48ae5554	107	bool xgmac;
5f0456b4	108	u32 min_id;
4a4ccde0	109	u32 dev_id;
758d5c73	110	const struct stmmac_regs_off regs;
5f0456b4 JA	111	const void *desc;
	112	const void *dma;
	113	const void *mac;
	114	const void *hwtimestamp;
	115	const void *mode;
4dbbe8dd	116	const void *tc;
3b1dd2c5	117	const void *mmc;
c3f3b972	118	const void *est;
5f0456b4 JA	119	int (setup)(struct stmmac_priv priv);
	120	int (quirks)(struct stmmac_priv priv);
	121	} stmmac_hw[] = {
	122	/* NOTE: New HW versions shall go to the end of this table */
	123	{
	124	.gmac = false,
	125	.gmac4 = false,
48ae5554	126	.xgmac = false,
5f0456b4	127	.min_id = 0,
758d5c73 JA	128	.regs = {
	129	.ptp_off = PTP_GMAC3_X_OFFSET,
	130	.mmc_off = MMC_GMAC3_X_OFFSET,
	131	},
5f0456b4 JA	132	.desc = NULL,
	133	.dma = &dwmac100_dma_ops,
	134	.mac = &dwmac100_ops,
	135	.hwtimestamp = &stmmac_ptp,
	136	.mode = NULL,
4dbbe8dd	137	.tc = NULL,
3b1dd2c5	138	.mmc = &dwmac_mmc_ops,
5f0456b4 JA	139	.setup = dwmac100_setup,
	140	.quirks = stmmac_dwmac1_quirks,
	141	}, {
	142	.gmac = true,
	143	.gmac4 = false,
48ae5554	144	.xgmac = false,
5f0456b4	145	.min_id = 0,
758d5c73 JA	146	.regs = {
	147	.ptp_off = PTP_GMAC3_X_OFFSET,
	148	.mmc_off = MMC_GMAC3_X_OFFSET,
	149	},
5f0456b4 JA	150	.desc = NULL,
	151	.dma = &dwmac1000_dma_ops,
	152	.mac = &dwmac1000_ops,
	153	.hwtimestamp = &stmmac_ptp,
	154	.mode = NULL,
4dbbe8dd	155	.tc = NULL,
3b1dd2c5	156	.mmc = &dwmac_mmc_ops,
5f0456b4 JA	157	.setup = dwmac1000_setup,
	158	.quirks = stmmac_dwmac1_quirks,
	159	}, {
	160	.gmac = false,
	161	.gmac4 = true,
48ae5554	162	.xgmac = false,
5f0456b4	163	.min_id = 0,
758d5c73 JA	164	.regs = {
	165	.ptp_off = PTP_GMAC4_OFFSET,
	166	.mmc_off = MMC_GMAC4_OFFSET,
c3f3b972	167	.est_off = EST_GMAC4_OFFSET,
758d5c73	168	},
5f0456b4 JA	169	.desc = &dwmac4_desc_ops,
	170	.dma = &dwmac4_dma_ops,
	171	.mac = &dwmac4_ops,
	172	.hwtimestamp = &stmmac_ptp,
	173	.mode = NULL,
cc577b01	174	.tc = &dwmac510_tc_ops,
3b1dd2c5	175	.mmc = &dwmac_mmc_ops,
c3f3b972	176	.est = &dwmac510_est_ops,
5f0456b4 JA	177	.setup = dwmac4_setup,
	178	.quirks = stmmac_dwmac4_quirks,
	179	}, {
	180	.gmac = false,
	181	.gmac4 = true,
48ae5554	182	.xgmac = false,
5f0456b4	183	.min_id = DWMAC_CORE_4_00,
758d5c73 JA	184	.regs = {
	185	.ptp_off = PTP_GMAC4_OFFSET,
	186	.mmc_off = MMC_GMAC4_OFFSET,
c3f3b972	187	.est_off = EST_GMAC4_OFFSET,
758d5c73	188	},
5f0456b4 JA	189	.desc = &dwmac4_desc_ops,
	190	.dma = &dwmac4_dma_ops,
	191	.mac = &dwmac410_ops,
	192	.hwtimestamp = &stmmac_ptp,
	193	.mode = &dwmac4_ring_mode_ops,
cc577b01	194	.tc = &dwmac510_tc_ops,
3b1dd2c5	195	.mmc = &dwmac_mmc_ops,
c3f3b972	196	.est = &dwmac510_est_ops,
5f0456b4 JA	197	.setup = dwmac4_setup,
	198	.quirks = NULL,
	199	}, {
	200	.gmac = false,
	201	.gmac4 = true,
48ae5554	202	.xgmac = false,
5f0456b4	203	.min_id = DWMAC_CORE_4_10,
758d5c73 JA	204	.regs = {
	205	.ptp_off = PTP_GMAC4_OFFSET,
	206	.mmc_off = MMC_GMAC4_OFFSET,
c3f3b972	207	.est_off = EST_GMAC4_OFFSET,
758d5c73	208	},
5f0456b4 JA	209	.desc = &dwmac4_desc_ops,
	210	.dma = &dwmac410_dma_ops,
	211	.mac = &dwmac410_ops,
	212	.hwtimestamp = &stmmac_ptp,
	213	.mode = &dwmac4_ring_mode_ops,
cc577b01	214	.tc = &dwmac510_tc_ops,
3b1dd2c5	215	.mmc = &dwmac_mmc_ops,
c3f3b972	216	.est = &dwmac510_est_ops,
5f0456b4 JA	217	.setup = dwmac4_setup,
	218	.quirks = NULL,
	219	}, {
	220	.gmac = false,
	221	.gmac4 = true,
48ae5554	222	.xgmac = false,
5f0456b4	223	.min_id = DWMAC_CORE_5_10,
758d5c73 JA	224	.regs = {
	225	.ptp_off = PTP_GMAC4_OFFSET,
	226	.mmc_off = MMC_GMAC4_OFFSET,
90d07e36	227	.est_off = EST_GMAC4_OFFSET,
758d5c73	228	},
5f0456b4 JA	229	.desc = &dwmac4_desc_ops,
	230	.dma = &dwmac410_dma_ops,
	231	.mac = &dwmac510_ops,
	232	.hwtimestamp = &stmmac_ptp,
	233	.mode = &dwmac4_ring_mode_ops,
4dbbe8dd	234	.tc = &dwmac510_tc_ops,
3b1dd2c5	235	.mmc = &dwmac_mmc_ops,
c3f3b972	236	.est = &dwmac510_est_ops,
5f0456b4 JA	237	.setup = dwmac4_setup,
5f0456b4 JA	238	.quirks = NULL,
48ae5554 JA	239	}, {
	240	.gmac = false,
	241	.gmac4 = false,
	242	.xgmac = true,
	243	.min_id = DWXGMAC_CORE_2_10,
4a4ccde0	244	.dev_id = DWXGMAC_ID,
48ae5554	245	.regs = {
4bb7aff9	246	.ptp_off = PTP_XGMAC_OFFSET,
b6cdf09f	247	.mmc_off = MMC_XGMAC_OFFSET,
c3f3b972	248	.est_off = EST_XGMAC_OFFSET,
48ae5554	249	},
874dfb65	250	.desc = &dwxgmac210_desc_ops,
d6ddfacd	251	.dma = &dwxgmac210_dma_ops,
2142754f	252	.mac = &dwxgmac210_ops,
4bb7aff9	253	.hwtimestamp = &stmmac_ptp,
48ae5554	254	.mode = NULL,
ec6ea8e3	255	.tc = &dwmac510_tc_ops,
b6cdf09f	256	.mmc = &dwxgmac_mmc_ops,
c3f3b972	257	.est = &dwmac510_est_ops,
2142754f	258	.setup = dwxgmac2_setup,
48ae5554	259	.quirks = NULL,
4a4ccde0 JA	260	}, {
	261	.gmac = false,
	262	.gmac4 = false,
	263	.xgmac = true,
	264	.min_id = DWXLGMAC_CORE_2_00,
	265	.dev_id = DWXLGMAC_ID,
	266	.regs = {
	267	.ptp_off = PTP_XGMAC_OFFSET,
	268	.mmc_off = MMC_XGMAC_OFFSET,
c3f3b972	269	.est_off = EST_XGMAC_OFFSET,
4a4ccde0 JA	270	},
	271	.desc = &dwxgmac210_desc_ops,
	272	.dma = &dwxgmac210_dma_ops,
	273	.mac = &dwxlgmac2_ops,
	274	.hwtimestamp = &stmmac_ptp,
	275	.mode = NULL,
	276	.tc = &dwmac510_tc_ops,
	277	.mmc = &dwxgmac_mmc_ops,
c3f3b972	278	.est = &dwmac510_est_ops,
4a4ccde0 JA	279	.setup = dwxlgmac2_setup,
4a4ccde0 JA	280	.quirks = stmmac_dwxlgmac_quirks,
48ae5554	281	},
5f0456b4 JA	282	};
	283
	284	int stmmac_hwif_init(struct stmmac_priv *priv)
	285	{
48ae5554	286	bool needs_xgmac = priv->plat->has_xgmac;
5f0456b4 JA	287	bool needs_gmac4 = priv->plat->has_gmac4;
	288	bool needs_gmac = priv->plat->has_gmac;
	289	const struct stmmac_hwif_entry *entry;
	290	struct mac_device_info *mac;
eb38401c	291	bool needs_setup = true;
4a4ccde0	292	u32 id, dev_id = 0;
5f0456b4	293	int i, ret;
5f0456b4 JA	294
	295	if (needs_gmac) {
	296	id = stmmac_get_id(priv, GMAC_VERSION);
48ae5554	297	} else if (needs_gmac4 \|\| needs_xgmac) {
5f0456b4	298	id = stmmac_get_id(priv, GMAC4_VERSION);
4a4ccde0 JA	299	if (needs_xgmac)
4a4ccde0 JA	300	dev_id = stmmac_get_dev_id(priv, GMAC4_VERSION);
eb38401c JA	301	} else {
eb38401c JA	302	id = 0;
5f0456b4 JA	303	}
	304
	305	/* Save ID for later use */
	306	priv->synopsys_id = id;
	307
758d5c73 JA	308	/* Lets assume some safe values first */
	309	priv->ptpaddr = priv->ioaddr +
	310	(needs_gmac4 ? PTP_GMAC4_OFFSET : PTP_GMAC3_X_OFFSET);
	311	priv->mmcaddr = priv->ioaddr +
	312	(needs_gmac4 ? MMC_GMAC4_OFFSET : MMC_GMAC3_X_OFFSET);
c3f3b972 RT	313	if (needs_gmac4)
	314	priv->estaddr = priv->ioaddr + EST_GMAC4_OFFSET;
	315	else if (needs_xgmac)
	316	priv->estaddr = priv->ioaddr + EST_XGMAC_OFFSET;
758d5c73	317
5f0456b4 JA	318	/* Check for HW specific setup first */
5f0456b4 JA	319	if (priv->plat->setup) {
eb38401c JA	320	mac = priv->plat->setup(priv);
	321	needs_setup = false;
	322	} else {
	323	mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
5f0456b4 JA	324	}
5f0456b4 JA	325
5f0456b4 JA	326	if (!mac)
	327	return -ENOMEM;
	328
	329	/* Fallback to generic HW */
	330	for (i = ARRAY_SIZE(stmmac_hw) - 1; i >= 0; i--) {
	331	entry = &stmmac_hw[i];
	332
	333	if (needs_gmac ^ entry->gmac)
	334	continue;
	335	if (needs_gmac4 ^ entry->gmac4)
	336	continue;
48ae5554 JA	337	if (needs_xgmac ^ entry->xgmac)
48ae5554 JA	338	continue;
eb38401c JA	339	/* Use synopsys_id var because some setups can override this */
eb38401c JA	340	if (priv->synopsys_id < entry->min_id)
5f0456b4	341	continue;
4a4ccde0 JA	342	if (needs_xgmac && (dev_id ^ entry->dev_id))
4a4ccde0 JA	343	continue;
5f0456b4	344
eb38401c JA	345	/* Only use generic HW helpers if needed */
	346	mac->desc = mac->desc ? : entry->desc;
	347	mac->dma = mac->dma ? : entry->dma;
	348	mac->mac = mac->mac ? : entry->mac;
	349	mac->ptp = mac->ptp ? : entry->hwtimestamp;
	350	mac->mode = mac->mode ? : entry->mode;
	351	mac->tc = mac->tc ? : entry->tc;
3b1dd2c5	352	mac->mmc = mac->mmc ? : entry->mmc;
c3f3b972	353	mac->est = mac->est ? : entry->est;
5f0456b4 JA	354
5f0456b4 JA	355	priv->hw = mac;
758d5c73 JA	356	priv->ptpaddr = priv->ioaddr + entry->regs.ptp_off;
758d5c73 JA	357	priv->mmcaddr = priv->ioaddr + entry->regs.mmc_off;
c3f3b972 RT	358	if (entry->est)
c3f3b972 RT	359	priv->estaddr = priv->ioaddr + entry->regs.est_off;
5f0456b4 JA	360
5f0456b4 JA	361	/* Entry found */
eb38401c JA	362	if (needs_setup) {
	363	ret = entry->setup(priv);
	364	if (ret)
	365	return ret;
	366	}
5f0456b4	367
7cfde0af JA	368	/* Save quirks, if needed for posterior use */
7cfde0af JA	369	priv->hwif_quirks = entry->quirks;
5f0456b4 JA	370	return 0;
	371	}
	372
	373	dev_err(priv->device, "Failed to find HW IF (id=0x%x, gmac=%d/%d)\n",
	374	id, needs_gmac, needs_gmac4);
	375	return -EINVAL;
	376	}