[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / dwxgmac2_dma.c

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
 * stmmac XGMAC support.
 */

#include <linux/iopoll.h>
#include "stmmac.h"
#include "dwxgmac2.h"

static int dwxgmac2_dma_reset(void __iomem *ioaddr)
{
	u32 value = readl(ioaddr + XGMAC_DMA_MODE);

	/* DMA SW reset */
	writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE);

	return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value,
				  !(value & XGMAC_SWR), 0, 100000);
}

static void dwxgmac2_dma_init(void __iomem *ioaddr,
			      struct stmmac_dma_cfg *dma_cfg, int atds)
{
	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);

	if (dma_cfg->aal)
		value |= XGMAC_AAL;

	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
}

static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,
				   struct stmmac_dma_cfg *dma_cfg, u32 chan)
{
	u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));

	if (dma_cfg->pblx8)
		value |= XGMAC_PBLx8;

	writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
	writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
}

static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr,
				      struct stmmac_dma_cfg *dma_cfg,
				      u32 dma_rx_phy, u32 chan)
{
	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
	u32 value;

	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	value &= ~XGMAC_RxPBL;
	value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;
	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));

	writel(dma_rx_phy, ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
}

static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr,
				      struct stmmac_dma_cfg *dma_cfg,
				      u32 dma_tx_phy, u32 chan)
{
	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
	u32 value;

	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	value &= ~XGMAC_TxPBL;
	value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL;
	value |= XGMAC_OSP;
	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));

	writel(dma_tx_phy, ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
}

static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
{
	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
	int i;

	if (axi->axi_lpi_en)
		value |= XGMAC_EN_LPI;
	if (axi->axi_xit_frm)
		value |= XGMAC_LPI_XIT_PKT;

	value &= ~XGMAC_WR_OSR_LMT;
	value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) &
		XGMAC_WR_OSR_LMT;

	value &= ~XGMAC_RD_OSR_LMT;
	value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) &
		XGMAC_RD_OSR_LMT;

	value &= ~XGMAC_BLEN;
	for (i = 0; i < AXI_BLEN; i++) {
		if (axi->axi_blen[i])
			value &= ~XGMAC_UNDEF;

		switch (axi->axi_blen[i]) {
		case 256:
			value |= XGMAC_BLEN256;
			break;
		case 128:
			value |= XGMAC_BLEN128;
			break;
		case 64:
			value |= XGMAC_BLEN64;
			break;
		case 32:
			value |= XGMAC_BLEN32;
			break;
		case 16:
			value |= XGMAC_BLEN16;
			break;
		case 8:
			value |= XGMAC_BLEN8;
			break;
		case 4:
			value |= XGMAC_BLEN4;
			break;
		}
	}

	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
}

static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,
				 u32 channel, int fifosz, u8 qmode)
{
	u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
	unsigned int rqs = fifosz / 256 - 1;

	if (mode == SF_DMA_MODE) {
		value |= XGMAC_RSF;
	} else {
		value &= ~XGMAC_RSF;
		value &= ~XGMAC_RTC;

		if (mode <= 64)
			value |= 0x0 << XGMAC_RTC_SHIFT;
		else if (mode <= 96)
			value |= 0x2 << XGMAC_RTC_SHIFT;
		else
			value |= 0x3 << XGMAC_RTC_SHIFT;
	}

	value &= ~XGMAC_RQS;
	value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS;

	writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));

	/* Enable MTL RX overflow */
	value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));
	writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel));
}

static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode,
				 u32 channel, int fifosz, u8 qmode)
{
	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
	unsigned int tqs = fifosz / 256 - 1;

	if (mode == SF_DMA_MODE) {
		value |= XGMAC_TSF;
	} else {
		value &= ~XGMAC_TSF;
		value &= ~XGMAC_TTC;

		if (mode <= 64)
			value |= 0x0 << XGMAC_TTC_SHIFT;
		else if (mode <= 96)
			value |= 0x2 << XGMAC_TTC_SHIFT;
		else if (mode <= 128)
			value |= 0x3 << XGMAC_TTC_SHIFT;
		else if (mode <= 192)
			value |= 0x4 << XGMAC_TTC_SHIFT;
		else if (mode <= 256)
			value |= 0x5 << XGMAC_TTC_SHIFT;
		else if (mode <= 384)
			value |= 0x6 << XGMAC_TTC_SHIFT;
		else
			value |= 0x7 << XGMAC_TTC_SHIFT;
	}

	/* Use static TC to Queue mapping */
	value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP;

	value &= ~XGMAC_TXQEN;
	if (qmode != MTL_QUEUE_AVB)
		value |= 0x2 << XGMAC_TXQEN_SHIFT;
	else
		value |= 0x1 << XGMAC_TXQEN_SHIFT;

	value &= ~XGMAC_TQS;
	value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS;

	writel(value, ioaddr +  XGMAC_MTL_TXQ_OPMODE(channel));
}

static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan)
{
	writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
}

static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan)
{
	writel(0, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
}

static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan)
{
	u32 value;

	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	value |= XGMAC_TXST;
	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));

	value = readl(ioaddr + XGMAC_TX_CONFIG);
	value |= XGMAC_CONFIG_TE;
	writel(value, ioaddr + XGMAC_TX_CONFIG);
}

static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan)
{
	u32 value;

	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	value &= ~XGMAC_TXST;
	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));

	value = readl(ioaddr + XGMAC_TX_CONFIG);
	value &= ~XGMAC_CONFIG_TE;
	writel(value, ioaddr + XGMAC_TX_CONFIG);
}

static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan)
{
	u32 value;

	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	value |= XGMAC_RXST;
	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));

	value = readl(ioaddr + XGMAC_RX_CONFIG);
	value |= XGMAC_CONFIG_RE;
	writel(value, ioaddr + XGMAC_RX_CONFIG);
}

static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan)
{
	u32 value;

	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	value &= ~XGMAC_RXST;
	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));

	value = readl(ioaddr + XGMAC_RX_CONFIG);
	value &= ~XGMAC_CONFIG_RE;
	writel(value, ioaddr + XGMAC_RX_CONFIG);
}

static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,
				  struct stmmac_extra_stats *x, u32 chan)
{
	u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));
	int ret = 0;

	/* ABNORMAL interrupts */
	if (unlikely(intr_status & XGMAC_AIS)) {
		if (unlikely(intr_status & XGMAC_TPS)) {
			x->tx_process_stopped_irq++;
			ret |= tx_hard_error;
		}
		if (unlikely(intr_status & XGMAC_FBE)) {
			x->fatal_bus_error_irq++;
			ret |= tx_hard_error;
		}
	}

	/* TX/RX NORMAL interrupts */
	if (likely(intr_status & XGMAC_NIS)) {
		x->normal_irq_n++;

		if (likely(intr_status & XGMAC_RI)) {
			u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
			if (likely(value & XGMAC_RIE)) {
				x->rx_normal_irq_n++;
				ret |= handle_rx;
			}
		}
		if (likely(intr_status & XGMAC_TI)) {
			x->tx_normal_irq_n++;
			ret |= handle_tx;
		}
	}

	/* Clear interrupts */
	writel(~0x0, ioaddr + XGMAC_DMA_CH_STATUS(chan));

	return ret;
}

static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
				    struct dma_features *dma_cap)
{
	u32 hw_cap;

	/*  MAC HW feature 0 */
	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);
	dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16;
	dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14;
	dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12;
	dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11;
	dma_cap->av &= (hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10;
	dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7;
	dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6;
	dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1;

	/* MAC HW feature 1 */
	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);
	dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18;
	dma_cap->tx_fifo_size =
		128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6);
	dma_cap->rx_fifo_size =
		128 << ((hw_cap & XGMAC_HWFEAT_RXFIFOSIZE) >> 0);

	/* MAC HW feature 2 */
	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
	dma_cap->pps_out_num = (hw_cap & XGMAC_HWFEAT_PPSOUTNUM) >> 24;
	dma_cap->number_tx_channel =
		((hw_cap & XGMAC_HWFEAT_TXCHCNT) >> 18) + 1;
	dma_cap->number_rx_channel =
		((hw_cap & XGMAC_HWFEAT_RXCHCNT) >> 12) + 1;
	dma_cap->number_tx_queues =
		((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1;
	dma_cap->number_rx_queues =
		((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1;
}

static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan)
{
	u32 i;

	for (i = 0; i < nchan; i++)
		writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(i));
}

static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
{
	writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));
}

static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
{
	writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan));
}

static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
{
	writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan));
}

static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
{
	writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan));
}

static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
{
	u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));

	if (en)
		value |= XGMAC_TSE;
	else
		value &= ~XGMAC_TSE;

	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
}

static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
{
	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));

	value &= ~XGMAC_TXQEN;
	if (qmode != MTL_QUEUE_AVB) {
		value |= 0x2 << XGMAC_TXQEN_SHIFT;
		writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel));
	} else {
		value |= 0x1 << XGMAC_TXQEN_SHIFT;
	}

	writel(value, ioaddr +  XGMAC_MTL_TXQ_OPMODE(channel));
}

static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
{
	u32 value;

	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	value |= bfsize << 1;
	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
}

const struct stmmac_dma_ops dwxgmac210_dma_ops = {
	.reset = dwxgmac2_dma_reset,
	.init = dwxgmac2_dma_init,
	.init_chan = dwxgmac2_dma_init_chan,
	.init_rx_chan = dwxgmac2_dma_init_rx_chan,
	.init_tx_chan = dwxgmac2_dma_init_tx_chan,
	.axi = dwxgmac2_dma_axi,
	.dump_regs = NULL,
	.dma_rx_mode = dwxgmac2_dma_rx_mode,
	.dma_tx_mode = dwxgmac2_dma_tx_mode,
	.enable_dma_irq = dwxgmac2_enable_dma_irq,
	.disable_dma_irq = dwxgmac2_disable_dma_irq,
	.start_tx = dwxgmac2_dma_start_tx,
	.stop_tx = dwxgmac2_dma_stop_tx,
	.start_rx = dwxgmac2_dma_start_rx,
	.stop_rx = dwxgmac2_dma_stop_rx,
	.dma_interrupt = dwxgmac2_dma_interrupt,
	.get_hw_feature = dwxgmac2_get_hw_feature,
	.rx_watchdog = dwxgmac2_rx_watchdog,
	.set_rx_ring_len = dwxgmac2_set_rx_ring_len,
	.set_tx_ring_len = dwxgmac2_set_tx_ring_len,
	.set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
	.set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
	.enable_tso = dwxgmac2_enable_tso,
	.qmode = dwxgmac2_qmode,
	.set_bfsize = dwxgmac2_set_bfsize,
};
Commit	Line	Data
d6ddfacd JA	1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	2	/*
	3	* Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
	4	* stmmac XGMAC support.
	5	*/
	6
	7	#include <linux/iopoll.h>
	8	#include "stmmac.h"
	9	#include "dwxgmac2.h"
	10
	11	static int dwxgmac2_dma_reset(void __iomem *ioaddr)
	12	{
	13	u32 value = readl(ioaddr + XGMAC_DMA_MODE);
	14
	15	/* DMA SW reset */
	16	writel(value \| XGMAC_SWR, ioaddr + XGMAC_DMA_MODE);
	17
	18	return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value,
	19	!(value & XGMAC_SWR), 0, 100000);
	20	}
	21
	22	static void dwxgmac2_dma_init(void __iomem *ioaddr,
	23	struct stmmac_dma_cfg *dma_cfg, int atds)
	24	{
	25	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
	26
	27	if (dma_cfg->aal)
	28	value \|= XGMAC_AAL;
	29
	30	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
	31	}
	32
	33	static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,
	34	struct stmmac_dma_cfg *dma_cfg, u32 chan)
	35	{
	36	u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
	37
	38	if (dma_cfg->pblx8)
	39	value \|= XGMAC_PBLx8;
	40
	41	writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
	42	writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
	43	}
	44
	45	static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr,
	46	struct stmmac_dma_cfg *dma_cfg,
	47	u32 dma_rx_phy, u32 chan)
	48	{
	49	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
	50	u32 value;
	51
	52	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	53	value &= ~XGMAC_RxPBL;
	54	value \|= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;
	55	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	56
	57	writel(dma_rx_phy, ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
	58	}
	59
	60	static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr,
	61	struct stmmac_dma_cfg *dma_cfg,
	62	u32 dma_tx_phy, u32 chan)
	63	{
	64	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
65	u32 value;
66
67	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
68	value &= ~XGMAC_TxPBL;
69	value \|= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL;
70	value \|= XGMAC_OSP;
71	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
72
73	writel(dma_tx_phy, ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
74	}
75
76	static void dwxgmac2_dma_axi(void __iomem ioaddr, struct stmmac_axi axi)
77	{
78	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
79	int i;
80
81	if (axi->axi_lpi_en)
82	value \|= XGMAC_EN_LPI;
83	if (axi->axi_xit_frm)
84	value \|= XGMAC_LPI_XIT_PKT;
85
86	value &= ~XGMAC_WR_OSR_LMT;
87	value \|= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) &
88	XGMAC_WR_OSR_LMT;
89
90	value &= ~XGMAC_RD_OSR_LMT;
91	value \|= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) &
92	XGMAC_RD_OSR_LMT;
93
94	value &= ~XGMAC_BLEN;
95	for (i = 0; i < AXI_BLEN; i++) {
96	if (axi->axi_blen[i])
97	value &= ~XGMAC_UNDEF;
98
99	switch (axi->axi_blen[i]) {
100	case 256:
101	value \|= XGMAC_BLEN256;
102	break;
103	case 128:
104	value \|= XGMAC_BLEN128;
105	break;
106	case 64:
107	value \|= XGMAC_BLEN64;
108	break;
109	case 32:
110	value \|= XGMAC_BLEN32;
111	break;
112	case 16:
113	value \|= XGMAC_BLEN16;
114	break;
115	case 8:
116	value \|= XGMAC_BLEN8;
117	break;
118	case 4:
119	value \|= XGMAC_BLEN4;
120	break;
121	}
122	}
123
124	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
125	}
126
127	static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,
128	u32 channel, int fifosz, u8 qmode)
129	{
130	u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
131	unsigned int rqs = fifosz / 256 - 1;
132
133	if (mode == SF_DMA_MODE) {
134	value \|= XGMAC_RSF;
135	} else {
136	value &= ~XGMAC_RSF;
137	value &= ~XGMAC_RTC;
138
139	if (mode <= 64)
140	value \|= 0x0 << XGMAC_RTC_SHIFT;
141	else if (mode <= 96)
142	value \|= 0x2 << XGMAC_RTC_SHIFT;
143	else
144	value \|= 0x3 << XGMAC_RTC_SHIFT;
145	}
146
147	value &= ~XGMAC_RQS;
148	value \|= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS;
149
150	writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
151
152	/* Enable MTL RX overflow */
153	value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));
154	writel(value \| XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel));
155	}
156
157	static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode,
158	u32 channel, int fifosz, u8 qmode)
159	{
160	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
161	unsigned int tqs = fifosz / 256 - 1;
162
163	if (mode == SF_DMA_MODE) {
164	value \|= XGMAC_TSF;
165	} else {
166	value &= ~XGMAC_TSF;
167	value &= ~XGMAC_TTC;
168
169	if (mode <= 64)
170	value \|= 0x0 << XGMAC_TTC_SHIFT;
171	else if (mode <= 96)
172	value \|= 0x2 << XGMAC_TTC_SHIFT;
173	else if (mode <= 128)
174	value \|= 0x3 << XGMAC_TTC_SHIFT;
175	else if (mode <= 192)
176	value \|= 0x4 << XGMAC_TTC_SHIFT;
177	else if (mode <= 256)
178	value \|= 0x5 << XGMAC_TTC_SHIFT;
179	else if (mode <= 384)
180	value \|= 0x6 << XGMAC_TTC_SHIFT;
181	else
182	value \|= 0x7 << XGMAC_TTC_SHIFT;
183	}
184
ec6ea8e3 JA	185	/* Use static TC to Queue mapping */
	186	value \|= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP;
	187
d6ddfacd JA	188	value &= ~XGMAC_TXQEN;
	189	if (qmode != MTL_QUEUE_AVB)
	190	value \|= 0x2 << XGMAC_TXQEN_SHIFT;
	191	else
	192	value \|= 0x1 << XGMAC_TXQEN_SHIFT;
	193
	194	value &= ~XGMAC_TQS;
	195	value \|= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS;
	196
	197	writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
	198	}
	199
	200	static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan)
	201	{
	202	writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
	203	}
	204
	205	static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan)
	206	{
	207	writel(0, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
	208	}
	209
	210	static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan)
	211	{
	212	u32 value;
	213
	214	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	215	value \|= XGMAC_TXST;
	216	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	217
	218	value = readl(ioaddr + XGMAC_TX_CONFIG);
	219	value \|= XGMAC_CONFIG_TE;
	220	writel(value, ioaddr + XGMAC_TX_CONFIG);
	221	}
	222
	223	static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan)
	224	{
	225	u32 value;
	226
	227	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	228	value &= ~XGMAC_TXST;
	229	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	230
	231	value = readl(ioaddr + XGMAC_TX_CONFIG);
	232	value &= ~XGMAC_CONFIG_TE;
	233	writel(value, ioaddr + XGMAC_TX_CONFIG);
	234	}
	235
	236	static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan)
	237	{
	238	u32 value;
	239
	240	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	241	value \|= XGMAC_RXST;
	242	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	243
	244	value = readl(ioaddr + XGMAC_RX_CONFIG);
	245	value \|= XGMAC_CONFIG_RE;
	246	writel(value, ioaddr + XGMAC_RX_CONFIG);
	247	}
	248
	249	static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan)
	250	{
	251	u32 value;
252
253	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
254	value &= ~XGMAC_RXST;
255	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
256
257	value = readl(ioaddr + XGMAC_RX_CONFIG);
258	value &= ~XGMAC_CONFIG_RE;
259	writel(value, ioaddr + XGMAC_RX_CONFIG);
260	}
261
262	static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,
263	struct stmmac_extra_stats *x, u32 chan)
264	{
265	u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));
266	int ret = 0;
267
268	/* ABNORMAL interrupts */
269	if (unlikely(intr_status & XGMAC_AIS)) {
270	if (unlikely(intr_status & XGMAC_TPS)) {
271	x->tx_process_stopped_irq++;
272	ret \|= tx_hard_error;
273	}
274	if (unlikely(intr_status & XGMAC_FBE)) {
275	x->fatal_bus_error_irq++;
276	ret \|= tx_hard_error;
277	}
278	}
279
280	/* TX/RX NORMAL interrupts */
281	if (likely(intr_status & XGMAC_NIS)) {
282	x->normal_irq_n++;
283
284	if (likely(intr_status & XGMAC_RI)) {
285	u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
286	if (likely(value & XGMAC_RIE)) {
287	x->rx_normal_irq_n++;
288	ret \|= handle_rx;
289	}
290	}
291	if (likely(intr_status & XGMAC_TI)) {
292	x->tx_normal_irq_n++;
293	ret \|= handle_tx;
294	}
295	}
296
297	/* Clear interrupts */
298	writel(~0x0, ioaddr + XGMAC_DMA_CH_STATUS(chan));
299
300	return ret;
301	}
302
303	static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
304	struct dma_features *dma_cap)
305	{
306	u32 hw_cap;
307
308	/* MAC HW feature 0 */
309	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);
310	dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16;
311	dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14;
312	dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12;
313	dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11;
314	dma_cap->av &= (hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10;
315	dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7;
316	dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6;
317	dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1;
318
319	/* MAC HW feature 1 */
320	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);
321	dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18;
322	dma_cap->tx_fifo_size =
323	128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6);
324	dma_cap->rx_fifo_size =
325	128 << ((hw_cap & XGMAC_HWFEAT_RXFIFOSIZE) >> 0);
326
327	/* MAC HW feature 2 */
328	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
329	dma_cap->pps_out_num = (hw_cap & XGMAC_HWFEAT_PPSOUTNUM) >> 24;
330	dma_cap->number_tx_channel =
331	((hw_cap & XGMAC_HWFEAT_TXCHCNT) >> 18) + 1;
332	dma_cap->number_rx_channel =
333	((hw_cap & XGMAC_HWFEAT_RXCHCNT) >> 12) + 1;
334	dma_cap->number_tx_queues =
335	((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1;
336	dma_cap->number_rx_queues =
337	((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1;
338	}
339
340	static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan)
341	{
342	u32 i;
343
344	for (i = 0; i < nchan; i++)
345	writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(i));
346	}
347
348	static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
349	{
350	writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));
351	}
352
353	static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
354	{
355	writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan));
356	}
357
358	static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
359	{
360	writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan));
361	}
362
363	static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
364	{
365	writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan));
366	}
367
368	static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
369	{
370	u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
371
372	if (en)
373	value \|= XGMAC_TSE;
374	else
375	value &= ~XGMAC_TSE;
376
377	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
378	}
379
ec6ea8e3 JA	380	static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
	381	{
	382	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
	383
	384	value &= ~XGMAC_TXQEN;
	385	if (qmode != MTL_QUEUE_AVB) {
	386	value \|= 0x2 << XGMAC_TXQEN_SHIFT;
	387	writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel));
	388	} else {
	389	value \|= 0x1 << XGMAC_TXQEN_SHIFT;
	390	}
	391
	392	writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
	393	}
	394
d6ddfacd JA	395	static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
	396	{
	397	u32 value;
	398
	399	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	400	value \|= bfsize << 1;
	401	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	402	}
	403
	404	const struct stmmac_dma_ops dwxgmac210_dma_ops = {
	405	.reset = dwxgmac2_dma_reset,
	406	.init = dwxgmac2_dma_init,
	407	.init_chan = dwxgmac2_dma_init_chan,
	408	.init_rx_chan = dwxgmac2_dma_init_rx_chan,
	409	.init_tx_chan = dwxgmac2_dma_init_tx_chan,
	410	.axi = dwxgmac2_dma_axi,
	411	.dump_regs = NULL,
	412	.dma_rx_mode = dwxgmac2_dma_rx_mode,
	413	.dma_tx_mode = dwxgmac2_dma_tx_mode,
	414	.enable_dma_irq = dwxgmac2_enable_dma_irq,
	415	.disable_dma_irq = dwxgmac2_disable_dma_irq,
	416	.start_tx = dwxgmac2_dma_start_tx,
	417	.stop_tx = dwxgmac2_dma_stop_tx,
	418	.start_rx = dwxgmac2_dma_start_rx,
	419	.stop_rx = dwxgmac2_dma_stop_rx,
	420	.dma_interrupt = dwxgmac2_dma_interrupt,
	421	.get_hw_feature = dwxgmac2_get_hw_feature,
	422	.rx_watchdog = dwxgmac2_rx_watchdog,
	423	.set_rx_ring_len = dwxgmac2_set_rx_ring_len,
	424	.set_tx_ring_len = dwxgmac2_set_tx_ring_len,
	425	.set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
	426	.set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
	427	.enable_tso = dwxgmac2_enable_tso,
ec6ea8e3	428	.qmode = dwxgmac2_qmode,
d6ddfacd JA	429	.set_bfsize = dwxgmac2_set_bfsize,
d6ddfacd JA	430	};