[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / dwxgmac2_dma.c

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
 * stmmac XGMAC support.
 */

#include <linux/iopoll.h>
#include "stmmac.h"
#include "dwxgmac2.h"

static int dwxgmac2_dma_reset(void __iomem *ioaddr)
{
	u32 value = readl(ioaddr + XGMAC_DMA_MODE);

	/* DMA SW reset */
	writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE);

	return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value,
				  !(value & XGMAC_SWR), 0, 100000);
}

static void dwxgmac2_dma_init(void __iomem *ioaddr,
			      struct stmmac_dma_cfg *dma_cfg, int atds)
{
	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);

	if (dma_cfg->aal)
		value |= XGMAC_AAL;

	writel(value | XGMAC_EAME, ioaddr + XGMAC_DMA_SYSBUS_MODE);
}

static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,
				   struct stmmac_dma_cfg *dma_cfg, u32 chan)
{
	u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));

	if (dma_cfg->pblx8)
		value |= XGMAC_PBLx8;

	writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
	writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
}

static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr,
				      struct stmmac_dma_cfg *dma_cfg,
				      dma_addr_t phy, u32 chan)
{
	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
	u32 value;

	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	value &= ~XGMAC_RxPBL;
	value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;
	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));

	writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan));
	writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
}

static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr,
				      struct stmmac_dma_cfg *dma_cfg,
				      dma_addr_t phy, u32 chan)
{
	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
	u32 value;

	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	value &= ~XGMAC_TxPBL;
	value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL;
	value |= XGMAC_OSP;
	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));

	writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan));
	writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
}

static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
{
	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
	int i;

	if (axi->axi_lpi_en)
		value |= XGMAC_EN_LPI;
	if (axi->axi_xit_frm)
		value |= XGMAC_LPI_XIT_PKT;

	value &= ~XGMAC_WR_OSR_LMT;
	value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) &
		XGMAC_WR_OSR_LMT;

	value &= ~XGMAC_RD_OSR_LMT;
	value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) &
		XGMAC_RD_OSR_LMT;

	if (!axi->axi_fb)
		value |= XGMAC_UNDEF;

	value &= ~XGMAC_BLEN;
	for (i = 0; i < AXI_BLEN; i++) {
		switch (axi->axi_blen[i]) {
		case 256:
			value |= XGMAC_BLEN256;
			break;
		case 128:
			value |= XGMAC_BLEN128;
			break;
		case 64:
			value |= XGMAC_BLEN64;
			break;
		case 32:
			value |= XGMAC_BLEN32;
			break;
		case 16:
			value |= XGMAC_BLEN16;
			break;
		case 8:
			value |= XGMAC_BLEN8;
			break;
		case 4:
			value |= XGMAC_BLEN4;
			break;
		}
	}

	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
	writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL);
	writel(XGMAC_RDPS, ioaddr + XGMAC_RX_EDMA_CTRL);
}

static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,
				 u32 channel, int fifosz, u8 qmode)
{
	u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
	unsigned int rqs = fifosz / 256 - 1;

	if (mode == SF_DMA_MODE) {
		value |= XGMAC_RSF;
	} else {
		value &= ~XGMAC_RSF;
		value &= ~XGMAC_RTC;

		if (mode <= 64)
			value |= 0x0 << XGMAC_RTC_SHIFT;
		else if (mode <= 96)
			value |= 0x2 << XGMAC_RTC_SHIFT;
		else
			value |= 0x3 << XGMAC_RTC_SHIFT;
	}

	value &= ~XGMAC_RQS;
	value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS;

	if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
		u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
		unsigned int rfd, rfa;

		value |= XGMAC_EHFC;

		/* Set Threshold for Activating Flow Control to min 2 frames,
		 * i.e. 1500 * 2 = 3000 bytes.
		 *
		 * Set Threshold for Deactivating Flow Control to min 1 frame,
		 * i.e. 1500 bytes.
		 */
		switch (fifosz) {
		case 4096:
			/* This violates the above formula because of FIFO size
			 * limit therefore overflow may occur in spite of this.
			 */
			rfd = 0x03; /* Full-2.5K */
			rfa = 0x01; /* Full-1.5K */
			break;

		case 8192:
			rfd = 0x06; /* Full-4K */
			rfa = 0x0a; /* Full-6K */
			break;

		case 16384:
			rfd = 0x06; /* Full-4K */
			rfa = 0x12; /* Full-10K */
			break;

		default:
			rfd = 0x06; /* Full-4K */
			rfa = 0x1e; /* Full-16K */
			break;
		}

		flow &= ~XGMAC_RFD;
		flow |= rfd << XGMAC_RFD_SHIFT;

		flow &= ~XGMAC_RFA;
		flow |= rfa << XGMAC_RFA_SHIFT;

		writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
	}

	writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));

	/* Enable MTL RX overflow */
	value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));
	writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel));
}

static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode,
				 u32 channel, int fifosz, u8 qmode)
{
	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
	unsigned int tqs = fifosz / 256 - 1;

	if (mode == SF_DMA_MODE) {
		value |= XGMAC_TSF;
	} else {
		value &= ~XGMAC_TSF;
		value &= ~XGMAC_TTC;

		if (mode <= 64)
			value |= 0x0 << XGMAC_TTC_SHIFT;
		else if (mode <= 96)
			value |= 0x2 << XGMAC_TTC_SHIFT;
		else if (mode <= 128)
			value |= 0x3 << XGMAC_TTC_SHIFT;
		else if (mode <= 192)
			value |= 0x4 << XGMAC_TTC_SHIFT;
		else if (mode <= 256)
			value |= 0x5 << XGMAC_TTC_SHIFT;
		else if (mode <= 384)
			value |= 0x6 << XGMAC_TTC_SHIFT;
		else
			value |= 0x7 << XGMAC_TTC_SHIFT;
	}

	/* Use static TC to Queue mapping */
	value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP;

	value &= ~XGMAC_TXQEN;
	if (qmode != MTL_QUEUE_AVB)
		value |= 0x2 << XGMAC_TXQEN_SHIFT;
	else
		value |= 0x1 << XGMAC_TXQEN_SHIFT;

	value &= ~XGMAC_TQS;
	value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS;

	writel(value, ioaddr +  XGMAC_MTL_TXQ_OPMODE(channel));
}

static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan)
{
	writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
}

static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan)
{
	writel(0, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
}

static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan)
{
	u32 value;

	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	value |= XGMAC_TXST;
	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));

	value = readl(ioaddr + XGMAC_TX_CONFIG);
	value |= XGMAC_CONFIG_TE;
	writel(value, ioaddr + XGMAC_TX_CONFIG);
}

static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan)
{
	u32 value;

	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	value &= ~XGMAC_TXST;
	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));

	value = readl(ioaddr + XGMAC_TX_CONFIG);
	value &= ~XGMAC_CONFIG_TE;
	writel(value, ioaddr + XGMAC_TX_CONFIG);
}

static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan)
{
	u32 value;

	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	value |= XGMAC_RXST;
	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));

	value = readl(ioaddr + XGMAC_RX_CONFIG);
	value |= XGMAC_CONFIG_RE;
	writel(value, ioaddr + XGMAC_RX_CONFIG);
}

static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan)
{
	u32 value;

	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	value &= ~XGMAC_RXST;
	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
}

static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,
				  struct stmmac_extra_stats *x, u32 chan)
{
	u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));
	u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
	int ret = 0;

	/* ABNORMAL interrupts */
	if (unlikely(intr_status & XGMAC_AIS)) {
		if (unlikely(intr_status & XGMAC_TPS)) {
			x->tx_process_stopped_irq++;
			ret |= tx_hard_error;
		}
		if (unlikely(intr_status & XGMAC_FBE)) {
			x->fatal_bus_error_irq++;
			ret |= tx_hard_error;
		}
	}

	/* TX/RX NORMAL interrupts */
	if (likely(intr_status & XGMAC_NIS)) {
		x->normal_irq_n++;

		if (likely(intr_status & XGMAC_RI)) {
			x->rx_normal_irq_n++;
			ret |= handle_rx;
		}
		if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) {
			x->tx_normal_irq_n++;
			ret |= handle_tx;
		}
	}

	/* Clear interrupts */
	writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan));

	return ret;
}

static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
				    struct dma_features *dma_cap)
{
	u32 hw_cap;

	/*  MAC HW feature 0 */
	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);
	dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16;
	dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14;
	dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12;
	dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11;
	dma_cap->av &= (hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10;
	dma_cap->rmon = (hw_cap & XGMAC_HWFEAT_MMCSEL) >> 8;
	dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7;
	dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6;
	dma_cap->vlhash = (hw_cap & XGMAC_HWFEAT_VLHASH) >> 4;
	dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1;

	/* MAC HW feature 1 */
	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);
	dma_cap->rssen = (hw_cap & XGMAC_HWFEAT_RSSEN) >> 20;
	dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18;

	dma_cap->addr64 = (hw_cap & XGMAC_HWFEAT_ADDR64) >> 14;
	switch (dma_cap->addr64) {
	case 0:
		dma_cap->addr64 = 32;
		break;
	case 1:
		dma_cap->addr64 = 40;
		break;
	case 2:
		dma_cap->addr64 = 48;
		break;
	default:
		dma_cap->addr64 = 32;
		break;
	}

	dma_cap->tx_fifo_size =
		128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6);
	dma_cap->rx_fifo_size =
		128 << ((hw_cap & XGMAC_HWFEAT_RXFIFOSIZE) >> 0);

	/* MAC HW feature 2 */
	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
	dma_cap->pps_out_num = (hw_cap & XGMAC_HWFEAT_PPSOUTNUM) >> 24;
	dma_cap->number_tx_channel =
		((hw_cap & XGMAC_HWFEAT_TXCHCNT) >> 18) + 1;
	dma_cap->number_rx_channel =
		((hw_cap & XGMAC_HWFEAT_RXCHCNT) >> 12) + 1;
	dma_cap->number_tx_queues =
		((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1;
	dma_cap->number_rx_queues =
		((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1;

	/* MAC HW feature 3 */
	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3);
	dma_cap->asp = (hw_cap & XGMAC_HWFEAT_ASP) >> 14;
}

static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan)
{
	u32 i;

	for (i = 0; i < nchan; i++)
		writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(i));
}

static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
{
	writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));
}

static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
{
	writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan));
}

static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
{
	writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan));
}

static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
{
	writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan));
}

static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
{
	u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));

	if (en)
		value |= XGMAC_TSE;
	else
		value &= ~XGMAC_TSE;

	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
}

static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
{
	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));

	value &= ~XGMAC_TXQEN;
	if (qmode != MTL_QUEUE_AVB) {
		value |= 0x2 << XGMAC_TXQEN_SHIFT;
		writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel));
	} else {
		value |= 0x1 << XGMAC_TXQEN_SHIFT;
	}

	writel(value, ioaddr +  XGMAC_MTL_TXQ_OPMODE(channel));
}

static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
{
	u32 value;

	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	value |= bfsize << 1;
	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
}

const struct stmmac_dma_ops dwxgmac210_dma_ops = {
	.reset = dwxgmac2_dma_reset,
	.init = dwxgmac2_dma_init,
	.init_chan = dwxgmac2_dma_init_chan,
	.init_rx_chan = dwxgmac2_dma_init_rx_chan,
	.init_tx_chan = dwxgmac2_dma_init_tx_chan,
	.axi = dwxgmac2_dma_axi,
	.dump_regs = NULL,
	.dma_rx_mode = dwxgmac2_dma_rx_mode,
	.dma_tx_mode = dwxgmac2_dma_tx_mode,
	.enable_dma_irq = dwxgmac2_enable_dma_irq,
	.disable_dma_irq = dwxgmac2_disable_dma_irq,
	.start_tx = dwxgmac2_dma_start_tx,
	.stop_tx = dwxgmac2_dma_stop_tx,
	.start_rx = dwxgmac2_dma_start_rx,
	.stop_rx = dwxgmac2_dma_stop_rx,
	.dma_interrupt = dwxgmac2_dma_interrupt,
	.get_hw_feature = dwxgmac2_get_hw_feature,
	.rx_watchdog = dwxgmac2_rx_watchdog,
	.set_rx_ring_len = dwxgmac2_set_rx_ring_len,
	.set_tx_ring_len = dwxgmac2_set_tx_ring_len,
	.set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
	.set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
	.enable_tso = dwxgmac2_enable_tso,
	.qmode = dwxgmac2_qmode,
	.set_bfsize = dwxgmac2_set_bfsize,
};
Commit	Line	Data
d6ddfacd JA	1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
	2	/*
	3	* Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
	4	* stmmac XGMAC support.
	5	*/
	6
	7	#include <linux/iopoll.h>
	8	#include "stmmac.h"
	9	#include "dwxgmac2.h"
	10
	11	static int dwxgmac2_dma_reset(void __iomem *ioaddr)
	12	{
	13	u32 value = readl(ioaddr + XGMAC_DMA_MODE);
	14
	15	/* DMA SW reset */
	16	writel(value \| XGMAC_SWR, ioaddr + XGMAC_DMA_MODE);
	17
	18	return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value,
	19	!(value & XGMAC_SWR), 0, 100000);
	20	}
	21
	22	static void dwxgmac2_dma_init(void __iomem *ioaddr,
	23	struct stmmac_dma_cfg *dma_cfg, int atds)
	24	{
	25	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
	26
	27	if (dma_cfg->aal)
	28	value \|= XGMAC_AAL;
	29
a993db88	30	writel(value \| XGMAC_EAME, ioaddr + XGMAC_DMA_SYSBUS_MODE);
d6ddfacd JA	31	}
	32
	33	static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,
	34	struct stmmac_dma_cfg *dma_cfg, u32 chan)
	35	{
	36	u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
	37
	38	if (dma_cfg->pblx8)
	39	value \|= XGMAC_PBLx8;
	40
	41	writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
	42	writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
	43	}
	44
	45	static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr,
	46	struct stmmac_dma_cfg *dma_cfg,
06a80a7d	47	dma_addr_t phy, u32 chan)
d6ddfacd JA	48	{
	49	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
	50	u32 value;
	51
	52	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	53	value &= ~XGMAC_RxPBL;
	54	value \|= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;
	55	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	56
06a80a7d JA	57	writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan));
06a80a7d JA	58	writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
d6ddfacd JA	59	}
	60
	61	static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr,
	62	struct stmmac_dma_cfg *dma_cfg,
06a80a7d	63	dma_addr_t phy, u32 chan)
d6ddfacd JA	64	{
	65	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
	66	u32 value;
	67
	68	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	69	value &= ~XGMAC_TxPBL;
	70	value \|= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL;
	71	value \|= XGMAC_OSP;
	72	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	73
06a80a7d JA	74	writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan));
06a80a7d JA	75	writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
d6ddfacd JA	76	}
	77
	78	static void dwxgmac2_dma_axi(void __iomem ioaddr, struct stmmac_axi axi)
	79	{
	80	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
	81	int i;
	82
	83	if (axi->axi_lpi_en)
	84	value \|= XGMAC_EN_LPI;
	85	if (axi->axi_xit_frm)
	86	value \|= XGMAC_LPI_XIT_PKT;
	87
	88	value &= ~XGMAC_WR_OSR_LMT;
	89	value \|= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) &
	90	XGMAC_WR_OSR_LMT;
	91
	92	value &= ~XGMAC_RD_OSR_LMT;
	93	value \|= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) &
	94	XGMAC_RD_OSR_LMT;
	95
900a81cc JA	96	if (!axi->axi_fb)
	97	value \|= XGMAC_UNDEF;
	98
d6ddfacd JA	99	value &= ~XGMAC_BLEN;
d6ddfacd JA	100	for (i = 0; i < AXI_BLEN; i++) {
d6ddfacd JA	101	switch (axi->axi_blen[i]) {
	102	case 256:
	103	value \|= XGMAC_BLEN256;
	104	break;
	105	case 128:
	106	value \|= XGMAC_BLEN128;
	107	break;
	108	case 64:
	109	value \|= XGMAC_BLEN64;
	110	break;
	111	case 32:
	112	value \|= XGMAC_BLEN32;
	113	break;
	114	case 16:
	115	value \|= XGMAC_BLEN16;
	116	break;
	117	case 8:
	118	value \|= XGMAC_BLEN8;
	119	break;
	120	case 4:
	121	value \|= XGMAC_BLEN4;
	122	break;
	123	}
	124	}
	125
	126	writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
8fe82bd4 JA	127	writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL);
8fe82bd4 JA	128	writel(XGMAC_RDPS, ioaddr + XGMAC_RX_EDMA_CTRL);
d6ddfacd JA	129	}
	130
	131	static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,
	132	u32 channel, int fifosz, u8 qmode)
	133	{
	134	u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
	135	unsigned int rqs = fifosz / 256 - 1;
	136
	137	if (mode == SF_DMA_MODE) {
	138	value \|= XGMAC_RSF;
	139	} else {
	140	value &= ~XGMAC_RSF;
	141	value &= ~XGMAC_RTC;
	142
	143	if (mode <= 64)
	144	value \|= 0x0 << XGMAC_RTC_SHIFT;
	145	else if (mode <= 96)
	146	value \|= 0x2 << XGMAC_RTC_SHIFT;
	147	else
	148	value \|= 0x3 << XGMAC_RTC_SHIFT;
	149	}
	150
	151	value &= ~XGMAC_RQS;
	152	value \|= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS;
	153
ff82cfc7 JA	154	if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
	155	u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
	156	unsigned int rfd, rfa;
	157
	158	value \|= XGMAC_EHFC;
	159
	160	/* Set Threshold for Activating Flow Control to min 2 frames,
	161	* i.e. 1500 * 2 = 3000 bytes.
	162	*
	163	* Set Threshold for Deactivating Flow Control to min 1 frame,
	164	* i.e. 1500 bytes.
	165	*/
	166	switch (fifosz) {
	167	case 4096:
	168	/* This violates the above formula because of FIFO size
	169	* limit therefore overflow may occur in spite of this.
	170	*/
	171	rfd = 0x03; /* Full-2.5K */
	172	rfa = 0x01; /* Full-1.5K */
	173	break;
	174
	175	case 8192:
	176	rfd = 0x06; /* Full-4K */
	177	rfa = 0x0a; /* Full-6K */
	178	break;
	179
	180	case 16384:
	181	rfd = 0x06; /* Full-4K */
	182	rfa = 0x12; /* Full-10K */
	183	break;
	184
	185	default:
	186	rfd = 0x06; /* Full-4K */
	187	rfa = 0x1e; /* Full-16K */
	188	break;
	189	}
	190
	191	flow &= ~XGMAC_RFD;
	192	flow \|= rfd << XGMAC_RFD_SHIFT;
	193
	194	flow &= ~XGMAC_RFA;
	195	flow \|= rfa << XGMAC_RFA_SHIFT;
	196
	197	writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
	198	}
	199
d6ddfacd JA	200	writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
	201
	202	/* Enable MTL RX overflow */
	203	value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));
	204	writel(value \| XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel));
	205	}
	206
	207	static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode,
	208	u32 channel, int fifosz, u8 qmode)
	209	{
	210	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
	211	unsigned int tqs = fifosz / 256 - 1;
	212
	213	if (mode == SF_DMA_MODE) {
	214	value \|= XGMAC_TSF;
	215	} else {
	216	value &= ~XGMAC_TSF;
	217	value &= ~XGMAC_TTC;
	218
	219	if (mode <= 64)
	220	value \|= 0x0 << XGMAC_TTC_SHIFT;
	221	else if (mode <= 96)
	222	value \|= 0x2 << XGMAC_TTC_SHIFT;
	223	else if (mode <= 128)
	224	value \|= 0x3 << XGMAC_TTC_SHIFT;
	225	else if (mode <= 192)
	226	value \|= 0x4 << XGMAC_TTC_SHIFT;
	227	else if (mode <= 256)
	228	value \|= 0x5 << XGMAC_TTC_SHIFT;
	229	else if (mode <= 384)
	230	value \|= 0x6 << XGMAC_TTC_SHIFT;
	231	else
	232	value \|= 0x7 << XGMAC_TTC_SHIFT;
	233	}
	234
ec6ea8e3 JA	235	/* Use static TC to Queue mapping */
	236	value \|= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP;
	237
d6ddfacd JA	238	value &= ~XGMAC_TXQEN;
	239	if (qmode != MTL_QUEUE_AVB)
	240	value \|= 0x2 << XGMAC_TXQEN_SHIFT;
	241	else
	242	value \|= 0x1 << XGMAC_TXQEN_SHIFT;
	243
	244	value &= ~XGMAC_TQS;
	245	value \|= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS;
	246
	247	writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
	248	}
	249
	250	static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan)
	251	{
	252	writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
	253	}
	254
	255	static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan)
	256	{
	257	writel(0, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
	258	}
	259
	260	static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan)
	261	{
	262	u32 value;
	263
	264	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	265	value \|= XGMAC_TXST;
	266	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	267
	268	value = readl(ioaddr + XGMAC_TX_CONFIG);
	269	value \|= XGMAC_CONFIG_TE;
	270	writel(value, ioaddr + XGMAC_TX_CONFIG);
	271	}
	272
	273	static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan)
	274	{
	275	u32 value;
	276
	277	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	278	value &= ~XGMAC_TXST;
	279	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	280
	281	value = readl(ioaddr + XGMAC_TX_CONFIG);
	282	value &= ~XGMAC_CONFIG_TE;
	283	writel(value, ioaddr + XGMAC_TX_CONFIG);
	284	}
	285
	286	static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan)
	287	{
	288	u32 value;
	289
	290	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	291	value \|= XGMAC_RXST;
	292	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	293
	294	value = readl(ioaddr + XGMAC_RX_CONFIG);
	295	value \|= XGMAC_CONFIG_RE;
	296	writel(value, ioaddr + XGMAC_RX_CONFIG);
	297	}
	298
	299	static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan)
	300	{
	301	u32 value;
302
303	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
304	value &= ~XGMAC_RXST;
305	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
d6ddfacd JA	306	}
	307
	308	static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,
	309	struct stmmac_extra_stats *x, u32 chan)
	310	{
	311	u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));
fcc509eb	312	u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
d6ddfacd JA	313	int ret = 0;
	314
	315	/* ABNORMAL interrupts */
	316	if (unlikely(intr_status & XGMAC_AIS)) {
	317	if (unlikely(intr_status & XGMAC_TPS)) {
	318	x->tx_process_stopped_irq++;
	319	ret \|= tx_hard_error;
	320	}
	321	if (unlikely(intr_status & XGMAC_FBE)) {
	322	x->fatal_bus_error_irq++;
	323	ret \|= tx_hard_error;
	324	}
	325	}
	326
	327	/* TX/RX NORMAL interrupts */
	328	if (likely(intr_status & XGMAC_NIS)) {
	329	x->normal_irq_n++;
	330
	331	if (likely(intr_status & XGMAC_RI)) {
ae9f346d JA	332	x->rx_normal_irq_n++;
ae9f346d JA	333	ret \|= handle_rx;
d6ddfacd	334	}
ae9f346d	335	if (likely(intr_status & (XGMAC_TI \| XGMAC_TBU))) {
d6ddfacd JA	336	x->tx_normal_irq_n++;
	337	ret \|= handle_tx;
	338	}
	339	}
	340
	341	/* Clear interrupts */
fcc509eb	342	writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan));
d6ddfacd JA	343
	344	return ret;
	345	}
	346
	347	static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
	348	struct dma_features *dma_cap)
	349	{
	350	u32 hw_cap;
	351
	352	/* MAC HW feature 0 */
	353	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);
	354	dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16;
	355	dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14;
	356	dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12;
	357	dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11;
	358	dma_cap->av &= (hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10;
b6cdf09f	359	dma_cap->rmon = (hw_cap & XGMAC_HWFEAT_MMCSEL) >> 8;
d6ddfacd JA	360	dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7;
d6ddfacd JA	361	dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6;
3cd1cfcb	362	dma_cap->vlhash = (hw_cap & XGMAC_HWFEAT_VLHASH) >> 4;
d6ddfacd JA	363	dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1;
	364
	365	/* MAC HW feature 1 */
	366	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);
76067459	367	dma_cap->rssen = (hw_cap & XGMAC_HWFEAT_RSSEN) >> 20;
d6ddfacd	368	dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18;
a993db88 JA	369
	370	dma_cap->addr64 = (hw_cap & XGMAC_HWFEAT_ADDR64) >> 14;
	371	switch (dma_cap->addr64) {
	372	case 0:
	373	dma_cap->addr64 = 32;
	374	break;
	375	case 1:
	376	dma_cap->addr64 = 40;
	377	break;
	378	case 2:
	379	dma_cap->addr64 = 48;
	380	break;
	381	default:
	382	dma_cap->addr64 = 32;
	383	break;
	384	}
	385
d6ddfacd JA	386	dma_cap->tx_fifo_size =
	387	128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6);
	388	dma_cap->rx_fifo_size =
	389	128 << ((hw_cap & XGMAC_HWFEAT_RXFIFOSIZE) >> 0);
	390
	391	/* MAC HW feature 2 */
	392	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
	393	dma_cap->pps_out_num = (hw_cap & XGMAC_HWFEAT_PPSOUTNUM) >> 24;
	394	dma_cap->number_tx_channel =
	395	((hw_cap & XGMAC_HWFEAT_TXCHCNT) >> 18) + 1;
	396	dma_cap->number_rx_channel =
	397	((hw_cap & XGMAC_HWFEAT_RXCHCNT) >> 12) + 1;
	398	dma_cap->number_tx_queues =
	399	((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1;
	400	dma_cap->number_rx_queues =
	401	((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1;
56e58d6c JA	402
	403	/* MAC HW feature 3 */
	404	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3);
	405	dma_cap->asp = (hw_cap & XGMAC_HWFEAT_ASP) >> 14;
d6ddfacd JA	406	}
	407
	408	static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan)
	409	{
	410	u32 i;
	411
	412	for (i = 0; i < nchan; i++)
	413	writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(i));
	414	}
	415
	416	static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
	417	{
	418	writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));
	419	}
	420
	421	static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
	422	{
	423	writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan));
	424	}
	425
	426	static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
	427	{
	428	writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan));
	429	}
	430
	431	static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
	432	{
	433	writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan));
	434	}
	435
	436	static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
	437	{
	438	u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	439
	440	if (en)
	441	value \|= XGMAC_TSE;
	442	else
	443	value &= ~XGMAC_TSE;
	444
	445	writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
	446	}
	447
ec6ea8e3 JA	448	static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
	449	{
	450	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
	451
	452	value &= ~XGMAC_TXQEN;
	453	if (qmode != MTL_QUEUE_AVB) {
	454	value \|= 0x2 << XGMAC_TXQEN_SHIFT;
	455	writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel));
	456	} else {
	457	value \|= 0x1 << XGMAC_TXQEN_SHIFT;
	458	}
	459
	460	writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
	461	}
	462
d6ddfacd JA	463	static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
	464	{
	465	u32 value;
	466
	467	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	468	value \|= bfsize << 1;
	469	writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
	470	}
	471
	472	const struct stmmac_dma_ops dwxgmac210_dma_ops = {
	473	.reset = dwxgmac2_dma_reset,
	474	.init = dwxgmac2_dma_init,
	475	.init_chan = dwxgmac2_dma_init_chan,
	476	.init_rx_chan = dwxgmac2_dma_init_rx_chan,
	477	.init_tx_chan = dwxgmac2_dma_init_tx_chan,
	478	.axi = dwxgmac2_dma_axi,
	479	.dump_regs = NULL,
	480	.dma_rx_mode = dwxgmac2_dma_rx_mode,
	481	.dma_tx_mode = dwxgmac2_dma_tx_mode,
	482	.enable_dma_irq = dwxgmac2_enable_dma_irq,
	483	.disable_dma_irq = dwxgmac2_disable_dma_irq,
	484	.start_tx = dwxgmac2_dma_start_tx,
	485	.stop_tx = dwxgmac2_dma_stop_tx,
	486	.start_rx = dwxgmac2_dma_start_rx,
	487	.stop_rx = dwxgmac2_dma_stop_rx,
	488	.dma_interrupt = dwxgmac2_dma_interrupt,
	489	.get_hw_feature = dwxgmac2_get_hw_feature,
	490	.rx_watchdog = dwxgmac2_rx_watchdog,
	491	.set_rx_ring_len = dwxgmac2_set_rx_ring_len,
	492	.set_tx_ring_len = dwxgmac2_set_tx_ring_len,
	493	.set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
	494	.set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
	495	.enable_tso = dwxgmac2_enable_tso,
ec6ea8e3	496	.qmode = dwxgmac2_qmode,
d6ddfacd JA	497	.set_bfsize = dwxgmac2_set_bfsize,
d6ddfacd JA	498	};