[linux-block.git] / drivers / net / ethernet / stmicro / stmmac / dwmac4_lib.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2007-2015  STMicroelectronics Ltd
 *
 * Author: Alexandre Torgue <alexandre.torgue@st.com>
 */

#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/delay.h>
#include "common.h"
#include "dwmac4_dma.h"
#include "dwmac4.h"
#include "stmmac.h"

int dwmac4_dma_reset(void __iomem *ioaddr)
{
	u32 value = readl(ioaddr + DMA_BUS_MODE);

	/* DMA SW reset */
	value |= DMA_BUS_MODE_SFT_RESET;
	writel(value, ioaddr + DMA_BUS_MODE);

	return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
				 !(value & DMA_BUS_MODE_SFT_RESET),
				 10000, 1000000);
}

void dwmac4_set_rx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr,
			    u32 tail_ptr, u32 chan)
{
	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;

	writel(tail_ptr, ioaddr + DMA_CHAN_RX_END_ADDR(dwmac4_addrs, chan));
}

void dwmac4_set_tx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr,
			    u32 tail_ptr, u32 chan)
{
	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;

	writel(tail_ptr, ioaddr + DMA_CHAN_TX_END_ADDR(dwmac4_addrs, chan));
}

void dwmac4_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
			 u32 chan)
{
	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));

	value |= DMA_CONTROL_ST;
	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));

	value = readl(ioaddr + GMAC_CONFIG);
	value |= GMAC_CONFIG_TE;
	writel(value, ioaddr + GMAC_CONFIG);
}

void dwmac4_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
			u32 chan)
{
	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;

	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));

	value &= ~DMA_CONTROL_ST;
	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
}

void dwmac4_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
			 u32 chan)
{
	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;

	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));

	value |= DMA_CONTROL_SR;

	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));

	value = readl(ioaddr + GMAC_CONFIG);
	value |= GMAC_CONFIG_RE;
	writel(value, ioaddr + GMAC_CONFIG);
}

void dwmac4_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr,
			u32 chan)
{
	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));

	value &= ~DMA_CONTROL_SR;
	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
}

void dwmac4_set_tx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr,
			    u32 len, u32 chan)
{
	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;

	writel(len, ioaddr + DMA_CHAN_TX_RING_LEN(dwmac4_addrs, chan));
}

void dwmac4_set_rx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr,
			    u32 len, u32 chan)
{
	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;

	writel(len, ioaddr + DMA_CHAN_RX_RING_LEN(dwmac4_addrs, chan));
}

void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
			   u32 chan, bool rx, bool tx)
{
	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));

	if (rx)
		value |= DMA_CHAN_INTR_DEFAULT_RX;
	if (tx)
		value |= DMA_CHAN_INTR_DEFAULT_TX;

	writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
}

void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
			     u32 chan, bool rx, bool tx)
{
	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));

	if (rx)
		value |= DMA_CHAN_INTR_DEFAULT_RX_4_10;
	if (tx)
		value |= DMA_CHAN_INTR_DEFAULT_TX_4_10;

	writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
}

void dwmac4_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
			    u32 chan, bool rx, bool tx)
{
	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));

	if (rx)
		value &= ~DMA_CHAN_INTR_DEFAULT_RX;
	if (tx)
		value &= ~DMA_CHAN_INTR_DEFAULT_TX;

	writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
}

void dwmac410_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
			      u32 chan, bool rx, bool tx)
{
	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));

	if (rx)
		value &= ~DMA_CHAN_INTR_DEFAULT_RX_4_10;
	if (tx)
		value &= ~DMA_CHAN_INTR_DEFAULT_TX_4_10;

	writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
}

int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr,
			 struct stmmac_extra_stats *x, u32 chan, u32 dir)
{
	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
	u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(dwmac4_addrs, chan));
	u32 intr_en = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
	struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[chan];
	struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[chan];
	int ret = 0;

	if (dir == DMA_DIR_RX)
		intr_status &= DMA_CHAN_STATUS_MSK_RX;
	else if (dir == DMA_DIR_TX)
		intr_status &= DMA_CHAN_STATUS_MSK_TX;

	/* ABNORMAL interrupts */
	if (unlikely(intr_status & DMA_CHAN_STATUS_AIS)) {
		if (unlikely(intr_status & DMA_CHAN_STATUS_RBU))
			x->rx_buf_unav_irq++;
		if (unlikely(intr_status & DMA_CHAN_STATUS_RPS))
			x->rx_process_stopped_irq++;
		if (unlikely(intr_status & DMA_CHAN_STATUS_RWT))
			x->rx_watchdog_irq++;
		if (unlikely(intr_status & DMA_CHAN_STATUS_ETI))
			x->tx_early_irq++;
		if (unlikely(intr_status & DMA_CHAN_STATUS_TPS)) {
			x->tx_process_stopped_irq++;
			ret = tx_hard_error;
		}
		if (unlikely(intr_status & DMA_CHAN_STATUS_FBE)) {
			x->fatal_bus_error_irq++;
			ret = tx_hard_error;
		}
	}
	/* TX/RX NORMAL interrupts */
	if (likely(intr_status & DMA_CHAN_STATUS_RI)) {
		u64_stats_update_begin(&rxq_stats->syncp);
		rxq_stats->rx_normal_irq_n++;
		u64_stats_update_end(&rxq_stats->syncp);
		ret |= handle_rx;
	}
	if (likely(intr_status & DMA_CHAN_STATUS_TI)) {
		u64_stats_update_begin(&txq_stats->syncp);
		txq_stats->tx_normal_irq_n++;
		u64_stats_update_end(&txq_stats->syncp);
		ret |= handle_tx;
	}

	if (unlikely(intr_status & DMA_CHAN_STATUS_TBU))
		ret |= handle_tx;
	if (unlikely(intr_status & DMA_CHAN_STATUS_ERI))
		x->rx_early_irq++;

	writel(intr_status & intr_en,
	       ioaddr + DMA_CHAN_STATUS(dwmac4_addrs, chan));
	return ret;
}

void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
				unsigned int high, unsigned int low)
{
	unsigned long data;

	data = (addr[5] << 8) | addr[4];
	/* For MAC Addr registers se have to set the Address Enable (AE)
	 * bit that has no effect on the High Reg 0 where the bit 31 (MO)
	 * is RO.
	 */
	data |= (STMMAC_CHAN0 << GMAC_HI_DCS_SHIFT);
	writel(data | GMAC_HI_REG_AE, ioaddr + high);
	data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
	writel(data, ioaddr + low);
}

/* Enable disable MAC RX/TX */
void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable)
{
	u32 value = readl(ioaddr + GMAC_CONFIG);
	u32 old_val = value;

	if (enable)
		value |= GMAC_CONFIG_RE | GMAC_CONFIG_TE;
	else
		value &= ~(GMAC_CONFIG_TE | GMAC_CONFIG_RE);

	if (value != old_val)
		writel(value, ioaddr + GMAC_CONFIG);
}

void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
				unsigned int high, unsigned int low)
{
	unsigned int hi_addr, lo_addr;

	/* Read the MAC address from the hardware */
	hi_addr = readl(ioaddr + high);
	lo_addr = readl(ioaddr + low);

	/* Extract the MAC address from the high and low words */
	addr[0] = lo_addr & 0xff;
	addr[1] = (lo_addr >> 8) & 0xff;
	addr[2] = (lo_addr >> 16) & 0xff;
	addr[3] = (lo_addr >> 24) & 0xff;
	addr[4] = hi_addr & 0xff;
	addr[5] = (hi_addr >> 8) & 0xff;
}
Commit	Line	Data
75a6faf6	1	// SPDX-License-Identifier: GPL-2.0-only
48863ce5 AT	2	/*
	3	* Copyright (C) 2007-2015 STMicroelectronics Ltd
	4	*
48863ce5 AT	5	* Author: Alexandre Torgue <alexandre.torgue@st.com>
	6	*/
	7
	8	#include <linux/io.h>
45d0da49	9	#include <linux/iopoll.h>
48863ce5 AT	10	#include <linux/delay.h>
	11	#include "common.h"
	12	#include "dwmac4_dma.h"
	13	#include "dwmac4.h"
33719b57	14	#include "stmmac.h"
48863ce5 AT	15
	16	int dwmac4_dma_reset(void __iomem *ioaddr)
	17	{
	18	u32 value = readl(ioaddr + DMA_BUS_MODE);
48863ce5 AT	19
	20	/* DMA SW reset */
	21	value \|= DMA_BUS_MODE_SFT_RESET;
	22	writel(value, ioaddr + DMA_BUS_MODE);
48863ce5	23
45d0da49 DZ	24	return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
45d0da49 DZ	25	!(value & DMA_BUS_MODE_SFT_RESET),
9d14edfd	26	10000, 1000000);
48863ce5 AT	27	}
48863ce5 AT	28
1d84b487 AH	29	void dwmac4_set_rx_tail_ptr(struct stmmac_priv priv, void __iomem ioaddr,
1d84b487 AH	30	u32 tail_ptr, u32 chan)
48863ce5	31	{
33719b57 AH	32	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
	33
	34	writel(tail_ptr, ioaddr + DMA_CHAN_RX_END_ADDR(dwmac4_addrs, chan));
48863ce5 AT	35	}
48863ce5 AT	36
1d84b487 AH	37	void dwmac4_set_tx_tail_ptr(struct stmmac_priv priv, void __iomem ioaddr,
1d84b487 AH	38	u32 tail_ptr, u32 chan)
48863ce5	39	{
33719b57 AH	40	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
	41
	42	writel(tail_ptr, ioaddr + DMA_CHAN_TX_END_ADDR(dwmac4_addrs, chan));
48863ce5 AT	43	}
48863ce5 AT	44
1d84b487 AH	45	void dwmac4_dma_start_tx(struct stmmac_priv priv, void __iomem ioaddr,
1d84b487 AH	46	u32 chan)
48863ce5	47	{
33719b57 AH	48	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
33719b57 AH	49	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
48863ce5 AT	50
48863ce5 AT	51	value \|= DMA_CONTROL_ST;
33719b57	52	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
48863ce5 AT	53
	54	value = readl(ioaddr + GMAC_CONFIG);
	55	value \|= GMAC_CONFIG_TE;
	56	writel(value, ioaddr + GMAC_CONFIG);
	57	}
	58
1d84b487 AH	59	void dwmac4_dma_stop_tx(struct stmmac_priv priv, void __iomem ioaddr,
1d84b487 AH	60	u32 chan)
48863ce5	61	{
33719b57 AH	62	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
	63
	64	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
48863ce5 AT	65
48863ce5 AT	66	value &= ~DMA_CONTROL_ST;
33719b57	67	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
48863ce5 AT	68	}
48863ce5 AT	69
1d84b487 AH	70	void dwmac4_dma_start_rx(struct stmmac_priv priv, void __iomem ioaddr,
1d84b487 AH	71	u32 chan)
48863ce5	72	{
33719b57 AH	73	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
	74
	75	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
48863ce5 AT	76
	77	value \|= DMA_CONTROL_SR;
	78
33719b57	79	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
48863ce5 AT	80
	81	value = readl(ioaddr + GMAC_CONFIG);
	82	value \|= GMAC_CONFIG_RE;
	83	writel(value, ioaddr + GMAC_CONFIG);
	84	}
	85
1d84b487 AH	86	void dwmac4_dma_stop_rx(struct stmmac_priv priv, void __iomem ioaddr,
1d84b487 AH	87	u32 chan)
48863ce5	88	{
33719b57 AH	89	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
33719b57 AH	90	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
48863ce5 AT	91
48863ce5 AT	92	value &= ~DMA_CONTROL_SR;
33719b57	93	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
48863ce5 AT	94	}
48863ce5 AT	95
1d84b487 AH	96	void dwmac4_set_tx_ring_len(struct stmmac_priv priv, void __iomem ioaddr,
1d84b487 AH	97	u32 len, u32 chan)
48863ce5	98	{
33719b57 AH	99	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
	100
	101	writel(len, ioaddr + DMA_CHAN_TX_RING_LEN(dwmac4_addrs, chan));
48863ce5 AT	102	}
48863ce5 AT	103
1d84b487 AH	104	void dwmac4_set_rx_ring_len(struct stmmac_priv priv, void __iomem ioaddr,
1d84b487 AH	105	u32 len, u32 chan)
48863ce5	106	{
33719b57 AH	107	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
	108
	109	writel(len, ioaddr + DMA_CHAN_RX_RING_LEN(dwmac4_addrs, chan));
48863ce5 AT	110	}
48863ce5 AT	111
1d84b487 AH	112	void dwmac4_enable_dma_irq(struct stmmac_priv priv, void __iomem ioaddr,
1d84b487 AH	113	u32 chan, bool rx, bool tx)
48863ce5	114	{
33719b57 AH	115	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
33719b57 AH	116	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
021bd5e3 JA	117
	118	if (rx)
	119	value \|= DMA_CHAN_INTR_DEFAULT_RX;
	120	if (tx)
	121	value \|= DMA_CHAN_INTR_DEFAULT_TX;
	122
33719b57	123	writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
48863ce5 AT	124	}
48863ce5 AT	125
1d84b487 AH	126	void dwmac410_enable_dma_irq(struct stmmac_priv priv, void __iomem ioaddr,
1d84b487 AH	127	u32 chan, bool rx, bool tx)
48863ce5	128	{
33719b57 AH	129	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
33719b57 AH	130	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
021bd5e3 JA	131
	132	if (rx)
	133	value \|= DMA_CHAN_INTR_DEFAULT_RX_4_10;
	134	if (tx)
	135	value \|= DMA_CHAN_INTR_DEFAULT_TX_4_10;
	136
33719b57	137	writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
48863ce5 AT	138	}
48863ce5 AT	139
1d84b487 AH	140	void dwmac4_disable_dma_irq(struct stmmac_priv priv, void __iomem ioaddr,
1d84b487 AH	141	u32 chan, bool rx, bool tx)
48863ce5	142	{
33719b57 AH	143	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
33719b57 AH	144	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
021bd5e3 JA	145
	146	if (rx)
	147	value &= ~DMA_CHAN_INTR_DEFAULT_RX;
	148	if (tx)
	149	value &= ~DMA_CHAN_INTR_DEFAULT_TX;
	150
33719b57	151	writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
021bd5e3 JA	152	}
021bd5e3 JA	153
1d84b487 AH	154	void dwmac410_disable_dma_irq(struct stmmac_priv priv, void __iomem ioaddr,
1d84b487 AH	155	u32 chan, bool rx, bool tx)
021bd5e3	156	{
33719b57 AH	157	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
33719b57 AH	158	u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
021bd5e3 JA	159
	160	if (rx)
	161	value &= ~DMA_CHAN_INTR_DEFAULT_RX_4_10;
	162	if (tx)
	163	value &= ~DMA_CHAN_INTR_DEFAULT_TX_4_10;
	164
33719b57	165	writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
48863ce5 AT	166	}
48863ce5 AT	167
1d84b487	168	int dwmac4_dma_interrupt(struct stmmac_priv priv, void __iomem ioaddr,
7e1c520c	169	struct stmmac_extra_stats *x, u32 chan, u32 dir)
48863ce5	170	{
33719b57 AH	171	const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
	172	u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(dwmac4_addrs, chan));
	173	u32 intr_en = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
8070274b JZ	174	struct stmmac_rxq_stats *rxq_stats = &priv->xstats.rxq_stats[chan];
8070274b JZ	175	struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[chan];
1103d3a5	176	int ret = 0;
48863ce5	177
7e1c520c OBL	178	if (dir == DMA_DIR_RX)
	179	intr_status &= DMA_CHAN_STATUS_MSK_RX;
	180	else if (dir == DMA_DIR_TX)
	181	intr_status &= DMA_CHAN_STATUS_MSK_TX;
	182
48863ce5 AT	183	/* ABNORMAL interrupts */
	184	if (unlikely(intr_status & DMA_CHAN_STATUS_AIS)) {
	185	if (unlikely(intr_status & DMA_CHAN_STATUS_RBU))
	186	x->rx_buf_unav_irq++;
	187	if (unlikely(intr_status & DMA_CHAN_STATUS_RPS))
	188	x->rx_process_stopped_irq++;
	189	if (unlikely(intr_status & DMA_CHAN_STATUS_RWT))
	190	x->rx_watchdog_irq++;
	191	if (unlikely(intr_status & DMA_CHAN_STATUS_ETI))
	192	x->tx_early_irq++;
	193	if (unlikely(intr_status & DMA_CHAN_STATUS_TPS)) {
	194	x->tx_process_stopped_irq++;
	195	ret = tx_hard_error;
	196	}
	197	if (unlikely(intr_status & DMA_CHAN_STATUS_FBE)) {
	198	x->fatal_bus_error_irq++;
	199	ret = tx_hard_error;
	200	}
	201	}
	202	/* TX/RX NORMAL interrupts */
6ccf12ae	203	if (likely(intr_status & DMA_CHAN_STATUS_RI)) {
8070274b JZ	204	u64_stats_update_begin(&rxq_stats->syncp);
	205	rxq_stats->rx_normal_irq_n++;
	206	u64_stats_update_end(&rxq_stats->syncp);
6ccf12ae WVK	207	ret \|= handle_rx;
6ccf12ae WVK	208	}
1975df88	209	if (likely(intr_status & DMA_CHAN_STATUS_TI)) {
8070274b JZ	210	u64_stats_update_begin(&txq_stats->syncp);
	211	txq_stats->tx_normal_irq_n++;
	212	u64_stats_update_end(&txq_stats->syncp);
6ccf12ae	213	ret \|= handle_tx;
48863ce5	214	}
133466c3	215
1975df88 VW	216	if (unlikely(intr_status & DMA_CHAN_STATUS_TBU))
1975df88 VW	217	ret \|= handle_tx;
6ccf12ae WVK	218	if (unlikely(intr_status & DMA_CHAN_STATUS_ERI))
6ccf12ae WVK	219	x->rx_early_irq++;
48863ce5	220
33719b57 AH	221	writel(intr_status & intr_en,
33719b57 AH	222	ioaddr + DMA_CHAN_STATUS(dwmac4_addrs, chan));
48863ce5 AT	223	return ret;
	224	}
	225
76660757	226	void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
48863ce5 AT	227	unsigned int high, unsigned int low)
	228	{
	229	unsigned long data;
	230
	231	data = (addr[5] << 8) \| addr[4];
	232	/* For MAC Addr registers se have to set the Address Enable (AE)
	233	* bit that has no effect on the High Reg 0 where the bit 31 (MO)
	234	* is RO.
	235	*/
	236	data \|= (STMMAC_CHAN0 << GMAC_HI_DCS_SHIFT);
	237	writel(data \| GMAC_HI_REG_AE, ioaddr + high);
	238	data = (addr[3] << 24) \| (addr[2] << 16) \| (addr[1] << 8) \| addr[0];
	239	writel(data, ioaddr + low);
	240	}
	241
	242	/* Enable disable MAC RX/TX */
	243	void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable)
	244	{
	245	u32 value = readl(ioaddr + GMAC_CONFIG);
284779db	246	u32 old_val = value;
48863ce5 AT	247
	248	if (enable)
	249	value \|= GMAC_CONFIG_RE \| GMAC_CONFIG_TE;
	250	else
	251	value &= ~(GMAC_CONFIG_TE \| GMAC_CONFIG_RE);
	252
284779db VW	253	if (value != old_val)
284779db VW	254	writel(value, ioaddr + GMAC_CONFIG);
48863ce5 AT	255	}
	256
	257	void stmmac_dwmac4_get_mac_addr(void __iomem ioaddr, unsigned char addr,
	258	unsigned int high, unsigned int low)
	259	{
	260	unsigned int hi_addr, lo_addr;
	261
	262	/* Read the MAC address from the hardware */
	263	hi_addr = readl(ioaddr + high);
	264	lo_addr = readl(ioaddr + low);
	265
	266	/* Extract the MAC address from the high and low words */
	267	addr[0] = lo_addr & 0xff;
	268	addr[1] = (lo_addr >> 8) & 0xff;
	269	addr[2] = (lo_addr >> 16) & 0xff;
	270	addr[3] = (lo_addr >> 24) & 0xff;
	271	addr[4] = hi_addr & 0xff;
	272	addr[5] = (hi_addr >> 8) & 0xff;
	273	}