[linux-block.git] / drivers / net / ethernet / stmicro / stmmac / dwmac4_descs.c

/*
 * This contains the functions to handle the descriptors for DesignWare databook
 * 4.xx.
 *
 * Copyright (C) 2015  STMicroelectronics Ltd
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * Author: Alexandre Torgue <alexandre.torgue@st.com>
 */

#include <linux/stmmac.h>
#include "common.h"
#include "dwmac4_descs.h"

static int dwmac4_wrback_get_tx_status(void *data, struct stmmac_extra_stats *x,
				       struct dma_desc *p,
				       void __iomem *ioaddr)
{
	struct net_device_stats *stats = (struct net_device_stats *)data;
	unsigned int tdes3;
	int ret = tx_done;

	tdes3 = le32_to_cpu(p->des3);

	/* Get tx owner first */
	if (unlikely(tdes3 & TDES3_OWN))
		return tx_dma_own;

	/* Verify tx error by looking at the last segment. */
	if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
		return tx_not_ls;

	if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
		if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
			x->tx_jabber++;
		if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
			x->tx_frame_flushed++;
		if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
			x->tx_losscarrier++;
			stats->tx_carrier_errors++;
		}
		if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
			x->tx_carrier++;
			stats->tx_carrier_errors++;
		}
		if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
			     (tdes3 & TDES3_EXCESSIVE_COLLISION)))
			stats->collisions +=
			    (tdes3 & TDES3_COLLISION_COUNT_MASK)
			    >> TDES3_COLLISION_COUNT_SHIFT;

		if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
			x->tx_deferred++;

		if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR))
			x->tx_underflow++;

		if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
			x->tx_ip_header_error++;

		if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
			x->tx_payload_error++;

		ret = tx_err;
	}

	if (unlikely(tdes3 & TDES3_DEFERRED))
		x->tx_deferred++;

	return ret;
}

static int dwmac4_wrback_get_rx_status(void *data, struct stmmac_extra_stats *x,
				       struct dma_desc *p)
{
	struct net_device_stats *stats = (struct net_device_stats *)data;
	unsigned int rdes1 = le32_to_cpu(p->des1);
	unsigned int rdes2 = le32_to_cpu(p->des2);
	unsigned int rdes3 = le32_to_cpu(p->des3);
	int message_type;
	int ret = good_frame;

	if (unlikely(rdes3 & RDES3_OWN))
		return dma_own;

	/* Verify rx error by looking at the last segment. */
	if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
		return discard_frame;

	if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
		if (unlikely(rdes3 & RDES3_GIANT_PACKET))
			stats->rx_length_errors++;
		if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
			x->rx_gmac_overflow++;

		if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
			x->rx_watchdog++;

		if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
			x->rx_mii++;

		if (unlikely(rdes3 & RDES3_CRC_ERROR)) {
			x->rx_crc_errors++;
			stats->rx_crc_errors++;
		}

		if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
			x->dribbling_bit++;

		ret = discard_frame;
	}

	message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;

	if (rdes1 & RDES1_IP_HDR_ERROR)
		x->ip_hdr_err++;
	if (rdes1 & RDES1_IP_CSUM_BYPASSED)
		x->ip_csum_bypassed++;
	if (rdes1 & RDES1_IPV4_HEADER)
		x->ipv4_pkt_rcvd++;
	if (rdes1 & RDES1_IPV6_HEADER)
		x->ipv6_pkt_rcvd++;

	if (message_type == RDES_EXT_NO_PTP)
		x->no_ptp_rx_msg_type_ext++;
	else if (message_type == RDES_EXT_SYNC)
		x->ptp_rx_msg_type_sync++;
	else if (message_type == RDES_EXT_FOLLOW_UP)
		x->ptp_rx_msg_type_follow_up++;
	else if (message_type == RDES_EXT_DELAY_REQ)
		x->ptp_rx_msg_type_delay_req++;
	else if (message_type == RDES_EXT_DELAY_RESP)
		x->ptp_rx_msg_type_delay_resp++;
	else if (message_type == RDES_EXT_PDELAY_REQ)
		x->ptp_rx_msg_type_pdelay_req++;
	else if (message_type == RDES_EXT_PDELAY_RESP)
		x->ptp_rx_msg_type_pdelay_resp++;
	else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
		x->ptp_rx_msg_type_pdelay_follow_up++;
	else if (message_type == RDES_PTP_ANNOUNCE)
		x->ptp_rx_msg_type_announce++;
	else if (message_type == RDES_PTP_MANAGEMENT)
		x->ptp_rx_msg_type_management++;
	else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
		x->ptp_rx_msg_pkt_reserved_type++;

	if (rdes1 & RDES1_PTP_PACKET_TYPE)
		x->ptp_frame_type++;
	if (rdes1 & RDES1_PTP_VER)
		x->ptp_ver++;
	if (rdes1 & RDES1_TIMESTAMP_DROPPED)
		x->timestamp_dropped++;

	if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
		x->sa_rx_filter_fail++;
		ret = discard_frame;
	}
	if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
		x->da_rx_filter_fail++;
		ret = discard_frame;
	}

	if (rdes2 & RDES2_L3_FILTER_MATCH)
		x->l3_filter_match++;
	if (rdes2 & RDES2_L4_FILTER_MATCH)
		x->l4_filter_match++;
	if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
	    >> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
		x->l3_l4_filter_no_match++;

	return ret;
}

static int dwmac4_rd_get_tx_len(struct dma_desc *p)
{
	return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
}

static int dwmac4_get_tx_owner(struct dma_desc *p)
{
	return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT;
}

static void dwmac4_set_tx_owner(struct dma_desc *p)
{
	p->des3 |= cpu_to_le32(TDES3_OWN);
}

static void dwmac4_set_rx_owner(struct dma_desc *p)
{
	p->des3 |= cpu_to_le32(RDES3_OWN);
}

static int dwmac4_get_tx_ls(struct dma_desc *p)
{
	return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR)
		>> TDES3_LAST_DESCRIPTOR_SHIFT;
}

static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
{
	return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK);
}

static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
{
	p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE);
}

static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
{
	/* Context type from W/B descriptor must be zero */
	if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
		return 0;

	/* Tx Timestamp Status is 1 so des0 and des1'll have valid values */
	if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
		return 1;

	return 0;
}

static inline u64 dwmac4_get_timestamp(void *desc, u32 ats)
{
	struct dma_desc *p = (struct dma_desc *)desc;
	u64 ns;

	ns = le32_to_cpu(p->des0);
	/* convert high/sec time stamp value to nanosecond */
	ns += le32_to_cpu(p->des1) * 1000000000ULL;

	return ns;
}

static int dwmac4_rx_check_timestamp(void *desc)
{
	struct dma_desc *p = (struct dma_desc *)desc;
	u32 own, ctxt;
	int ret = 1;

	own = p->des3 & RDES3_OWN;
	ctxt = ((p->des3 & RDES3_CONTEXT_DESCRIPTOR)
		>> RDES3_CONTEXT_DESCRIPTOR_SHIFT);

	if (likely(!own && ctxt)) {
		if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff))
			/* Corrupted value */
			ret = -EINVAL;
		else
			/* A valid Timestamp is ready to be read */
			ret = 0;
	}

	/* Timestamp not ready */
	return ret;
}

static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
						 u32 ats)
{
	struct dma_desc *p = (struct dma_desc *)desc;
	int ret = -EINVAL;

	/* Get the status from normal w/b descriptor */
	if (likely(p->des3 & TDES3_RS1V)) {
		if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {
			int i = 0;

			/* Check if timestamp is OK from context descriptor */
			do {
				ret = dwmac4_rx_check_timestamp(next_desc);
				if (ret < 0)
					goto exit;
				i++;

			} while ((ret == 1) && (i < 10));

			if (i == 10)
				ret = -EBUSY;
		}
	}
exit:
	if (likely(ret == 0))
		return 1;

	return 0;
}

static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
				   int mode, int end)
{
	p->des3 = cpu_to_le32(RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);

	if (!disable_rx_ic)
		p->des3 |= cpu_to_le32(RDES3_INT_ON_COMPLETION_EN);
}

static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
{
	p->des0 = 0;
	p->des1 = 0;
	p->des2 = 0;
	p->des3 = 0;
}

static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
				      bool csum_flag, int mode, bool tx_own,
				      bool ls, unsigned int tot_pkt_len)
{
	unsigned int tdes3 = le32_to_cpu(p->des3);

	p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);

	tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK;
	if (is_fs)
		tdes3 |= TDES3_FIRST_DESCRIPTOR;
	else
		tdes3 &= ~TDES3_FIRST_DESCRIPTOR;

	if (likely(csum_flag))
		tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
	else
		tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);

	if (ls)
		tdes3 |= TDES3_LAST_DESCRIPTOR;
	else
		tdes3 &= ~TDES3_LAST_DESCRIPTOR;

	/* Finally set the OWN bit. Later the DMA will start! */
	if (tx_own)
		tdes3 |= TDES3_OWN;

	if (is_fs & tx_own)
		/* When the own bit, for the first frame, has to be set, all
		 * descriptors for the same frame has to be set before, to
		 * avoid race condition.
		 */
		dma_wmb();

	p->des3 = cpu_to_le32(tdes3);
}

static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
					  int len1, int len2, bool tx_own,
					  bool ls, unsigned int tcphdrlen,
					  unsigned int tcppayloadlen)
{
	unsigned int tdes3 = le32_to_cpu(p->des3);

	if (len1)
		p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK));

	if (len2)
		p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
			    & TDES2_BUFFER2_SIZE_MASK);

	if (is_fs) {
		tdes3 |= TDES3_FIRST_DESCRIPTOR |
			 TDES3_TCP_SEGMENTATION_ENABLE |
			 ((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
			  TDES3_SLOT_NUMBER_MASK) |
			 ((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
	} else {
		tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
	}

	if (ls)
		tdes3 |= TDES3_LAST_DESCRIPTOR;
	else
		tdes3 &= ~TDES3_LAST_DESCRIPTOR;

	/* Finally set the OWN bit. Later the DMA will start! */
	if (tx_own)
		tdes3 |= TDES3_OWN;

	if (is_fs & tx_own)
		/* When the own bit, for the first frame, has to be set, all
		 * descriptors for the same frame has to be set before, to
		 * avoid race condition.
		 */
		dma_wmb();

	p->des3 = cpu_to_le32(tdes3);
}

static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)
{
	p->des2 = 0;
	p->des3 = 0;
}

static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
{
	p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION);
}

static void dwmac4_display_ring(void *head, unsigned int size, bool rx)
{
	struct dma_desc *p = (struct dma_desc *)head;
	int i;

	pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");

	for (i = 0; i < size; i++) {
		pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
			i, (unsigned int)virt_to_phys(p),
			le32_to_cpu(p->des0), le32_to_cpu(p->des1),
			le32_to_cpu(p->des2), le32_to_cpu(p->des3));
		p++;
	}
}

static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
{
	p->des0 = 0;
	p->des1 = 0;
	p->des2 = cpu_to_le32(mss);
	p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
}

const struct stmmac_desc_ops dwmac4_desc_ops = {
	.tx_status = dwmac4_wrback_get_tx_status,
	.rx_status = dwmac4_wrback_get_rx_status,
	.get_tx_len = dwmac4_rd_get_tx_len,
	.get_tx_owner = dwmac4_get_tx_owner,
	.set_tx_owner = dwmac4_set_tx_owner,
	.set_rx_owner = dwmac4_set_rx_owner,
	.get_tx_ls = dwmac4_get_tx_ls,
	.get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
	.enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
	.get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
	.get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
	.get_timestamp = dwmac4_get_timestamp,
	.set_tx_ic = dwmac4_rd_set_tx_ic,
	.prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
	.prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
	.release_tx_desc = dwmac4_release_tx_desc,
	.init_rx_desc = dwmac4_rd_init_rx_desc,
	.init_tx_desc = dwmac4_rd_init_tx_desc,
	.display_ring = dwmac4_display_ring,
	.set_mss = dwmac4_set_mss_ctxt,
};

const struct stmmac_mode_ops dwmac4_ring_mode_ops = { };
Commit	Line	Data
753a7109 AT	1	/*
	2	* This contains the functions to handle the descriptors for DesignWare databook
	3	* 4.xx.
	4	*
	5	* Copyright (C) 2015 STMicroelectronics Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* Author: Alexandre Torgue <alexandre.torgue@st.com>
	12	*/
	13
	14	#include <linux/stmmac.h>
	15	#include "common.h"
	16	#include "dwmac4_descs.h"
	17
	18	static int dwmac4_wrback_get_tx_status(void data, struct stmmac_extra_stats x,
	19	struct dma_desc *p,
	20	void __iomem *ioaddr)
	21	{
	22	struct net_device_stats stats = (struct net_device_stats )data;
	23	unsigned int tdes3;
	24	int ret = tx_done;
	25
f8be0d78	26	tdes3 = le32_to_cpu(p->des3);
753a7109 AT	27
	28	/* Get tx owner first */
	29	if (unlikely(tdes3 & TDES3_OWN))
	30	return tx_dma_own;
	31
	32	/* Verify tx error by looking at the last segment. */
	33	if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
	34	return tx_not_ls;
	35
	36	if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
	37	if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
	38	x->tx_jabber++;
	39	if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
	40	x->tx_frame_flushed++;
	41	if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
	42	x->tx_losscarrier++;
	43	stats->tx_carrier_errors++;
	44	}
	45	if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
	46	x->tx_carrier++;
	47	stats->tx_carrier_errors++;
	48	}
	49	if (unlikely((tdes3 & TDES3_LATE_COLLISION) \|\|
	50	(tdes3 & TDES3_EXCESSIVE_COLLISION)))
	51	stats->collisions +=
	52	(tdes3 & TDES3_COLLISION_COUNT_MASK)
	53	>> TDES3_COLLISION_COUNT_SHIFT;
	54
	55	if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
	56	x->tx_deferred++;
	57
	58	if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR))
	59	x->tx_underflow++;
	60
	61	if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
	62	x->tx_ip_header_error++;
	63
	64	if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
	65	x->tx_payload_error++;
	66
	67	ret = tx_err;
	68	}
	69
	70	if (unlikely(tdes3 & TDES3_DEFERRED))
	71	x->tx_deferred++;
	72
	73	return ret;
	74	}
	75
	76	static int dwmac4_wrback_get_rx_status(void data, struct stmmac_extra_stats x,
	77	struct dma_desc *p)
	78	{
	79	struct net_device_stats stats = (struct net_device_stats )data;
f8be0d78 MW	80	unsigned int rdes1 = le32_to_cpu(p->des1);
	81	unsigned int rdes2 = le32_to_cpu(p->des2);
	82	unsigned int rdes3 = le32_to_cpu(p->des3);
753a7109 AT	83	int message_type;
	84	int ret = good_frame;
	85
	86	if (unlikely(rdes3 & RDES3_OWN))
	87	return dma_own;
	88
	89	/* Verify rx error by looking at the last segment. */
	90	if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
	91	return discard_frame;
	92
	93	if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
	94	if (unlikely(rdes3 & RDES3_GIANT_PACKET))
	95	stats->rx_length_errors++;
	96	if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
	97	x->rx_gmac_overflow++;
	98
	99	if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
	100	x->rx_watchdog++;
	101
	102	if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
	103	x->rx_mii++;
	104
	105	if (unlikely(rdes3 & RDES3_CRC_ERROR)) {
e0a76606	106	x->rx_crc_errors++;
753a7109 AT	107	stats->rx_crc_errors++;
	108	}
	109
	110	if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
	111	x->dribbling_bit++;
	112
	113	ret = discard_frame;
	114	}
	115
	116	message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;
	117
	118	if (rdes1 & RDES1_IP_HDR_ERROR)
	119	x->ip_hdr_err++;
	120	if (rdes1 & RDES1_IP_CSUM_BYPASSED)
	121	x->ip_csum_bypassed++;
	122	if (rdes1 & RDES1_IPV4_HEADER)
	123	x->ipv4_pkt_rcvd++;
	124	if (rdes1 & RDES1_IPV6_HEADER)
	125	x->ipv6_pkt_rcvd++;
ee112c12 GC	126
	127	if (message_type == RDES_EXT_NO_PTP)
	128	x->no_ptp_rx_msg_type_ext++;
	129	else if (message_type == RDES_EXT_SYNC)
	130	x->ptp_rx_msg_type_sync++;
753a7109	131	else if (message_type == RDES_EXT_FOLLOW_UP)
ee112c12	132	x->ptp_rx_msg_type_follow_up++;
753a7109	133	else if (message_type == RDES_EXT_DELAY_REQ)
ee112c12	134	x->ptp_rx_msg_type_delay_req++;
753a7109	135	else if (message_type == RDES_EXT_DELAY_RESP)
ee112c12	136	x->ptp_rx_msg_type_delay_resp++;
753a7109	137	else if (message_type == RDES_EXT_PDELAY_REQ)
ee112c12	138	x->ptp_rx_msg_type_pdelay_req++;
753a7109	139	else if (message_type == RDES_EXT_PDELAY_RESP)
ee112c12	140	x->ptp_rx_msg_type_pdelay_resp++;
753a7109	141	else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
ee112c12 GC	142	x->ptp_rx_msg_type_pdelay_follow_up++;
	143	else if (message_type == RDES_PTP_ANNOUNCE)
	144	x->ptp_rx_msg_type_announce++;
	145	else if (message_type == RDES_PTP_MANAGEMENT)
	146	x->ptp_rx_msg_type_management++;
	147	else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
	148	x->ptp_rx_msg_pkt_reserved_type++;
753a7109 AT	149
	150	if (rdes1 & RDES1_PTP_PACKET_TYPE)
	151	x->ptp_frame_type++;
	152	if (rdes1 & RDES1_PTP_VER)
	153	x->ptp_ver++;
	154	if (rdes1 & RDES1_TIMESTAMP_DROPPED)
	155	x->timestamp_dropped++;
	156
	157	if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
	158	x->sa_rx_filter_fail++;
	159	ret = discard_frame;
	160	}
	161	if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
	162	x->da_rx_filter_fail++;
	163	ret = discard_frame;
	164	}
	165
	166	if (rdes2 & RDES2_L3_FILTER_MATCH)
	167	x->l3_filter_match++;
	168	if (rdes2 & RDES2_L4_FILTER_MATCH)
	169	x->l4_filter_match++;
	170	if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
	171	>> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
	172	x->l3_l4_filter_no_match++;
	173
	174	return ret;
	175	}
	176
	177	static int dwmac4_rd_get_tx_len(struct dma_desc *p)
	178	{
f8be0d78	179	return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
753a7109 AT	180	}
	181
	182	static int dwmac4_get_tx_owner(struct dma_desc *p)
	183	{
f8be0d78	184	return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT;
753a7109 AT	185	}
	186
	187	static void dwmac4_set_tx_owner(struct dma_desc *p)
	188	{
f8be0d78	189	p->des3 \|= cpu_to_le32(TDES3_OWN);
753a7109 AT	190	}
	191
	192	static void dwmac4_set_rx_owner(struct dma_desc *p)
	193	{
f8be0d78	194	p->des3 \|= cpu_to_le32(RDES3_OWN);
753a7109 AT	195	}
	196
	197	static int dwmac4_get_tx_ls(struct dma_desc *p)
	198	{
f8be0d78 MW	199	return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR)
f8be0d78 MW	200	>> TDES3_LAST_DESCRIPTOR_SHIFT;
753a7109 AT	201	}
	202
	203	static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
	204	{
f8be0d78	205	return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK);
753a7109 AT	206	}
	207
	208	static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
	209	{
f8be0d78	210	p->des2 \|= cpu_to_le32(TDES2_TIMESTAMP_ENABLE);
753a7109 AT	211	}
	212
	213	static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
	214	{
ba1ffd74	215	/* Context type from W/B descriptor must be zero */
f9aa9dc7	216	if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
33d4c482	217	return 0;
ba1ffd74 GC	218
ba1ffd74 GC	219	/* Tx Timestamp Status is 1 so des0 and des1'll have valid values */
f9aa9dc7	220	if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
33d4c482	221	return 1;
ba1ffd74	222
33d4c482	223	return 0;
753a7109 AT	224	}
753a7109 AT	225
ba1ffd74	226	static inline u64 dwmac4_get_timestamp(void *desc, u32 ats)
753a7109 AT	227	{
	228	struct dma_desc p = (struct dma_desc )desc;
	229	u64 ns;
	230
f8be0d78	231	ns = le32_to_cpu(p->des0);
753a7109	232	/* convert high/sec time stamp value to nanosecond */
f8be0d78	233	ns += le32_to_cpu(p->des1) * 1000000000ULL;
753a7109 AT	234
	235	return ns;
	236	}
	237
ba1ffd74 GC	238	static int dwmac4_rx_check_timestamp(void *desc)
	239	{
	240	struct dma_desc p = (struct dma_desc )desc;
	241	u32 own, ctxt;
	242	int ret = 1;
	243
	244	own = p->des3 & RDES3_OWN;
	245	ctxt = ((p->des3 & RDES3_CONTEXT_DESCRIPTOR)
	246	>> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
	247
	248	if (likely(!own && ctxt)) {
	249	if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff))
	250	/* Corrupted value */
	251	ret = -EINVAL;
	252	else
	253	/* A valid Timestamp is ready to be read */
	254	ret = 0;
	255	}
	256
	257	/* Timestamp not ready */
	258	return ret;
	259	}
	260
a1762456 FH	261	static int dwmac4_wrback_get_rx_timestamp_status(void desc, void next_desc,
a1762456 FH	262	u32 ats)
753a7109 AT	263	{
753a7109 AT	264	struct dma_desc p = (struct dma_desc )desc;
ba1ffd74 GC	265	int ret = -EINVAL;
	266
	267	/* Get the status from normal w/b descriptor */
	268	if (likely(p->des3 & TDES3_RS1V)) {
f9aa9dc7	269	if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {
ba1ffd74 GC	270	int i = 0;
	271
	272	/* Check if timestamp is OK from context descriptor */
	273	do {
a1762456	274	ret = dwmac4_rx_check_timestamp(next_desc);
ba1ffd74 GC	275	if (ret < 0)
	276	goto exit;
	277	i++;
753a7109	278
9454360d	279	} while ((ret == 1) && (i < 10));
ba1ffd74 GC	280
	281	if (i == 10)
	282	ret = -EBUSY;
	283	}
	284	}
	285	exit:
33d4c482 MM	286	if (likely(ret == 0))
	287	return 1;
	288
	289	return 0;
753a7109 AT	290	}
	291
	292	static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
	293	int mode, int end)
	294	{
f8be0d78	295	p->des3 = cpu_to_le32(RDES3_OWN \| RDES3_BUFFER1_VALID_ADDR);
753a7109 AT	296
753a7109 AT	297	if (!disable_rx_ic)
f8be0d78	298	p->des3 \|= cpu_to_le32(RDES3_INT_ON_COMPLETION_EN);
753a7109 AT	299	}
	300
	301	static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
	302	{
	303	p->des0 = 0;
	304	p->des1 = 0;
	305	p->des2 = 0;
	306	p->des3 = 0;
	307	}
	308
	309	static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
	310	bool csum_flag, int mode, bool tx_own,
fe6af0e1	311	bool ls, unsigned int tot_pkt_len)
753a7109	312	{
f8be0d78	313	unsigned int tdes3 = le32_to_cpu(p->des3);
753a7109	314
f8be0d78	315	p->des2 \|= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);
753a7109	316
fe6af0e1	317	tdes3 \|= tot_pkt_len & TDES3_PACKET_SIZE_MASK;
753a7109 AT	318	if (is_fs)
	319	tdes3 \|= TDES3_FIRST_DESCRIPTOR;
	320	else
	321	tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
	322
	323	if (likely(csum_flag))
	324	tdes3 \|= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
	325	else
	326	tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
	327
	328	if (ls)
	329	tdes3 \|= TDES3_LAST_DESCRIPTOR;
	330	else
	331	tdes3 &= ~TDES3_LAST_DESCRIPTOR;
	332
	333	/* Finally set the OWN bit. Later the DMA will start! */
	334	if (tx_own)
	335	tdes3 \|= TDES3_OWN;
	336
	337	if (is_fs & tx_own)
	338	/* When the own bit, for the first frame, has to be set, all
	339	* descriptors for the same frame has to be set before, to
	340	* avoid race condition.
	341	*/
ad688cdb	342	dma_wmb();
753a7109	343
f8be0d78	344	p->des3 = cpu_to_le32(tdes3);
753a7109 AT	345	}
	346
	347	static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
	348	int len1, int len2, bool tx_own,
	349	bool ls, unsigned int tcphdrlen,
	350	unsigned int tcppayloadlen)
	351	{
f8be0d78	352	unsigned int tdes3 = le32_to_cpu(p->des3);
753a7109 AT	353
753a7109 AT	354	if (len1)
f8be0d78	355	p->des2 \|= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK));
753a7109 AT	356
753a7109 AT	357	if (len2)
f8be0d78 MW	358	p->des2 \|= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
f8be0d78 MW	359	& TDES2_BUFFER2_SIZE_MASK);
753a7109 AT	360
	361	if (is_fs) {
	362	tdes3 \|= TDES3_FIRST_DESCRIPTOR \|
	363	TDES3_TCP_SEGMENTATION_ENABLE \|
	364	((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
	365	TDES3_SLOT_NUMBER_MASK) \|
	366	((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
	367	} else {
	368	tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
	369	}
	370
	371	if (ls)
	372	tdes3 \|= TDES3_LAST_DESCRIPTOR;
	373	else
	374	tdes3 &= ~TDES3_LAST_DESCRIPTOR;
	375
	376	/* Finally set the OWN bit. Later the DMA will start! */
	377	if (tx_own)
	378	tdes3 \|= TDES3_OWN;
	379
	380	if (is_fs & tx_own)
	381	/* When the own bit, for the first frame, has to be set, all
	382	* descriptors for the same frame has to be set before, to
	383	* avoid race condition.
	384	*/
ad688cdb	385	dma_wmb();
753a7109	386
f8be0d78	387	p->des3 = cpu_to_le32(tdes3);
753a7109 AT	388	}
	389
	390	static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)
	391	{
	392	p->des2 = 0;
	393	p->des3 = 0;
	394	}
	395
	396	static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
	397	{
f8be0d78	398	p->des2 \|= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION);
753a7109 AT	399	}
	400
	401	static void dwmac4_display_ring(void *head, unsigned int size, bool rx)
	402	{
	403	struct dma_desc p = (struct dma_desc )head;
	404	int i;
	405
	406	pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
	407
	408	for (i = 0; i < size; i++) {
8be0328e GC	409	pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
8be0328e GC	410	i, (unsigned int)virt_to_phys(p),
f8be0d78 MW	411	le32_to_cpu(p->des0), le32_to_cpu(p->des1),
f8be0d78 MW	412	le32_to_cpu(p->des2), le32_to_cpu(p->des3));
753a7109 AT	413	p++;
	414	}
	415	}
	416
	417	static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
	418	{
	419	p->des0 = 0;
	420	p->des1 = 0;
f8be0d78 MW	421	p->des2 = cpu_to_le32(mss);
f8be0d78 MW	422	p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE \| TDES3_CTXT_TCMSSV);
753a7109 AT	423	}
	424
	425	const struct stmmac_desc_ops dwmac4_desc_ops = {
	426	.tx_status = dwmac4_wrback_get_tx_status,
	427	.rx_status = dwmac4_wrback_get_rx_status,
	428	.get_tx_len = dwmac4_rd_get_tx_len,
	429	.get_tx_owner = dwmac4_get_tx_owner,
	430	.set_tx_owner = dwmac4_set_tx_owner,
	431	.set_rx_owner = dwmac4_set_rx_owner,
	432	.get_tx_ls = dwmac4_get_tx_ls,
	433	.get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
	434	.enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
	435	.get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
ba1ffd74 GC	436	.get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
ba1ffd74 GC	437	.get_timestamp = dwmac4_get_timestamp,
753a7109 AT	438	.set_tx_ic = dwmac4_rd_set_tx_ic,
	439	.prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
	440	.prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
	441	.release_tx_desc = dwmac4_release_tx_desc,
	442	.init_rx_desc = dwmac4_rd_init_rx_desc,
	443	.init_tx_desc = dwmac4_rd_init_tx_desc,
	444	.display_ring = dwmac4_display_ring,
	445	.set_mss = dwmac4_set_mss_ctxt,
	446	};
	447
	448	const struct stmmac_mode_ops dwmac4_ring_mode_ops = { };