Commit | Line | Data |
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477286b5 AT |
1 | /* |
2 | * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. | |
3 | * DWC Ether MAC version 4.00 has been used for developing this code. | |
4 | * | |
5 | * This only implements the mac core functions for this chip. | |
6 | * | |
7 | * Copyright (C) 2015 STMicroelectronics Ltd | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2, as published by the Free Software Foundation. | |
12 | * | |
13 | * Author: Alexandre Torgue <alexandre.torgue@st.com> | |
14 | */ | |
15 | ||
16 | #include <linux/crc32.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/ethtool.h> | |
19 | #include <linux/io.h> | |
70523e63 | 20 | #include "stmmac_pcs.h" |
477286b5 AT |
21 | #include "dwmac4.h" |
22 | ||
23 | static void dwmac4_core_init(struct mac_device_info *hw, int mtu) | |
24 | { | |
25 | void __iomem *ioaddr = hw->pcsr; | |
26 | u32 value = readl(ioaddr + GMAC_CONFIG); | |
27 | ||
28 | value |= GMAC_CORE_INIT; | |
29 | ||
30 | if (mtu > 1500) | |
31 | value |= GMAC_CONFIG_2K; | |
32 | if (mtu > 2000) | |
33 | value |= GMAC_CONFIG_JE; | |
34 | ||
02e57b9d GC |
35 | if (hw->ps) { |
36 | value |= GMAC_CONFIG_TE; | |
37 | ||
38 | if (hw->ps == SPEED_1000) { | |
39 | value &= ~GMAC_CONFIG_PS; | |
40 | } else { | |
41 | value |= GMAC_CONFIG_PS; | |
42 | ||
43 | if (hw->ps == SPEED_10) | |
44 | value &= ~GMAC_CONFIG_FES; | |
45 | else | |
46 | value |= GMAC_CONFIG_FES; | |
47 | } | |
48 | } | |
49 | ||
477286b5 AT |
50 | writel(value, ioaddr + GMAC_CONFIG); |
51 | ||
52 | /* Mask GMAC interrupts */ | |
3fe5cadb GC |
53 | value = GMAC_INT_DEFAULT_MASK; |
54 | if (hw->pmt) | |
55 | value |= GMAC_INT_PMT_EN; | |
56 | if (hw->pcs) | |
57 | value |= GMAC_PCS_IRQ_DEFAULT; | |
58 | ||
59 | writel(value, ioaddr + GMAC_INT_EN); | |
477286b5 AT |
60 | } |
61 | ||
4f6046f5 JP |
62 | static void dwmac4_rx_queue_enable(struct mac_device_info *hw, |
63 | u8 mode, u32 queue) | |
9eb12474 | 64 | { |
65 | void __iomem *ioaddr = hw->pcsr; | |
66 | u32 value = readl(ioaddr + GMAC_RXQ_CTRL0); | |
67 | ||
68 | value &= GMAC_RX_QUEUE_CLEAR(queue); | |
19d91873 | 69 | if (mode == MTL_QUEUE_AVB) |
4f6046f5 | 70 | value |= GMAC_RX_AV_QUEUE_ENABLE(queue); |
19d91873 | 71 | else if (mode == MTL_QUEUE_DCB) |
4f6046f5 | 72 | value |= GMAC_RX_DCB_QUEUE_ENABLE(queue); |
9eb12474 | 73 | |
74 | writel(value, ioaddr + GMAC_RXQ_CTRL0); | |
75 | } | |
76 | ||
a8f5102a JP |
77 | static void dwmac4_rx_queue_priority(struct mac_device_info *hw, |
78 | u32 prio, u32 queue) | |
79 | { | |
80 | void __iomem *ioaddr = hw->pcsr; | |
81 | u32 base_register; | |
82 | u32 value; | |
83 | ||
84 | base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3; | |
85 | ||
86 | value = readl(ioaddr + base_register); | |
87 | ||
88 | value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue); | |
89 | value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) & | |
90 | GMAC_RXQCTRL_PSRQX_MASK(queue); | |
91 | writel(value, ioaddr + base_register); | |
92 | } | |
93 | ||
94 | static void dwmac4_tx_queue_priority(struct mac_device_info *hw, | |
95 | u32 prio, u32 queue) | |
96 | { | |
97 | void __iomem *ioaddr = hw->pcsr; | |
98 | u32 base_register; | |
99 | u32 value; | |
100 | ||
101 | base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1; | |
102 | ||
103 | value = readl(ioaddr + base_register); | |
104 | ||
105 | value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue); | |
106 | value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) & | |
107 | GMAC_TXQCTRL_PSTQX_MASK(queue); | |
108 | ||
109 | writel(value, ioaddr + base_register); | |
110 | } | |
111 | ||
abe80fdc JP |
112 | static void dwmac4_tx_queue_routing(struct mac_device_info *hw, |
113 | u8 packet, u32 queue) | |
114 | { | |
115 | void __iomem *ioaddr = hw->pcsr; | |
116 | u32 value; | |
117 | ||
118 | const struct stmmac_rx_routing route_possibilities[] = { | |
119 | { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT }, | |
120 | { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT }, | |
121 | { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT }, | |
122 | { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT }, | |
123 | { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT }, | |
124 | }; | |
125 | ||
126 | value = readl(ioaddr + GMAC_RXQ_CTRL1); | |
127 | ||
128 | /* routing configuration */ | |
129 | value &= ~route_possibilities[packet - 1].reg_mask; | |
130 | value |= (queue << route_possibilities[packet-1].reg_shift) & | |
131 | route_possibilities[packet - 1].reg_mask; | |
132 | ||
133 | /* some packets require extra ops */ | |
134 | if (packet == PACKET_AVCPQ) { | |
135 | value &= ~GMAC_RXQCTRL_TACPQE; | |
136 | value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT; | |
137 | } else if (packet == PACKET_MCBCQ) { | |
138 | value &= ~GMAC_RXQCTRL_MCBCQEN; | |
139 | value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT; | |
140 | } | |
141 | ||
142 | writel(value, ioaddr + GMAC_RXQ_CTRL1); | |
143 | } | |
144 | ||
d0a9c9f9 JP |
145 | static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw, |
146 | u32 rx_alg) | |
147 | { | |
148 | void __iomem *ioaddr = hw->pcsr; | |
149 | u32 value = readl(ioaddr + MTL_OPERATION_MODE); | |
150 | ||
151 | value &= ~MTL_OPERATION_RAA; | |
152 | switch (rx_alg) { | |
153 | case MTL_RX_ALGORITHM_SP: | |
154 | value |= MTL_OPERATION_RAA_SP; | |
155 | break; | |
156 | case MTL_RX_ALGORITHM_WSP: | |
157 | value |= MTL_OPERATION_RAA_WSP; | |
158 | break; | |
159 | default: | |
160 | break; | |
161 | } | |
162 | ||
163 | writel(value, ioaddr + MTL_OPERATION_MODE); | |
164 | } | |
165 | ||
166 | static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw, | |
167 | u32 tx_alg) | |
168 | { | |
169 | void __iomem *ioaddr = hw->pcsr; | |
170 | u32 value = readl(ioaddr + MTL_OPERATION_MODE); | |
171 | ||
172 | value &= ~MTL_OPERATION_SCHALG_MASK; | |
173 | switch (tx_alg) { | |
174 | case MTL_TX_ALGORITHM_WRR: | |
175 | value |= MTL_OPERATION_SCHALG_WRR; | |
176 | break; | |
177 | case MTL_TX_ALGORITHM_WFQ: | |
178 | value |= MTL_OPERATION_SCHALG_WFQ; | |
179 | break; | |
180 | case MTL_TX_ALGORITHM_DWRR: | |
181 | value |= MTL_OPERATION_SCHALG_DWRR; | |
182 | break; | |
183 | case MTL_TX_ALGORITHM_SP: | |
184 | value |= MTL_OPERATION_SCHALG_SP; | |
185 | break; | |
186 | default: | |
187 | break; | |
188 | } | |
189 | } | |
190 | ||
6a3a7193 JP |
191 | static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw, |
192 | u32 weight, u32 queue) | |
193 | { | |
194 | void __iomem *ioaddr = hw->pcsr; | |
195 | u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue)); | |
196 | ||
197 | value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK; | |
198 | value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK; | |
199 | writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue)); | |
200 | } | |
201 | ||
d43042f4 JP |
202 | static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan) |
203 | { | |
204 | void __iomem *ioaddr = hw->pcsr; | |
205 | u32 value; | |
206 | ||
207 | if (queue < 4) | |
208 | value = readl(ioaddr + MTL_RXQ_DMA_MAP0); | |
209 | else | |
210 | value = readl(ioaddr + MTL_RXQ_DMA_MAP1); | |
211 | ||
212 | if (queue == 0 || queue == 4) { | |
213 | value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK; | |
214 | value |= MTL_RXQ_DMA_Q04MDMACH(chan); | |
215 | } else { | |
216 | value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue); | |
217 | value |= MTL_RXQ_DMA_QXMDMACH(chan, queue); | |
218 | } | |
219 | ||
220 | if (queue < 4) | |
221 | writel(value, ioaddr + MTL_RXQ_DMA_MAP0); | |
222 | else | |
223 | writel(value, ioaddr + MTL_RXQ_DMA_MAP1); | |
224 | } | |
225 | ||
19d91873 JP |
226 | static void dwmac4_config_cbs(struct mac_device_info *hw, |
227 | u32 send_slope, u32 idle_slope, | |
228 | u32 high_credit, u32 low_credit, u32 queue) | |
229 | { | |
230 | void __iomem *ioaddr = hw->pcsr; | |
231 | u32 value; | |
232 | ||
233 | pr_debug("Queue %d configured as AVB. Parameters:\n", queue); | |
234 | pr_debug("\tsend_slope: 0x%08x\n", send_slope); | |
235 | pr_debug("\tidle_slope: 0x%08x\n", idle_slope); | |
236 | pr_debug("\thigh_credit: 0x%08x\n", high_credit); | |
237 | pr_debug("\tlow_credit: 0x%08x\n", low_credit); | |
238 | ||
239 | /* enable AV algorithm */ | |
240 | value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue)); | |
241 | value |= MTL_ETS_CTRL_AVALG; | |
242 | value |= MTL_ETS_CTRL_CC; | |
243 | writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue)); | |
244 | ||
245 | /* configure send slope */ | |
246 | value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue)); | |
247 | value &= ~MTL_SEND_SLP_CRED_SSC_MASK; | |
248 | value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK; | |
249 | writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue)); | |
250 | ||
251 | /* configure idle slope (same register as tx weight) */ | |
252 | dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue); | |
253 | ||
254 | /* configure high credit */ | |
255 | value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue)); | |
256 | value &= ~MTL_HIGH_CRED_HC_MASK; | |
257 | value |= high_credit & MTL_HIGH_CRED_HC_MASK; | |
258 | writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue)); | |
259 | ||
260 | /* configure high credit */ | |
261 | value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue)); | |
262 | value &= ~MTL_HIGH_CRED_LC_MASK; | |
263 | value |= low_credit & MTL_HIGH_CRED_LC_MASK; | |
264 | writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue)); | |
265 | } | |
266 | ||
fbf68229 | 267 | static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space) |
477286b5 AT |
268 | { |
269 | void __iomem *ioaddr = hw->pcsr; | |
270 | int i; | |
271 | ||
fbf68229 LC |
272 | for (i = 0; i < GMAC_REG_NUM; i++) |
273 | reg_space[i] = readl(ioaddr + i * 4); | |
477286b5 AT |
274 | } |
275 | ||
276 | static int dwmac4_rx_ipc_enable(struct mac_device_info *hw) | |
277 | { | |
278 | void __iomem *ioaddr = hw->pcsr; | |
279 | u32 value = readl(ioaddr + GMAC_CONFIG); | |
280 | ||
281 | if (hw->rx_csum) | |
282 | value |= GMAC_CONFIG_IPC; | |
283 | else | |
284 | value &= ~GMAC_CONFIG_IPC; | |
285 | ||
286 | writel(value, ioaddr + GMAC_CONFIG); | |
287 | ||
288 | value = readl(ioaddr + GMAC_CONFIG); | |
289 | ||
290 | return !!(value & GMAC_CONFIG_IPC); | |
291 | } | |
292 | ||
293 | static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode) | |
294 | { | |
295 | void __iomem *ioaddr = hw->pcsr; | |
296 | unsigned int pmt = 0; | |
297 | ||
298 | if (mode & WAKE_MAGIC) { | |
299 | pr_debug("GMAC: WOL Magic frame\n"); | |
300 | pmt |= power_down | magic_pkt_en; | |
301 | } | |
302 | if (mode & WAKE_UCAST) { | |
303 | pr_debug("GMAC: WOL on global unicast\n"); | |
19cd1203 | 304 | pmt |= power_down | global_unicast | wake_up_frame_en; |
477286b5 AT |
305 | } |
306 | ||
307 | writel(pmt, ioaddr + GMAC_PMT); | |
308 | } | |
309 | ||
310 | static void dwmac4_set_umac_addr(struct mac_device_info *hw, | |
311 | unsigned char *addr, unsigned int reg_n) | |
312 | { | |
313 | void __iomem *ioaddr = hw->pcsr; | |
314 | ||
315 | stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), | |
316 | GMAC_ADDR_LOW(reg_n)); | |
317 | } | |
318 | ||
319 | static void dwmac4_get_umac_addr(struct mac_device_info *hw, | |
320 | unsigned char *addr, unsigned int reg_n) | |
321 | { | |
322 | void __iomem *ioaddr = hw->pcsr; | |
323 | ||
324 | stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), | |
325 | GMAC_ADDR_LOW(reg_n)); | |
326 | } | |
327 | ||
b4b7b772 | 328 | static void dwmac4_set_eee_mode(struct mac_device_info *hw, |
329 | bool en_tx_lpi_clockgating) | |
afbb1674 | 330 | { |
331 | void __iomem *ioaddr = hw->pcsr; | |
332 | u32 value; | |
333 | ||
334 | /* Enable the link status receive on RGMII, SGMII ore SMII | |
335 | * receive path and instruct the transmit to enter in LPI | |
336 | * state. | |
337 | */ | |
338 | value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS); | |
339 | value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA; | |
340 | ||
b4b7b772 | 341 | if (en_tx_lpi_clockgating) |
342 | value |= GMAC4_LPI_CTRL_STATUS_LPITCSE; | |
343 | ||
afbb1674 | 344 | writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS); |
345 | } | |
346 | ||
347 | static void dwmac4_reset_eee_mode(struct mac_device_info *hw) | |
348 | { | |
349 | void __iomem *ioaddr = hw->pcsr; | |
350 | u32 value; | |
351 | ||
352 | value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS); | |
353 | value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA); | |
354 | writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS); | |
355 | } | |
356 | ||
357 | static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link) | |
358 | { | |
359 | void __iomem *ioaddr = hw->pcsr; | |
360 | u32 value; | |
361 | ||
362 | value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS); | |
363 | ||
364 | if (link) | |
365 | value |= GMAC4_LPI_CTRL_STATUS_PLS; | |
366 | else | |
367 | value &= ~GMAC4_LPI_CTRL_STATUS_PLS; | |
368 | ||
369 | writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS); | |
370 | } | |
371 | ||
372 | static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw) | |
373 | { | |
374 | void __iomem *ioaddr = hw->pcsr; | |
f4ec6064 | 375 | int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16); |
afbb1674 | 376 | |
377 | /* Program the timers in the LPI timer control register: | |
378 | * LS: minimum time (ms) for which the link | |
379 | * status from PHY should be ok before transmitting | |
380 | * the LPI pattern. | |
381 | * TW: minimum time (us) for which the core waits | |
382 | * after it has stopped transmitting the LPI pattern. | |
383 | */ | |
384 | writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL); | |
385 | } | |
386 | ||
477286b5 AT |
387 | static void dwmac4_set_filter(struct mac_device_info *hw, |
388 | struct net_device *dev) | |
389 | { | |
390 | void __iomem *ioaddr = (void __iomem *)dev->base_addr; | |
391 | unsigned int value = 0; | |
392 | ||
393 | if (dev->flags & IFF_PROMISC) { | |
394 | value = GMAC_PACKET_FILTER_PR; | |
395 | } else if ((dev->flags & IFF_ALLMULTI) || | |
396 | (netdev_mc_count(dev) > HASH_TABLE_SIZE)) { | |
397 | /* Pass all multi */ | |
398 | value = GMAC_PACKET_FILTER_PM; | |
399 | /* Set the 64 bits of the HASH tab. To be updated if taller | |
400 | * hash table is used | |
401 | */ | |
402 | writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31); | |
403 | writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63); | |
404 | } else if (!netdev_mc_empty(dev)) { | |
405 | u32 mc_filter[2]; | |
406 | struct netdev_hw_addr *ha; | |
407 | ||
408 | /* Hash filter for multicast */ | |
409 | value = GMAC_PACKET_FILTER_HMC; | |
410 | ||
411 | memset(mc_filter, 0, sizeof(mc_filter)); | |
412 | netdev_for_each_mc_addr(ha, dev) { | |
413 | /* The upper 6 bits of the calculated CRC are used to | |
414 | * index the content of the Hash Table Reg 0 and 1. | |
415 | */ | |
416 | int bit_nr = | |
417 | (bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26); | |
418 | /* The most significant bit determines the register | |
419 | * to use while the other 5 bits determines the bit | |
420 | * within the selected register | |
421 | */ | |
422 | mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F)); | |
423 | } | |
424 | writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31); | |
425 | writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63); | |
426 | } | |
427 | ||
428 | /* Handle multiple unicast addresses */ | |
429 | if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) { | |
430 | /* Switch to promiscuous mode if more than 128 addrs | |
431 | * are required | |
432 | */ | |
433 | value |= GMAC_PACKET_FILTER_PR; | |
434 | } else if (!netdev_uc_empty(dev)) { | |
435 | int reg = 1; | |
436 | struct netdev_hw_addr *ha; | |
437 | ||
438 | netdev_for_each_uc_addr(ha, dev) { | |
ca8bdaf1 | 439 | dwmac4_set_umac_addr(hw, ha->addr, reg); |
477286b5 AT |
440 | reg++; |
441 | } | |
442 | } | |
443 | ||
444 | writel(value, ioaddr + GMAC_PACKET_FILTER); | |
445 | } | |
446 | ||
447 | static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex, | |
29feff39 JP |
448 | unsigned int fc, unsigned int pause_time, |
449 | u32 tx_cnt) | |
477286b5 AT |
450 | { |
451 | void __iomem *ioaddr = hw->pcsr; | |
477286b5 | 452 | unsigned int flow = 0; |
29feff39 | 453 | u32 queue = 0; |
477286b5 AT |
454 | |
455 | pr_debug("GMAC Flow-Control:\n"); | |
456 | if (fc & FLOW_RX) { | |
457 | pr_debug("\tReceive Flow-Control ON\n"); | |
458 | flow |= GMAC_RX_FLOW_CTRL_RFE; | |
459 | writel(flow, ioaddr + GMAC_RX_FLOW_CTRL); | |
460 | } | |
461 | if (fc & FLOW_TX) { | |
462 | pr_debug("\tTransmit Flow-Control ON\n"); | |
477286b5 | 463 | |
29feff39 | 464 | if (duplex) |
477286b5 | 465 | pr_debug("\tduplex mode: PAUSE %d\n", pause_time); |
29feff39 JP |
466 | |
467 | for (queue = 0; queue < tx_cnt; queue++) { | |
468 | flow |= GMAC_TX_FLOW_CTRL_TFE; | |
469 | ||
470 | if (duplex) | |
471 | flow |= | |
472 | (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT); | |
473 | ||
474 | writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue)); | |
477286b5 AT |
475 | } |
476 | } | |
477 | } | |
478 | ||
70523e63 GC |
479 | static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral, |
480 | bool loopback) | |
477286b5 | 481 | { |
70523e63 GC |
482 | dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback); |
483 | } | |
477286b5 | 484 | |
70523e63 GC |
485 | static void dwmac4_rane(void __iomem *ioaddr, bool restart) |
486 | { | |
487 | dwmac_rane(ioaddr, GMAC_PCS_BASE, restart); | |
488 | } | |
477286b5 | 489 | |
70523e63 GC |
490 | static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv) |
491 | { | |
492 | dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv); | |
477286b5 AT |
493 | } |
494 | ||
70523e63 GC |
495 | /* RGMII or SMII interface */ |
496 | static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x) | |
477286b5 | 497 | { |
70523e63 | 498 | u32 status; |
477286b5 | 499 | |
70523e63 GC |
500 | status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS); |
501 | x->irq_rgmii_n++; | |
477286b5 | 502 | |
70523e63 GC |
503 | /* Check the link status */ |
504 | if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) { | |
505 | int speed_value; | |
477286b5 | 506 | |
70523e63 | 507 | x->pcs_link = 1; |
477286b5 | 508 | |
70523e63 GC |
509 | speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >> |
510 | GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT); | |
511 | if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125) | |
512 | x->pcs_speed = SPEED_1000; | |
513 | else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25) | |
514 | x->pcs_speed = SPEED_100; | |
515 | else | |
516 | x->pcs_speed = SPEED_10; | |
517 | ||
518 | x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK); | |
477286b5 | 519 | |
70523e63 GC |
520 | pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed, |
521 | x->pcs_duplex ? "Full" : "Half"); | |
522 | } else { | |
523 | x->pcs_link = 0; | |
524 | pr_info("Link is Down\n"); | |
525 | } | |
477286b5 AT |
526 | } |
527 | ||
8f71a88d JP |
528 | static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan) |
529 | { | |
530 | void __iomem *ioaddr = hw->pcsr; | |
531 | u32 mtl_int_qx_status; | |
532 | int ret = 0; | |
533 | ||
534 | mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS); | |
535 | ||
536 | /* Check MTL Interrupt */ | |
537 | if (mtl_int_qx_status & MTL_INT_QX(chan)) { | |
538 | /* read Queue x Interrupt status */ | |
539 | u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan)); | |
540 | ||
541 | if (status & MTL_RX_OVERFLOW_INT) { | |
542 | /* clear Interrupt */ | |
543 | writel(status | MTL_RX_OVERFLOW_INT, | |
544 | ioaddr + MTL_CHAN_INT_CTRL(chan)); | |
545 | ret = CORE_IRQ_MTL_RX_OVERFLOW; | |
546 | } | |
547 | } | |
548 | ||
549 | return ret; | |
550 | } | |
551 | ||
477286b5 AT |
552 | static int dwmac4_irq_status(struct mac_device_info *hw, |
553 | struct stmmac_extra_stats *x) | |
554 | { | |
555 | void __iomem *ioaddr = hw->pcsr; | |
477286b5 AT |
556 | u32 intr_status; |
557 | int ret = 0; | |
558 | ||
559 | intr_status = readl(ioaddr + GMAC_INT_STATUS); | |
560 | ||
561 | /* Not used events (e.g. MMC interrupts) are not handled. */ | |
562 | if ((intr_status & mmc_tx_irq)) | |
563 | x->mmc_tx_irq_n++; | |
564 | if (unlikely(intr_status & mmc_rx_irq)) | |
565 | x->mmc_rx_irq_n++; | |
566 | if (unlikely(intr_status & mmc_rx_csum_offload_irq)) | |
567 | x->mmc_rx_csum_offload_irq_n++; | |
568 | /* Clear the PMT bits 5 and 6 by reading the PMT status reg */ | |
569 | if (unlikely(intr_status & pmt_irq)) { | |
570 | readl(ioaddr + GMAC_PMT); | |
571 | x->irq_receive_pmt_irq_n++; | |
572 | } | |
573 | ||
70523e63 GC |
574 | dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x); |
575 | if (intr_status & PCS_RGSMIIIS_IRQ) | |
576 | dwmac4_phystatus(ioaddr, x); | |
577 | ||
477286b5 AT |
578 | return ret; |
579 | } | |
580 | ||
ad5a87d7 JP |
581 | static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x, |
582 | u32 rx_queues, u32 tx_queues) | |
477286b5 AT |
583 | { |
584 | u32 value; | |
ad5a87d7 JP |
585 | u32 queue; |
586 | ||
587 | for (queue = 0; queue < tx_queues; queue++) { | |
588 | value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue)); | |
589 | ||
590 | if (value & MTL_DEBUG_TXSTSFSTS) | |
591 | x->mtl_tx_status_fifo_full++; | |
592 | if (value & MTL_DEBUG_TXFSTS) | |
593 | x->mtl_tx_fifo_not_empty++; | |
594 | if (value & MTL_DEBUG_TWCSTS) | |
595 | x->mmtl_fifo_ctrl++; | |
596 | if (value & MTL_DEBUG_TRCSTS_MASK) { | |
597 | u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK) | |
598 | >> MTL_DEBUG_TRCSTS_SHIFT; | |
599 | if (trcsts == MTL_DEBUG_TRCSTS_WRITE) | |
600 | x->mtl_tx_fifo_read_ctrl_write++; | |
601 | else if (trcsts == MTL_DEBUG_TRCSTS_TXW) | |
602 | x->mtl_tx_fifo_read_ctrl_wait++; | |
603 | else if (trcsts == MTL_DEBUG_TRCSTS_READ) | |
604 | x->mtl_tx_fifo_read_ctrl_read++; | |
605 | else | |
606 | x->mtl_tx_fifo_read_ctrl_idle++; | |
607 | } | |
608 | if (value & MTL_DEBUG_TXPAUSED) | |
609 | x->mac_tx_in_pause++; | |
477286b5 | 610 | } |
477286b5 | 611 | |
ad5a87d7 JP |
612 | for (queue = 0; queue < rx_queues; queue++) { |
613 | value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue)); | |
477286b5 | 614 | |
ad5a87d7 JP |
615 | if (value & MTL_DEBUG_RXFSTS_MASK) { |
616 | u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK) | |
617 | >> MTL_DEBUG_RRCSTS_SHIFT; | |
477286b5 | 618 | |
ad5a87d7 JP |
619 | if (rxfsts == MTL_DEBUG_RXFSTS_FULL) |
620 | x->mtl_rx_fifo_fill_level_full++; | |
621 | else if (rxfsts == MTL_DEBUG_RXFSTS_AT) | |
622 | x->mtl_rx_fifo_fill_above_thresh++; | |
623 | else if (rxfsts == MTL_DEBUG_RXFSTS_BT) | |
624 | x->mtl_rx_fifo_fill_below_thresh++; | |
625 | else | |
626 | x->mtl_rx_fifo_fill_level_empty++; | |
627 | } | |
628 | if (value & MTL_DEBUG_RRCSTS_MASK) { | |
629 | u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >> | |
630 | MTL_DEBUG_RRCSTS_SHIFT; | |
631 | ||
632 | if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH) | |
633 | x->mtl_rx_fifo_read_ctrl_flush++; | |
634 | else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT) | |
635 | x->mtl_rx_fifo_read_ctrl_read_data++; | |
636 | else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA) | |
637 | x->mtl_rx_fifo_read_ctrl_status++; | |
638 | else | |
639 | x->mtl_rx_fifo_read_ctrl_idle++; | |
640 | } | |
641 | if (value & MTL_DEBUG_RWCSTS) | |
642 | x->mtl_rx_fifo_ctrl_active++; | |
477286b5 | 643 | } |
477286b5 AT |
644 | |
645 | /* GMAC debug */ | |
646 | value = readl(ioaddr + GMAC_DEBUG); | |
647 | ||
648 | if (value & GMAC_DEBUG_TFCSTS_MASK) { | |
649 | u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK) | |
650 | >> GMAC_DEBUG_TFCSTS_SHIFT; | |
651 | ||
652 | if (tfcsts == GMAC_DEBUG_TFCSTS_XFER) | |
653 | x->mac_tx_frame_ctrl_xfer++; | |
654 | else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE) | |
655 | x->mac_tx_frame_ctrl_pause++; | |
656 | else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT) | |
657 | x->mac_tx_frame_ctrl_wait++; | |
658 | else | |
659 | x->mac_tx_frame_ctrl_idle++; | |
660 | } | |
661 | if (value & GMAC_DEBUG_TPESTS) | |
662 | x->mac_gmii_tx_proto_engine++; | |
663 | if (value & GMAC_DEBUG_RFCFCSTS_MASK) | |
664 | x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK) | |
665 | >> GMAC_DEBUG_RFCFCSTS_SHIFT; | |
666 | if (value & GMAC_DEBUG_RPESTS) | |
667 | x->mac_gmii_rx_proto_engine++; | |
668 | } | |
669 | ||
670 | static const struct stmmac_ops dwmac4_ops = { | |
671 | .core_init = dwmac4_core_init, | |
672 | .rx_ipc = dwmac4_rx_ipc_enable, | |
9eb12474 | 673 | .rx_queue_enable = dwmac4_rx_queue_enable, |
a8f5102a JP |
674 | .rx_queue_prio = dwmac4_rx_queue_priority, |
675 | .tx_queue_prio = dwmac4_tx_queue_priority, | |
abe80fdc | 676 | .rx_queue_routing = dwmac4_tx_queue_routing, |
d0a9c9f9 JP |
677 | .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms, |
678 | .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms, | |
6a3a7193 | 679 | .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight, |
d43042f4 | 680 | .map_mtl_to_dma = dwmac4_map_mtl_dma, |
19d91873 | 681 | .config_cbs = dwmac4_config_cbs, |
477286b5 AT |
682 | .dump_regs = dwmac4_dump_regs, |
683 | .host_irq_status = dwmac4_irq_status, | |
8f71a88d | 684 | .host_mtl_irq_status = dwmac4_irq_mtl_status, |
477286b5 AT |
685 | .flow_ctrl = dwmac4_flow_ctrl, |
686 | .pmt = dwmac4_pmt, | |
687 | .set_umac_addr = dwmac4_set_umac_addr, | |
688 | .get_umac_addr = dwmac4_get_umac_addr, | |
afbb1674 | 689 | .set_eee_mode = dwmac4_set_eee_mode, |
690 | .reset_eee_mode = dwmac4_reset_eee_mode, | |
691 | .set_eee_timer = dwmac4_set_eee_timer, | |
692 | .set_eee_pls = dwmac4_set_eee_pls, | |
70523e63 GC |
693 | .pcs_ctrl_ane = dwmac4_ctrl_ane, |
694 | .pcs_rane = dwmac4_rane, | |
695 | .pcs_get_adv_lp = dwmac4_get_adv_lp, | |
477286b5 AT |
696 | .debug = dwmac4_debug, |
697 | .set_filter = dwmac4_set_filter, | |
698 | }; | |
699 | ||
700 | struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins, | |
701 | int perfect_uc_entries, int *synopsys_id) | |
702 | { | |
703 | struct mac_device_info *mac; | |
704 | u32 hwid = readl(ioaddr + GMAC_VERSION); | |
705 | ||
706 | mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL); | |
707 | if (!mac) | |
708 | return NULL; | |
709 | ||
710 | mac->pcsr = ioaddr; | |
711 | mac->multicast_filter_bins = mcbins; | |
712 | mac->unicast_filter_entries = perfect_uc_entries; | |
713 | mac->mcast_bits_log2 = 0; | |
714 | ||
715 | if (mac->multicast_filter_bins) | |
716 | mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins); | |
717 | ||
718 | mac->mac = &dwmac4_ops; | |
719 | ||
720 | mac->link.port = GMAC_CONFIG_PS; | |
721 | mac->link.duplex = GMAC_CONFIG_DM; | |
722 | mac->link.speed = GMAC_CONFIG_FES; | |
723 | mac->mii.addr = GMAC_MDIO_ADDR; | |
724 | mac->mii.data = GMAC_MDIO_DATA; | |
b91dce4c LC |
725 | mac->mii.addr_shift = 21; |
726 | mac->mii.addr_mask = GENMASK(25, 21); | |
727 | mac->mii.reg_shift = 16; | |
728 | mac->mii.reg_mask = GENMASK(20, 16); | |
729 | mac->mii.clk_csr_shift = 8; | |
730 | mac->mii.clk_csr_mask = GENMASK(11, 8); | |
477286b5 AT |
731 | |
732 | /* Get and dump the chip ID */ | |
733 | *synopsys_id = stmmac_get_synopsys_id(hwid); | |
734 | ||
735 | if (*synopsys_id > DWMAC_CORE_4_00) | |
736 | mac->dma = &dwmac410_dma_ops; | |
737 | else | |
738 | mac->dma = &dwmac4_dma_ops; | |
739 | ||
740 | return mac; | |
741 | } |