Commit | Line | Data |
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477286b5 AT |
1 | /* |
2 | * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. | |
3 | * DWC Ether MAC version 4.00 has been used for developing this code. | |
4 | * | |
5 | * This only implements the mac core functions for this chip. | |
6 | * | |
7 | * Copyright (C) 2015 STMicroelectronics Ltd | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2, as published by the Free Software Foundation. | |
12 | * | |
13 | * Author: Alexandre Torgue <alexandre.torgue@st.com> | |
14 | */ | |
15 | ||
16 | #include <linux/crc32.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/ethtool.h> | |
19 | #include <linux/io.h> | |
70523e63 | 20 | #include "stmmac_pcs.h" |
477286b5 AT |
21 | #include "dwmac4.h" |
22 | ||
23 | static void dwmac4_core_init(struct mac_device_info *hw, int mtu) | |
24 | { | |
25 | void __iomem *ioaddr = hw->pcsr; | |
26 | u32 value = readl(ioaddr + GMAC_CONFIG); | |
27 | ||
28 | value |= GMAC_CORE_INIT; | |
29 | ||
30 | if (mtu > 1500) | |
31 | value |= GMAC_CONFIG_2K; | |
32 | if (mtu > 2000) | |
33 | value |= GMAC_CONFIG_JE; | |
34 | ||
02e57b9d GC |
35 | if (hw->ps) { |
36 | value |= GMAC_CONFIG_TE; | |
37 | ||
38 | if (hw->ps == SPEED_1000) { | |
39 | value &= ~GMAC_CONFIG_PS; | |
40 | } else { | |
41 | value |= GMAC_CONFIG_PS; | |
42 | ||
43 | if (hw->ps == SPEED_10) | |
44 | value &= ~GMAC_CONFIG_FES; | |
45 | else | |
46 | value |= GMAC_CONFIG_FES; | |
47 | } | |
48 | } | |
49 | ||
477286b5 AT |
50 | writel(value, ioaddr + GMAC_CONFIG); |
51 | ||
52 | /* Mask GMAC interrupts */ | |
3fe5cadb GC |
53 | value = GMAC_INT_DEFAULT_MASK; |
54 | if (hw->pmt) | |
55 | value |= GMAC_INT_PMT_EN; | |
56 | if (hw->pcs) | |
57 | value |= GMAC_PCS_IRQ_DEFAULT; | |
58 | ||
59 | writel(value, ioaddr + GMAC_INT_EN); | |
477286b5 AT |
60 | } |
61 | ||
4f6046f5 JP |
62 | static void dwmac4_rx_queue_enable(struct mac_device_info *hw, |
63 | u8 mode, u32 queue) | |
9eb12474 | 64 | { |
65 | void __iomem *ioaddr = hw->pcsr; | |
66 | u32 value = readl(ioaddr + GMAC_RXQ_CTRL0); | |
67 | ||
68 | value &= GMAC_RX_QUEUE_CLEAR(queue); | |
4f6046f5 JP |
69 | if (mode == MTL_RX_AVB) |
70 | value |= GMAC_RX_AV_QUEUE_ENABLE(queue); | |
71 | else if (mode == MTL_RX_DCB) | |
72 | value |= GMAC_RX_DCB_QUEUE_ENABLE(queue); | |
9eb12474 | 73 | |
74 | writel(value, ioaddr + GMAC_RXQ_CTRL0); | |
75 | } | |
76 | ||
d0a9c9f9 JP |
77 | static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw, |
78 | u32 rx_alg) | |
79 | { | |
80 | void __iomem *ioaddr = hw->pcsr; | |
81 | u32 value = readl(ioaddr + MTL_OPERATION_MODE); | |
82 | ||
83 | value &= ~MTL_OPERATION_RAA; | |
84 | switch (rx_alg) { | |
85 | case MTL_RX_ALGORITHM_SP: | |
86 | value |= MTL_OPERATION_RAA_SP; | |
87 | break; | |
88 | case MTL_RX_ALGORITHM_WSP: | |
89 | value |= MTL_OPERATION_RAA_WSP; | |
90 | break; | |
91 | default: | |
92 | break; | |
93 | } | |
94 | ||
95 | writel(value, ioaddr + MTL_OPERATION_MODE); | |
96 | } | |
97 | ||
98 | static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw, | |
99 | u32 tx_alg) | |
100 | { | |
101 | void __iomem *ioaddr = hw->pcsr; | |
102 | u32 value = readl(ioaddr + MTL_OPERATION_MODE); | |
103 | ||
104 | value &= ~MTL_OPERATION_SCHALG_MASK; | |
105 | switch (tx_alg) { | |
106 | case MTL_TX_ALGORITHM_WRR: | |
107 | value |= MTL_OPERATION_SCHALG_WRR; | |
108 | break; | |
109 | case MTL_TX_ALGORITHM_WFQ: | |
110 | value |= MTL_OPERATION_SCHALG_WFQ; | |
111 | break; | |
112 | case MTL_TX_ALGORITHM_DWRR: | |
113 | value |= MTL_OPERATION_SCHALG_DWRR; | |
114 | break; | |
115 | case MTL_TX_ALGORITHM_SP: | |
116 | value |= MTL_OPERATION_SCHALG_SP; | |
117 | break; | |
118 | default: | |
119 | break; | |
120 | } | |
121 | } | |
122 | ||
6a3a7193 JP |
123 | static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw, |
124 | u32 weight, u32 queue) | |
125 | { | |
126 | void __iomem *ioaddr = hw->pcsr; | |
127 | u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue)); | |
128 | ||
129 | value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK; | |
130 | value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK; | |
131 | writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue)); | |
132 | } | |
133 | ||
d43042f4 JP |
134 | static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan) |
135 | { | |
136 | void __iomem *ioaddr = hw->pcsr; | |
137 | u32 value; | |
138 | ||
139 | if (queue < 4) | |
140 | value = readl(ioaddr + MTL_RXQ_DMA_MAP0); | |
141 | else | |
142 | value = readl(ioaddr + MTL_RXQ_DMA_MAP1); | |
143 | ||
144 | if (queue == 0 || queue == 4) { | |
145 | value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK; | |
146 | value |= MTL_RXQ_DMA_Q04MDMACH(chan); | |
147 | } else { | |
148 | value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue); | |
149 | value |= MTL_RXQ_DMA_QXMDMACH(chan, queue); | |
150 | } | |
151 | ||
152 | if (queue < 4) | |
153 | writel(value, ioaddr + MTL_RXQ_DMA_MAP0); | |
154 | else | |
155 | writel(value, ioaddr + MTL_RXQ_DMA_MAP1); | |
156 | } | |
157 | ||
fbf68229 | 158 | static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space) |
477286b5 AT |
159 | { |
160 | void __iomem *ioaddr = hw->pcsr; | |
161 | int i; | |
162 | ||
fbf68229 LC |
163 | for (i = 0; i < GMAC_REG_NUM; i++) |
164 | reg_space[i] = readl(ioaddr + i * 4); | |
477286b5 AT |
165 | } |
166 | ||
167 | static int dwmac4_rx_ipc_enable(struct mac_device_info *hw) | |
168 | { | |
169 | void __iomem *ioaddr = hw->pcsr; | |
170 | u32 value = readl(ioaddr + GMAC_CONFIG); | |
171 | ||
172 | if (hw->rx_csum) | |
173 | value |= GMAC_CONFIG_IPC; | |
174 | else | |
175 | value &= ~GMAC_CONFIG_IPC; | |
176 | ||
177 | writel(value, ioaddr + GMAC_CONFIG); | |
178 | ||
179 | value = readl(ioaddr + GMAC_CONFIG); | |
180 | ||
181 | return !!(value & GMAC_CONFIG_IPC); | |
182 | } | |
183 | ||
184 | static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode) | |
185 | { | |
186 | void __iomem *ioaddr = hw->pcsr; | |
187 | unsigned int pmt = 0; | |
188 | ||
189 | if (mode & WAKE_MAGIC) { | |
190 | pr_debug("GMAC: WOL Magic frame\n"); | |
191 | pmt |= power_down | magic_pkt_en; | |
192 | } | |
193 | if (mode & WAKE_UCAST) { | |
194 | pr_debug("GMAC: WOL on global unicast\n"); | |
19cd1203 | 195 | pmt |= power_down | global_unicast | wake_up_frame_en; |
477286b5 AT |
196 | } |
197 | ||
198 | writel(pmt, ioaddr + GMAC_PMT); | |
199 | } | |
200 | ||
201 | static void dwmac4_set_umac_addr(struct mac_device_info *hw, | |
202 | unsigned char *addr, unsigned int reg_n) | |
203 | { | |
204 | void __iomem *ioaddr = hw->pcsr; | |
205 | ||
206 | stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), | |
207 | GMAC_ADDR_LOW(reg_n)); | |
208 | } | |
209 | ||
210 | static void dwmac4_get_umac_addr(struct mac_device_info *hw, | |
211 | unsigned char *addr, unsigned int reg_n) | |
212 | { | |
213 | void __iomem *ioaddr = hw->pcsr; | |
214 | ||
215 | stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), | |
216 | GMAC_ADDR_LOW(reg_n)); | |
217 | } | |
218 | ||
b4b7b772 | 219 | static void dwmac4_set_eee_mode(struct mac_device_info *hw, |
220 | bool en_tx_lpi_clockgating) | |
afbb1674 | 221 | { |
222 | void __iomem *ioaddr = hw->pcsr; | |
223 | u32 value; | |
224 | ||
225 | /* Enable the link status receive on RGMII, SGMII ore SMII | |
226 | * receive path and instruct the transmit to enter in LPI | |
227 | * state. | |
228 | */ | |
229 | value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS); | |
230 | value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA; | |
231 | ||
b4b7b772 | 232 | if (en_tx_lpi_clockgating) |
233 | value |= GMAC4_LPI_CTRL_STATUS_LPITCSE; | |
234 | ||
afbb1674 | 235 | writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS); |
236 | } | |
237 | ||
238 | static void dwmac4_reset_eee_mode(struct mac_device_info *hw) | |
239 | { | |
240 | void __iomem *ioaddr = hw->pcsr; | |
241 | u32 value; | |
242 | ||
243 | value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS); | |
244 | value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA); | |
245 | writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS); | |
246 | } | |
247 | ||
248 | static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link) | |
249 | { | |
250 | void __iomem *ioaddr = hw->pcsr; | |
251 | u32 value; | |
252 | ||
253 | value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS); | |
254 | ||
255 | if (link) | |
256 | value |= GMAC4_LPI_CTRL_STATUS_PLS; | |
257 | else | |
258 | value &= ~GMAC4_LPI_CTRL_STATUS_PLS; | |
259 | ||
260 | writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS); | |
261 | } | |
262 | ||
263 | static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw) | |
264 | { | |
265 | void __iomem *ioaddr = hw->pcsr; | |
f4ec6064 | 266 | int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16); |
afbb1674 | 267 | |
268 | /* Program the timers in the LPI timer control register: | |
269 | * LS: minimum time (ms) for which the link | |
270 | * status from PHY should be ok before transmitting | |
271 | * the LPI pattern. | |
272 | * TW: minimum time (us) for which the core waits | |
273 | * after it has stopped transmitting the LPI pattern. | |
274 | */ | |
275 | writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL); | |
276 | } | |
277 | ||
477286b5 AT |
278 | static void dwmac4_set_filter(struct mac_device_info *hw, |
279 | struct net_device *dev) | |
280 | { | |
281 | void __iomem *ioaddr = (void __iomem *)dev->base_addr; | |
282 | unsigned int value = 0; | |
283 | ||
284 | if (dev->flags & IFF_PROMISC) { | |
285 | value = GMAC_PACKET_FILTER_PR; | |
286 | } else if ((dev->flags & IFF_ALLMULTI) || | |
287 | (netdev_mc_count(dev) > HASH_TABLE_SIZE)) { | |
288 | /* Pass all multi */ | |
289 | value = GMAC_PACKET_FILTER_PM; | |
290 | /* Set the 64 bits of the HASH tab. To be updated if taller | |
291 | * hash table is used | |
292 | */ | |
293 | writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31); | |
294 | writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63); | |
295 | } else if (!netdev_mc_empty(dev)) { | |
296 | u32 mc_filter[2]; | |
297 | struct netdev_hw_addr *ha; | |
298 | ||
299 | /* Hash filter for multicast */ | |
300 | value = GMAC_PACKET_FILTER_HMC; | |
301 | ||
302 | memset(mc_filter, 0, sizeof(mc_filter)); | |
303 | netdev_for_each_mc_addr(ha, dev) { | |
304 | /* The upper 6 bits of the calculated CRC are used to | |
305 | * index the content of the Hash Table Reg 0 and 1. | |
306 | */ | |
307 | int bit_nr = | |
308 | (bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26); | |
309 | /* The most significant bit determines the register | |
310 | * to use while the other 5 bits determines the bit | |
311 | * within the selected register | |
312 | */ | |
313 | mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F)); | |
314 | } | |
315 | writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31); | |
316 | writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63); | |
317 | } | |
318 | ||
319 | /* Handle multiple unicast addresses */ | |
320 | if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) { | |
321 | /* Switch to promiscuous mode if more than 128 addrs | |
322 | * are required | |
323 | */ | |
324 | value |= GMAC_PACKET_FILTER_PR; | |
325 | } else if (!netdev_uc_empty(dev)) { | |
326 | int reg = 1; | |
327 | struct netdev_hw_addr *ha; | |
328 | ||
329 | netdev_for_each_uc_addr(ha, dev) { | |
ca8bdaf1 | 330 | dwmac4_set_umac_addr(hw, ha->addr, reg); |
477286b5 AT |
331 | reg++; |
332 | } | |
333 | } | |
334 | ||
335 | writel(value, ioaddr + GMAC_PACKET_FILTER); | |
336 | } | |
337 | ||
338 | static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex, | |
29feff39 JP |
339 | unsigned int fc, unsigned int pause_time, |
340 | u32 tx_cnt) | |
477286b5 AT |
341 | { |
342 | void __iomem *ioaddr = hw->pcsr; | |
477286b5 | 343 | unsigned int flow = 0; |
29feff39 | 344 | u32 queue = 0; |
477286b5 AT |
345 | |
346 | pr_debug("GMAC Flow-Control:\n"); | |
347 | if (fc & FLOW_RX) { | |
348 | pr_debug("\tReceive Flow-Control ON\n"); | |
349 | flow |= GMAC_RX_FLOW_CTRL_RFE; | |
350 | writel(flow, ioaddr + GMAC_RX_FLOW_CTRL); | |
351 | } | |
352 | if (fc & FLOW_TX) { | |
353 | pr_debug("\tTransmit Flow-Control ON\n"); | |
477286b5 | 354 | |
29feff39 | 355 | if (duplex) |
477286b5 | 356 | pr_debug("\tduplex mode: PAUSE %d\n", pause_time); |
29feff39 JP |
357 | |
358 | for (queue = 0; queue < tx_cnt; queue++) { | |
359 | flow |= GMAC_TX_FLOW_CTRL_TFE; | |
360 | ||
361 | if (duplex) | |
362 | flow |= | |
363 | (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT); | |
364 | ||
365 | writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue)); | |
477286b5 AT |
366 | } |
367 | } | |
368 | } | |
369 | ||
70523e63 GC |
370 | static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral, |
371 | bool loopback) | |
477286b5 | 372 | { |
70523e63 GC |
373 | dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback); |
374 | } | |
477286b5 | 375 | |
70523e63 GC |
376 | static void dwmac4_rane(void __iomem *ioaddr, bool restart) |
377 | { | |
378 | dwmac_rane(ioaddr, GMAC_PCS_BASE, restart); | |
379 | } | |
477286b5 | 380 | |
70523e63 GC |
381 | static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv) |
382 | { | |
383 | dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv); | |
477286b5 AT |
384 | } |
385 | ||
70523e63 GC |
386 | /* RGMII or SMII interface */ |
387 | static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x) | |
477286b5 | 388 | { |
70523e63 | 389 | u32 status; |
477286b5 | 390 | |
70523e63 GC |
391 | status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS); |
392 | x->irq_rgmii_n++; | |
477286b5 | 393 | |
70523e63 GC |
394 | /* Check the link status */ |
395 | if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) { | |
396 | int speed_value; | |
477286b5 | 397 | |
70523e63 | 398 | x->pcs_link = 1; |
477286b5 | 399 | |
70523e63 GC |
400 | speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >> |
401 | GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT); | |
402 | if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125) | |
403 | x->pcs_speed = SPEED_1000; | |
404 | else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25) | |
405 | x->pcs_speed = SPEED_100; | |
406 | else | |
407 | x->pcs_speed = SPEED_10; | |
408 | ||
409 | x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK); | |
477286b5 | 410 | |
70523e63 GC |
411 | pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed, |
412 | x->pcs_duplex ? "Full" : "Half"); | |
413 | } else { | |
414 | x->pcs_link = 0; | |
415 | pr_info("Link is Down\n"); | |
416 | } | |
477286b5 AT |
417 | } |
418 | ||
8f71a88d JP |
419 | static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan) |
420 | { | |
421 | void __iomem *ioaddr = hw->pcsr; | |
422 | u32 mtl_int_qx_status; | |
423 | int ret = 0; | |
424 | ||
425 | mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS); | |
426 | ||
427 | /* Check MTL Interrupt */ | |
428 | if (mtl_int_qx_status & MTL_INT_QX(chan)) { | |
429 | /* read Queue x Interrupt status */ | |
430 | u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan)); | |
431 | ||
432 | if (status & MTL_RX_OVERFLOW_INT) { | |
433 | /* clear Interrupt */ | |
434 | writel(status | MTL_RX_OVERFLOW_INT, | |
435 | ioaddr + MTL_CHAN_INT_CTRL(chan)); | |
436 | ret = CORE_IRQ_MTL_RX_OVERFLOW; | |
437 | } | |
438 | } | |
439 | ||
440 | return ret; | |
441 | } | |
442 | ||
477286b5 AT |
443 | static int dwmac4_irq_status(struct mac_device_info *hw, |
444 | struct stmmac_extra_stats *x) | |
445 | { | |
446 | void __iomem *ioaddr = hw->pcsr; | |
477286b5 AT |
447 | u32 intr_status; |
448 | int ret = 0; | |
449 | ||
450 | intr_status = readl(ioaddr + GMAC_INT_STATUS); | |
451 | ||
452 | /* Not used events (e.g. MMC interrupts) are not handled. */ | |
453 | if ((intr_status & mmc_tx_irq)) | |
454 | x->mmc_tx_irq_n++; | |
455 | if (unlikely(intr_status & mmc_rx_irq)) | |
456 | x->mmc_rx_irq_n++; | |
457 | if (unlikely(intr_status & mmc_rx_csum_offload_irq)) | |
458 | x->mmc_rx_csum_offload_irq_n++; | |
459 | /* Clear the PMT bits 5 and 6 by reading the PMT status reg */ | |
460 | if (unlikely(intr_status & pmt_irq)) { | |
461 | readl(ioaddr + GMAC_PMT); | |
462 | x->irq_receive_pmt_irq_n++; | |
463 | } | |
464 | ||
70523e63 GC |
465 | dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x); |
466 | if (intr_status & PCS_RGSMIIIS_IRQ) | |
467 | dwmac4_phystatus(ioaddr, x); | |
468 | ||
477286b5 AT |
469 | return ret; |
470 | } | |
471 | ||
472 | static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x) | |
473 | { | |
474 | u32 value; | |
475 | ||
476 | /* Currently only channel 0 is supported */ | |
477 | value = readl(ioaddr + MTL_CHAN_TX_DEBUG(STMMAC_CHAN0)); | |
478 | ||
479 | if (value & MTL_DEBUG_TXSTSFSTS) | |
480 | x->mtl_tx_status_fifo_full++; | |
481 | if (value & MTL_DEBUG_TXFSTS) | |
482 | x->mtl_tx_fifo_not_empty++; | |
483 | if (value & MTL_DEBUG_TWCSTS) | |
484 | x->mmtl_fifo_ctrl++; | |
485 | if (value & MTL_DEBUG_TRCSTS_MASK) { | |
486 | u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK) | |
487 | >> MTL_DEBUG_TRCSTS_SHIFT; | |
488 | if (trcsts == MTL_DEBUG_TRCSTS_WRITE) | |
489 | x->mtl_tx_fifo_read_ctrl_write++; | |
490 | else if (trcsts == MTL_DEBUG_TRCSTS_TXW) | |
491 | x->mtl_tx_fifo_read_ctrl_wait++; | |
492 | else if (trcsts == MTL_DEBUG_TRCSTS_READ) | |
493 | x->mtl_tx_fifo_read_ctrl_read++; | |
494 | else | |
495 | x->mtl_tx_fifo_read_ctrl_idle++; | |
496 | } | |
497 | if (value & MTL_DEBUG_TXPAUSED) | |
498 | x->mac_tx_in_pause++; | |
499 | ||
500 | value = readl(ioaddr + MTL_CHAN_RX_DEBUG(STMMAC_CHAN0)); | |
501 | ||
502 | if (value & MTL_DEBUG_RXFSTS_MASK) { | |
503 | u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK) | |
504 | >> MTL_DEBUG_RRCSTS_SHIFT; | |
505 | ||
506 | if (rxfsts == MTL_DEBUG_RXFSTS_FULL) | |
507 | x->mtl_rx_fifo_fill_level_full++; | |
508 | else if (rxfsts == MTL_DEBUG_RXFSTS_AT) | |
509 | x->mtl_rx_fifo_fill_above_thresh++; | |
510 | else if (rxfsts == MTL_DEBUG_RXFSTS_BT) | |
511 | x->mtl_rx_fifo_fill_below_thresh++; | |
512 | else | |
513 | x->mtl_rx_fifo_fill_level_empty++; | |
514 | } | |
515 | if (value & MTL_DEBUG_RRCSTS_MASK) { | |
516 | u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >> | |
517 | MTL_DEBUG_RRCSTS_SHIFT; | |
518 | ||
519 | if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH) | |
520 | x->mtl_rx_fifo_read_ctrl_flush++; | |
521 | else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT) | |
522 | x->mtl_rx_fifo_read_ctrl_read_data++; | |
523 | else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA) | |
524 | x->mtl_rx_fifo_read_ctrl_status++; | |
525 | else | |
526 | x->mtl_rx_fifo_read_ctrl_idle++; | |
527 | } | |
528 | if (value & MTL_DEBUG_RWCSTS) | |
529 | x->mtl_rx_fifo_ctrl_active++; | |
530 | ||
531 | /* GMAC debug */ | |
532 | value = readl(ioaddr + GMAC_DEBUG); | |
533 | ||
534 | if (value & GMAC_DEBUG_TFCSTS_MASK) { | |
535 | u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK) | |
536 | >> GMAC_DEBUG_TFCSTS_SHIFT; | |
537 | ||
538 | if (tfcsts == GMAC_DEBUG_TFCSTS_XFER) | |
539 | x->mac_tx_frame_ctrl_xfer++; | |
540 | else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE) | |
541 | x->mac_tx_frame_ctrl_pause++; | |
542 | else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT) | |
543 | x->mac_tx_frame_ctrl_wait++; | |
544 | else | |
545 | x->mac_tx_frame_ctrl_idle++; | |
546 | } | |
547 | if (value & GMAC_DEBUG_TPESTS) | |
548 | x->mac_gmii_tx_proto_engine++; | |
549 | if (value & GMAC_DEBUG_RFCFCSTS_MASK) | |
550 | x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK) | |
551 | >> GMAC_DEBUG_RFCFCSTS_SHIFT; | |
552 | if (value & GMAC_DEBUG_RPESTS) | |
553 | x->mac_gmii_rx_proto_engine++; | |
554 | } | |
555 | ||
556 | static const struct stmmac_ops dwmac4_ops = { | |
557 | .core_init = dwmac4_core_init, | |
558 | .rx_ipc = dwmac4_rx_ipc_enable, | |
9eb12474 | 559 | .rx_queue_enable = dwmac4_rx_queue_enable, |
d0a9c9f9 JP |
560 | .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms, |
561 | .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms, | |
6a3a7193 | 562 | .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight, |
d43042f4 | 563 | .map_mtl_to_dma = dwmac4_map_mtl_dma, |
477286b5 AT |
564 | .dump_regs = dwmac4_dump_regs, |
565 | .host_irq_status = dwmac4_irq_status, | |
8f71a88d | 566 | .host_mtl_irq_status = dwmac4_irq_mtl_status, |
477286b5 AT |
567 | .flow_ctrl = dwmac4_flow_ctrl, |
568 | .pmt = dwmac4_pmt, | |
569 | .set_umac_addr = dwmac4_set_umac_addr, | |
570 | .get_umac_addr = dwmac4_get_umac_addr, | |
afbb1674 | 571 | .set_eee_mode = dwmac4_set_eee_mode, |
572 | .reset_eee_mode = dwmac4_reset_eee_mode, | |
573 | .set_eee_timer = dwmac4_set_eee_timer, | |
574 | .set_eee_pls = dwmac4_set_eee_pls, | |
70523e63 GC |
575 | .pcs_ctrl_ane = dwmac4_ctrl_ane, |
576 | .pcs_rane = dwmac4_rane, | |
577 | .pcs_get_adv_lp = dwmac4_get_adv_lp, | |
477286b5 AT |
578 | .debug = dwmac4_debug, |
579 | .set_filter = dwmac4_set_filter, | |
580 | }; | |
581 | ||
582 | struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins, | |
583 | int perfect_uc_entries, int *synopsys_id) | |
584 | { | |
585 | struct mac_device_info *mac; | |
586 | u32 hwid = readl(ioaddr + GMAC_VERSION); | |
587 | ||
588 | mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL); | |
589 | if (!mac) | |
590 | return NULL; | |
591 | ||
592 | mac->pcsr = ioaddr; | |
593 | mac->multicast_filter_bins = mcbins; | |
594 | mac->unicast_filter_entries = perfect_uc_entries; | |
595 | mac->mcast_bits_log2 = 0; | |
596 | ||
597 | if (mac->multicast_filter_bins) | |
598 | mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins); | |
599 | ||
600 | mac->mac = &dwmac4_ops; | |
601 | ||
602 | mac->link.port = GMAC_CONFIG_PS; | |
603 | mac->link.duplex = GMAC_CONFIG_DM; | |
604 | mac->link.speed = GMAC_CONFIG_FES; | |
605 | mac->mii.addr = GMAC_MDIO_ADDR; | |
606 | mac->mii.data = GMAC_MDIO_DATA; | |
b91dce4c LC |
607 | mac->mii.addr_shift = 21; |
608 | mac->mii.addr_mask = GENMASK(25, 21); | |
609 | mac->mii.reg_shift = 16; | |
610 | mac->mii.reg_mask = GENMASK(20, 16); | |
611 | mac->mii.clk_csr_shift = 8; | |
612 | mac->mii.clk_csr_mask = GENMASK(11, 8); | |
477286b5 AT |
613 | |
614 | /* Get and dump the chip ID */ | |
615 | *synopsys_id = stmmac_get_synopsys_id(hwid); | |
616 | ||
617 | if (*synopsys_id > DWMAC_CORE_4_00) | |
618 | mac->dma = &dwmac410_dma_ops; | |
619 | else | |
620 | mac->dma = &dwmac4_dma_ops; | |
621 | ||
622 | return mac; | |
623 | } |