[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / dwmac100_core.c

/*******************************************************************************
  This is the driver for the MAC 10/100 on-chip Ethernet controller
  currently tested on all the ST boards based on STb7109 and stx7200 SoCs.

  DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
  this code.

  This only implements the mac core functions for this chip.

  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#include <linux/crc32.h>
#include <asm/io.h>
#include "dwmac100.h"

static void dwmac100_core_init(struct mac_device_info *hw, int mtu)
{
	void __iomem *ioaddr = hw->pcsr;
	u32 value = readl(ioaddr + MAC_CONTROL);

	writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL);

#ifdef STMMAC_VLAN_TAG_USED
	writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
#endif
}

static void dwmac100_dump_mac_regs(struct mac_device_info *hw)
{
	void __iomem *ioaddr = hw->pcsr;
	pr_info("\t----------------------------------------------\n"
		"\t  DWMAC 100 CSR (base addr = 0x%p)\n"
		"\t----------------------------------------------\n", ioaddr);
	pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
		readl(ioaddr + MAC_CONTROL));
	pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
		readl(ioaddr + MAC_ADDR_HIGH));
	pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
		readl(ioaddr + MAC_ADDR_LOW));
	pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
		MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
	pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
		MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
	pr_info("\tflow control (offset 0x%x): 0x%08x\n",
		MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
	pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
		readl(ioaddr + MAC_VLAN1));
	pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
		readl(ioaddr + MAC_VLAN2));
}

static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)
{
	return 0;
}

static int dwmac100_irq_status(struct mac_device_info *hw,
			       struct stmmac_extra_stats *x)
{
	return 0;
}

static void dwmac100_set_umac_addr(struct mac_device_info *hw,
				   unsigned char *addr,
				   unsigned int reg_n)
{
	void __iomem *ioaddr = hw->pcsr;
	stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
}

static void dwmac100_get_umac_addr(struct mac_device_info *hw,
				   unsigned char *addr,
				   unsigned int reg_n)
{
	void __iomem *ioaddr = hw->pcsr;
	stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
}

static void dwmac100_set_filter(struct mac_device_info *hw,
				struct net_device *dev)
{
	void __iomem *ioaddr = (void __iomem *)dev->base_addr;
	u32 value = readl(ioaddr + MAC_CONTROL);

	if (dev->flags & IFF_PROMISC) {
		value |= MAC_CONTROL_PR;
		value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
			   MAC_CONTROL_HP);
	} else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
		   || (dev->flags & IFF_ALLMULTI)) {
		value |= MAC_CONTROL_PM;
		value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
		writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
		writel(0xffffffff, ioaddr + MAC_HASH_LOW);
	} else if (netdev_mc_empty(dev)) {	/* no multicast */
		value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
			   MAC_CONTROL_HO | MAC_CONTROL_HP);
	} else {
		u32 mc_filter[2];
		struct netdev_hw_addr *ha;

		/* Perfect filter mode for physical address and Hash
		 * filter for multicast
		 */
		value |= MAC_CONTROL_HP;
		value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
			   MAC_CONTROL_IF | MAC_CONTROL_HO);

		memset(mc_filter, 0, sizeof(mc_filter));
		netdev_for_each_mc_addr(ha, dev) {
			/* The upper 6 bits of the calculated CRC are used to
			 * index the contens of the hash table
			 */
			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
			/* The most significant bit determines the register to
			 * use (H/L) while the other 5 bits determine the bit
			 * within the register.
			 */
			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
		}
		writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
		writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
	}

	writel(value, ioaddr + MAC_CONTROL);
}

static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
			       unsigned int fc, unsigned int pause_time)
{
	void __iomem *ioaddr = hw->pcsr;
	unsigned int flow = MAC_FLOW_CTRL_ENABLE;

	if (duplex)
		flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
	writel(flow, ioaddr + MAC_FLOW_CTRL);
}

/* No PMT module supported on ST boards with this Eth chip. */
static void dwmac100_pmt(struct mac_device_info *hw, unsigned long mode)
{
	return;
}

static const struct stmmac_ops dwmac100_ops = {
	.core_init = dwmac100_core_init,
	.rx_ipc = dwmac100_rx_ipc_enable,
	.dump_regs = dwmac100_dump_mac_regs,
	.host_irq_status = dwmac100_irq_status,
	.set_filter = dwmac100_set_filter,
	.flow_ctrl = dwmac100_flow_ctrl,
	.pmt = dwmac100_pmt,
	.set_umac_addr = dwmac100_set_umac_addr,
	.get_umac_addr = dwmac100_get_umac_addr,
};

struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id)
{
	struct mac_device_info *mac;

	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
	if (!mac)
		return NULL;

	pr_info("\tDWMAC100\n");

	mac->pcsr = ioaddr;
	mac->mac = &dwmac100_ops;
	mac->dma = &dwmac100_dma_ops;

	mac->link.port = MAC_CONTROL_PS;
	mac->link.duplex = MAC_CONTROL_F;
	mac->link.speed = 0;
	mac->mii.addr = MAC_MII_ADDR;
	mac->mii.data = MAC_MII_DATA;
	/* Synopsys Id is not available on old chips */
	*synopsys_id = 0;

	return mac;
}
Commit	Line	Data
3c32be63 GC	1	/*******************************************************************************
	2	This is the driver for the MAC 10/100 on-chip Ethernet controller
	3	currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
	4
	5	DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
	6	this code.
	7
	8	This only implements the mac core functions for this chip.
	9
	10	Copyright (C) 2007-2009 STMicroelectronics Ltd
	11
	12	This program is free software; you can redistribute it and/or modify it
	13	under the terms and conditions of the GNU General Public License,
	14	version 2, as published by the Free Software Foundation.
	15
	16	This program is distributed in the hope it will be useful, but WITHOUT
	17	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	18	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	19	more details.
	20
	21	You should have received a copy of the GNU General Public License along with
	22	this program; if not, write to the Free Software Foundation, Inc.,
	23	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	24
	25	The full GNU General Public License is included in this distribution in
	26	the file called "COPYING".
	27
	28	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	29	*******************************************************************************/
	30
	31	#include <linux/crc32.h>
b7f080cf	32	#include <asm/io.h>
3c32be63 GC	33	#include "dwmac100.h"
3c32be63 GC	34
7ed24bbe	35	static void dwmac100_core_init(struct mac_device_info *hw, int mtu)
3c32be63	36	{
7ed24bbe	37	void __iomem *ioaddr = hw->pcsr;
3c32be63 GC	38	u32 value = readl(ioaddr + MAC_CONTROL);
	39
	40	writel((value \| MAC_CORE_INIT), ioaddr + MAC_CONTROL);
	41
	42	#ifdef STMMAC_VLAN_TAG_USED
	43	writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
	44	#endif
3c32be63 GC	45	}
3c32be63 GC	46
7ed24bbe	47	static void dwmac100_dump_mac_regs(struct mac_device_info *hw)
3c32be63	48	{
7ed24bbe	49	void __iomem *ioaddr = hw->pcsr;
3c32be63	50	pr_info("\t----------------------------------------------\n"
74af4c7d	51	"\t DWMAC 100 CSR (base addr = 0x%p)\n"
ceb69499	52	"\t----------------------------------------------\n", ioaddr);
3c32be63 GC	53	pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
	54	readl(ioaddr + MAC_CONTROL));
	55	pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
	56	readl(ioaddr + MAC_ADDR_HIGH));
	57	pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
	58	readl(ioaddr + MAC_ADDR_LOW));
	59	pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
	60	MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
	61	pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
	62	MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
	63	pr_info("\tflow control (offset 0x%x): 0x%08x\n",
	64	MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
	65	pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
	66	readl(ioaddr + MAC_VLAN1));
	67	pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
	68	readl(ioaddr + MAC_VLAN2));
3c32be63 GC	69	}
3c32be63 GC	70
7ed24bbe	71	static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)
38912bdb DS	72	{
	73	return 0;
	74	}
	75
7ed24bbe	76	static int dwmac100_irq_status(struct mac_device_info *hw,
0982a0f6	77	struct stmmac_extra_stats *x)
3c32be63	78	{
d765955d	79	return 0;
3c32be63 GC	80	}
3c32be63 GC	81
7ed24bbe VB	82	static void dwmac100_set_umac_addr(struct mac_device_info *hw,
7ed24bbe VB	83	unsigned char *addr,
3c32be63 GC	84	unsigned int reg_n)
3c32be63 GC	85	{
7ed24bbe	86	void __iomem *ioaddr = hw->pcsr;
3c32be63 GC	87	stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
	88	}
	89
7ed24bbe VB	90	static void dwmac100_get_umac_addr(struct mac_device_info *hw,
7ed24bbe VB	91	unsigned char *addr,
3c32be63 GC	92	unsigned int reg_n)
3c32be63 GC	93	{
7ed24bbe	94	void __iomem *ioaddr = hw->pcsr;
3c32be63 GC	95	stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
	96	}
	97
3b57de95 VB	98	static void dwmac100_set_filter(struct mac_device_info *hw,
3b57de95 VB	99	struct net_device *dev)
3c32be63	100	{
ceb69499	101	void __iomem ioaddr = (void __iomem )dev->base_addr;
3c32be63 GC	102	u32 value = readl(ioaddr + MAC_CONTROL);
	103
	104	if (dev->flags & IFF_PROMISC) {
	105	value \|= MAC_CONTROL_PR;
	106	value &= ~(MAC_CONTROL_PM \| MAC_CONTROL_IF \| MAC_CONTROL_HO \|
	107	MAC_CONTROL_HP);
	108	} else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
	109	\|\| (dev->flags & IFF_ALLMULTI)) {
	110	value \|= MAC_CONTROL_PM;
	111	value &= ~(MAC_CONTROL_PR \| MAC_CONTROL_IF \| MAC_CONTROL_HO);
	112	writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
	113	writel(0xffffffff, ioaddr + MAC_HASH_LOW);
	114	} else if (netdev_mc_empty(dev)) { /* no multicast */
	115	value &= ~(MAC_CONTROL_PM \| MAC_CONTROL_PR \| MAC_CONTROL_IF \|
	116	MAC_CONTROL_HO \| MAC_CONTROL_HP);
	117	} else {
	118	u32 mc_filter[2];
	119	struct netdev_hw_addr *ha;
	120
	121	/* Perfect filter mode for physical address and Hash
ceb69499 GC	122	* filter for multicast
ceb69499 GC	123	*/
3c32be63 GC	124	value \|= MAC_CONTROL_HP;
	125	value &= ~(MAC_CONTROL_PM \| MAC_CONTROL_PR \|
	126	MAC_CONTROL_IF \| MAC_CONTROL_HO);
	127
	128	memset(mc_filter, 0, sizeof(mc_filter));
	129	netdev_for_each_mc_addr(ha, dev) {
	130	/* The upper 6 bits of the calculated CRC are used to
ceb69499 GC	131	* index the contens of the hash table
	132	*/
	133	int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
3c32be63 GC	134	/* The most significant bit determines the register to
3c32be63 GC	135	* use (H/L) while the other 5 bits determine the bit
ceb69499 GC	136	* within the register.
ceb69499 GC	137	*/
3c32be63 GC	138	mc_filter[bit_nr >> 5] \|= 1 << (bit_nr & 31);
	139	}
	140	writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
	141	writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
	142	}
	143
	144	writel(value, ioaddr + MAC_CONTROL);
3c32be63 GC	145	}
3c32be63 GC	146
7ed24bbe	147	static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
3c32be63 GC	148	unsigned int fc, unsigned int pause_time)
3c32be63 GC	149	{
7ed24bbe	150	void __iomem *ioaddr = hw->pcsr;
3c32be63 GC	151	unsigned int flow = MAC_FLOW_CTRL_ENABLE;
	152
	153	if (duplex)
	154	flow \|= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
	155	writel(flow, ioaddr + MAC_FLOW_CTRL);
3c32be63 GC	156	}
3c32be63 GC	157
ceb69499	158	/* No PMT module supported on ST boards with this Eth chip. */
7ed24bbe	159	static void dwmac100_pmt(struct mac_device_info *hw, unsigned long mode)
3c32be63 GC	160	{
	161	return;
	162	}
	163
cadb7924	164	static const struct stmmac_ops dwmac100_ops = {
3c32be63	165	.core_init = dwmac100_core_init,
38912bdb	166	.rx_ipc = dwmac100_rx_ipc_enable,
3c32be63 GC	167	.dump_regs = dwmac100_dump_mac_regs,
	168	.host_irq_status = dwmac100_irq_status,
	169	.set_filter = dwmac100_set_filter,
	170	.flow_ctrl = dwmac100_flow_ctrl,
	171	.pmt = dwmac100_pmt,
	172	.set_umac_addr = dwmac100_set_umac_addr,
	173	.get_umac_addr = dwmac100_get_umac_addr,
	174	};
	175
c623d149	176	struct mac_device_info dwmac100_setup(void __iomem ioaddr, int *synopsys_id)
3c32be63 GC	177	{
	178	struct mac_device_info *mac;
	179
	180	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
1ff21906 DC	181	if (!mac)
1ff21906 DC	182	return NULL;
3c32be63 GC	183
	184	pr_info("\tDWMAC100\n");
	185
7ed24bbe	186	mac->pcsr = ioaddr;
3c32be63	187	mac->mac = &dwmac100_ops;
3c32be63 GC	188	mac->dma = &dwmac100_dma_ops;
3c32be63 GC	189
3c32be63 GC	190	mac->link.port = MAC_CONTROL_PS;
	191	mac->link.duplex = MAC_CONTROL_F;
	192	mac->link.speed = 0;
	193	mac->mii.addr = MAC_MII_ADDR;
	194	mac->mii.data = MAC_MII_DATA;
c623d149 AT	195	/* Synopsys Id is not available on old chips */
c623d149 AT	196	*synopsys_id = 0;
3c32be63 GC	197
	198	return mac;
	199	}