[linux-block.git] / drivers / net / ethernet / stmicro / stmmac / dwmac1000_core.c

/*******************************************************************************
  This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
  DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
  developing this code.

  This only implements the mac core functions for this chip.

  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#include <linux/crc32.h>
#include <linux/slab.h>
#include <asm/io.h>
#include "dwmac1000.h"

static void dwmac1000_core_init(void __iomem *ioaddr)
{
	u32 value = readl(ioaddr + GMAC_CONTROL);
	value |= GMAC_CORE_INIT;
	writel(value, ioaddr + GMAC_CONTROL);

	/* Mask GMAC interrupts */
	writel(0x207, ioaddr + GMAC_INT_MASK);

#ifdef STMMAC_VLAN_TAG_USED
	/* Tag detection without filtering */
	writel(0x0, ioaddr + GMAC_VLAN_TAG);
#endif
}

static int dwmac1000_rx_ipc_enable(void __iomem *ioaddr)
{
	u32 value = readl(ioaddr + GMAC_CONTROL);

	value |= GMAC_CONTROL_IPC;
	writel(value, ioaddr + GMAC_CONTROL);

	value = readl(ioaddr + GMAC_CONTROL);

	return !!(value & GMAC_CONTROL_IPC);
}

static void dwmac1000_dump_regs(void __iomem *ioaddr)
{
	int i;
	pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);

	for (i = 0; i < 55; i++) {
		int offset = i * 4;
		pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
			offset, readl(ioaddr + offset));
	}
}

static void dwmac1000_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
				unsigned int reg_n)
{
	stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
				GMAC_ADDR_LOW(reg_n));
}

static void dwmac1000_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
				unsigned int reg_n)
{
	stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
				GMAC_ADDR_LOW(reg_n));
}

static void dwmac1000_set_filter(struct net_device *dev, int id)
{
	void __iomem *ioaddr = (void __iomem *) dev->base_addr;
	unsigned int value = 0;
	unsigned int perfect_addr_number;

	CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
		 __func__, netdev_mc_count(dev), netdev_uc_count(dev));

	if (dev->flags & IFF_PROMISC)
		value = GMAC_FRAME_FILTER_PR;
	else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
		   || (dev->flags & IFF_ALLMULTI)) {
		value = GMAC_FRAME_FILTER_PM;	/* pass all multi */
		writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
		writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
	} else if (!netdev_mc_empty(dev)) {
		u32 mc_filter[2];
		struct netdev_hw_addr *ha;

		/* Hash filter for multicast */
		value = GMAC_FRAME_FILTER_HMC;

		memset(mc_filter, 0, sizeof(mc_filter));
		netdev_for_each_mc_addr(ha, dev) {
			/* The upper 6 bits of the calculated CRC are used to
			   index the contens of the hash table */
			int bit_nr =
			    bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
			/* The most significant bit determines the register to
			 * use (H/L) while the other 5 bits determine the bit
			 * within the register. */
			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
		}
		writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
		writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
	}

	/* Extra 16 regs are available in cores newer than the 3.40. */
	if (id > DWMAC_CORE_3_40)
		perfect_addr_number = GMAC_MAX_PERFECT_ADDRESSES;
	else
		perfect_addr_number = GMAC_MAX_PERFECT_ADDRESSES / 2;

	/* Handle multiple unicast addresses (perfect filtering)*/
	if (netdev_uc_count(dev) > perfect_addr_number)
		/* Switch to promiscuous mode is more than 16 addrs
		   are required */
		value |= GMAC_FRAME_FILTER_PR;
	else {
		int reg = 1;
		struct netdev_hw_addr *ha;

		netdev_for_each_uc_addr(ha, dev) {
			dwmac1000_set_umac_addr(ioaddr, ha->addr, reg);
			reg++;
		}
	}

#ifdef FRAME_FILTER_DEBUG
	/* Enable Receive all mode (to debug filtering_fail errors) */
	value |= GMAC_FRAME_FILTER_RA;
#endif
	writel(value, ioaddr + GMAC_FRAME_FILTER);

	CHIP_DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
	    "HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
	    readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
}

static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
			   unsigned int fc, unsigned int pause_time)
{
	unsigned int flow = 0;

	CHIP_DBG(KERN_DEBUG "GMAC Flow-Control:\n");
	if (fc & FLOW_RX) {
		CHIP_DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
		flow |= GMAC_FLOW_CTRL_RFE;
	}
	if (fc & FLOW_TX) {
		CHIP_DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
		flow |= GMAC_FLOW_CTRL_TFE;
	}

	if (duplex) {
		CHIP_DBG(KERN_DEBUG "\tduplex mode: PAUSE %d\n", pause_time);
		flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
	}

	writel(flow, ioaddr + GMAC_FLOW_CTRL);
}

static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode)
{
	unsigned int pmt = 0;

	if (mode & WAKE_MAGIC) {
		CHIP_DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
		pmt |= power_down | magic_pkt_en;
	}
	if (mode & WAKE_UCAST) {
		CHIP_DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
		pmt |= global_unicast;
	}

	writel(pmt, ioaddr + GMAC_PMT);
}


static void dwmac1000_irq_status(void __iomem *ioaddr)
{
	u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);

	/* Not used events (e.g. MMC interrupts) are not handled. */
	if ((intr_status & mmc_tx_irq))
		CHIP_DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n",
		    readl(ioaddr + GMAC_MMC_TX_INTR));
	if (unlikely(intr_status & mmc_rx_irq))
		CHIP_DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n",
		    readl(ioaddr + GMAC_MMC_RX_INTR));
	if (unlikely(intr_status & mmc_rx_csum_offload_irq))
		CHIP_DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n",
		    readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
	if (unlikely(intr_status & pmt_irq)) {
		CHIP_DBG(KERN_DEBUG "GMAC: received Magic frame\n");
		/* clear the PMT bits 5 and 6 by reading the PMT
		 * status register. */
		readl(ioaddr + GMAC_PMT);
	}
}

static const struct stmmac_ops dwmac1000_ops = {
	.core_init = dwmac1000_core_init,
	.rx_ipc = dwmac1000_rx_ipc_enable,
	.dump_regs = dwmac1000_dump_regs,
	.host_irq_status = dwmac1000_irq_status,
	.set_filter = dwmac1000_set_filter,
	.flow_ctrl = dwmac1000_flow_ctrl,
	.pmt = dwmac1000_pmt,
	.set_umac_addr = dwmac1000_set_umac_addr,
	.get_umac_addr = dwmac1000_get_umac_addr,
};

struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr)
{
	struct mac_device_info *mac;
	u32 hwid = readl(ioaddr + GMAC_VERSION);

	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
	if (!mac)
		return NULL;

	mac->mac = &dwmac1000_ops;
	mac->dma = &dwmac1000_dma_ops;

	mac->link.port = GMAC_CONTROL_PS;
	mac->link.duplex = GMAC_CONTROL_DM;
	mac->link.speed = GMAC_CONTROL_FES;
	mac->mii.addr = GMAC_MII_ADDR;
	mac->mii.data = GMAC_MII_DATA;
	mac->synopsys_uid = hwid;

	return mac;
}
Commit	Line	Data
21d437cc GC	1	/*******************************************************************************
	2	This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
	3	DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
	4	developing this code.
	5
	6	This only implements the mac core functions for this chip.
	7
	8	Copyright (C) 2007-2009 STMicroelectronics Ltd
	9
	10	This program is free software; you can redistribute it and/or modify it
	11	under the terms and conditions of the GNU General Public License,
	12	version 2, as published by the Free Software Foundation.
	13
	14	This program is distributed in the hope it will be useful, but WITHOUT
	15	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	more details.
	18
	19	You should have received a copy of the GNU General Public License along with
	20	this program; if not, write to the Free Software Foundation, Inc.,
	21	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	22
	23	The full GNU General Public License is included in this distribution in
	24	the file called "COPYING".
	25
	26	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	27	*******************************************************************************/
	28
	29	#include <linux/crc32.h>
5a0e3ad6	30	#include <linux/slab.h>
b7f080cf	31	#include <asm/io.h>
21d437cc GC	32	#include "dwmac1000.h"
21d437cc GC	33
ad01b7d4	34	static void dwmac1000_core_init(void __iomem *ioaddr)
21d437cc GC	35	{
	36	u32 value = readl(ioaddr + GMAC_CONTROL);
	37	value \|= GMAC_CORE_INIT;
	38	writel(value, ioaddr + GMAC_CONTROL);
	39
21d437cc GC	40	/* Mask GMAC interrupts */
	41	writel(0x207, ioaddr + GMAC_INT_MASK);
	42
	43	#ifdef STMMAC_VLAN_TAG_USED
	44	/* Tag detection without filtering */
	45	writel(0x0, ioaddr + GMAC_VLAN_TAG);
	46	#endif
21d437cc GC	47	}
21d437cc GC	48
38912bdb	49	static int dwmac1000_rx_ipc_enable(void __iomem *ioaddr)
ebbb293f GC	50	{
	51	u32 value = readl(ioaddr + GMAC_CONTROL);
	52
	53	value \|= GMAC_CONTROL_IPC;
	54	writel(value, ioaddr + GMAC_CONTROL);
	55
	56	value = readl(ioaddr + GMAC_CONTROL);
	57
	58	return !!(value & GMAC_CONTROL_IPC);
	59	}
	60
ad01b7d4	61	static void dwmac1000_dump_regs(void __iomem *ioaddr)
21d437cc GC	62	{
21d437cc GC	63	int i;
1f0f6388	64	pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
21d437cc GC	65
	66	for (i = 0; i < 55; i++) {
	67	int offset = i * 4;
	68	pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
	69	offset, readl(ioaddr + offset));
	70	}
21d437cc GC	71	}
21d437cc GC	72
ad01b7d4	73	static void dwmac1000_set_umac_addr(void __iomem ioaddr, unsigned char addr,
21d437cc GC	74	unsigned int reg_n)
	75	{
	76	stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
	77	GMAC_ADDR_LOW(reg_n));
	78	}
	79
ad01b7d4	80	static void dwmac1000_get_umac_addr(void __iomem ioaddr, unsigned char addr,
21d437cc GC	81	unsigned int reg_n)
	82	{
	83	stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
	84	GMAC_ADDR_LOW(reg_n));
	85	}
	86
cffb13f4	87	static void dwmac1000_set_filter(struct net_device *dev, int id)
21d437cc	88	{
ad01b7d4	89	void __iomem ioaddr = (void __iomem ) dev->base_addr;
21d437cc	90	unsigned int value = 0;
cffb13f4	91	unsigned int perfect_addr_number;
21d437cc	92
56b106ae GC	93	CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
56b106ae GC	94	__func__, netdev_mc_count(dev), netdev_uc_count(dev));
21d437cc GC	95
	96	if (dev->flags & IFF_PROMISC)
	97	value = GMAC_FRAME_FILTER_PR;
4cd24eaf	98	else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
21d437cc GC	99	\|\| (dev->flags & IFF_ALLMULTI)) {
	100	value = GMAC_FRAME_FILTER_PM; /* pass all multi */
	101	writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
	102	writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
4cd24eaf	103	} else if (!netdev_mc_empty(dev)) {
21d437cc	104	u32 mc_filter[2];
22bedad3	105	struct netdev_hw_addr *ha;
21d437cc GC	106
	107	/* Hash filter for multicast */
	108	value = GMAC_FRAME_FILTER_HMC;
	109
	110	memset(mc_filter, 0, sizeof(mc_filter));
22bedad3	111	netdev_for_each_mc_addr(ha, dev) {
21d437cc GC	112	/* The upper 6 bits of the calculated CRC are used to
	113	index the contens of the hash table */
	114	int bit_nr =
22bedad3	115	bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
21d437cc GC	116	/* The most significant bit determines the register to
	117	* use (H/L) while the other 5 bits determine the bit
	118	* within the register. */
	119	mc_filter[bit_nr >> 5] \|= 1 << (bit_nr & 31);
	120	}
	121	writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
	122	writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
	123	}
	124
cffb13f4 GC	125	/* Extra 16 regs are available in cores newer than the 3.40. */
	126	if (id > DWMAC_CORE_3_40)
	127	perfect_addr_number = GMAC_MAX_PERFECT_ADDRESSES;
	128	else
	129	perfect_addr_number = GMAC_MAX_PERFECT_ADDRESSES / 2;
	130
21d437cc	131	/* Handle multiple unicast addresses (perfect filtering)*/
cffb13f4	132	if (netdev_uc_count(dev) > perfect_addr_number)
21d437cc GC	133	/* Switch to promiscuous mode is more than 16 addrs
	134	are required */
	135	value \|= GMAC_FRAME_FILTER_PR;
	136	else {
	137	int reg = 1;
	138	struct netdev_hw_addr *ha;
	139
32e7bfc4 JP	140	netdev_for_each_uc_addr(ha, dev) {
	141	dwmac1000_set_umac_addr(ioaddr, ha->addr, reg);
	142	reg++;
21d437cc GC	143	}
	144	}
	145
	146	#ifdef FRAME_FILTER_DEBUG
	147	/* Enable Receive all mode (to debug filtering_fail errors) */
	148	value \|= GMAC_FRAME_FILTER_RA;
	149	#endif
	150	writel(value, ioaddr + GMAC_FRAME_FILTER);
	151
56b106ae	152	CHIP_DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
21d437cc GC	153	"HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
21d437cc GC	154	readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
21d437cc GC	155	}
21d437cc GC	156
ad01b7d4	157	static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
21d437cc GC	158	unsigned int fc, unsigned int pause_time)
	159	{
	160	unsigned int flow = 0;
	161
56b106ae	162	CHIP_DBG(KERN_DEBUG "GMAC Flow-Control:\n");
21d437cc	163	if (fc & FLOW_RX) {
56b106ae	164	CHIP_DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
21d437cc GC	165	flow \|= GMAC_FLOW_CTRL_RFE;
	166	}
	167	if (fc & FLOW_TX) {
56b106ae	168	CHIP_DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
21d437cc GC	169	flow \|= GMAC_FLOW_CTRL_TFE;
	170	}
	171
	172	if (duplex) {
56b106ae	173	CHIP_DBG(KERN_DEBUG "\tduplex mode: PAUSE %d\n", pause_time);
21d437cc GC	174	flow \|= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
	175	}
	176
	177	writel(flow, ioaddr + GMAC_FLOW_CTRL);
21d437cc GC	178	}
21d437cc GC	179
ad01b7d4	180	static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode)
21d437cc GC	181	{
	182	unsigned int pmt = 0;
	183
74ae2fd7	184	if (mode & WAKE_MAGIC) {
56b106ae	185	CHIP_DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
21d437cc	186	pmt \|= power_down \| magic_pkt_en;
74ae2fd7 GC	187	}
74ae2fd7 GC	188	if (mode & WAKE_UCAST) {
56b106ae	189	CHIP_DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
21d437cc GC	190	pmt \|= global_unicast;
	191	}
	192
	193	writel(pmt, ioaddr + GMAC_PMT);
21d437cc GC	194	}
	195
	196
ad01b7d4	197	static void dwmac1000_irq_status(void __iomem *ioaddr)
21d437cc GC	198	{
	199	u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
	200
	201	/* Not used events (e.g. MMC interrupts) are not handled. */
	202	if ((intr_status & mmc_tx_irq))
56b106ae	203	CHIP_DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n",
21d437cc GC	204	readl(ioaddr + GMAC_MMC_TX_INTR));
21d437cc GC	205	if (unlikely(intr_status & mmc_rx_irq))
56b106ae	206	CHIP_DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n",
21d437cc GC	207	readl(ioaddr + GMAC_MMC_RX_INTR));
21d437cc GC	208	if (unlikely(intr_status & mmc_rx_csum_offload_irq))
56b106ae	209	CHIP_DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n",
21d437cc GC	210	readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
21d437cc GC	211	if (unlikely(intr_status & pmt_irq)) {
56b106ae	212	CHIP_DBG(KERN_DEBUG "GMAC: received Magic frame\n");
21d437cc GC	213	/* clear the PMT bits 5 and 6 by reading the PMT
	214	* status register. */
	215	readl(ioaddr + GMAC_PMT);
	216	}
21d437cc GC	217	}
21d437cc GC	218
cadb7924	219	static const struct stmmac_ops dwmac1000_ops = {
21d437cc	220	.core_init = dwmac1000_core_init,
38912bdb	221	.rx_ipc = dwmac1000_rx_ipc_enable,
21d437cc GC	222	.dump_regs = dwmac1000_dump_regs,
	223	.host_irq_status = dwmac1000_irq_status,
	224	.set_filter = dwmac1000_set_filter,
	225	.flow_ctrl = dwmac1000_flow_ctrl,
	226	.pmt = dwmac1000_pmt,
	227	.set_umac_addr = dwmac1000_set_umac_addr,
	228	.get_umac_addr = dwmac1000_get_umac_addr,
	229	};
	230
ad01b7d4	231	struct mac_device_info dwmac1000_setup(void __iomem ioaddr)
21d437cc GC	232	{
21d437cc GC	233	struct mac_device_info *mac;
f0b9d786	234	u32 hwid = readl(ioaddr + GMAC_VERSION);
21d437cc GC	235
21d437cc GC	236	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
1ff21906 DC	237	if (!mac)
1ff21906 DC	238	return NULL;
21d437cc GC	239
21d437cc GC	240	mac->mac = &dwmac1000_ops;
21d437cc GC	241	mac->dma = &dwmac1000_dma_ops;
21d437cc GC	242
21d437cc GC	243	mac->link.port = GMAC_CONTROL_PS;
	244	mac->link.duplex = GMAC_CONTROL_DM;
	245	mac->link.speed = GMAC_CONTROL_FES;
	246	mac->mii.addr = GMAC_MII_ADDR;
	247	mac->mii.data = GMAC_MII_DATA;
f0b9d786	248	mac->synopsys_uid = hwid;
21d437cc GC	249
	250	return mac;
	251	}