[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / dwmac1000.h

/*******************************************************************************
  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/
#ifndef __DWMAC1000_H__
#define __DWMAC1000_H__

#include <linux/phy.h>
#include "common.h"

#define GMAC_CONTROL		0x00000000	/* Configuration */
#define GMAC_FRAME_FILTER	0x00000004	/* Frame Filter */
#define GMAC_HASH_HIGH		0x00000008	/* Multicast Hash Table High */
#define GMAC_HASH_LOW		0x0000000c	/* Multicast Hash Table Low */
#define GMAC_MII_ADDR		0x00000010	/* MII Address */
#define GMAC_MII_DATA		0x00000014	/* MII Data */
#define GMAC_FLOW_CTRL		0x00000018	/* Flow Control */
#define GMAC_VLAN_TAG		0x0000001c	/* VLAN Tag */
#define GMAC_DEBUG		0x00000024	/* GMAC debug register */
#define GMAC_WAKEUP_FILTER	0x00000028	/* Wake-up Frame Filter */

#define GMAC_INT_STATUS		0x00000038	/* interrupt status register */
#define GMAC_INT_STATUS_PMT	BIT(3)
#define GMAC_INT_STATUS_MMCIS	BIT(4)
#define GMAC_INT_STATUS_MMCRIS	BIT(5)
#define GMAC_INT_STATUS_MMCTIS	BIT(6)
#define GMAC_INT_STATUS_MMCCSUM	BIT(7)
#define GMAC_INT_STATUS_TSTAMP	BIT(9)
#define GMAC_INT_STATUS_LPIIS	BIT(10)

/* interrupt mask register */
#define	GMAC_INT_MASK		0x0000003c
#define	GMAC_INT_DISABLE_RGMII		BIT(0)
#define	GMAC_INT_DISABLE_PCSLINK	BIT(1)
#define	GMAC_INT_DISABLE_PCSAN		BIT(2)
#define	GMAC_INT_DISABLE_PMT		BIT(3)
#define	GMAC_INT_DISABLE_TIMESTAMP	BIT(9)
#define	GMAC_INT_DISABLE_PCS	(GMAC_INT_DISABLE_RGMII | \
				 GMAC_INT_DISABLE_PCSLINK | \
				 GMAC_INT_DISABLE_PCSAN)
#define	GMAC_INT_DEFAULT_MASK	(GMAC_INT_DISABLE_TIMESTAMP | \
				 GMAC_INT_DISABLE_PCS)

/* PMT Control and Status */
#define GMAC_PMT		0x0000002c
enum power_event {
	pointer_reset = 0x80000000,
	global_unicast = 0x00000200,
	wake_up_rx_frame = 0x00000040,
	magic_frame = 0x00000020,
	wake_up_frame_en = 0x00000004,
	magic_pkt_en = 0x00000002,
	power_down = 0x00000001,
};

/* Energy Efficient Ethernet (EEE)
 *
 * LPI status, timer and control register offset
 */
#define LPI_CTRL_STATUS	0x0030
#define LPI_TIMER_CTRL	0x0034

/* LPI control and status defines */
#define LPI_CTRL_STATUS_LPITXA	0x00080000	/* Enable LPI TX Automate */
#define LPI_CTRL_STATUS_PLSEN	0x00040000	/* Enable PHY Link Status */
#define LPI_CTRL_STATUS_PLS	0x00020000	/* PHY Link Status */
#define LPI_CTRL_STATUS_LPIEN	0x00010000	/* LPI Enable */
#define LPI_CTRL_STATUS_RLPIST	0x00000200	/* Receive LPI state */
#define LPI_CTRL_STATUS_TLPIST	0x00000100	/* Transmit LPI state */
#define LPI_CTRL_STATUS_RLPIEX	0x00000008	/* Receive LPI Exit */
#define LPI_CTRL_STATUS_RLPIEN	0x00000004	/* Receive LPI Entry */
#define LPI_CTRL_STATUS_TLPIEX	0x00000002	/* Transmit LPI Exit */
#define LPI_CTRL_STATUS_TLPIEN	0x00000001	/* Transmit LPI Entry */

/* GMAC HW ADDR regs */
#define GMAC_ADDR_HIGH(reg)	(((reg > 15) ? 0x00000800 : 0x00000040) + \
				(reg * 8))
#define GMAC_ADDR_LOW(reg)	(((reg > 15) ? 0x00000804 : 0x00000044) + \
				(reg * 8))
#define GMAC_MAX_PERFECT_ADDRESSES	1

#define GMAC_PCS_BASE		0x000000c0	/* PCS register base */
#define GMAC_RGSMIIIS		0x000000d8	/* RGMII/SMII status */

/* SGMII/RGMII status register */
#define GMAC_RGSMIIIS_LNKMODE		BIT(0)
#define GMAC_RGSMIIIS_SPEED		GENMASK(2, 1)
#define GMAC_RGSMIIIS_SPEED_SHIFT	1
#define GMAC_RGSMIIIS_LNKSTS		BIT(3)
#define GMAC_RGSMIIIS_JABTO		BIT(4)
#define GMAC_RGSMIIIS_FALSECARDET	BIT(5)
#define GMAC_RGSMIIIS_SMIDRXS		BIT(16)
/* LNKMOD */
#define GMAC_RGSMIIIS_LNKMOD_MASK	0x1
/* LNKSPEED */
#define GMAC_RGSMIIIS_SPEED_125		0x2
#define GMAC_RGSMIIIS_SPEED_25		0x1
#define GMAC_RGSMIIIS_SPEED_2_5		0x0

/* GMAC Configuration defines */
#define GMAC_CONTROL_2K 0x08000000	/* IEEE 802.3as 2K packets */
#define GMAC_CONTROL_TC	0x01000000	/* Transmit Conf. in RGMII/SGMII */
#define GMAC_CONTROL_WD	0x00800000	/* Disable Watchdog on receive */
#define GMAC_CONTROL_JD	0x00400000	/* Jabber disable */
#define GMAC_CONTROL_BE	0x00200000	/* Frame Burst Enable */
#define GMAC_CONTROL_JE	0x00100000	/* Jumbo frame */
enum inter_frame_gap {
	GMAC_CONTROL_IFG_88 = 0x00040000,
	GMAC_CONTROL_IFG_80 = 0x00020000,
	GMAC_CONTROL_IFG_40 = 0x000e0000,
};
#define GMAC_CONTROL_DCRS	0x00010000	/* Disable carrier sense */
#define GMAC_CONTROL_PS		0x00008000	/* Port Select 0:GMI 1:MII */
#define GMAC_CONTROL_FES	0x00004000	/* Speed 0:10 1:100 */
#define GMAC_CONTROL_DO		0x00002000	/* Disable Rx Own */
#define GMAC_CONTROL_LM		0x00001000	/* Loop-back mode */
#define GMAC_CONTROL_DM		0x00000800	/* Duplex Mode */
#define GMAC_CONTROL_IPC	0x00000400	/* Checksum Offload */
#define GMAC_CONTROL_DR		0x00000200	/* Disable Retry */
#define GMAC_CONTROL_LUD	0x00000100	/* Link up/down */
#define GMAC_CONTROL_ACS	0x00000080	/* Auto Pad/FCS Stripping */
#define GMAC_CONTROL_DC		0x00000010	/* Deferral Check */
#define GMAC_CONTROL_TE		0x00000008	/* Transmitter Enable */
#define GMAC_CONTROL_RE		0x00000004	/* Receiver Enable */

#define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \
			GMAC_CONTROL_BE | GMAC_CONTROL_DCRS)

/* GMAC Frame Filter defines */
#define GMAC_FRAME_FILTER_PR	0x00000001	/* Promiscuous Mode */
#define GMAC_FRAME_FILTER_HUC	0x00000002	/* Hash Unicast */
#define GMAC_FRAME_FILTER_HMC	0x00000004	/* Hash Multicast */
#define GMAC_FRAME_FILTER_DAIF	0x00000008	/* DA Inverse Filtering */
#define GMAC_FRAME_FILTER_PM	0x00000010	/* Pass all multicast */
#define GMAC_FRAME_FILTER_DBF	0x00000020	/* Disable Broadcast frames */
#define GMAC_FRAME_FILTER_SAIF	0x00000100	/* Inverse Filtering */
#define GMAC_FRAME_FILTER_SAF	0x00000200	/* Source Address Filter */
#define GMAC_FRAME_FILTER_HPF	0x00000400	/* Hash or perfect Filter */
#define GMAC_FRAME_FILTER_RA	0x80000000	/* Receive all mode */
/* GMII ADDR  defines */
#define GMAC_MII_ADDR_WRITE	0x00000002	/* MII Write */
#define GMAC_MII_ADDR_BUSY	0x00000001	/* MII Busy */
/* GMAC FLOW CTRL defines */
#define GMAC_FLOW_CTRL_PT_MASK	0xffff0000	/* Pause Time Mask */
#define GMAC_FLOW_CTRL_PT_SHIFT	16
#define GMAC_FLOW_CTRL_UP	0x00000008	/* Unicast pause frame enable */
#define GMAC_FLOW_CTRL_RFE	0x00000004	/* Rx Flow Control Enable */
#define GMAC_FLOW_CTRL_TFE	0x00000002	/* Tx Flow Control Enable */
#define GMAC_FLOW_CTRL_FCB_BPA	0x00000001	/* Flow Control Busy ... */

/* DEBUG Register defines */
/* MTL TxStatus FIFO */
#define GMAC_DEBUG_TXSTSFSTS	BIT(25)	/* MTL TxStatus FIFO Full Status */
#define GMAC_DEBUG_TXFSTS	BIT(24) /* MTL Tx FIFO Not Empty Status */
#define GMAC_DEBUG_TWCSTS	BIT(22) /* MTL Tx FIFO Write Controller */
/* MTL Tx FIFO Read Controller Status */
#define GMAC_DEBUG_TRCSTS_MASK	GENMASK(21, 20)
#define GMAC_DEBUG_TRCSTS_SHIFT	20
#define GMAC_DEBUG_TRCSTS_IDLE	0
#define GMAC_DEBUG_TRCSTS_READ	1
#define GMAC_DEBUG_TRCSTS_TXW	2
#define GMAC_DEBUG_TRCSTS_WRITE	3
#define GMAC_DEBUG_TXPAUSED	BIT(19) /* MAC Transmitter in PAUSE */
/* MAC Transmit Frame Controller Status */
#define GMAC_DEBUG_TFCSTS_MASK	GENMASK(18, 17)
#define GMAC_DEBUG_TFCSTS_SHIFT	17
#define GMAC_DEBUG_TFCSTS_IDLE	0
#define GMAC_DEBUG_TFCSTS_WAIT	1
#define GMAC_DEBUG_TFCSTS_GEN_PAUSE	2
#define GMAC_DEBUG_TFCSTS_XFER	3
/* MAC GMII or MII Transmit Protocol Engine Status */
#define GMAC_DEBUG_TPESTS	BIT(16)
#define GMAC_DEBUG_RXFSTS_MASK	GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
#define GMAC_DEBUG_RXFSTS_SHIFT	8
#define GMAC_DEBUG_RXFSTS_EMPTY	0
#define GMAC_DEBUG_RXFSTS_BT	1
#define GMAC_DEBUG_RXFSTS_AT	2
#define GMAC_DEBUG_RXFSTS_FULL	3
#define GMAC_DEBUG_RRCSTS_MASK	GENMASK(6, 5) /* MTL Rx FIFO Read Controller */
#define GMAC_DEBUG_RRCSTS_SHIFT	5
#define GMAC_DEBUG_RRCSTS_IDLE	0
#define GMAC_DEBUG_RRCSTS_RDATA	1
#define GMAC_DEBUG_RRCSTS_RSTAT	2
#define GMAC_DEBUG_RRCSTS_FLUSH	3
#define GMAC_DEBUG_RWCSTS	BIT(4) /* MTL Rx FIFO Write Controller Active */
/* MAC Receive Frame Controller FIFO Status */
#define GMAC_DEBUG_RFCFCSTS_MASK	GENMASK(2, 1)
#define GMAC_DEBUG_RFCFCSTS_SHIFT	1
/* MAC GMII or MII Receive Protocol Engine Status */
#define GMAC_DEBUG_RPESTS	BIT(0)

/*--- DMA BLOCK defines ---*/
/* DMA Bus Mode register defines */
#define DMA_BUS_MODE_DA		0x00000002	/* Arbitration scheme */
#define DMA_BUS_MODE_DSL_MASK	0x0000007c	/* Descriptor Skip Length */
#define DMA_BUS_MODE_DSL_SHIFT	2		/*   (in DWORDS)      */
/* Programmable burst length (passed thorugh platform)*/
#define DMA_BUS_MODE_PBL_MASK	0x00003f00	/* Programmable Burst Len */
#define DMA_BUS_MODE_PBL_SHIFT	8
#define DMA_BUS_MODE_ATDS	0x00000080	/* Alternate Descriptor Size */

enum rx_tx_priority_ratio {
	double_ratio = 0x00004000,	/* 2:1 */
	triple_ratio = 0x00008000,	/* 3:1 */
	quadruple_ratio = 0x0000c000,	/* 4:1 */
};

#define DMA_BUS_MODE_FB		0x00010000	/* Fixed burst */
#define DMA_BUS_MODE_MB		0x04000000	/* Mixed burst */
#define DMA_BUS_MODE_RPBL_MASK	0x007e0000	/* Rx-Programmable Burst Len */
#define DMA_BUS_MODE_RPBL_SHIFT	17
#define DMA_BUS_MODE_USP	0x00800000
#define DMA_BUS_MODE_MAXPBL	0x01000000
#define DMA_BUS_MODE_AAL	0x02000000

/* DMA CRS Control and Status Register Mapping */
#define DMA_HOST_TX_DESC	  0x00001048	/* Current Host Tx descriptor */
#define DMA_HOST_RX_DESC	  0x0000104c	/* Current Host Rx descriptor */
/*  DMA Bus Mode register defines */
#define DMA_BUS_PR_RATIO_MASK	  0x0000c000	/* Rx/Tx priority ratio */
#define DMA_BUS_PR_RATIO_SHIFT	  14
#define DMA_BUS_FB	  	  0x00010000	/* Fixed Burst */

/* DMA operation mode defines (start/stop tx/rx are placed in common header)*/
/* Disable Drop TCP/IP csum error */
#define DMA_CONTROL_DT		0x04000000
#define DMA_CONTROL_RSF		0x02000000	/* Receive Store and Forward */
#define DMA_CONTROL_DFF		0x01000000	/* Disaable flushing */
/* Threshold for Activating the FC */
enum rfa {
	act_full_minus_1 = 0x00800000,
	act_full_minus_2 = 0x00800200,
	act_full_minus_3 = 0x00800400,
	act_full_minus_4 = 0x00800600,
};
/* Threshold for Deactivating the FC */
enum rfd {
	deac_full_minus_1 = 0x00400000,
	deac_full_minus_2 = 0x00400800,
	deac_full_minus_3 = 0x00401000,
	deac_full_minus_4 = 0x00401800,
};
#define DMA_CONTROL_TSF	0x00200000	/* Transmit  Store and Forward */

enum ttc_control {
	DMA_CONTROL_TTC_64 = 0x00000000,
	DMA_CONTROL_TTC_128 = 0x00004000,
	DMA_CONTROL_TTC_192 = 0x00008000,
	DMA_CONTROL_TTC_256 = 0x0000c000,
	DMA_CONTROL_TTC_40 = 0x00010000,
	DMA_CONTROL_TTC_32 = 0x00014000,
	DMA_CONTROL_TTC_24 = 0x00018000,
	DMA_CONTROL_TTC_16 = 0x0001c000,
};
#define DMA_CONTROL_TC_TX_MASK	0xfffe3fff

#define DMA_CONTROL_EFC		0x00000100
#define DMA_CONTROL_FEF		0x00000080
#define DMA_CONTROL_FUF		0x00000040

/* Receive flow control activation field
 * RFA field in DMA control register, bits 23,10:9
 */
#define DMA_CONTROL_RFA_MASK	0x00800600

/* Receive flow control deactivation field
 * RFD field in DMA control register, bits 22,12:11
 */
#define DMA_CONTROL_RFD_MASK	0x00401800

/* RFD and RFA fields are encoded as follows
 *
 *   Bit Field
 *   0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled)
 *   0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled)
 *   0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled)
 *   0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled)
 *   1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled)
 *   1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled)
 *   1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled)
 *   1,11 - Reserved
 *
 * RFD should always be > RFA for a given FIFO size. RFD == RFA may work,
 * but packet throughput performance may not be as expected.
 *
 * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame
 * detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause
 * Description).
 *
 * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6),
 * is set to 0. This allows pause frames with a quanta of 0 to be sent
 * as an XOFF message to the link peer.
 */

#define RFA_FULL_MINUS_1K	0x00000000
#define RFA_FULL_MINUS_2K	0x00000200
#define RFA_FULL_MINUS_3K	0x00000400
#define RFA_FULL_MINUS_4K	0x00000600
#define RFA_FULL_MINUS_5K	0x00800000
#define RFA_FULL_MINUS_6K	0x00800200
#define RFA_FULL_MINUS_7K	0x00800400

#define RFD_FULL_MINUS_1K	0x00000000
#define RFD_FULL_MINUS_2K	0x00000800
#define RFD_FULL_MINUS_3K	0x00001000
#define RFD_FULL_MINUS_4K	0x00001800
#define RFD_FULL_MINUS_5K	0x00400000
#define RFD_FULL_MINUS_6K	0x00400800
#define RFD_FULL_MINUS_7K	0x00401000

enum rtc_control {
	DMA_CONTROL_RTC_64 = 0x00000000,
	DMA_CONTROL_RTC_32 = 0x00000008,
	DMA_CONTROL_RTC_96 = 0x00000010,
	DMA_CONTROL_RTC_128 = 0x00000018,
};
#define DMA_CONTROL_TC_RX_MASK	0xffffffe7

#define DMA_CONTROL_OSF	0x00000004	/* Operate on second frame */

/* MMC registers offset */
#define GMAC_MMC_CTRL      0x100
#define GMAC_MMC_RX_INTR   0x104
#define GMAC_MMC_TX_INTR   0x108
#define GMAC_MMC_RX_CSUM_OFFLOAD   0x208
#define GMAC_EXTHASH_BASE  0x500

extern const struct stmmac_dma_ops dwmac1000_dma_ops;
#endif /* __DWMAC1000_H__ */
Commit	Line	Data
47dd7a54 GC	1	/*******************************************************************************
	2	Copyright (C) 2007-2009 STMicroelectronics Ltd
	3
	4	This program is free software; you can redistribute it and/or modify it
	5	under the terms and conditions of the GNU General Public License,
	6	version 2, as published by the Free Software Foundation.
	7
	8	This program is distributed in the hope it will be useful, but WITHOUT
	9	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	more details.
	12
47dd7a54 GC	13	The full GNU General Public License is included in this distribution in
	14	the file called "COPYING".
	15
	16	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	17	*******************************************************************************/
bd4242df RK	18	#ifndef __DWMAC1000_H__
bd4242df RK	19	#define __DWMAC1000_H__
47dd7a54	20
21d437cc GC	21	#include <linux/phy.h>
	22	#include "common.h"
	23
47dd7a54 GC	24	#define GMAC_CONTROL 0x00000000 /* Configuration */
	25	#define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */
	26	#define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */
	27	#define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */
	28	#define GMAC_MII_ADDR 0x00000010 /* MII Address */
	29	#define GMAC_MII_DATA 0x00000014 /* MII Data */
	30	#define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */
	31	#define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */
2f7a791c	32	#define GMAC_DEBUG 0x00000024 /* GMAC debug register */
47dd7a54 GC	33	#define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
	34
	35	#define GMAC_INT_STATUS 0x00000038 /* interrupt status register */
3fe5cadb GC	36	#define GMAC_INT_STATUS_PMT BIT(3)
	37	#define GMAC_INT_STATUS_MMCIS BIT(4)
	38	#define GMAC_INT_STATUS_MMCRIS BIT(5)
	39	#define GMAC_INT_STATUS_MMCTIS BIT(6)
	40	#define GMAC_INT_STATUS_MMCCSUM BIT(7)
	41	#define GMAC_INT_STATUS_TSTAMP BIT(9)
	42	#define GMAC_INT_STATUS_LPIIS BIT(10)
	43
	44	/* interrupt mask register */
	45	#define GMAC_INT_MASK 0x0000003c
	46	#define GMAC_INT_DISABLE_RGMII BIT(0)
	47	#define GMAC_INT_DISABLE_PCSLINK BIT(1)
	48	#define GMAC_INT_DISABLE_PCSAN BIT(2)
	49	#define GMAC_INT_DISABLE_PMT BIT(3)
	50	#define GMAC_INT_DISABLE_TIMESTAMP BIT(9)
	51	#define GMAC_INT_DISABLE_PCS (GMAC_INT_DISABLE_RGMII \| \
	52	GMAC_INT_DISABLE_PCSLINK \| \
	53	GMAC_INT_DISABLE_PCSAN)
	54	#define GMAC_INT_DEFAULT_MASK (GMAC_INT_DISABLE_TIMESTAMP \| \
	55	GMAC_INT_DISABLE_PCS)
47dd7a54 GC	56
	57	/* PMT Control and Status */
	58	#define GMAC_PMT 0x0000002c
	59	enum power_event {
	60	pointer_reset = 0x80000000,
	61	global_unicast = 0x00000200,
	62	wake_up_rx_frame = 0x00000040,
	63	magic_frame = 0x00000020,
	64	wake_up_frame_en = 0x00000004,
	65	magic_pkt_en = 0x00000002,
	66	power_down = 0x00000001,
	67	};
	68
d765955d GC	69	/* Energy Efficient Ethernet (EEE)
	70	*
	71	* LPI status, timer and control register offset
	72	*/
	73	#define LPI_CTRL_STATUS 0x0030
	74	#define LPI_TIMER_CTRL 0x0034
	75
	76	/* LPI control and status defines */
	77	#define LPI_CTRL_STATUS_LPITXA 0x00080000 /* Enable LPI TX Automate */
	78	#define LPI_CTRL_STATUS_PLSEN 0x00040000 /* Enable PHY Link Status */
	79	#define LPI_CTRL_STATUS_PLS 0x00020000 /* PHY Link Status */
	80	#define LPI_CTRL_STATUS_LPIEN 0x00010000 /* LPI Enable */
	81	#define LPI_CTRL_STATUS_RLPIST 0x00000200 /* Receive LPI state */
	82	#define LPI_CTRL_STATUS_TLPIST 0x00000100 /* Transmit LPI state */
	83	#define LPI_CTRL_STATUS_RLPIEX 0x00000008 /* Receive LPI Exit */
	84	#define LPI_CTRL_STATUS_RLPIEN 0x00000004 /* Receive LPI Entry */
	85	#define LPI_CTRL_STATUS_TLPIEX 0x00000002 /* Transmit LPI Exit */
	86	#define LPI_CTRL_STATUS_TLPIEN 0x00000001 /* Transmit LPI Entry */
	87
47dd7a54	88	/* GMAC HW ADDR regs */
cffb13f4 GC	89	#define GMAC_ADDR_HIGH(reg) (((reg > 15) ? 0x00000800 : 0x00000040) + \
	90	(reg * 8))
	91	#define GMAC_ADDR_LOW(reg) (((reg > 15) ? 0x00000804 : 0x00000044) + \
	92	(reg * 8))
aefef4c1	93	#define GMAC_MAX_PERFECT_ADDRESSES 1
47dd7a54	94
70523e63 GC	95	#define GMAC_PCS_BASE 0x000000c0 /* PCS register base */
	96	#define GMAC_RGSMIIIS 0x000000d8 /* RGMII/SMII status */
	97
	98	/* SGMII/RGMII status register */
	99	#define GMAC_RGSMIIIS_LNKMODE BIT(0)
	100	#define GMAC_RGSMIIIS_SPEED GENMASK(2, 1)
	101	#define GMAC_RGSMIIIS_SPEED_SHIFT 1
	102	#define GMAC_RGSMIIIS_LNKSTS BIT(3)
	103	#define GMAC_RGSMIIIS_JABTO BIT(4)
	104	#define GMAC_RGSMIIIS_FALSECARDET BIT(5)
	105	#define GMAC_RGSMIIIS_SMIDRXS BIT(16)
	106	/* LNKMOD */
	107	#define GMAC_RGSMIIIS_LNKMOD_MASK 0x1
	108	/* LNKSPEED */
	109	#define GMAC_RGSMIIIS_SPEED_125 0x2
	110	#define GMAC_RGSMIIIS_SPEED_25 0x1
	111	#define GMAC_RGSMIIIS_SPEED_2_5 0x0
e58bb43f	112
47dd7a54	113	/* GMAC Configuration defines */
2618abb7	114	#define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */
47dd7a54 GC	115	#define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */
	116	#define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */
	117	#define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */
	118	#define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
	119	#define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */
	120	enum inter_frame_gap {
	121	GMAC_CONTROL_IFG_88 = 0x00040000,
	122	GMAC_CONTROL_IFG_80 = 0x00020000,
	123	GMAC_CONTROL_IFG_40 = 0x000e0000,
	124	};
ceb69499 GC	125	#define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense */
	126	#define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */
	127	#define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */
	128	#define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */
	129	#define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
	130	#define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */
	131	#define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */
	132	#define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */
	133	#define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */
	134	#define GMAC_CONTROL_ACS 0x00000080 /* Auto Pad/FCS Stripping */
	135	#define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */
	136	#define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
	137	#define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
47dd7a54 GC	138
47dd7a54 GC	139	#define GMAC_CORE_INIT (GMAC_CONTROL_JD \| GMAC_CONTROL_PS \| GMAC_CONTROL_ACS \| \
b1dee479	140	GMAC_CONTROL_BE \| GMAC_CONTROL_DCRS)
47dd7a54 GC	141
	142	/* GMAC Frame Filter defines */
	143	#define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
	144	#define GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */
	145	#define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */
	146	#define GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */
	147	#define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */
	148	#define GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */
	149	#define GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */
	150	#define GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */
	151	#define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */
	152	#define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */
	153	/* GMII ADDR defines */
	154	#define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */
	155	#define GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */
	156	/* GMAC FLOW CTRL defines */
	157	#define GMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */
	158	#define GMAC_FLOW_CTRL_PT_SHIFT 16
2453beb6	159	#define GMAC_FLOW_CTRL_UP 0x00000008 /* Unicast pause frame enable */
47dd7a54 GC	160	#define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
	161	#define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
	162	#define GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */
	163
2f7a791c GC	164	/* DEBUG Register defines */
	165	/* MTL TxStatus FIFO */
	166	#define GMAC_DEBUG_TXSTSFSTS BIT(25) /* MTL TxStatus FIFO Full Status */
	167	#define GMAC_DEBUG_TXFSTS BIT(24) /* MTL Tx FIFO Not Empty Status */
	168	#define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */
	169	/* MTL Tx FIFO Read Controller Status */
	170	#define GMAC_DEBUG_TRCSTS_MASK GENMASK(21, 20)
	171	#define GMAC_DEBUG_TRCSTS_SHIFT 20
	172	#define GMAC_DEBUG_TRCSTS_IDLE 0
	173	#define GMAC_DEBUG_TRCSTS_READ 1
	174	#define GMAC_DEBUG_TRCSTS_TXW 2
	175	#define GMAC_DEBUG_TRCSTS_WRITE 3
	176	#define GMAC_DEBUG_TXPAUSED BIT(19) /* MAC Transmitter in PAUSE */
	177	/* MAC Transmit Frame Controller Status */
	178	#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
	179	#define GMAC_DEBUG_TFCSTS_SHIFT 17
	180	#define GMAC_DEBUG_TFCSTS_IDLE 0
	181	#define GMAC_DEBUG_TFCSTS_WAIT 1
	182	#define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
	183	#define GMAC_DEBUG_TFCSTS_XFER 3
	184	/* MAC GMII or MII Transmit Protocol Engine Status */
	185	#define GMAC_DEBUG_TPESTS BIT(16)
	186	#define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
	187	#define GMAC_DEBUG_RXFSTS_SHIFT 8
	188	#define GMAC_DEBUG_RXFSTS_EMPTY 0
	189	#define GMAC_DEBUG_RXFSTS_BT 1
	190	#define GMAC_DEBUG_RXFSTS_AT 2
	191	#define GMAC_DEBUG_RXFSTS_FULL 3
	192	#define GMAC_DEBUG_RRCSTS_MASK GENMASK(6, 5) /* MTL Rx FIFO Read Controller */
	193	#define GMAC_DEBUG_RRCSTS_SHIFT 5
	194	#define GMAC_DEBUG_RRCSTS_IDLE 0
	195	#define GMAC_DEBUG_RRCSTS_RDATA 1
	196	#define GMAC_DEBUG_RRCSTS_RSTAT 2
	197	#define GMAC_DEBUG_RRCSTS_FLUSH 3
	198	#define GMAC_DEBUG_RWCSTS BIT(4) /* MTL Rx FIFO Write Controller Active */
	199	/* MAC Receive Frame Controller FIFO Status */
	200	#define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
	201	#define GMAC_DEBUG_RFCFCSTS_SHIFT 1
	202	/* MAC GMII or MII Receive Protocol Engine Status */
	203	#define GMAC_DEBUG_RPESTS BIT(0)
	204
47dd7a54 GC	205	/--- DMA BLOCK defines ---/
47dd7a54 GC	206	/* DMA Bus Mode register defines */
47dd7a54 GC	207	#define DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */
47dd7a54 GC	208	#define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
ceb69499	209	#define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
47dd7a54 GC	210	/* Programmable burst length (passed thorugh platform)*/
	211	#define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
	212	#define DMA_BUS_MODE_PBL_SHIFT 8
c24602ef	213	#define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */
47dd7a54 GC	214
47dd7a54 GC	215	enum rx_tx_priority_ratio {
ceb69499 GC	216	double_ratio = 0x00004000, /* 2:1 */
	217	triple_ratio = 0x00008000, /* 3:1 */
	218	quadruple_ratio = 0x0000c000, /* 4:1 */
47dd7a54 GC	219	};
	220
	221	#define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
b9cde0a8	222	#define DMA_BUS_MODE_MB 0x04000000 /* Mixed burst */
825658a2	223	#define DMA_BUS_MODE_RPBL_MASK 0x007e0000 /* Rx-Programmable Burst Len */
47dd7a54 GC	224	#define DMA_BUS_MODE_RPBL_SHIFT 17
47dd7a54 GC	225	#define DMA_BUS_MODE_USP 0x00800000
afea0365	226	#define DMA_BUS_MODE_MAXPBL 0x01000000
47dd7a54 GC	227	#define DMA_BUS_MODE_AAL 0x02000000
	228
	229	/* DMA CRS Control and Status Register Mapping */
	230	#define DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */
	231	#define DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */
	232	/* DMA Bus Mode register defines */
	233	#define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */
	234	#define DMA_BUS_PR_RATIO_SHIFT 14
	235	#define DMA_BUS_FB 0x00010000 /* Fixed Burst */
	236
	237	/* DMA operation mode defines (start/stop tx/rx are placed in common header)*/
ceb69499 GC	238	/* Disable Drop TCP/IP csum error */
	239	#define DMA_CONTROL_DT 0x04000000
	240	#define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */
	241	#define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */
af901ca1	242	/* Threshold for Activating the FC */
47dd7a54 GC	243	enum rfa {
	244	act_full_minus_1 = 0x00800000,
	245	act_full_minus_2 = 0x00800200,
	246	act_full_minus_3 = 0x00800400,
	247	act_full_minus_4 = 0x00800600,
	248	};
af901ca1	249	/* Threshold for Deactivating the FC */
47dd7a54 GC	250	enum rfd {
	251	deac_full_minus_1 = 0x00400000,
	252	deac_full_minus_2 = 0x00400800,
	253	deac_full_minus_3 = 0x00401000,
	254	deac_full_minus_4 = 0x00401800,
	255	};
ceb69499	256	#define DMA_CONTROL_TSF 0x00200000 /* Transmit Store and Forward */
47dd7a54 GC	257
	258	enum ttc_control {
	259	DMA_CONTROL_TTC_64 = 0x00000000,
	260	DMA_CONTROL_TTC_128 = 0x00004000,
	261	DMA_CONTROL_TTC_192 = 0x00008000,
	262	DMA_CONTROL_TTC_256 = 0x0000c000,
	263	DMA_CONTROL_TTC_40 = 0x00010000,
	264	DMA_CONTROL_TTC_32 = 0x00014000,
	265	DMA_CONTROL_TTC_24 = 0x00018000,
	266	DMA_CONTROL_TTC_16 = 0x0001c000,
	267	};
	268	#define DMA_CONTROL_TC_TX_MASK 0xfffe3fff
	269
	270	#define DMA_CONTROL_EFC 0x00000100
	271	#define DMA_CONTROL_FEF 0x00000080
	272	#define DMA_CONTROL_FUF 0x00000040
	273
2453beb6 VB	274	/* Receive flow control activation field
	275	* RFA field in DMA control register, bits 23,10:9
	276	*/
	277	#define DMA_CONTROL_RFA_MASK 0x00800600
	278
	279	/* Receive flow control deactivation field
	280	* RFD field in DMA control register, bits 22,12:11
	281	*/
	282	#define DMA_CONTROL_RFD_MASK 0x00401800
	283
	284	/* RFD and RFA fields are encoded as follows
	285	*
	286	* Bit Field
	287	* 0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled)
	288	* 0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled)
	289	* 0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled)
	290	* 0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled)
	291	* 1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled)
	292	* 1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled)
	293	* 1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled)
	294	* 1,11 - Reserved
	295	*
	296	* RFD should always be > RFA for a given FIFO size. RFD == RFA may work,
	297	* but packet throughput performance may not be as expected.
	298	*
	299	* Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame
	300	* detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause
	301	* Description).
	302	*
	303	* Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6),
	304	* is set to 0. This allows pause frames with a quanta of 0 to be sent
	305	* as an XOFF message to the link peer.
	306	*/
	307
	308	#define RFA_FULL_MINUS_1K 0x00000000
	309	#define RFA_FULL_MINUS_2K 0x00000200
	310	#define RFA_FULL_MINUS_3K 0x00000400
	311	#define RFA_FULL_MINUS_4K 0x00000600
	312	#define RFA_FULL_MINUS_5K 0x00800000
	313	#define RFA_FULL_MINUS_6K 0x00800200
	314	#define RFA_FULL_MINUS_7K 0x00800400
	315
	316	#define RFD_FULL_MINUS_1K 0x00000000
	317	#define RFD_FULL_MINUS_2K 0x00000800
	318	#define RFD_FULL_MINUS_3K 0x00001000
	319	#define RFD_FULL_MINUS_4K 0x00001800
	320	#define RFD_FULL_MINUS_5K 0x00400000
	321	#define RFD_FULL_MINUS_6K 0x00400800
	322	#define RFD_FULL_MINUS_7K 0x00401000
	323
47dd7a54 GC	324	enum rtc_control {
	325	DMA_CONTROL_RTC_64 = 0x00000000,
	326	DMA_CONTROL_RTC_32 = 0x00000008,
	327	DMA_CONTROL_RTC_96 = 0x00000010,
	328	DMA_CONTROL_RTC_128 = 0x00000018,
	329	};
	330	#define DMA_CONTROL_TC_RX_MASK 0xffffffe7
	331
	332	#define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */
	333
	334	/* MMC registers offset */
	335	#define GMAC_MMC_CTRL 0x100
	336	#define GMAC_MMC_RX_INTR 0x104
	337	#define GMAC_MMC_TX_INTR 0x108
	338	#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208
3b57de95	339	#define GMAC_EXTHASH_BASE 0x500
21d437cc	340
cadb7924	341	extern const struct stmmac_dma_ops dwmac1000_dma_ops;
bd4242df	342	#endif /* __DWMAC1000_H__ */