[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / dwmac-socfpga.c

/* Copyright Altera Corporation (C) 2014. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2,
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * Adopted from dwmac-sti.c
 */

#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_net.h>
#include <linux/phy.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/stmmac.h>
#include "stmmac.h"

#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003

struct socfpga_dwmac {
	int	interface;
	u32	reg_offset;
	u32	reg_shift;
	struct	device *dev;
	struct regmap *sys_mgr_base_addr;
	struct reset_control *stmmac_rst;
};

static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
{
	struct device_node *np = dev->of_node;
	struct regmap *sys_mgr_base_addr;
	u32 reg_offset, reg_shift;
	int ret;

	dwmac->stmmac_rst = devm_reset_control_get(dev,
						  STMMAC_RESOURCE_NAME);
	if (IS_ERR(dwmac->stmmac_rst)) {
		dev_info(dev, "Could not get reset control!\n");
		return -EINVAL;
	}

	dwmac->interface = of_get_phy_mode(np);

	sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
	if (IS_ERR(sys_mgr_base_addr)) {
		dev_info(dev, "No sysmgr-syscon node found\n");
		return PTR_ERR(sys_mgr_base_addr);
	}

	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
	if (ret) {
		dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
		return -EINVAL;
	}

	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);
	if (ret) {
		dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
		return -EINVAL;
	}

	dwmac->reg_offset = reg_offset;
	dwmac->reg_shift = reg_shift;
	dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
	dwmac->dev = dev;

	return 0;
}

static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac)
{
	struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
	int phymode = dwmac->interface;
	u32 reg_offset = dwmac->reg_offset;
	u32 reg_shift = dwmac->reg_shift;
	u32 ctrl, val;

	switch (phymode) {
	case PHY_INTERFACE_MODE_RGMII:
		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
		break;
	case PHY_INTERFACE_MODE_MII:
	case PHY_INTERFACE_MODE_GMII:
		val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
		break;
	default:
		dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
		return -EINVAL;
	}

	regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
	ctrl |= val << reg_shift;

	regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
	return 0;
}

static void *socfpga_dwmac_probe(struct platform_device *pdev)
{
	struct device		*dev = &pdev->dev;
	int			ret;
	struct socfpga_dwmac	*dwmac;

	dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
	if (!dwmac)
		return ERR_PTR(-ENOMEM);

	ret = socfpga_dwmac_parse_data(dwmac, dev);
	if (ret) {
		dev_err(dev, "Unable to parse OF data\n");
		return ERR_PTR(ret);
	}

	ret = socfpga_dwmac_setup(dwmac);
	if (ret) {
		dev_err(dev, "couldn't setup SoC glue (%d)\n", ret);
		return ERR_PTR(ret);
	}

	return dwmac;
}

static void socfpga_dwmac_exit(struct platform_device *pdev, void *priv)
{
	struct socfpga_dwmac	*dwmac = priv;

	/* On socfpga platform exit, assert and hold reset to the
	 * enet controller - the default state after a hard reset.
	 */
	if (dwmac->stmmac_rst)
		reset_control_assert(dwmac->stmmac_rst);
}

static int socfpga_dwmac_init(struct platform_device *pdev, void *priv)
{
	struct socfpga_dwmac	*dwmac = priv;
	struct net_device *ndev = platform_get_drvdata(pdev);
	struct stmmac_priv *stpriv = NULL;
	int ret = 0;

	if (ndev)
		stpriv = netdev_priv(ndev);

	/* Assert reset to the enet controller before changing the phy mode */
	if (dwmac->stmmac_rst)
		reset_control_assert(dwmac->stmmac_rst);

	/* Setup the phy mode in the system manager registers according to
	 * devicetree configuration
	 */
	ret = socfpga_dwmac_setup(dwmac);

	/* Deassert reset for the phy configuration to be sampled by
	 * the enet controller, and operation to start in requested mode
	 */
	if (dwmac->stmmac_rst)
		reset_control_deassert(dwmac->stmmac_rst);

	/* Before the enet controller is suspended, the phy is suspended.
	 * This causes the phy clock to be gated. The enet controller is
	 * resumed before the phy, so the clock is still gated "off" when
	 * the enet controller is resumed. This code makes sure the phy
	 * is "resumed" before reinitializing the enet controller since
	 * the enet controller depends on an active phy clock to complete
	 * a DMA reset. A DMA reset will "time out" if executed
	 * with no phy clock input on the Synopsys enet controller.
	 * Verified through Synopsys Case #8000711656.
	 *
	 * Note that the phy clock is also gated when the phy is isolated.
	 * Phy "suspend" and "isolate" controls are located in phy basic
	 * control register 0, and can be modified by the phy driver
	 * framework.
	 */
	if (stpriv && stpriv->phydev)
		phy_resume(stpriv->phydev);

	return ret;
}

const struct stmmac_of_data socfpga_gmac_data = {
	.setup = socfpga_dwmac_probe,
	.init = socfpga_dwmac_init,
	.exit = socfpga_dwmac_exit,
};
Commit	Line	Data
801d233b DN	1	/* Copyright Altera Corporation (C) 2014. All rights reserved.
	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License, version 2,
	5	* as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	14	*
	15	* Adopted from dwmac-sti.c
	16	*/
	17
	18	#include <linux/mfd/syscon.h>
	19	#include <linux/of.h>
	20	#include <linux/of_net.h>
	21	#include <linux/phy.h>
	22	#include <linux/regmap.h>
2d871aa0	23	#include <linux/reset.h>
801d233b	24	#include <linux/stmmac.h>
2d871aa0	25	#include "stmmac.h"
801d233b DN	26
	27	#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
	28	#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
	29	#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
	30	#define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
	31	#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
	32
	33	struct socfpga_dwmac {
	34	int interface;
	35	u32 reg_offset;
	36	u32 reg_shift;
	37	struct device *dev;
	38	struct regmap *sys_mgr_base_addr;
2d871aa0	39	struct reset_control *stmmac_rst;
801d233b DN	40	};
	41
	42	static int socfpga_dwmac_parse_data(struct socfpga_dwmac dwmac, struct device dev)
	43	{
	44	struct device_node *np = dev->of_node;
	45	struct regmap *sys_mgr_base_addr;
	46	u32 reg_offset, reg_shift;
	47	int ret;
	48
2d871aa0 VB	49	dwmac->stmmac_rst = devm_reset_control_get(dev,
	50	STMMAC_RESOURCE_NAME);
	51	if (IS_ERR(dwmac->stmmac_rst)) {
	52	dev_info(dev, "Could not get reset control!\n");
	53	return -EINVAL;
	54	}
	55
801d233b DN	56	dwmac->interface = of_get_phy_mode(np);
	57
	58	sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
	59	if (IS_ERR(sys_mgr_base_addr)) {
	60	dev_info(dev, "No sysmgr-syscon node found\n");
	61	return PTR_ERR(sys_mgr_base_addr);
	62	}
	63
	64	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
	65	if (ret) {
	66	dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
	67	return -EINVAL;
	68	}
	69
	70	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);
	71	if (ret) {
	72	dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
	73	return -EINVAL;
	74	}
	75
	76	dwmac->reg_offset = reg_offset;
	77	dwmac->reg_shift = reg_shift;
	78	dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
	79	dwmac->dev = dev;
	80
	81	return 0;
	82	}
	83
	84	static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac)
	85	{
	86	struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
	87	int phymode = dwmac->interface;
	88	u32 reg_offset = dwmac->reg_offset;
	89	u32 reg_shift = dwmac->reg_shift;
	90	u32 ctrl, val;
	91
	92	switch (phymode) {
	93	case PHY_INTERFACE_MODE_RGMII:
	94	val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
	95	break;
	96	case PHY_INTERFACE_MODE_MII:
	97	case PHY_INTERFACE_MODE_GMII:
	98	val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
	99	break;
	100	default:
	101	dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
	102	return -EINVAL;
	103	}
	104
	105	regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
	106	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
	107	ctrl \|= val << reg_shift;
	108
	109	regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
	110	return 0;
	111	}
	112
	113	static void socfpga_dwmac_probe(struct platform_device pdev)
	114	{
	115	struct device *dev = &pdev->dev;
	116	int ret;
	117	struct socfpga_dwmac *dwmac;
	118
	119	dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
120	if (!dwmac)
121	return ERR_PTR(-ENOMEM);
122
123	ret = socfpga_dwmac_parse_data(dwmac, dev);
124	if (ret) {
125	dev_err(dev, "Unable to parse OF data\n");
126	return ERR_PTR(ret);
127	}
128
129	ret = socfpga_dwmac_setup(dwmac);
130	if (ret) {
131	dev_err(dev, "couldn't setup SoC glue (%d)\n", ret);
132	return ERR_PTR(ret);
133	}
134
135	return dwmac;
136	}
137
2d871aa0 VB	138	static void socfpga_dwmac_exit(struct platform_device pdev, void priv)
	139	{
	140	struct socfpga_dwmac *dwmac = priv;
	141
	142	/* On socfpga platform exit, assert and hold reset to the
	143	* enet controller - the default state after a hard reset.
	144	*/
	145	if (dwmac->stmmac_rst)
	146	reset_control_assert(dwmac->stmmac_rst);
	147	}
	148
	149	static int socfpga_dwmac_init(struct platform_device pdev, void priv)
	150	{
	151	struct socfpga_dwmac *dwmac = priv;
	152	struct net_device *ndev = platform_get_drvdata(pdev);
	153	struct stmmac_priv *stpriv = NULL;
	154	int ret = 0;
	155
	156	if (ndev)
	157	stpriv = netdev_priv(ndev);
	158
	159	/* Assert reset to the enet controller before changing the phy mode */
	160	if (dwmac->stmmac_rst)
	161	reset_control_assert(dwmac->stmmac_rst);
	162
	163	/* Setup the phy mode in the system manager registers according to
	164	* devicetree configuration
	165	*/
	166	ret = socfpga_dwmac_setup(dwmac);
	167
	168	/* Deassert reset for the phy configuration to be sampled by
	169	* the enet controller, and operation to start in requested mode
	170	*/
	171	if (dwmac->stmmac_rst)
	172	reset_control_deassert(dwmac->stmmac_rst);
	173
	174	/* Before the enet controller is suspended, the phy is suspended.
	175	* This causes the phy clock to be gated. The enet controller is
	176	* resumed before the phy, so the clock is still gated "off" when
	177	* the enet controller is resumed. This code makes sure the phy
	178	* is "resumed" before reinitializing the enet controller since
	179	* the enet controller depends on an active phy clock to complete
	180	* a DMA reset. A DMA reset will "time out" if executed
	181	* with no phy clock input on the Synopsys enet controller.
	182	* Verified through Synopsys Case #8000711656.
	183	*
	184	* Note that the phy clock is also gated when the phy is isolated.
	185	* Phy "suspend" and "isolate" controls are located in phy basic
	186	* control register 0, and can be modified by the phy driver
	187	* framework.
	188	*/
	189	if (stpriv && stpriv->phydev)
	190	phy_resume(stpriv->phydev);
	191
	192	return ret;
	193	}
	194
801d233b DN	195	const struct stmmac_of_data socfpga_gmac_data = {
801d233b DN	196	.setup = socfpga_dwmac_probe,
2d871aa0 VB	197	.init = socfpga_dwmac_init,
2d871aa0 VB	198	.exit = socfpga_dwmac_exit,
801d233b	199	};