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stmmac: add tx_skbuff_dma to save descriptors used by PTP
[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / common.h
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 STMMAC Common Header File
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23*******************************************************************************/
24
bd4242df
RK		 25#ifndef __COMMON_H__
26#define __COMMON_H__
27
bfab27a1 28#include <linux/etherdevice.h>
5e33c791 29#include <linux/netdevice.h>
bfab27a1
GC		 30#include <linux/phy.h>
31#include <linux/module.h>
32#include <linux/init.h>
8f617541
GC		 33#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
34#define STMMAC_VLAN_TAG_USED
35#include <linux/if_vlan.h>
36#endif
37
56b106ae 38#include "descs.h"
1c901a46 39#include "mmc.h"
56b106ae
GC		 40
41#undef CHIP_DEBUG_PRINT
42/* Turn-on extra printk debug for MAC core, dma and descriptors */
43/* #define CHIP_DEBUG_PRINT */
44
45#ifdef CHIP_DEBUG_PRINT
46#define CHIP_DBG(fmt, args...) printk(fmt, ## args)
47#else
48#define CHIP_DBG(fmt, args...) do { } while (0)
49#endif
50
62a2ab93
GC		 51/* Synopsys Core versions */
52#define DWMAC_CORE_3_40 0x34
53#define DWMAC_CORE_3_50 0x35
54
56b106ae
GC		 55#undef FRAME_FILTER_DEBUG
56/* #define FRAME_FILTER_DEBUG */
47dd7a54 57
47dd7a54
GC		 58struct stmmac_extra_stats {
59 /* Transmit errors */
60 unsigned long tx_underflow ____cacheline_aligned;
61 unsigned long tx_carrier;
62 unsigned long tx_losscarrier;
3c20f72f 63 unsigned long vlan_tag;
47dd7a54
GC		 64 unsigned long tx_deferred;
65 unsigned long tx_vlan;
66 unsigned long tx_jabber;
67 unsigned long tx_frame_flushed;
68 unsigned long tx_payload_error;
69 unsigned long tx_ip_header_error;
70 /* Receive errors */
71 unsigned long rx_desc;
3c20f72f
GC		 72 unsigned long sa_filter_fail;
73 unsigned long overflow_error;
74 unsigned long ipc_csum_error;
47dd7a54
GC		 75 unsigned long rx_collision;
76 unsigned long rx_crc;
1cc5a735 77 unsigned long dribbling_bit;
1b924032 78 unsigned long rx_length;
47dd7a54
GC		 79 unsigned long rx_mii;
80 unsigned long rx_multicast;
81 unsigned long rx_gmac_overflow;
82 unsigned long rx_watchdog;
83 unsigned long da_rx_filter_fail;
84 unsigned long sa_rx_filter_fail;
85 unsigned long rx_missed_cntr;
86 unsigned long rx_overflow_cntr;
87 unsigned long rx_vlan;
62a2ab93 88 /* Tx/Rx IRQ error info */
47dd7a54
GC		 89 unsigned long tx_undeflow_irq;
90 unsigned long tx_process_stopped_irq;
91 unsigned long tx_jabber_irq;
92 unsigned long rx_overflow_irq;
93 unsigned long rx_buf_unav_irq;
94 unsigned long rx_process_stopped_irq;
95 unsigned long rx_watchdog_irq;
96 unsigned long tx_early_irq;
97 unsigned long fatal_bus_error_irq;
62a2ab93
GC		 98 /* Tx/Rx IRQ Events */
99 unsigned long rx_early_irq;
47dd7a54
GC		 100 unsigned long threshold;
101 unsigned long tx_pkt_n;
102 unsigned long rx_pkt_n;
47dd7a54 103 unsigned long normal_irq_n;
9125cdd1
GC		 104 unsigned long rx_normal_irq_n;
105 unsigned long napi_poll;
106 unsigned long tx_normal_irq_n;
107 unsigned long tx_clean;
108 unsigned long tx_reset_ic_bit;
62a2ab93
GC		 109 unsigned long irq_receive_pmt_irq_n;
110 /* MMC info */
d765955d
GC		 111 unsigned long mmc_tx_irq_n;
112 unsigned long mmc_rx_irq_n;
113 unsigned long mmc_rx_csum_offload_irq_n;
114 /* EEE */
d765955d
GC		 115 unsigned long irq_tx_path_in_lpi_mode_n;
116 unsigned long irq_tx_path_exit_lpi_mode_n;
117 unsigned long irq_rx_path_in_lpi_mode_n;
118 unsigned long irq_rx_path_exit_lpi_mode_n;
119 unsigned long phy_eee_wakeup_error_n;
c24602ef
GC		 120 /* Extended RDES status */
121 unsigned long ip_hdr_err;
122 unsigned long ip_payload_err;
123 unsigned long ip_csum_bypassed;
124 unsigned long ipv4_pkt_rcvd;
125 unsigned long ipv6_pkt_rcvd;
126 unsigned long rx_msg_type_ext_no_ptp;
127 unsigned long rx_msg_type_sync;
128 unsigned long rx_msg_type_follow_up;
129 unsigned long rx_msg_type_delay_req;
130 unsigned long rx_msg_type_delay_resp;
131 unsigned long rx_msg_type_pdelay_req;
132 unsigned long rx_msg_type_pdelay_resp;
133 unsigned long rx_msg_type_pdelay_follow_up;
134 unsigned long ptp_frame_type;
135 unsigned long ptp_ver;
136 unsigned long timestamp_dropped;
137 unsigned long av_pkt_rcvd;
138 unsigned long av_tagged_pkt_rcvd;
139 unsigned long vlan_tag_priority_val;
140 unsigned long l3_filter_match;
141 unsigned long l4_filter_match;
142 unsigned long l3_l4_filter_no_match;
0982a0f6
GC		 143 /* PCS */
144 unsigned long irq_pcs_ane_n;
145 unsigned long irq_pcs_link_n;
146 unsigned long irq_rgmii_n;
e58bb43f
GC		 147 unsigned long pcs_link;
148 unsigned long pcs_duplex;
149 unsigned long pcs_speed;
47dd7a54
GC		 150};
151
cd7201f4
GC		 152/* CSR Frequency Access Defines*/
153#define CSR_F_35M 35000000
154#define CSR_F_60M 60000000
155#define CSR_F_100M 100000000
156#define CSR_F_150M 150000000
157#define CSR_F_250M 250000000
158#define CSR_F_300M 300000000
159
160#define MAC_CSR_H_FRQ_MASK 0x20
161
aec7ff27
GC		 162#define HASH_TABLE_SIZE 64
163#define PAUSE_TIME 0x200
164
165/* Flow Control defines */
166#define FLOW_OFF 0
167#define FLOW_RX 1
168#define FLOW_TX 2
169#define FLOW_AUTO (FLOW_TX | FLOW_RX)
170
e58bb43f
GC		 171/* PCS defines */
172#define STMMAC_PCS_RGMII (1 << 0)
173#define STMMAC_PCS_SGMII (1 << 1)
174#define STMMAC_PCS_TBI (1 << 2)
175#define STMMAC_PCS_RTBI (1 << 3)
176
aec7ff27
GC		 177#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
178
1db123fb
RK		 179/* DAM HW feature register fields */
180#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
181#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
182#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
183#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
184#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
185#define DMA_HW_FEAT_ADDMACADRSEL 0x00000020 /* Multiple MAC Addr Reg */
186#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
187#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
188#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
189#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
190#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
191#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
192#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 Timestamp */
193#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 Adv Timestamp */
194#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
195#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
196#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
197#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP csum Offload(Type 1) in Rx */
198#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP csum Offload(Type 2) in Rx */
199#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
200#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. of additional Rx Channels */
201#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. of additional Tx Channels */
202#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate (Enhanced Descriptor) */
203#define DMA_HW_FEAT_INTTSEN 0x02000000 /* Timestamping with Internal
204 System Time */
205#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
206#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN Insertion */
207#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY interface */
0f1f88a8 208#define DEFAULT_DMA_PBL 8
1db123fb 209
62a2ab93
GC		 210/* Max/Min RI Watchdog Timer count value */
211#define MAX_DMA_RIWT 0xff
212#define MIN_DMA_RIWT 0x20
9125cdd1
GC		 213/* Tx coalesce parameters */
214#define STMMAC_COAL_TX_TIMER 40000
215#define STMMAC_MAX_COAL_TX_TICK 100000
216#define STMMAC_TX_MAX_FRAMES 256
217#define STMMAC_TX_FRAMES 64
218
aec7ff27 219enum rx_frame_status { /* IPC status */
47dd7a54
GC		 220 good_frame = 0,
221 discard_frame = 1,
222 csum_none = 2,
3eeb2997 223 llc_snap = 4,
47dd7a54
GC		 224};
225
9125cdd1
GC		 226enum dma_irq_status {
227 tx_hard_error = 0x1,
228 tx_hard_error_bump_tc = 0x2,
229 handle_rx = 0x4,
230 handle_tx = 0x8,
aec7ff27 231};
47dd7a54 232
0982a0f6
GC		 233#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 1)
234#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 2)
235#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 3)
236#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 4)
237
238#define CORE_PCS_ANE_COMPLETE (1 << 5)
239#define CORE_PCS_LINK_STATUS (1 << 6)
240#define CORE_RGMII_IRQ (1 << 7)
d765955d 241
e58bb43f
GC		 242struct rgmii_adv {
243 unsigned int pause;
244 unsigned int duplex;
245 unsigned int lp_pause;
246 unsigned int lp_duplex;
247};
248
249#define STMMAC_PCS_PAUSE 1
250#define STMMAC_PCS_ASYM_PAUSE 2
251
e7434821
GC		 252/* DMA HW capabilities */
253struct dma_features {
254 unsigned int mbps_10_100;
255 unsigned int mbps_1000;
256 unsigned int half_duplex;
257 unsigned int hash_filter;
258 unsigned int multi_addr;
259 unsigned int pcs;
260 unsigned int sma_mdio;
261 unsigned int pmt_remote_wake_up;
262 unsigned int pmt_magic_frame;
263 unsigned int rmon;
264 /* IEEE 1588-2002*/
265 unsigned int time_stamp;
266 /* IEEE 1588-2008*/
267 unsigned int atime_stamp;
268 /* 802.3az - Energy-Efficient Ethernet (EEE) */
269 unsigned int eee;
270 unsigned int av;
271 /* TX and RX csum */
272 unsigned int tx_coe;
273 unsigned int rx_coe_type1;
274 unsigned int rx_coe_type2;
275 unsigned int rxfifo_over_2048;
276 /* TX and RX number of channels */
277 unsigned int number_rx_channel;
278 unsigned int number_tx_channel;
279 /* Alternate (enhanced) DESC mode*/
280 unsigned int enh_desc;
281};
282
aec7ff27
GC		 283/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
284#define BUF_SIZE_16KiB 16384
285#define BUF_SIZE_8KiB 8192
286#define BUF_SIZE_4KiB 4096
287#define BUF_SIZE_2KiB 2048
47dd7a54 288
aec7ff27
GC		 289/* Power Down and WOL */
290#define PMT_NOT_SUPPORTED 0
291#define PMT_SUPPORTED 1
47dd7a54 292
aec7ff27
GC		 293/* Common MAC defines */
294#define MAC_CTRL_REG 0x00000000 /* MAC Control */
295#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
296#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
47dd7a54 297
d765955d
GC		 298/* Default LPI timers */
299#define STMMAC_DEFAULT_LIT_LS_TIMER 0x3E8
300#define STMMAC_DEFAULT_TWT_LS_TIMER 0x0
301
4a7d666a
GC		 302#define STMMAC_CHAIN_MODE 0x1
303#define STMMAC_RING_MODE 0x2
304
db98a0b0
GC		 305struct stmmac_desc_ops {
306 /* DMA RX descriptor ring initialization */
c24602ef
GC		 307 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
308 int end);
db98a0b0 309 /* DMA TX descriptor ring initialization */
c24602ef 310 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
47dd7a54
GC		 311
312 /* Invoked by the xmit function to prepare the tx descriptor */
313 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
4a7d666a 314 int csum_flag, int mode);
47dd7a54
GC		 315 /* Set/get the owner of the descriptor */
316 void (*set_tx_owner) (struct dma_desc *p);
317 int (*get_tx_owner) (struct dma_desc *p);
318 /* Invoked by the xmit function to close the tx descriptor */
319 void (*close_tx_desc) (struct dma_desc *p);
320 /* Clean the tx descriptor as soon as the tx irq is received */
4a7d666a 321 void (*release_tx_desc) (struct dma_desc *p, int mode);
47dd7a54
GC		 322 /* Clear interrupt on tx frame completion. When this bit is
323 * set an interrupt happens as soon as the frame is transmitted */
324 void (*clear_tx_ic) (struct dma_desc *p);
325 /* Last tx segment reports the transmit status */
326 int (*get_tx_ls) (struct dma_desc *p);
327 /* Return the transmit status looking at the TDES1 */
328 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
ad01b7d4 329 struct dma_desc *p, void __iomem *ioaddr);
47dd7a54
GC		 330 /* Get the buffer size from the descriptor */
331 int (*get_tx_len) (struct dma_desc *p);
332 /* Handle extra events on specific interrupts hw dependent */
47dd7a54
GC		 333 int (*get_rx_owner) (struct dma_desc *p);
334 void (*set_rx_owner) (struct dma_desc *p);
335 /* Get the receive frame size */
38912bdb 336 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
47dd7a54
GC		 337 /* Return the reception status looking at the RDES1 */
338 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
339 struct dma_desc *p);
c24602ef
GC		 340 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
341 struct dma_extended_desc *p);
db98a0b0
GC		 342};
343
344struct stmmac_dma_ops {
345 /* DMA core initialization */
b9cde0a8 346 int (*init) (void __iomem *ioaddr, int pbl, int fb, int mb,
c24602ef 347 int burst_len, u32 dma_tx, u32 dma_rx, int atds);
db98a0b0 348 /* Dump DMA registers */
ad01b7d4 349 void (*dump_regs) (void __iomem *ioaddr);
db98a0b0
GC		 350 /* Set tx/rx threshold in the csr6 register
351 * An invalid value enables the store-and-forward mode */
ad01b7d4 352 void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
db98a0b0
GC		 353 /* To track extra statistic (if supported) */
354 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
ad01b7d4
GC		 355 void __iomem *ioaddr);
356 void (*enable_dma_transmission) (void __iomem *ioaddr);
357 void (*enable_dma_irq) (void __iomem *ioaddr);
358 void (*disable_dma_irq) (void __iomem *ioaddr);
359 void (*start_tx) (void __iomem *ioaddr);
360 void (*stop_tx) (void __iomem *ioaddr);
361 void (*start_rx) (void __iomem *ioaddr);
362 void (*stop_rx) (void __iomem *ioaddr);
363 int (*dma_interrupt) (void __iomem *ioaddr,
aec7ff27 364 struct stmmac_extra_stats *x);
e7434821
GC		 365 /* If supported then get the optional core features */
366 unsigned int (*get_hw_feature) (void __iomem *ioaddr);
62a2ab93
GC		 367 /* Program the HW RX Watchdog */
368 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
db98a0b0
GC		 369};
370
371struct stmmac_ops {
372 /* MAC core initialization */
ad01b7d4 373 void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned;
38912bdb
DS		 374 /* Enable and verify that the IPC module is supported */
375 int (*rx_ipc) (void __iomem *ioaddr);
db98a0b0 376 /* Dump MAC registers */
ad01b7d4 377 void (*dump_regs) (void __iomem *ioaddr);
db98a0b0 378 /* Handle extra events on specific interrupts hw dependent */
0982a0f6
GC		 379 int (*host_irq_status) (void __iomem *ioaddr,
380 struct stmmac_extra_stats *x);
47dd7a54 381 /* Multicast filter setting */
cffb13f4 382 void (*set_filter) (struct net_device *dev, int id);
47dd7a54 383 /* Flow control setting */
ad01b7d4 384 void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
47dd7a54
GC		 385 unsigned int fc, unsigned int pause_time);
386 /* Set power management mode (e.g. magic frame) */
ad01b7d4 387 void (*pmt) (void __iomem *ioaddr, unsigned long mode);
47dd7a54 388 /* Set/Get Unicast MAC addresses */
ad01b7d4 389 void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
db98a0b0 390 unsigned int reg_n);
ad01b7d4 391 void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
db98a0b0 392 unsigned int reg_n);
d765955d
GC		 393 void (*set_eee_mode) (void __iomem *ioaddr);
394 void (*reset_eee_mode) (void __iomem *ioaddr);
395 void (*set_eee_timer) (void __iomem *ioaddr, int ls, int tw);
396 void (*set_eee_pls) (void __iomem *ioaddr, int link);
e58bb43f
GC		 397 void (*ctrl_ane) (void __iomem *ioaddr, bool restart);
398 void (*get_adv) (void __iomem *ioaddr, struct rgmii_adv *adv);
47dd7a54
GC		 399};
400
401struct mac_link {
402 int port;
403 int duplex;
404 int speed;
405};
406
407struct mii_regs {
408 unsigned int addr; /* MII Address */
409 unsigned int data; /* MII Data */
410};
411
286a8372
GC		 412struct stmmac_ring_mode_ops {
413 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
414 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
415 void (*refill_desc3) (int bfsize, struct dma_desc *p);
4a7d666a 416 void (*init_desc3) (struct dma_desc *p);
286a8372
GC		 417 void (*clean_desc3) (struct dma_desc *p);
418 int (*set_16kib_bfsize) (int mtu);
419};
420
4a7d666a 421struct stmmac_chain_mode_ops {
c24602ef
GC		 422 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
423 unsigned int extend_desc);
4a7d666a
GC		 424 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
425 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
4a7d666a
GC		 426};
427
47dd7a54 428struct mac_device_info {
cadb7924 429 const struct stmmac_ops *mac;
430 const struct stmmac_desc_ops *desc;
431 const struct stmmac_dma_ops *dma;
286a8372 432 const struct stmmac_ring_mode_ops *ring;
4a7d666a 433 const struct stmmac_chain_mode_ops *chain;
db98a0b0
GC		 434 struct mii_regs mii; /* MII register Addresses */
435 struct mac_link link;
f0b9d786 436 unsigned int synopsys_uid;
47dd7a54
GC		 437};
438
ad01b7d4
GC		 439struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
440struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
aec7ff27 441
ad01b7d4 442extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
aec7ff27 443 unsigned int high, unsigned int low);
ad01b7d4 444extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
aec7ff27 445 unsigned int high, unsigned int low);
bfab27a1
GC		 446
447extern void stmmac_set_mac(void __iomem *ioaddr, bool enable);
448
ad01b7d4 449extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
286a8372 450extern const struct stmmac_ring_mode_ops ring_mode_ops;
4a7d666a 451extern const struct stmmac_chain_mode_ops chain_mode_ops;
bd4242df
RK		 452
453#endif /* __COMMON_H__ */
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