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stmmac: merge get_rx_owner into rx_status routine.
[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / common.h
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 STMMAC Common Header File
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23*******************************************************************************/
24
bd4242df
RK		 25#ifndef __COMMON_H__
26#define __COMMON_H__
27
bfab27a1 28#include <linux/etherdevice.h>
5e33c791 29#include <linux/netdevice.h>
afea0365 30#include <linux/stmmac.h>
bfab27a1
GC		 31#include <linux/phy.h>
32#include <linux/module.h>
8f617541
GC		 33#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
34#define STMMAC_VLAN_TAG_USED
35#include <linux/if_vlan.h>
36#endif
37
56b106ae 38#include "descs.h"
1c901a46 39#include "mmc.h"
56b106ae 40
62a2ab93
GC		 41/* Synopsys Core versions */
42#define DWMAC_CORE_3_40 0x34
43#define DWMAC_CORE_3_50 0x35
44
e3ad57c9
GC		 45#define DMA_TX_SIZE 512
46#define DMA_RX_SIZE 512
47#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
48
56b106ae
GC		 49#undef FRAME_FILTER_DEBUG
50/* #define FRAME_FILTER_DEBUG */
47dd7a54 51
915c199f 52/* Extra statistic and debug information exposed by ethtool */
47dd7a54
GC		 53struct stmmac_extra_stats {
54 /* Transmit errors */
55 unsigned long tx_underflow ____cacheline_aligned;
56 unsigned long tx_carrier;
57 unsigned long tx_losscarrier;
3c20f72f 58 unsigned long vlan_tag;
47dd7a54
GC		 59 unsigned long tx_deferred;
60 unsigned long tx_vlan;
61 unsigned long tx_jabber;
62 unsigned long tx_frame_flushed;
63 unsigned long tx_payload_error;
64 unsigned long tx_ip_header_error;
65 /* Receive errors */
66 unsigned long rx_desc;
3c20f72f
GC		 67 unsigned long sa_filter_fail;
68 unsigned long overflow_error;
69 unsigned long ipc_csum_error;
47dd7a54
GC		 70 unsigned long rx_collision;
71 unsigned long rx_crc;
1cc5a735 72 unsigned long dribbling_bit;
1b924032 73 unsigned long rx_length;
47dd7a54
GC		 74 unsigned long rx_mii;
75 unsigned long rx_multicast;
76 unsigned long rx_gmac_overflow;
77 unsigned long rx_watchdog;
78 unsigned long da_rx_filter_fail;
79 unsigned long sa_rx_filter_fail;
80 unsigned long rx_missed_cntr;
81 unsigned long rx_overflow_cntr;
82 unsigned long rx_vlan;
62a2ab93 83 /* Tx/Rx IRQ error info */
47dd7a54
GC		 84 unsigned long tx_undeflow_irq;
85 unsigned long tx_process_stopped_irq;
86 unsigned long tx_jabber_irq;
87 unsigned long rx_overflow_irq;
88 unsigned long rx_buf_unav_irq;
89 unsigned long rx_process_stopped_irq;
90 unsigned long rx_watchdog_irq;
91 unsigned long tx_early_irq;
92 unsigned long fatal_bus_error_irq;
62a2ab93
GC		 93 /* Tx/Rx IRQ Events */
94 unsigned long rx_early_irq;
47dd7a54
GC		 95 unsigned long threshold;
96 unsigned long tx_pkt_n;
97 unsigned long rx_pkt_n;
47dd7a54 98 unsigned long normal_irq_n;
9125cdd1
GC		 99 unsigned long rx_normal_irq_n;
100 unsigned long napi_poll;
101 unsigned long tx_normal_irq_n;
102 unsigned long tx_clean;
103 unsigned long tx_reset_ic_bit;
62a2ab93
GC		 104 unsigned long irq_receive_pmt_irq_n;
105 /* MMC info */
d765955d
GC		 106 unsigned long mmc_tx_irq_n;
107 unsigned long mmc_rx_irq_n;
108 unsigned long mmc_rx_csum_offload_irq_n;
109 /* EEE */
d765955d
GC		 110 unsigned long irq_tx_path_in_lpi_mode_n;
111 unsigned long irq_tx_path_exit_lpi_mode_n;
112 unsigned long irq_rx_path_in_lpi_mode_n;
113 unsigned long irq_rx_path_exit_lpi_mode_n;
114 unsigned long phy_eee_wakeup_error_n;
c24602ef
GC		 115 /* Extended RDES status */
116 unsigned long ip_hdr_err;
117 unsigned long ip_payload_err;
118 unsigned long ip_csum_bypassed;
119 unsigned long ipv4_pkt_rcvd;
120 unsigned long ipv6_pkt_rcvd;
121 unsigned long rx_msg_type_ext_no_ptp;
122 unsigned long rx_msg_type_sync;
123 unsigned long rx_msg_type_follow_up;
124 unsigned long rx_msg_type_delay_req;
125 unsigned long rx_msg_type_delay_resp;
126 unsigned long rx_msg_type_pdelay_req;
127 unsigned long rx_msg_type_pdelay_resp;
128 unsigned long rx_msg_type_pdelay_follow_up;
129 unsigned long ptp_frame_type;
130 unsigned long ptp_ver;
131 unsigned long timestamp_dropped;
132 unsigned long av_pkt_rcvd;
133 unsigned long av_tagged_pkt_rcvd;
134 unsigned long vlan_tag_priority_val;
135 unsigned long l3_filter_match;
136 unsigned long l4_filter_match;
137 unsigned long l3_l4_filter_no_match;
0982a0f6
GC		 138 /* PCS */
139 unsigned long irq_pcs_ane_n;
140 unsigned long irq_pcs_link_n;
141 unsigned long irq_rgmii_n;
e58bb43f
GC		 142 unsigned long pcs_link;
143 unsigned long pcs_duplex;
144 unsigned long pcs_speed;
2f7a791c
GC		 145 /* debug register */
146 unsigned long mtl_tx_status_fifo_full;
147 unsigned long mtl_tx_fifo_not_empty;
148 unsigned long mmtl_fifo_ctrl;
149 unsigned long mtl_tx_fifo_read_ctrl_write;
150 unsigned long mtl_tx_fifo_read_ctrl_wait;
151 unsigned long mtl_tx_fifo_read_ctrl_read;
152 unsigned long mtl_tx_fifo_read_ctrl_idle;
153 unsigned long mac_tx_in_pause;
154 unsigned long mac_tx_frame_ctrl_xfer;
155 unsigned long mac_tx_frame_ctrl_idle;
156 unsigned long mac_tx_frame_ctrl_wait;
157 unsigned long mac_tx_frame_ctrl_pause;
158 unsigned long mac_gmii_tx_proto_engine;
159 unsigned long mtl_rx_fifo_fill_level_full;
160 unsigned long mtl_rx_fifo_fill_above_thresh;
161 unsigned long mtl_rx_fifo_fill_below_thresh;
162 unsigned long mtl_rx_fifo_fill_level_empty;
163 unsigned long mtl_rx_fifo_read_ctrl_flush;
164 unsigned long mtl_rx_fifo_read_ctrl_read_data;
165 unsigned long mtl_rx_fifo_read_ctrl_status;
166 unsigned long mtl_rx_fifo_read_ctrl_idle;
167 unsigned long mtl_rx_fifo_ctrl_active;
168 unsigned long mac_rx_frame_ctrl_fifo;
169 unsigned long mac_gmii_rx_proto_engine;
47dd7a54
GC		 170};
171
cd7201f4
GC		 172/* CSR Frequency Access Defines*/
173#define CSR_F_35M 35000000
174#define CSR_F_60M 60000000
175#define CSR_F_100M 100000000
176#define CSR_F_150M 150000000
177#define CSR_F_250M 250000000
178#define CSR_F_300M 300000000
179
180#define MAC_CSR_H_FRQ_MASK 0x20
181
aec7ff27 182#define HASH_TABLE_SIZE 64
f88203a2 183#define PAUSE_TIME 0xffff
aec7ff27
GC		 184
185/* Flow Control defines */
186#define FLOW_OFF 0
187#define FLOW_RX 1
188#define FLOW_TX 2
189#define FLOW_AUTO (FLOW_TX | FLOW_RX)
190
e58bb43f
GC		 191/* PCS defines */
192#define STMMAC_PCS_RGMII (1 << 0)
193#define STMMAC_PCS_SGMII (1 << 1)
194#define STMMAC_PCS_TBI (1 << 2)
195#define STMMAC_PCS_RTBI (1 << 3)
196
ceb69499 197#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
aec7ff27 198
1db123fb 199/* DAM HW feature register fields */
ceb69499
GC		 200#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
201#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
202#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
203#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
204#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
205#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
206#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
207#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
208#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
209#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
210#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
211#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
212#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
213#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
214#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
215#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
216#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
217#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
218#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
219#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
220#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
221#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
222#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
223/* Timestamping with Internal System Time */
224#define DMA_HW_FEAT_INTTSEN 0x02000000
225#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
226#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
227#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
0f1f88a8 228#define DEFAULT_DMA_PBL 8
1db123fb 229
62a2ab93
GC		 230/* Max/Min RI Watchdog Timer count value */
231#define MAX_DMA_RIWT 0xff
232#define MIN_DMA_RIWT 0x20
9125cdd1
GC		 233/* Tx coalesce parameters */
234#define STMMAC_COAL_TX_TIMER 40000
235#define STMMAC_MAX_COAL_TX_TICK 100000
236#define STMMAC_TX_MAX_FRAMES 256
237#define STMMAC_TX_FRAMES 64
238
ceb69499
GC		 239/* Rx IPC status */
240enum rx_frame_status {
c1fa3212
FG		 241 good_frame = 0x0,
242 discard_frame = 0x1,
243 csum_none = 0x2,
244 llc_snap = 0x4,
245 dma_own = 0x8,
47dd7a54
GC		 246};
247
9125cdd1
GC		 248enum dma_irq_status {
249 tx_hard_error = 0x1,
250 tx_hard_error_bump_tc = 0x2,
251 handle_rx = 0x4,
252 handle_tx = 0x8,
aec7ff27 253};
47dd7a54 254
915c199f 255/* EEE and LPI defines */
162fb1d6 256#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
257#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
258#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
259#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
0982a0f6
GC		 260
261#define CORE_PCS_ANE_COMPLETE (1 << 5)
262#define CORE_PCS_LINK_STATUS (1 << 6)
263#define CORE_RGMII_IRQ (1 << 7)
d765955d 264
915c199f 265/* Physical Coding Sublayer */
e58bb43f
GC		 266struct rgmii_adv {
267 unsigned int pause;
268 unsigned int duplex;
269 unsigned int lp_pause;
270 unsigned int lp_duplex;
271};
272
273#define STMMAC_PCS_PAUSE 1
274#define STMMAC_PCS_ASYM_PAUSE 2
275
e7434821
GC		 276/* DMA HW capabilities */
277struct dma_features {
278 unsigned int mbps_10_100;
279 unsigned int mbps_1000;
280 unsigned int half_duplex;
281 unsigned int hash_filter;
282 unsigned int multi_addr;
283 unsigned int pcs;
284 unsigned int sma_mdio;
285 unsigned int pmt_remote_wake_up;
286 unsigned int pmt_magic_frame;
287 unsigned int rmon;
ceb69499 288 /* IEEE 1588-2002 */
e7434821 289 unsigned int time_stamp;
ceb69499 290 /* IEEE 1588-2008 */
e7434821
GC		 291 unsigned int atime_stamp;
292 /* 802.3az - Energy-Efficient Ethernet (EEE) */
293 unsigned int eee;
294 unsigned int av;
295 /* TX and RX csum */
296 unsigned int tx_coe;
297 unsigned int rx_coe_type1;
298 unsigned int rx_coe_type2;
299 unsigned int rxfifo_over_2048;
300 /* TX and RX number of channels */
301 unsigned int number_rx_channel;
302 unsigned int number_tx_channel;
ceb69499 303 /* Alternate (enhanced) DESC mode */
e7434821
GC		 304 unsigned int enh_desc;
305};
306
aec7ff27
GC		 307/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
308#define BUF_SIZE_16KiB 16384
309#define BUF_SIZE_8KiB 8192
310#define BUF_SIZE_4KiB 4096
311#define BUF_SIZE_2KiB 2048
47dd7a54 312
aec7ff27
GC		 313/* Power Down and WOL */
314#define PMT_NOT_SUPPORTED 0
315#define PMT_SUPPORTED 1
47dd7a54 316
aec7ff27
GC		 317/* Common MAC defines */
318#define MAC_CTRL_REG 0x00000000 /* MAC Control */
319#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
320#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
47dd7a54 321
d765955d 322/* Default LPI timers */
f5351ef7 323#define STMMAC_DEFAULT_LIT_LS 0x3E8
438a62b1 324#define STMMAC_DEFAULT_TWT_LS 0x1E
d765955d 325
4a7d666a
GC		 326#define STMMAC_CHAIN_MODE 0x1
327#define STMMAC_RING_MODE 0x2
328
2618abb7
VB		 329#define JUMBO_LEN 9000
330
915c199f 331/* Descriptors helpers */
db98a0b0
GC		 332struct stmmac_desc_ops {
333 /* DMA RX descriptor ring initialization */
c24602ef
GC		 334 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
335 int end);
db98a0b0 336 /* DMA TX descriptor ring initialization */
c24602ef 337 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
47dd7a54
GC		 338
339 /* Invoked by the xmit function to prepare the tx descriptor */
340 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
4a7d666a 341 int csum_flag, int mode);
47dd7a54
GC		 342 /* Set/get the owner of the descriptor */
343 void (*set_tx_owner) (struct dma_desc *p);
344 int (*get_tx_owner) (struct dma_desc *p);
345 /* Invoked by the xmit function to close the tx descriptor */
346 void (*close_tx_desc) (struct dma_desc *p);
347 /* Clean the tx descriptor as soon as the tx irq is received */
4a7d666a 348 void (*release_tx_desc) (struct dma_desc *p, int mode);
47dd7a54
GC		 349 /* Clear interrupt on tx frame completion. When this bit is
350 * set an interrupt happens as soon as the frame is transmitted */
351 void (*clear_tx_ic) (struct dma_desc *p);
352 /* Last tx segment reports the transmit status */
353 int (*get_tx_ls) (struct dma_desc *p);
354 /* Return the transmit status looking at the TDES1 */
355 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
ad01b7d4 356 struct dma_desc *p, void __iomem *ioaddr);
47dd7a54
GC		 357 /* Get the buffer size from the descriptor */
358 int (*get_tx_len) (struct dma_desc *p);
359 /* Handle extra events on specific interrupts hw dependent */
47dd7a54
GC		 360 void (*set_rx_owner) (struct dma_desc *p);
361 /* Get the receive frame size */
38912bdb 362 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
47dd7a54
GC		 363 /* Return the reception status looking at the RDES1 */
364 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
365 struct dma_desc *p);
c24602ef
GC		 366 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
367 struct dma_extended_desc *p);
891434b1
RK		 368 /* Set tx timestamp enable bit */
369 void (*enable_tx_timestamp) (struct dma_desc *p);
370 /* get tx timestamp status */
371 int (*get_tx_timestamp_status) (struct dma_desc *p);
372 /* get timestamp value */
ceb69499 373 u64(*get_timestamp) (void *desc, u32 ats);
891434b1
RK		 374 /* get rx timestamp status */
375 int (*get_rx_timestamp_status) (void *desc, u32 ats);
db98a0b0
GC		 376};
377
915af656
AS		 378extern const struct stmmac_desc_ops enh_desc_ops;
379extern const struct stmmac_desc_ops ndesc_ops;
380
915c199f 381/* Specific DMA helpers */
db98a0b0
GC		 382struct stmmac_dma_ops {
383 /* DMA core initialization */
495db273
GC		 384 int (*reset)(void __iomem *ioaddr);
385 void (*init)(void __iomem *ioaddr, int pbl, int fb, int mb,
afea0365
GC		 386 int aal, u32 dma_tx, u32 dma_rx, int atds);
387 /* Configure the AXI Bus Mode Register */
388 void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
db98a0b0 389 /* Dump DMA registers */
ad01b7d4 390 void (*dump_regs) (void __iomem *ioaddr);
db98a0b0
GC		 391 /* Set tx/rx threshold in the csr6 register
392 * An invalid value enables the store-and-forward mode */
f88203a2
VB		 393 void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
394 int rxfifosz);
db98a0b0
GC		 395 /* To track extra statistic (if supported) */
396 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
ad01b7d4
GC		 397 void __iomem *ioaddr);
398 void (*enable_dma_transmission) (void __iomem *ioaddr);
399 void (*enable_dma_irq) (void __iomem *ioaddr);
400 void (*disable_dma_irq) (void __iomem *ioaddr);
401 void (*start_tx) (void __iomem *ioaddr);
402 void (*stop_tx) (void __iomem *ioaddr);
403 void (*start_rx) (void __iomem *ioaddr);
404 void (*stop_rx) (void __iomem *ioaddr);
405 int (*dma_interrupt) (void __iomem *ioaddr,
aec7ff27 406 struct stmmac_extra_stats *x);
e7434821
GC		 407 /* If supported then get the optional core features */
408 unsigned int (*get_hw_feature) (void __iomem *ioaddr);
62a2ab93
GC		 409 /* Program the HW RX Watchdog */
410 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
db98a0b0
GC		 411};
412
7ed24bbe
VB		 413struct mac_device_info;
414
915c199f 415/* Helpers to program the MAC core */
db98a0b0
GC		 416struct stmmac_ops {
417 /* MAC core initialization */
7ed24bbe 418 void (*core_init)(struct mac_device_info *hw, int mtu);
38912bdb 419 /* Enable and verify that the IPC module is supported */
7ed24bbe 420 int (*rx_ipc)(struct mac_device_info *hw);
db98a0b0 421 /* Dump MAC registers */
7ed24bbe 422 void (*dump_regs)(struct mac_device_info *hw);
db98a0b0 423 /* Handle extra events on specific interrupts hw dependent */
7ed24bbe
VB		 424 int (*host_irq_status)(struct mac_device_info *hw,
425 struct stmmac_extra_stats *x);
47dd7a54 426 /* Multicast filter setting */
3b57de95 427 void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
47dd7a54 428 /* Flow control setting */
7ed24bbe
VB		 429 void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
430 unsigned int fc, unsigned int pause_time);
47dd7a54 431 /* Set power management mode (e.g. magic frame) */
7ed24bbe 432 void (*pmt)(struct mac_device_info *hw, unsigned long mode);
47dd7a54 433 /* Set/Get Unicast MAC addresses */
7ed24bbe
VB		 434 void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
435 unsigned int reg_n);
436 void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
437 unsigned int reg_n);
438 void (*set_eee_mode)(struct mac_device_info *hw);
439 void (*reset_eee_mode)(struct mac_device_info *hw);
440 void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
441 void (*set_eee_pls)(struct mac_device_info *hw, int link);
442 void (*ctrl_ane)(struct mac_device_info *hw, bool restart);
443 void (*get_adv)(struct mac_device_info *hw, struct rgmii_adv *adv);
2f7a791c 444 void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x);
47dd7a54
GC		 445};
446
915c199f 447/* PTP and HW Timer helpers */
891434b1
RK		 448struct stmmac_hwtimestamp {
449 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
19d857c9 450 u32 (*config_sub_second_increment) (void __iomem *ioaddr, u32 clk_rate);
891434b1 451 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
ceb69499
GC		 452 int (*config_addend) (void __iomem *ioaddr, u32 addend);
453 int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
454 int add_sub);
455 u64(*get_systime) (void __iomem *ioaddr);
891434b1
RK		 456};
457
915af656
AS		 458extern const struct stmmac_hwtimestamp stmmac_ptp;
459
47dd7a54
GC		 460struct mac_link {
461 int port;
462 int duplex;
463 int speed;
464};
465
466struct mii_regs {
467 unsigned int addr; /* MII Address */
468 unsigned int data; /* MII Data */
469};
470
915c199f 471/* Helpers to manage the descriptors for chain and ring modes */
29896a67 472struct stmmac_mode_ops {
c24602ef
GC		 473 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
474 unsigned int extend_desc);
4a7d666a 475 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
362b37be 476 int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);
29896a67
GC		 477 int (*set_16kib_bfsize)(int mtu);
478 void (*init_desc3)(struct dma_desc *p);
891434b1
RK		 479 void (*refill_desc3) (void *priv, struct dma_desc *p);
480 void (*clean_desc3) (void *priv, struct dma_desc *p);
4a7d666a
GC		 481};
482
47dd7a54 483struct mac_device_info {
ceb69499
GC		 484 const struct stmmac_ops *mac;
485 const struct stmmac_desc_ops *desc;
486 const struct stmmac_dma_ops *dma;
29896a67 487 const struct stmmac_mode_ops *mode;
891434b1 488 const struct stmmac_hwtimestamp *ptp;
db98a0b0
GC		 489 struct mii_regs mii; /* MII register Addresses */
490 struct mac_link link;
f0b9d786 491 unsigned int synopsys_uid;
7ed24bbe 492 void __iomem *pcsr; /* vpointer to device CSRs */
3b57de95
VB		 493 int multicast_filter_bins;
494 int unicast_filter_entries;
495 int mcast_bits_log2;
d2afb5bd 496 unsigned int rx_csum;
47dd7a54
GC		 497};
498
3b57de95
VB		 499struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
500 int perfect_uc_entries);
ad01b7d4 501struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
aec7ff27 502
d6cc64ef
JP		 503void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
504 unsigned int high, unsigned int low);
505void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
506 unsigned int high, unsigned int low);
bfab27a1 507
d6cc64ef 508void stmmac_set_mac(void __iomem *ioaddr, bool enable);
bfab27a1 509
d6cc64ef 510void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
29896a67
GC		 511extern const struct stmmac_mode_ops ring_mode_ops;
512extern const struct stmmac_mode_ops chain_mode_ops;
bd4242df
RK		 513
514#endif /* __COMMON_H__ */
Linux 6.x block layer and io_uring tree(s)