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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec...
[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / common.h
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 STMMAC Common Header File
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23*******************************************************************************/
24
bd4242df
RK		 25#ifndef __COMMON_H__
26#define __COMMON_H__
27
bfab27a1 28#include <linux/etherdevice.h>
5e33c791 29#include <linux/netdevice.h>
bfab27a1
GC		 30#include <linux/phy.h>
31#include <linux/module.h>
8f617541
GC		 32#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
33#define STMMAC_VLAN_TAG_USED
34#include <linux/if_vlan.h>
35#endif
36
56b106ae 37#include "descs.h"
1c901a46 38#include "mmc.h"
56b106ae 39
62a2ab93
GC		 40/* Synopsys Core versions */
41#define DWMAC_CORE_3_40 0x34
42#define DWMAC_CORE_3_50 0x35
43
56b106ae
GC		 44#undef FRAME_FILTER_DEBUG
45/* #define FRAME_FILTER_DEBUG */
47dd7a54 46
47dd7a54
GC		 47struct stmmac_extra_stats {
48 /* Transmit errors */
49 unsigned long tx_underflow ____cacheline_aligned;
50 unsigned long tx_carrier;
51 unsigned long tx_losscarrier;
3c20f72f 52 unsigned long vlan_tag;
47dd7a54
GC		 53 unsigned long tx_deferred;
54 unsigned long tx_vlan;
55 unsigned long tx_jabber;
56 unsigned long tx_frame_flushed;
57 unsigned long tx_payload_error;
58 unsigned long tx_ip_header_error;
59 /* Receive errors */
60 unsigned long rx_desc;
3c20f72f
GC		 61 unsigned long sa_filter_fail;
62 unsigned long overflow_error;
63 unsigned long ipc_csum_error;
47dd7a54
GC		 64 unsigned long rx_collision;
65 unsigned long rx_crc;
1cc5a735 66 unsigned long dribbling_bit;
1b924032 67 unsigned long rx_length;
47dd7a54
GC		 68 unsigned long rx_mii;
69 unsigned long rx_multicast;
70 unsigned long rx_gmac_overflow;
71 unsigned long rx_watchdog;
72 unsigned long da_rx_filter_fail;
73 unsigned long sa_rx_filter_fail;
74 unsigned long rx_missed_cntr;
75 unsigned long rx_overflow_cntr;
76 unsigned long rx_vlan;
62a2ab93 77 /* Tx/Rx IRQ error info */
47dd7a54
GC		 78 unsigned long tx_undeflow_irq;
79 unsigned long tx_process_stopped_irq;
80 unsigned long tx_jabber_irq;
81 unsigned long rx_overflow_irq;
82 unsigned long rx_buf_unav_irq;
83 unsigned long rx_process_stopped_irq;
84 unsigned long rx_watchdog_irq;
85 unsigned long tx_early_irq;
86 unsigned long fatal_bus_error_irq;
62a2ab93
GC		 87 /* Tx/Rx IRQ Events */
88 unsigned long rx_early_irq;
47dd7a54
GC		 89 unsigned long threshold;
90 unsigned long tx_pkt_n;
91 unsigned long rx_pkt_n;
47dd7a54 92 unsigned long normal_irq_n;
9125cdd1
GC		 93 unsigned long rx_normal_irq_n;
94 unsigned long napi_poll;
95 unsigned long tx_normal_irq_n;
96 unsigned long tx_clean;
97 unsigned long tx_reset_ic_bit;
62a2ab93
GC		 98 unsigned long irq_receive_pmt_irq_n;
99 /* MMC info */
d765955d
GC		 100 unsigned long mmc_tx_irq_n;
101 unsigned long mmc_rx_irq_n;
102 unsigned long mmc_rx_csum_offload_irq_n;
103 /* EEE */
d765955d
GC		 104 unsigned long irq_tx_path_in_lpi_mode_n;
105 unsigned long irq_tx_path_exit_lpi_mode_n;
106 unsigned long irq_rx_path_in_lpi_mode_n;
107 unsigned long irq_rx_path_exit_lpi_mode_n;
108 unsigned long phy_eee_wakeup_error_n;
c24602ef
GC		 109 /* Extended RDES status */
110 unsigned long ip_hdr_err;
111 unsigned long ip_payload_err;
112 unsigned long ip_csum_bypassed;
113 unsigned long ipv4_pkt_rcvd;
114 unsigned long ipv6_pkt_rcvd;
115 unsigned long rx_msg_type_ext_no_ptp;
116 unsigned long rx_msg_type_sync;
117 unsigned long rx_msg_type_follow_up;
118 unsigned long rx_msg_type_delay_req;
119 unsigned long rx_msg_type_delay_resp;
120 unsigned long rx_msg_type_pdelay_req;
121 unsigned long rx_msg_type_pdelay_resp;
122 unsigned long rx_msg_type_pdelay_follow_up;
123 unsigned long ptp_frame_type;
124 unsigned long ptp_ver;
125 unsigned long timestamp_dropped;
126 unsigned long av_pkt_rcvd;
127 unsigned long av_tagged_pkt_rcvd;
128 unsigned long vlan_tag_priority_val;
129 unsigned long l3_filter_match;
130 unsigned long l4_filter_match;
131 unsigned long l3_l4_filter_no_match;
0982a0f6
GC		 132 /* PCS */
133 unsigned long irq_pcs_ane_n;
134 unsigned long irq_pcs_link_n;
135 unsigned long irq_rgmii_n;
e58bb43f
GC		 136 unsigned long pcs_link;
137 unsigned long pcs_duplex;
138 unsigned long pcs_speed;
47dd7a54
GC		 139};
140
cd7201f4
GC		 141/* CSR Frequency Access Defines*/
142#define CSR_F_35M 35000000
143#define CSR_F_60M 60000000
144#define CSR_F_100M 100000000
145#define CSR_F_150M 150000000
146#define CSR_F_250M 250000000
147#define CSR_F_300M 300000000
148
149#define MAC_CSR_H_FRQ_MASK 0x20
150
aec7ff27
GC		 151#define HASH_TABLE_SIZE 64
152#define PAUSE_TIME 0x200
153
154/* Flow Control defines */
155#define FLOW_OFF 0
156#define FLOW_RX 1
157#define FLOW_TX 2
158#define FLOW_AUTO (FLOW_TX | FLOW_RX)
159
e58bb43f
GC		 160/* PCS defines */
161#define STMMAC_PCS_RGMII (1 << 0)
162#define STMMAC_PCS_SGMII (1 << 1)
163#define STMMAC_PCS_TBI (1 << 2)
164#define STMMAC_PCS_RTBI (1 << 3)
165
ceb69499 166#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
aec7ff27 167
1db123fb 168/* DAM HW feature register fields */
ceb69499
GC		 169#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
170#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
171#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
172#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
173#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
174#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
175#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
176#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
177#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
178#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
179#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
180#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
181#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
182#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
183#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
184#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
185#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
186#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
187#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
188#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
189#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
190#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
191#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
192/* Timestamping with Internal System Time */
193#define DMA_HW_FEAT_INTTSEN 0x02000000
194#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
195#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
196#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
0f1f88a8 197#define DEFAULT_DMA_PBL 8
1db123fb 198
62a2ab93
GC		 199/* Max/Min RI Watchdog Timer count value */
200#define MAX_DMA_RIWT 0xff
201#define MIN_DMA_RIWT 0x20
9125cdd1
GC		 202/* Tx coalesce parameters */
203#define STMMAC_COAL_TX_TIMER 40000
204#define STMMAC_MAX_COAL_TX_TICK 100000
205#define STMMAC_TX_MAX_FRAMES 256
206#define STMMAC_TX_FRAMES 64
207
ceb69499
GC		 208/* Rx IPC status */
209enum rx_frame_status {
47dd7a54
GC		 210 good_frame = 0,
211 discard_frame = 1,
212 csum_none = 2,
3eeb2997 213 llc_snap = 4,
47dd7a54
GC		 214};
215
9125cdd1
GC		 216enum dma_irq_status {
217 tx_hard_error = 0x1,
218 tx_hard_error_bump_tc = 0x2,
219 handle_rx = 0x4,
220 handle_tx = 0x8,
aec7ff27 221};
47dd7a54 222
0982a0f6
GC		 223#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 1)
224#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 2)
225#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 3)
226#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 4)
227
228#define CORE_PCS_ANE_COMPLETE (1 << 5)
229#define CORE_PCS_LINK_STATUS (1 << 6)
230#define CORE_RGMII_IRQ (1 << 7)
d765955d 231
e58bb43f
GC		 232struct rgmii_adv {
233 unsigned int pause;
234 unsigned int duplex;
235 unsigned int lp_pause;
236 unsigned int lp_duplex;
237};
238
239#define STMMAC_PCS_PAUSE 1
240#define STMMAC_PCS_ASYM_PAUSE 2
241
e7434821
GC		 242/* DMA HW capabilities */
243struct dma_features {
244 unsigned int mbps_10_100;
245 unsigned int mbps_1000;
246 unsigned int half_duplex;
247 unsigned int hash_filter;
248 unsigned int multi_addr;
249 unsigned int pcs;
250 unsigned int sma_mdio;
251 unsigned int pmt_remote_wake_up;
252 unsigned int pmt_magic_frame;
253 unsigned int rmon;
ceb69499 254 /* IEEE 1588-2002 */
e7434821 255 unsigned int time_stamp;
ceb69499 256 /* IEEE 1588-2008 */
e7434821
GC		 257 unsigned int atime_stamp;
258 /* 802.3az - Energy-Efficient Ethernet (EEE) */
259 unsigned int eee;
260 unsigned int av;
261 /* TX and RX csum */
262 unsigned int tx_coe;
263 unsigned int rx_coe_type1;
264 unsigned int rx_coe_type2;
265 unsigned int rxfifo_over_2048;
266 /* TX and RX number of channels */
267 unsigned int number_rx_channel;
268 unsigned int number_tx_channel;
ceb69499 269 /* Alternate (enhanced) DESC mode */
e7434821
GC		 270 unsigned int enh_desc;
271};
272
aec7ff27
GC		 273/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
274#define BUF_SIZE_16KiB 16384
275#define BUF_SIZE_8KiB 8192
276#define BUF_SIZE_4KiB 4096
277#define BUF_SIZE_2KiB 2048
47dd7a54 278
aec7ff27
GC		 279/* Power Down and WOL */
280#define PMT_NOT_SUPPORTED 0
281#define PMT_SUPPORTED 1
47dd7a54 282
aec7ff27
GC		 283/* Common MAC defines */
284#define MAC_CTRL_REG 0x00000000 /* MAC Control */
285#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
286#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
47dd7a54 287
d765955d 288/* Default LPI timers */
f5351ef7
GC		 289#define STMMAC_DEFAULT_LIT_LS 0x3E8
290#define STMMAC_DEFAULT_TWT_LS 0x0
d765955d 291
4a7d666a
GC		 292#define STMMAC_CHAIN_MODE 0x1
293#define STMMAC_RING_MODE 0x2
294
2618abb7
VB		 295#define JUMBO_LEN 9000
296
db98a0b0
GC		 297struct stmmac_desc_ops {
298 /* DMA RX descriptor ring initialization */
c24602ef
GC		 299 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
300 int end);
db98a0b0 301 /* DMA TX descriptor ring initialization */
c24602ef 302 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
47dd7a54
GC		 303
304 /* Invoked by the xmit function to prepare the tx descriptor */
305 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
4a7d666a 306 int csum_flag, int mode);
47dd7a54
GC		 307 /* Set/get the owner of the descriptor */
308 void (*set_tx_owner) (struct dma_desc *p);
309 int (*get_tx_owner) (struct dma_desc *p);
310 /* Invoked by the xmit function to close the tx descriptor */
311 void (*close_tx_desc) (struct dma_desc *p);
312 /* Clean the tx descriptor as soon as the tx irq is received */
4a7d666a 313 void (*release_tx_desc) (struct dma_desc *p, int mode);
47dd7a54
GC		 314 /* Clear interrupt on tx frame completion. When this bit is
315 * set an interrupt happens as soon as the frame is transmitted */
316 void (*clear_tx_ic) (struct dma_desc *p);
317 /* Last tx segment reports the transmit status */
318 int (*get_tx_ls) (struct dma_desc *p);
319 /* Return the transmit status looking at the TDES1 */
320 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
ad01b7d4 321 struct dma_desc *p, void __iomem *ioaddr);
47dd7a54
GC		 322 /* Get the buffer size from the descriptor */
323 int (*get_tx_len) (struct dma_desc *p);
324 /* Handle extra events on specific interrupts hw dependent */
47dd7a54
GC		 325 int (*get_rx_owner) (struct dma_desc *p);
326 void (*set_rx_owner) (struct dma_desc *p);
327 /* Get the receive frame size */
38912bdb 328 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
47dd7a54
GC		 329 /* Return the reception status looking at the RDES1 */
330 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
331 struct dma_desc *p);
c24602ef
GC		 332 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
333 struct dma_extended_desc *p);
891434b1
RK		 334 /* Set tx timestamp enable bit */
335 void (*enable_tx_timestamp) (struct dma_desc *p);
336 /* get tx timestamp status */
337 int (*get_tx_timestamp_status) (struct dma_desc *p);
338 /* get timestamp value */
ceb69499 339 u64(*get_timestamp) (void *desc, u32 ats);
891434b1
RK		 340 /* get rx timestamp status */
341 int (*get_rx_timestamp_status) (void *desc, u32 ats);
db98a0b0
GC		 342};
343
344struct stmmac_dma_ops {
345 /* DMA core initialization */
b9cde0a8 346 int (*init) (void __iomem *ioaddr, int pbl, int fb, int mb,
c24602ef 347 int burst_len, u32 dma_tx, u32 dma_rx, int atds);
db98a0b0 348 /* Dump DMA registers */
ad01b7d4 349 void (*dump_regs) (void __iomem *ioaddr);
db98a0b0
GC		 350 /* Set tx/rx threshold in the csr6 register
351 * An invalid value enables the store-and-forward mode */
ad01b7d4 352 void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
db98a0b0
GC		 353 /* To track extra statistic (if supported) */
354 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
ad01b7d4
GC		 355 void __iomem *ioaddr);
356 void (*enable_dma_transmission) (void __iomem *ioaddr);
357 void (*enable_dma_irq) (void __iomem *ioaddr);
358 void (*disable_dma_irq) (void __iomem *ioaddr);
359 void (*start_tx) (void __iomem *ioaddr);
360 void (*stop_tx) (void __iomem *ioaddr);
361 void (*start_rx) (void __iomem *ioaddr);
362 void (*stop_rx) (void __iomem *ioaddr);
363 int (*dma_interrupt) (void __iomem *ioaddr,
aec7ff27 364 struct stmmac_extra_stats *x);
e7434821
GC		 365 /* If supported then get the optional core features */
366 unsigned int (*get_hw_feature) (void __iomem *ioaddr);
62a2ab93
GC		 367 /* Program the HW RX Watchdog */
368 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
db98a0b0
GC		 369};
370
371struct stmmac_ops {
372 /* MAC core initialization */
2618abb7 373 void (*core_init) (void __iomem *ioaddr, int mtu);
38912bdb
DS		 374 /* Enable and verify that the IPC module is supported */
375 int (*rx_ipc) (void __iomem *ioaddr);
db98a0b0 376 /* Dump MAC registers */
ad01b7d4 377 void (*dump_regs) (void __iomem *ioaddr);
db98a0b0 378 /* Handle extra events on specific interrupts hw dependent */
0982a0f6
GC		 379 int (*host_irq_status) (void __iomem *ioaddr,
380 struct stmmac_extra_stats *x);
47dd7a54 381 /* Multicast filter setting */
cffb13f4 382 void (*set_filter) (struct net_device *dev, int id);
47dd7a54 383 /* Flow control setting */
ad01b7d4 384 void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
47dd7a54
GC		 385 unsigned int fc, unsigned int pause_time);
386 /* Set power management mode (e.g. magic frame) */
ad01b7d4 387 void (*pmt) (void __iomem *ioaddr, unsigned long mode);
47dd7a54 388 /* Set/Get Unicast MAC addresses */
ad01b7d4 389 void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
db98a0b0 390 unsigned int reg_n);
ad01b7d4 391 void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
db98a0b0 392 unsigned int reg_n);
d765955d
GC		 393 void (*set_eee_mode) (void __iomem *ioaddr);
394 void (*reset_eee_mode) (void __iomem *ioaddr);
395 void (*set_eee_timer) (void __iomem *ioaddr, int ls, int tw);
396 void (*set_eee_pls) (void __iomem *ioaddr, int link);
e58bb43f
GC		 397 void (*ctrl_ane) (void __iomem *ioaddr, bool restart);
398 void (*get_adv) (void __iomem *ioaddr, struct rgmii_adv *adv);
47dd7a54
GC		 399};
400
891434b1
RK		 401struct stmmac_hwtimestamp {
402 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
403 void (*config_sub_second_increment) (void __iomem *ioaddr);
404 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
ceb69499
GC		 405 int (*config_addend) (void __iomem *ioaddr, u32 addend);
406 int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
407 int add_sub);
408 u64(*get_systime) (void __iomem *ioaddr);
891434b1
RK		 409};
410
47dd7a54
GC		 411struct mac_link {
412 int port;
413 int duplex;
414 int speed;
415};
416
417struct mii_regs {
418 unsigned int addr; /* MII Address */
419 unsigned int data; /* MII Data */
420};
421
29896a67 422struct stmmac_mode_ops {
c24602ef
GC		 423 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
424 unsigned int extend_desc);
4a7d666a
GC		 425 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
426 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
29896a67
GC		 427 int (*set_16kib_bfsize)(int mtu);
428 void (*init_desc3)(struct dma_desc *p);
891434b1
RK		 429 void (*refill_desc3) (void *priv, struct dma_desc *p);
430 void (*clean_desc3) (void *priv, struct dma_desc *p);
4a7d666a
GC		 431};
432
47dd7a54 433struct mac_device_info {
ceb69499
GC		 434 const struct stmmac_ops *mac;
435 const struct stmmac_desc_ops *desc;
436 const struct stmmac_dma_ops *dma;
29896a67 437 const struct stmmac_mode_ops *mode;
891434b1 438 const struct stmmac_hwtimestamp *ptp;
db98a0b0
GC		 439 struct mii_regs mii; /* MII register Addresses */
440 struct mac_link link;
f0b9d786 441 unsigned int synopsys_uid;
47dd7a54
GC		 442};
443
ad01b7d4
GC		 444struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
445struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
aec7ff27 446
d6cc64ef
JP		 447void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
448 unsigned int high, unsigned int low);
449void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
450 unsigned int high, unsigned int low);
bfab27a1 451
d6cc64ef 452void stmmac_set_mac(void __iomem *ioaddr, bool enable);
bfab27a1 453
d6cc64ef 454void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
29896a67
GC		 455extern const struct stmmac_mode_ops ring_mode_ops;
456extern const struct stmmac_mode_ops chain_mode_ops;
bd4242df
RK		 457
458#endif /* __COMMON_H__ */
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