[linux-block.git] / drivers / net / ethernet / stmicro / stmmac / common.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*******************************************************************************
  STMMAC Common Header File

  Copyright (C) 2007-2009  STMicroelectronics Ltd


  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#ifndef __COMMON_H__
#define __COMMON_H__

#include <linux/etherdevice.h>
#include <linux/netdevice.h>
#include <linux/stmmac.h>
#include <linux/phy.h>
#include <linux/module.h>
#if IS_ENABLED(CONFIG_VLAN_8021Q)
#define STMMAC_VLAN_TAG_USED
#include <linux/if_vlan.h>
#endif

#include "descs.h"
#include "hwif.h"
#include "mmc.h"

/* Synopsys Core versions */
#define	DWMAC_CORE_3_40		0x34
#define	DWMAC_CORE_3_50		0x35
#define	DWMAC_CORE_4_00		0x40
#define DWMAC_CORE_4_10		0x41
#define DWMAC_CORE_5_00		0x50
#define DWMAC_CORE_5_10		0x51
#define DWXGMAC_CORE_2_10	0x21

#define STMMAC_CHAN0	0	/* Always supported and default for all chips */

/* These need to be power of two, and >= 4 */
#define DMA_TX_SIZE 512
#define DMA_RX_SIZE 512
#define STMMAC_GET_ENTRY(x, size)	((x + 1) & (size - 1))

#undef FRAME_FILTER_DEBUG
/* #define FRAME_FILTER_DEBUG */

/* Extra statistic and debug information exposed by ethtool */
struct stmmac_extra_stats {
	/* Transmit errors */
	unsigned long tx_underflow ____cacheline_aligned;
	unsigned long tx_carrier;
	unsigned long tx_losscarrier;
	unsigned long vlan_tag;
	unsigned long tx_deferred;
	unsigned long tx_vlan;
	unsigned long tx_jabber;
	unsigned long tx_frame_flushed;
	unsigned long tx_payload_error;
	unsigned long tx_ip_header_error;
	/* Receive errors */
	unsigned long rx_desc;
	unsigned long sa_filter_fail;
	unsigned long overflow_error;
	unsigned long ipc_csum_error;
	unsigned long rx_collision;
	unsigned long rx_crc_errors;
	unsigned long dribbling_bit;
	unsigned long rx_length;
	unsigned long rx_mii;
	unsigned long rx_multicast;
	unsigned long rx_gmac_overflow;
	unsigned long rx_watchdog;
	unsigned long da_rx_filter_fail;
	unsigned long sa_rx_filter_fail;
	unsigned long rx_missed_cntr;
	unsigned long rx_overflow_cntr;
	unsigned long rx_vlan;
	unsigned long rx_split_hdr_pkt_n;
	/* Tx/Rx IRQ error info */
	unsigned long tx_undeflow_irq;
	unsigned long tx_process_stopped_irq;
	unsigned long tx_jabber_irq;
	unsigned long rx_overflow_irq;
	unsigned long rx_buf_unav_irq;
	unsigned long rx_process_stopped_irq;
	unsigned long rx_watchdog_irq;
	unsigned long tx_early_irq;
	unsigned long fatal_bus_error_irq;
	/* Tx/Rx IRQ Events */
	unsigned long rx_early_irq;
	unsigned long threshold;
	unsigned long tx_pkt_n;
	unsigned long rx_pkt_n;
	unsigned long normal_irq_n;
	unsigned long rx_normal_irq_n;
	unsigned long napi_poll;
	unsigned long tx_normal_irq_n;
	unsigned long tx_clean;
	unsigned long tx_set_ic_bit;
	unsigned long irq_receive_pmt_irq_n;
	/* MMC info */
	unsigned long mmc_tx_irq_n;
	unsigned long mmc_rx_irq_n;
	unsigned long mmc_rx_csum_offload_irq_n;
	/* EEE */
	unsigned long irq_tx_path_in_lpi_mode_n;
	unsigned long irq_tx_path_exit_lpi_mode_n;
	unsigned long irq_rx_path_in_lpi_mode_n;
	unsigned long irq_rx_path_exit_lpi_mode_n;
	unsigned long phy_eee_wakeup_error_n;
	/* Extended RDES status */
	unsigned long ip_hdr_err;
	unsigned long ip_payload_err;
	unsigned long ip_csum_bypassed;
	unsigned long ipv4_pkt_rcvd;
	unsigned long ipv6_pkt_rcvd;
	unsigned long no_ptp_rx_msg_type_ext;
	unsigned long ptp_rx_msg_type_sync;
	unsigned long ptp_rx_msg_type_follow_up;
	unsigned long ptp_rx_msg_type_delay_req;
	unsigned long ptp_rx_msg_type_delay_resp;
	unsigned long ptp_rx_msg_type_pdelay_req;
	unsigned long ptp_rx_msg_type_pdelay_resp;
	unsigned long ptp_rx_msg_type_pdelay_follow_up;
	unsigned long ptp_rx_msg_type_announce;
	unsigned long ptp_rx_msg_type_management;
	unsigned long ptp_rx_msg_pkt_reserved_type;
	unsigned long ptp_frame_type;
	unsigned long ptp_ver;
	unsigned long timestamp_dropped;
	unsigned long av_pkt_rcvd;
	unsigned long av_tagged_pkt_rcvd;
	unsigned long vlan_tag_priority_val;
	unsigned long l3_filter_match;
	unsigned long l4_filter_match;
	unsigned long l3_l4_filter_no_match;
	/* PCS */
	unsigned long irq_pcs_ane_n;
	unsigned long irq_pcs_link_n;
	unsigned long irq_rgmii_n;
	unsigned long pcs_link;
	unsigned long pcs_duplex;
	unsigned long pcs_speed;
	/* debug register */
	unsigned long mtl_tx_status_fifo_full;
	unsigned long mtl_tx_fifo_not_empty;
	unsigned long mmtl_fifo_ctrl;
	unsigned long mtl_tx_fifo_read_ctrl_write;
	unsigned long mtl_tx_fifo_read_ctrl_wait;
	unsigned long mtl_tx_fifo_read_ctrl_read;
	unsigned long mtl_tx_fifo_read_ctrl_idle;
	unsigned long mac_tx_in_pause;
	unsigned long mac_tx_frame_ctrl_xfer;
	unsigned long mac_tx_frame_ctrl_idle;
	unsigned long mac_tx_frame_ctrl_wait;
	unsigned long mac_tx_frame_ctrl_pause;
	unsigned long mac_gmii_tx_proto_engine;
	unsigned long mtl_rx_fifo_fill_level_full;
	unsigned long mtl_rx_fifo_fill_above_thresh;
	unsigned long mtl_rx_fifo_fill_below_thresh;
	unsigned long mtl_rx_fifo_fill_level_empty;
	unsigned long mtl_rx_fifo_read_ctrl_flush;
	unsigned long mtl_rx_fifo_read_ctrl_read_data;
	unsigned long mtl_rx_fifo_read_ctrl_status;
	unsigned long mtl_rx_fifo_read_ctrl_idle;
	unsigned long mtl_rx_fifo_ctrl_active;
	unsigned long mac_rx_frame_ctrl_fifo;
	unsigned long mac_gmii_rx_proto_engine;
	/* TSO */
	unsigned long tx_tso_frames;
	unsigned long tx_tso_nfrags;
};

/* Safety Feature statistics exposed by ethtool */
struct stmmac_safety_stats {
	unsigned long mac_errors[32];
	unsigned long mtl_errors[32];
	unsigned long dma_errors[32];
};

/* Number of fields in Safety Stats */
#define STMMAC_SAFETY_FEAT_SIZE	\
	(sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))

/* CSR Frequency Access Defines*/
#define CSR_F_35M	35000000
#define CSR_F_60M	60000000
#define CSR_F_100M	100000000
#define CSR_F_150M	150000000
#define CSR_F_250M	250000000
#define CSR_F_300M	300000000

#define	MAC_CSR_H_FRQ_MASK	0x20

#define HASH_TABLE_SIZE 64
#define PAUSE_TIME 0xffff

/* Flow Control defines */
#define FLOW_OFF	0
#define FLOW_RX		1
#define FLOW_TX		2
#define FLOW_AUTO	(FLOW_TX | FLOW_RX)

/* PCS defines */
#define STMMAC_PCS_RGMII	(1 << 0)
#define STMMAC_PCS_SGMII	(1 << 1)
#define STMMAC_PCS_TBI		(1 << 2)
#define STMMAC_PCS_RTBI		(1 << 3)

#define SF_DMA_MODE 1		/* DMA STORE-AND-FORWARD Operation Mode */

/* DAM HW feature register fields */
#define DMA_HW_FEAT_MIISEL	0x00000001	/* 10/100 Mbps Support */
#define DMA_HW_FEAT_GMIISEL	0x00000002	/* 1000 Mbps Support */
#define DMA_HW_FEAT_HDSEL	0x00000004	/* Half-Duplex Support */
#define DMA_HW_FEAT_EXTHASHEN	0x00000008	/* Expanded DA Hash Filter */
#define DMA_HW_FEAT_HASHSEL	0x00000010	/* HASH Filter */
#define DMA_HW_FEAT_ADDMAC	0x00000020	/* Multiple MAC Addr Reg */
#define DMA_HW_FEAT_PCSSEL	0x00000040	/* PCS registers */
#define DMA_HW_FEAT_L3L4FLTREN	0x00000080	/* Layer 3 & Layer 4 Feature */
#define DMA_HW_FEAT_SMASEL	0x00000100	/* SMA(MDIO) Interface */
#define DMA_HW_FEAT_RWKSEL	0x00000200	/* PMT Remote Wakeup */
#define DMA_HW_FEAT_MGKSEL	0x00000400	/* PMT Magic Packet */
#define DMA_HW_FEAT_MMCSEL	0x00000800	/* RMON Module */
#define DMA_HW_FEAT_TSVER1SEL	0x00001000	/* Only IEEE 1588-2002 */
#define DMA_HW_FEAT_TSVER2SEL	0x00002000	/* IEEE 1588-2008 PTPv2 */
#define DMA_HW_FEAT_EEESEL	0x00004000	/* Energy Efficient Ethernet */
#define DMA_HW_FEAT_AVSEL	0x00008000	/* AV Feature */
#define DMA_HW_FEAT_TXCOESEL	0x00010000	/* Checksum Offload in Tx */
#define DMA_HW_FEAT_RXTYP1COE	0x00020000	/* IP COE (Type 1) in Rx */
#define DMA_HW_FEAT_RXTYP2COE	0x00040000	/* IP COE (Type 2) in Rx */
#define DMA_HW_FEAT_RXFIFOSIZE	0x00080000	/* Rx FIFO > 2048 Bytes */
#define DMA_HW_FEAT_RXCHCNT	0x00300000	/* No. additional Rx Channels */
#define DMA_HW_FEAT_TXCHCNT	0x00c00000	/* No. additional Tx Channels */
#define DMA_HW_FEAT_ENHDESSEL	0x01000000	/* Alternate Descriptor */
/* Timestamping with Internal System Time */
#define DMA_HW_FEAT_INTTSEN	0x02000000
#define DMA_HW_FEAT_FLEXIPPSEN	0x04000000	/* Flexible PPS Output */
#define DMA_HW_FEAT_SAVLANINS	0x08000000	/* Source Addr or VLAN */
#define DMA_HW_FEAT_ACTPHYIF	0x70000000	/* Active/selected PHY iface */
#define DEFAULT_DMA_PBL		8

/* PCS status and mask defines */
#define	PCS_ANE_IRQ		BIT(2)	/* PCS Auto-Negotiation */
#define	PCS_LINK_IRQ		BIT(1)	/* PCS Link */
#define	PCS_RGSMIIIS_IRQ	BIT(0)	/* RGMII or SMII Interrupt */

/* Max/Min RI Watchdog Timer count value */
#define MAX_DMA_RIWT		0xff
#define MIN_DMA_RIWT		0x10
#define DEF_DMA_RIWT		0xa0
/* Tx coalesce parameters */
#define STMMAC_COAL_TX_TIMER	1000
#define STMMAC_MAX_COAL_TX_TICK	100000
#define STMMAC_TX_MAX_FRAMES	256
#define STMMAC_TX_FRAMES	25
#define STMMAC_RX_FRAMES	0

/* Packets types */
enum packets_types {
	PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
	PACKET_PTPQ = 0x2, /* PTP Packets */
	PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
	PACKET_UPQ = 0x4, /* Untagged Packets */
	PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
};

/* Rx IPC status */
enum rx_frame_status {
	good_frame = 0x0,
	discard_frame = 0x1,
	csum_none = 0x2,
	llc_snap = 0x4,
	dma_own = 0x8,
	rx_not_ls = 0x10,
};

/* Tx status */
enum tx_frame_status {
	tx_done = 0x0,
	tx_not_ls = 0x1,
	tx_err = 0x2,
	tx_dma_own = 0x4,
};

enum dma_irq_status {
	tx_hard_error = 0x1,
	tx_hard_error_bump_tc = 0x2,
	handle_rx = 0x4,
	handle_tx = 0x8,
};

/* EEE and LPI defines */
#define	CORE_IRQ_TX_PATH_IN_LPI_MODE	(1 << 0)
#define	CORE_IRQ_TX_PATH_EXIT_LPI_MODE	(1 << 1)
#define	CORE_IRQ_RX_PATH_IN_LPI_MODE	(1 << 2)
#define	CORE_IRQ_RX_PATH_EXIT_LPI_MODE	(1 << 3)

#define CORE_IRQ_MTL_RX_OVERFLOW	BIT(8)

/* Physical Coding Sublayer */
struct rgmii_adv {
	unsigned int pause;
	unsigned int duplex;
	unsigned int lp_pause;
	unsigned int lp_duplex;
};

#define STMMAC_PCS_PAUSE	1
#define STMMAC_PCS_ASYM_PAUSE	2

/* DMA HW capabilities */
struct dma_features {
	unsigned int mbps_10_100;
	unsigned int mbps_1000;
	unsigned int half_duplex;
	unsigned int hash_filter;
	unsigned int multi_addr;
	unsigned int pcs;
	unsigned int sma_mdio;
	unsigned int pmt_remote_wake_up;
	unsigned int pmt_magic_frame;
	unsigned int rmon;
	/* IEEE 1588-2002 */
	unsigned int time_stamp;
	/* IEEE 1588-2008 */
	unsigned int atime_stamp;
	/* 802.3az - Energy-Efficient Ethernet (EEE) */
	unsigned int eee;
	unsigned int av;
	unsigned int hash_tb_sz;
	unsigned int tsoen;
	/* TX and RX csum */
	unsigned int tx_coe;
	unsigned int rx_coe;
	unsigned int rx_coe_type1;
	unsigned int rx_coe_type2;
	unsigned int rxfifo_over_2048;
	/* TX and RX number of channels */
	unsigned int number_rx_channel;
	unsigned int number_tx_channel;
	/* TX and RX number of queues */
	unsigned int number_rx_queues;
	unsigned int number_tx_queues;
	/* PPS output */
	unsigned int pps_out_num;
	/* Alternate (enhanced) DESC mode */
	unsigned int enh_desc;
	/* TX and RX FIFO sizes */
	unsigned int tx_fifo_size;
	unsigned int rx_fifo_size;
	/* Automotive Safety Package */
	unsigned int asp;
	/* RX Parser */
	unsigned int frpsel;
	unsigned int frpbs;
	unsigned int frpes;
	unsigned int addr64;
	unsigned int rssen;
	unsigned int vlhash;
	unsigned int sphen;
	unsigned int vlins;
	unsigned int dvlan;
	unsigned int l3l4fnum;
	unsigned int arpoffsel;
};

/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
#define BUF_SIZE_16KiB 16384
/* RX Buffer size must be < 8191 and multiple of 4/8/16 bytes */
#define BUF_SIZE_8KiB 8188
#define BUF_SIZE_4KiB 4096
#define BUF_SIZE_2KiB 2048

/* Power Down and WOL */
#define PMT_NOT_SUPPORTED 0
#define PMT_SUPPORTED 1

/* Common MAC defines */
#define MAC_CTRL_REG		0x00000000	/* MAC Control */
#define MAC_ENABLE_TX		0x00000008	/* Transmitter Enable */
#define MAC_ENABLE_RX		0x00000004	/* Receiver Enable */

/* Default LPI timers */
#define STMMAC_DEFAULT_LIT_LS	0x3E8
#define STMMAC_DEFAULT_TWT_LS	0x1E

#define STMMAC_CHAIN_MODE	0x1
#define STMMAC_RING_MODE	0x2

#define JUMBO_LEN		9000

/* Receive Side Scaling */
#define STMMAC_RSS_HASH_KEY_SIZE	40
#define STMMAC_RSS_MAX_TABLE_SIZE	256

/* VLAN */
#define STMMAC_VLAN_NONE	0x0
#define STMMAC_VLAN_REMOVE	0x1
#define STMMAC_VLAN_INSERT	0x2
#define STMMAC_VLAN_REPLACE	0x3

extern const struct stmmac_desc_ops enh_desc_ops;
extern const struct stmmac_desc_ops ndesc_ops;

struct mac_device_info;

extern const struct stmmac_hwtimestamp stmmac_ptp;
extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;

struct mac_link {
	u32 speed_mask;
	u32 speed10;
	u32 speed100;
	u32 speed1000;
	u32 speed2500;
	u32 duplex;
	struct {
		u32 speed2500;
		u32 speed5000;
		u32 speed10000;
	} xgmii;
};

struct mii_regs {
	unsigned int addr;	/* MII Address */
	unsigned int data;	/* MII Data */
	unsigned int addr_shift;	/* MII address shift */
	unsigned int reg_shift;		/* MII reg shift */
	unsigned int addr_mask;		/* MII address mask */
	unsigned int reg_mask;		/* MII reg mask */
	unsigned int clk_csr_shift;
	unsigned int clk_csr_mask;
};

struct mac_device_info {
	const struct stmmac_ops *mac;
	const struct stmmac_desc_ops *desc;
	const struct stmmac_dma_ops *dma;
	const struct stmmac_mode_ops *mode;
	const struct stmmac_hwtimestamp *ptp;
	const struct stmmac_tc_ops *tc;
	const struct stmmac_mmc_ops *mmc;
	struct mii_regs mii;	/* MII register Addresses */
	struct mac_link link;
	void __iomem *pcsr;     /* vpointer to device CSRs */
	unsigned int multicast_filter_bins;
	unsigned int unicast_filter_entries;
	unsigned int mcast_bits_log2;
	unsigned int rx_csum;
	unsigned int pcs;
	unsigned int pmt;
	unsigned int ps;
};

struct stmmac_rx_routing {
	u32 reg_mask;
	u32 reg_shift;
};

int dwmac100_setup(struct stmmac_priv *priv);
int dwmac1000_setup(struct stmmac_priv *priv);
int dwmac4_setup(struct stmmac_priv *priv);
int dwxgmac2_setup(struct stmmac_priv *priv);

void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
			 unsigned int high, unsigned int low);
void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
			 unsigned int high, unsigned int low);
void stmmac_set_mac(void __iomem *ioaddr, bool enable);

void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
				unsigned int high, unsigned int low);
void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
				unsigned int high, unsigned int low);
void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);

void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);

extern const struct stmmac_mode_ops ring_mode_ops;
extern const struct stmmac_mode_ops chain_mode_ops;
extern const struct stmmac_desc_ops dwmac4_desc_ops;

#endif /* __COMMON_H__ */
Commit	Line	Data
4fa9c49f	1	/* SPDX-License-Identifier: GPL-2.0-only */
47dd7a54 GC	2	/*******************************************************************************
	3	STMMAC Common Header File
	4
	5	Copyright (C) 2007-2009 STMicroelectronics Ltd
	6
47dd7a54 GC	7
	8	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	9	*******************************************************************************/
	10
bd4242df RK	11	#ifndef __COMMON_H__
	12	#define __COMMON_H__
	13
bfab27a1	14	#include <linux/etherdevice.h>
5e33c791	15	#include <linux/netdevice.h>
afea0365	16	#include <linux/stmmac.h>
bfab27a1 GC	17	#include <linux/phy.h>
bfab27a1 GC	18	#include <linux/module.h>
12c70f30	19	#if IS_ENABLED(CONFIG_VLAN_8021Q)
8f617541 GC	20	#define STMMAC_VLAN_TAG_USED
	21	#include <linux/if_vlan.h>
	22	#endif
	23
56b106ae	24	#include "descs.h"
42de047d	25	#include "hwif.h"
1c901a46	26	#include "mmc.h"
56b106ae	27
62a2ab93	28	/* Synopsys Core versions */
48ae5554 JA	29	#define DWMAC_CORE_3_40 0x34
	30	#define DWMAC_CORE_3_50 0x35
	31	#define DWMAC_CORE_4_00 0x40
	32	#define DWMAC_CORE_4_10 0x41
	33	#define DWMAC_CORE_5_00 0x50
	34	#define DWMAC_CORE_5_10 0x51
	35	#define DWXGMAC_CORE_2_10 0x21
	36
48863ce5	37	#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
62a2ab93	38
22d3efe5	39	/* These need to be power of two, and >= 4 */
e3ad57c9 GC	40	#define DMA_TX_SIZE 512
	41	#define DMA_RX_SIZE 512
	42	#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
	43
56b106ae GC	44	#undef FRAME_FILTER_DEBUG
56b106ae GC	45	/* #define FRAME_FILTER_DEBUG */
47dd7a54	46
915c199f	47	/* Extra statistic and debug information exposed by ethtool */
47dd7a54 GC	48	struct stmmac_extra_stats {
	49	/* Transmit errors */
	50	unsigned long tx_underflow ____cacheline_aligned;
	51	unsigned long tx_carrier;
	52	unsigned long tx_losscarrier;
3c20f72f	53	unsigned long vlan_tag;
47dd7a54 GC	54	unsigned long tx_deferred;
	55	unsigned long tx_vlan;
	56	unsigned long tx_jabber;
	57	unsigned long tx_frame_flushed;
	58	unsigned long tx_payload_error;
	59	unsigned long tx_ip_header_error;
	60	/* Receive errors */
	61	unsigned long rx_desc;
3c20f72f GC	62	unsigned long sa_filter_fail;
	63	unsigned long overflow_error;
	64	unsigned long ipc_csum_error;
47dd7a54	65	unsigned long rx_collision;
e0a76606	66	unsigned long rx_crc_errors;
1cc5a735	67	unsigned long dribbling_bit;
1b924032	68	unsigned long rx_length;
47dd7a54 GC	69	unsigned long rx_mii;
	70	unsigned long rx_multicast;
	71	unsigned long rx_gmac_overflow;
	72	unsigned long rx_watchdog;
	73	unsigned long da_rx_filter_fail;
	74	unsigned long sa_rx_filter_fail;
	75	unsigned long rx_missed_cntr;
	76	unsigned long rx_overflow_cntr;
	77	unsigned long rx_vlan;
b5418e13	78	unsigned long rx_split_hdr_pkt_n;
62a2ab93	79	/* Tx/Rx IRQ error info */
47dd7a54 GC	80	unsigned long tx_undeflow_irq;
	81	unsigned long tx_process_stopped_irq;
	82	unsigned long tx_jabber_irq;
	83	unsigned long rx_overflow_irq;
	84	unsigned long rx_buf_unav_irq;
	85	unsigned long rx_process_stopped_irq;
	86	unsigned long rx_watchdog_irq;
	87	unsigned long tx_early_irq;
	88	unsigned long fatal_bus_error_irq;
62a2ab93 GC	89	/* Tx/Rx IRQ Events */
62a2ab93 GC	90	unsigned long rx_early_irq;
47dd7a54 GC	91	unsigned long threshold;
	92	unsigned long tx_pkt_n;
	93	unsigned long rx_pkt_n;
47dd7a54	94	unsigned long normal_irq_n;
9125cdd1 GC	95	unsigned long rx_normal_irq_n;
	96	unsigned long napi_poll;
	97	unsigned long tx_normal_irq_n;
	98	unsigned long tx_clean;
0e80bdc9	99	unsigned long tx_set_ic_bit;
62a2ab93 GC	100	unsigned long irq_receive_pmt_irq_n;
62a2ab93 GC	101	/* MMC info */
d765955d GC	102	unsigned long mmc_tx_irq_n;
	103	unsigned long mmc_rx_irq_n;
	104	unsigned long mmc_rx_csum_offload_irq_n;
	105	/* EEE */
d765955d GC	106	unsigned long irq_tx_path_in_lpi_mode_n;
	107	unsigned long irq_tx_path_exit_lpi_mode_n;
	108	unsigned long irq_rx_path_in_lpi_mode_n;
	109	unsigned long irq_rx_path_exit_lpi_mode_n;
	110	unsigned long phy_eee_wakeup_error_n;
c24602ef GC	111	/* Extended RDES status */
	112	unsigned long ip_hdr_err;
	113	unsigned long ip_payload_err;
	114	unsigned long ip_csum_bypassed;
	115	unsigned long ipv4_pkt_rcvd;
	116	unsigned long ipv6_pkt_rcvd;
ee112c12 GC	117	unsigned long no_ptp_rx_msg_type_ext;
	118	unsigned long ptp_rx_msg_type_sync;
	119	unsigned long ptp_rx_msg_type_follow_up;
	120	unsigned long ptp_rx_msg_type_delay_req;
	121	unsigned long ptp_rx_msg_type_delay_resp;
	122	unsigned long ptp_rx_msg_type_pdelay_req;
	123	unsigned long ptp_rx_msg_type_pdelay_resp;
	124	unsigned long ptp_rx_msg_type_pdelay_follow_up;
	125	unsigned long ptp_rx_msg_type_announce;
	126	unsigned long ptp_rx_msg_type_management;
	127	unsigned long ptp_rx_msg_pkt_reserved_type;
c24602ef GC	128	unsigned long ptp_frame_type;
	129	unsigned long ptp_ver;
	130	unsigned long timestamp_dropped;
	131	unsigned long av_pkt_rcvd;
	132	unsigned long av_tagged_pkt_rcvd;
	133	unsigned long vlan_tag_priority_val;
	134	unsigned long l3_filter_match;
	135	unsigned long l4_filter_match;
	136	unsigned long l3_l4_filter_no_match;
0982a0f6 GC	137	/* PCS */
	138	unsigned long irq_pcs_ane_n;
	139	unsigned long irq_pcs_link_n;
	140	unsigned long irq_rgmii_n;
e58bb43f GC	141	unsigned long pcs_link;
	142	unsigned long pcs_duplex;
	143	unsigned long pcs_speed;
2f7a791c GC	144	/* debug register */
	145	unsigned long mtl_tx_status_fifo_full;
	146	unsigned long mtl_tx_fifo_not_empty;
	147	unsigned long mmtl_fifo_ctrl;
	148	unsigned long mtl_tx_fifo_read_ctrl_write;
	149	unsigned long mtl_tx_fifo_read_ctrl_wait;
	150	unsigned long mtl_tx_fifo_read_ctrl_read;
	151	unsigned long mtl_tx_fifo_read_ctrl_idle;
	152	unsigned long mac_tx_in_pause;
	153	unsigned long mac_tx_frame_ctrl_xfer;
	154	unsigned long mac_tx_frame_ctrl_idle;
	155	unsigned long mac_tx_frame_ctrl_wait;
	156	unsigned long mac_tx_frame_ctrl_pause;
	157	unsigned long mac_gmii_tx_proto_engine;
	158	unsigned long mtl_rx_fifo_fill_level_full;
	159	unsigned long mtl_rx_fifo_fill_above_thresh;
	160	unsigned long mtl_rx_fifo_fill_below_thresh;
	161	unsigned long mtl_rx_fifo_fill_level_empty;
	162	unsigned long mtl_rx_fifo_read_ctrl_flush;
	163	unsigned long mtl_rx_fifo_read_ctrl_read_data;
	164	unsigned long mtl_rx_fifo_read_ctrl_status;
	165	unsigned long mtl_rx_fifo_read_ctrl_idle;
	166	unsigned long mtl_rx_fifo_ctrl_active;
	167	unsigned long mac_rx_frame_ctrl_fifo;
	168	unsigned long mac_gmii_rx_proto_engine;
f748be53 AT	169	/* TSO */
	170	unsigned long tx_tso_frames;
	171	unsigned long tx_tso_nfrags;
47dd7a54 GC	172	};
47dd7a54 GC	173
8bf993a5 JA	174	/* Safety Feature statistics exposed by ethtool */
	175	struct stmmac_safety_stats {
	176	unsigned long mac_errors[32];
	177	unsigned long mtl_errors[32];
	178	unsigned long dma_errors[32];
	179	};
	180
	181	/* Number of fields in Safety Stats */
	182	#define STMMAC_SAFETY_FEAT_SIZE \
	183	(sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
	184
cd7201f4 GC	185	/* CSR Frequency Access Defines*/
	186	#define CSR_F_35M 35000000
	187	#define CSR_F_60M 60000000
	188	#define CSR_F_100M 100000000
	189	#define CSR_F_150M 150000000
	190	#define CSR_F_250M 250000000
	191	#define CSR_F_300M 300000000
	192
	193	#define MAC_CSR_H_FRQ_MASK 0x20
	194
aec7ff27	195	#define HASH_TABLE_SIZE 64
f88203a2	196	#define PAUSE_TIME 0xffff
aec7ff27 GC	197
	198	/* Flow Control defines */
	199	#define FLOW_OFF 0
	200	#define FLOW_RX 1
	201	#define FLOW_TX 2
	202	#define FLOW_AUTO (FLOW_TX \| FLOW_RX)
	203
e58bb43f GC	204	/* PCS defines */
	205	#define STMMAC_PCS_RGMII (1 << 0)
	206	#define STMMAC_PCS_SGMII (1 << 1)
	207	#define STMMAC_PCS_TBI (1 << 2)
	208	#define STMMAC_PCS_RTBI (1 << 3)
	209
ceb69499	210	#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
aec7ff27	211
1db123fb	212	/* DAM HW feature register fields */
ceb69499 GC	213	#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
	214	#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
	215	#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
	216	#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
	217	#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
	218	#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
	219	#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
	220	#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
	221	#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
	222	#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
	223	#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
	224	#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
	225	#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
	226	#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
	227	#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
	228	#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
	229	#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
	230	#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
	231	#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
	232	#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
	233	#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
	234	#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
	235	#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
	236	/* Timestamping with Internal System Time */
	237	#define DMA_HW_FEAT_INTTSEN 0x02000000
	238	#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
	239	#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
	240	#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
0f1f88a8	241	#define DEFAULT_DMA_PBL 8
1db123fb	242
70523e63 GC	243	/* PCS status and mask defines */
	244	#define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
	245	#define PCS_LINK_IRQ BIT(1) /* PCS Link */
	246	#define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
	247
62a2ab93 GC	248	/* Max/Min RI Watchdog Timer count value */
62a2ab93 GC	249	#define MAX_DMA_RIWT 0xff
01d1689d	250	#define MIN_DMA_RIWT 0x10
4e4337cc	251	#define DEF_DMA_RIWT 0xa0
9125cdd1	252	/* Tx coalesce parameters */
8fce3331	253	#define STMMAC_COAL_TX_TIMER 1000
9125cdd1 GC	254	#define STMMAC_MAX_COAL_TX_TICK 100000
9125cdd1 GC	255	#define STMMAC_TX_MAX_FRAMES 256
da202451 JA	256	#define STMMAC_TX_FRAMES 25
da202451 JA	257	#define STMMAC_RX_FRAMES 0
9125cdd1	258
abe80fdc JP	259	/* Packets types */
	260	enum packets_types {
	261	PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
	262	PACKET_PTPQ = 0x2, /* PTP Packets */
	263	PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
	264	PACKET_UPQ = 0x4, /* Untagged Packets */
	265	PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
	266	};
	267
ceb69499 GC	268	/* Rx IPC status */
ceb69499 GC	269	enum rx_frame_status {
c1fa3212 FG	270	good_frame = 0x0,
	271	discard_frame = 0x1,
	272	csum_none = 0x2,
	273	llc_snap = 0x4,
	274	dma_own = 0x8,
753a7109	275	rx_not_ls = 0x10,
47dd7a54 GC	276	};
47dd7a54 GC	277
c363b658 FG	278	/* Tx status */
	279	enum tx_frame_status {
	280	tx_done = 0x0,
	281	tx_not_ls = 0x1,
	282	tx_err = 0x2,
	283	tx_dma_own = 0x4,
	284	};
	285
9125cdd1 GC	286	enum dma_irq_status {
	287	tx_hard_error = 0x1,
	288	tx_hard_error_bump_tc = 0x2,
	289	handle_rx = 0x4,
	290	handle_tx = 0x8,
aec7ff27	291	};
47dd7a54	292
915c199f	293	/* EEE and LPI defines */
162fb1d6	294	#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
	295	#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
	296	#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
	297	#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
0982a0f6	298
48863ce5	299	#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
d765955d	300
915c199f	301	/* Physical Coding Sublayer */
e58bb43f GC	302	struct rgmii_adv {
	303	unsigned int pause;
	304	unsigned int duplex;
	305	unsigned int lp_pause;
	306	unsigned int lp_duplex;
	307	};
	308
	309	#define STMMAC_PCS_PAUSE 1
	310	#define STMMAC_PCS_ASYM_PAUSE 2
	311
e7434821 GC	312	/* DMA HW capabilities */
	313	struct dma_features {
	314	unsigned int mbps_10_100;
	315	unsigned int mbps_1000;
	316	unsigned int half_duplex;
	317	unsigned int hash_filter;
	318	unsigned int multi_addr;
	319	unsigned int pcs;
	320	unsigned int sma_mdio;
	321	unsigned int pmt_remote_wake_up;
	322	unsigned int pmt_magic_frame;
	323	unsigned int rmon;
ceb69499	324	/* IEEE 1588-2002 */
e7434821	325	unsigned int time_stamp;
ceb69499	326	/* IEEE 1588-2008 */
e7434821 GC	327	unsigned int atime_stamp;
	328	/* 802.3az - Energy-Efficient Ethernet (EEE) */
	329	unsigned int eee;
	330	unsigned int av;
b8ef7020	331	unsigned int hash_tb_sz;
48863ce5	332	unsigned int tsoen;
e7434821 GC	333	/* TX and RX csum */
e7434821 GC	334	unsigned int tx_coe;
48863ce5	335	unsigned int rx_coe;
e7434821 GC	336	unsigned int rx_coe_type1;
	337	unsigned int rx_coe_type2;
	338	unsigned int rxfifo_over_2048;
	339	/* TX and RX number of channels */
	340	unsigned int number_rx_channel;
	341	unsigned int number_tx_channel;
9eb12474	342	/* TX and RX number of queues */
	343	unsigned int number_rx_queues;
	344	unsigned int number_tx_queues;
9a8a02c9 JA	345	/* PPS output */
9a8a02c9 JA	346	unsigned int pps_out_num;
ceb69499	347	/* Alternate (enhanced) DESC mode */
e7434821	348	unsigned int enh_desc;
11fbf811 TR	349	/* TX and RX FIFO sizes */
	350	unsigned int tx_fifo_size;
	351	unsigned int rx_fifo_size;
8bf993a5 JA	352	/* Automotive Safety Package */
8bf993a5 JA	353	unsigned int asp;
4dbbe8dd JA	354	/* RX Parser */
	355	unsigned int frpsel;
	356	unsigned int frpbs;
	357	unsigned int frpes;
a993db88	358	unsigned int addr64;
76067459	359	unsigned int rssen;
3cd1cfcb	360	unsigned int vlhash;
67afd6d1	361	unsigned int sphen;
30d93227 JA	362	unsigned int vlins;
30d93227 JA	363	unsigned int dvlan;
425eabdd	364	unsigned int l3l4fnum;
5904a980	365	unsigned int arpoffsel;
e7434821 GC	366	};
e7434821 GC	367
aec7ff27 GC	368	/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
aec7ff27 GC	369	#define BUF_SIZE_16KiB 16384
8137b6ef TT	370	/* RX Buffer size must be < 8191 and multiple of 4/8/16 bytes */
8137b6ef TT	371	#define BUF_SIZE_8KiB 8188
aec7ff27 GC	372	#define BUF_SIZE_4KiB 4096
aec7ff27 GC	373	#define BUF_SIZE_2KiB 2048
47dd7a54	374
aec7ff27 GC	375	/* Power Down and WOL */
	376	#define PMT_NOT_SUPPORTED 0
	377	#define PMT_SUPPORTED 1
47dd7a54	378
aec7ff27 GC	379	/* Common MAC defines */
	380	#define MAC_CTRL_REG 0x00000000 /* MAC Control */
	381	#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
28089222	382	#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
47dd7a54	383
d765955d	384	/* Default LPI timers */
f5351ef7	385	#define STMMAC_DEFAULT_LIT_LS 0x3E8
438a62b1	386	#define STMMAC_DEFAULT_TWT_LS 0x1E
d765955d	387
4a7d666a GC	388	#define STMMAC_CHAIN_MODE 0x1
	389	#define STMMAC_RING_MODE 0x2
	390
2618abb7 VB	391	#define JUMBO_LEN 9000
2618abb7 VB	392
76067459 JA	393	/* Receive Side Scaling */
	394	#define STMMAC_RSS_HASH_KEY_SIZE 40
	395	#define STMMAC_RSS_MAX_TABLE_SIZE 256
	396
30d93227 JA	397	/* VLAN */
	398	#define STMMAC_VLAN_NONE 0x0
	399	#define STMMAC_VLAN_REMOVE 0x1
	400	#define STMMAC_VLAN_INSERT 0x2
	401	#define STMMAC_VLAN_REPLACE 0x3
	402
915af656 AS	403	extern const struct stmmac_desc_ops enh_desc_ops;
	404	extern const struct stmmac_desc_ops ndesc_ops;
	405
7ed24bbe VB	406	struct mac_device_info;
7ed24bbe VB	407
915af656	408	extern const struct stmmac_hwtimestamp stmmac_ptp;
48863ce5	409	extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
915af656	410
47dd7a54	411	struct mac_link {
ca84dfb9 LC	412	u32 speed_mask;
	413	u32 speed10;
	414	u32 speed100;
	415	u32 speed1000;
2142754f	416	u32 speed2500;
ca84dfb9	417	u32 duplex;
5b0d7d7d JA	418	struct {
	419	u32 speed2500;
	420	u32 speed5000;
	421	u32 speed10000;
	422	} xgmii;
47dd7a54 GC	423	};
	424
	425	struct mii_regs {
	426	unsigned int addr; /* MII Address */
	427	unsigned int data; /* MII Data */
b91dce4c LC	428	unsigned int addr_shift; /* MII address shift */
	429	unsigned int reg_shift; /* MII reg shift */
	430	unsigned int addr_mask; /* MII address mask */
	431	unsigned int reg_mask; /* MII reg mask */
	432	unsigned int clk_csr_shift;
	433	unsigned int clk_csr_mask;
47dd7a54 GC	434	};
47dd7a54 GC	435
47dd7a54	436	struct mac_device_info {
ceb69499 GC	437	const struct stmmac_ops *mac;
	438	const struct stmmac_desc_ops *desc;
	439	const struct stmmac_dma_ops *dma;
29896a67	440	const struct stmmac_mode_ops *mode;
891434b1	441	const struct stmmac_hwtimestamp *ptp;
4dbbe8dd	442	const struct stmmac_tc_ops *tc;
3b1dd2c5	443	const struct stmmac_mmc_ops *mmc;
db98a0b0 GC	444	struct mii_regs mii; /* MII register Addresses */
db98a0b0 GC	445	struct mac_link link;
7ed24bbe	446	void __iomem pcsr; / vpointer to device CSRs */
b8ef7020 BH	447	unsigned int multicast_filter_bins;
	448	unsigned int unicast_filter_entries;
	449	unsigned int mcast_bits_log2;
d2afb5bd	450	unsigned int rx_csum;
3fe5cadb GC	451	unsigned int pcs;
3fe5cadb GC	452	unsigned int pmt;
02e57b9d	453	unsigned int ps;
47dd7a54 GC	454	};
47dd7a54 GC	455
abe80fdc JP	456	struct stmmac_rx_routing {
	457	u32 reg_mask;
	458	u32 reg_shift;
	459	};
	460
5f0456b4 JA	461	int dwmac100_setup(struct stmmac_priv *priv);
	462	int dwmac1000_setup(struct stmmac_priv *priv);
	463	int dwmac4_setup(struct stmmac_priv *priv);
2142754f	464	int dwxgmac2_setup(struct stmmac_priv *priv);
aec7ff27	465
d6cc64ef JP	466	void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
	467	unsigned int high, unsigned int low);
	468	void stmmac_get_mac_addr(void __iomem ioaddr, unsigned char addr,
	469	unsigned int high, unsigned int low);
d6cc64ef	470	void stmmac_set_mac(void __iomem *ioaddr, bool enable);
bfab27a1	471
477286b5 AT	472	void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
	473	unsigned int high, unsigned int low);
	474	void stmmac_dwmac4_get_mac_addr(void __iomem ioaddr, unsigned char addr,
	475	unsigned int high, unsigned int low);
	476	void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
	477
d6cc64ef	478	void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
70523e63	479
29896a67 GC	480	extern const struct stmmac_mode_ops ring_mode_ops;
29896a67 GC	481	extern const struct stmmac_mode_ops chain_mode_ops;
f748be53	482	extern const struct stmmac_desc_ops dwmac4_desc_ops;
bd4242df RK	483
bd4242df RK	484	#endif /* __COMMON_H__ */