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stmmac: add DMA support for GMAC 4.xx
[linux-block.git] / drivers / net / ethernet / stmicro / stmmac / common.h
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 STMMAC Common Header File
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23*******************************************************************************/
24
bd4242df
RK		 25#ifndef __COMMON_H__
26#define __COMMON_H__
27
bfab27a1 28#include <linux/etherdevice.h>
5e33c791 29#include <linux/netdevice.h>
afea0365 30#include <linux/stmmac.h>
bfab27a1
GC		 31#include <linux/phy.h>
32#include <linux/module.h>
8f617541
GC		 33#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
34#define STMMAC_VLAN_TAG_USED
35#include <linux/if_vlan.h>
36#endif
37
56b106ae 38#include "descs.h"
1c901a46 39#include "mmc.h"
56b106ae 40
62a2ab93
GC		 41/* Synopsys Core versions */
42#define DWMAC_CORE_3_40 0x34
43#define DWMAC_CORE_3_50 0x35
48863ce5
AT		 44#define DWMAC_CORE_4_00 0x40
45#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
62a2ab93 46
e3ad57c9
GC		 47#define DMA_TX_SIZE 512
48#define DMA_RX_SIZE 512
49#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
50
56b106ae
GC		 51#undef FRAME_FILTER_DEBUG
52/* #define FRAME_FILTER_DEBUG */
47dd7a54 53
915c199f 54/* Extra statistic and debug information exposed by ethtool */
47dd7a54
GC		 55struct stmmac_extra_stats {
56 /* Transmit errors */
57 unsigned long tx_underflow ____cacheline_aligned;
58 unsigned long tx_carrier;
59 unsigned long tx_losscarrier;
3c20f72f 60 unsigned long vlan_tag;
47dd7a54
GC		 61 unsigned long tx_deferred;
62 unsigned long tx_vlan;
63 unsigned long tx_jabber;
64 unsigned long tx_frame_flushed;
65 unsigned long tx_payload_error;
66 unsigned long tx_ip_header_error;
67 /* Receive errors */
68 unsigned long rx_desc;
3c20f72f
GC		 69 unsigned long sa_filter_fail;
70 unsigned long overflow_error;
71 unsigned long ipc_csum_error;
47dd7a54
GC		 72 unsigned long rx_collision;
73 unsigned long rx_crc;
1cc5a735 74 unsigned long dribbling_bit;
1b924032 75 unsigned long rx_length;
47dd7a54
GC		 76 unsigned long rx_mii;
77 unsigned long rx_multicast;
78 unsigned long rx_gmac_overflow;
79 unsigned long rx_watchdog;
80 unsigned long da_rx_filter_fail;
81 unsigned long sa_rx_filter_fail;
82 unsigned long rx_missed_cntr;
83 unsigned long rx_overflow_cntr;
84 unsigned long rx_vlan;
62a2ab93 85 /* Tx/Rx IRQ error info */
47dd7a54
GC		 86 unsigned long tx_undeflow_irq;
87 unsigned long tx_process_stopped_irq;
88 unsigned long tx_jabber_irq;
89 unsigned long rx_overflow_irq;
90 unsigned long rx_buf_unav_irq;
91 unsigned long rx_process_stopped_irq;
92 unsigned long rx_watchdog_irq;
93 unsigned long tx_early_irq;
94 unsigned long fatal_bus_error_irq;
62a2ab93
GC		 95 /* Tx/Rx IRQ Events */
96 unsigned long rx_early_irq;
47dd7a54
GC		 97 unsigned long threshold;
98 unsigned long tx_pkt_n;
99 unsigned long rx_pkt_n;
47dd7a54 100 unsigned long normal_irq_n;
9125cdd1
GC		 101 unsigned long rx_normal_irq_n;
102 unsigned long napi_poll;
103 unsigned long tx_normal_irq_n;
104 unsigned long tx_clean;
0e80bdc9 105 unsigned long tx_set_ic_bit;
62a2ab93
GC		 106 unsigned long irq_receive_pmt_irq_n;
107 /* MMC info */
d765955d
GC		 108 unsigned long mmc_tx_irq_n;
109 unsigned long mmc_rx_irq_n;
110 unsigned long mmc_rx_csum_offload_irq_n;
111 /* EEE */
d765955d
GC		 112 unsigned long irq_tx_path_in_lpi_mode_n;
113 unsigned long irq_tx_path_exit_lpi_mode_n;
114 unsigned long irq_rx_path_in_lpi_mode_n;
115 unsigned long irq_rx_path_exit_lpi_mode_n;
116 unsigned long phy_eee_wakeup_error_n;
c24602ef
GC		 117 /* Extended RDES status */
118 unsigned long ip_hdr_err;
119 unsigned long ip_payload_err;
120 unsigned long ip_csum_bypassed;
121 unsigned long ipv4_pkt_rcvd;
122 unsigned long ipv6_pkt_rcvd;
123 unsigned long rx_msg_type_ext_no_ptp;
124 unsigned long rx_msg_type_sync;
125 unsigned long rx_msg_type_follow_up;
126 unsigned long rx_msg_type_delay_req;
127 unsigned long rx_msg_type_delay_resp;
128 unsigned long rx_msg_type_pdelay_req;
129 unsigned long rx_msg_type_pdelay_resp;
130 unsigned long rx_msg_type_pdelay_follow_up;
131 unsigned long ptp_frame_type;
132 unsigned long ptp_ver;
133 unsigned long timestamp_dropped;
134 unsigned long av_pkt_rcvd;
135 unsigned long av_tagged_pkt_rcvd;
136 unsigned long vlan_tag_priority_val;
137 unsigned long l3_filter_match;
138 unsigned long l4_filter_match;
139 unsigned long l3_l4_filter_no_match;
0982a0f6
GC		 140 /* PCS */
141 unsigned long irq_pcs_ane_n;
142 unsigned long irq_pcs_link_n;
143 unsigned long irq_rgmii_n;
e58bb43f
GC		 144 unsigned long pcs_link;
145 unsigned long pcs_duplex;
146 unsigned long pcs_speed;
2f7a791c
GC		 147 /* debug register */
148 unsigned long mtl_tx_status_fifo_full;
149 unsigned long mtl_tx_fifo_not_empty;
150 unsigned long mmtl_fifo_ctrl;
151 unsigned long mtl_tx_fifo_read_ctrl_write;
152 unsigned long mtl_tx_fifo_read_ctrl_wait;
153 unsigned long mtl_tx_fifo_read_ctrl_read;
154 unsigned long mtl_tx_fifo_read_ctrl_idle;
155 unsigned long mac_tx_in_pause;
156 unsigned long mac_tx_frame_ctrl_xfer;
157 unsigned long mac_tx_frame_ctrl_idle;
158 unsigned long mac_tx_frame_ctrl_wait;
159 unsigned long mac_tx_frame_ctrl_pause;
160 unsigned long mac_gmii_tx_proto_engine;
161 unsigned long mtl_rx_fifo_fill_level_full;
162 unsigned long mtl_rx_fifo_fill_above_thresh;
163 unsigned long mtl_rx_fifo_fill_below_thresh;
164 unsigned long mtl_rx_fifo_fill_level_empty;
165 unsigned long mtl_rx_fifo_read_ctrl_flush;
166 unsigned long mtl_rx_fifo_read_ctrl_read_data;
167 unsigned long mtl_rx_fifo_read_ctrl_status;
168 unsigned long mtl_rx_fifo_read_ctrl_idle;
169 unsigned long mtl_rx_fifo_ctrl_active;
170 unsigned long mac_rx_frame_ctrl_fifo;
171 unsigned long mac_gmii_rx_proto_engine;
47dd7a54
GC		 172};
173
cd7201f4
GC		 174/* CSR Frequency Access Defines*/
175#define CSR_F_35M 35000000
176#define CSR_F_60M 60000000
177#define CSR_F_100M 100000000
178#define CSR_F_150M 150000000
179#define CSR_F_250M 250000000
180#define CSR_F_300M 300000000
181
182#define MAC_CSR_H_FRQ_MASK 0x20
183
aec7ff27 184#define HASH_TABLE_SIZE 64
f88203a2 185#define PAUSE_TIME 0xffff
aec7ff27
GC		 186
187/* Flow Control defines */
188#define FLOW_OFF 0
189#define FLOW_RX 1
190#define FLOW_TX 2
191#define FLOW_AUTO (FLOW_TX | FLOW_RX)
192
e58bb43f
GC		 193/* PCS defines */
194#define STMMAC_PCS_RGMII (1 << 0)
195#define STMMAC_PCS_SGMII (1 << 1)
196#define STMMAC_PCS_TBI (1 << 2)
197#define STMMAC_PCS_RTBI (1 << 3)
198
ceb69499 199#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
aec7ff27 200
1db123fb 201/* DAM HW feature register fields */
ceb69499
GC		 202#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
203#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
204#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
205#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
206#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
207#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
208#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
209#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
210#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
211#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
212#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
213#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
214#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
215#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
216#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
217#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
218#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
219#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
220#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
221#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
222#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
223#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
224#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
225/* Timestamping with Internal System Time */
226#define DMA_HW_FEAT_INTTSEN 0x02000000
227#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
228#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
229#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
0f1f88a8 230#define DEFAULT_DMA_PBL 8
1db123fb 231
62a2ab93
GC		 232/* Max/Min RI Watchdog Timer count value */
233#define MAX_DMA_RIWT 0xff
234#define MIN_DMA_RIWT 0x20
9125cdd1
GC		 235/* Tx coalesce parameters */
236#define STMMAC_COAL_TX_TIMER 40000
237#define STMMAC_MAX_COAL_TX_TICK 100000
238#define STMMAC_TX_MAX_FRAMES 256
239#define STMMAC_TX_FRAMES 64
240
ceb69499
GC		 241/* Rx IPC status */
242enum rx_frame_status {
c1fa3212
FG		 243 good_frame = 0x0,
244 discard_frame = 0x1,
245 csum_none = 0x2,
246 llc_snap = 0x4,
247 dma_own = 0x8,
753a7109 248 rx_not_ls = 0x10,
47dd7a54
GC		 249};
250
c363b658
FG		 251/* Tx status */
252enum tx_frame_status {
253 tx_done = 0x0,
254 tx_not_ls = 0x1,
255 tx_err = 0x2,
256 tx_dma_own = 0x4,
257};
258
9125cdd1
GC		 259enum dma_irq_status {
260 tx_hard_error = 0x1,
261 tx_hard_error_bump_tc = 0x2,
262 handle_rx = 0x4,
263 handle_tx = 0x8,
aec7ff27 264};
47dd7a54 265
915c199f 266/* EEE and LPI defines */
162fb1d6 267#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
268#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
269#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
270#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
0982a0f6
GC		 271
272#define CORE_PCS_ANE_COMPLETE (1 << 5)
273#define CORE_PCS_LINK_STATUS (1 << 6)
274#define CORE_RGMII_IRQ (1 << 7)
48863ce5 275#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
d765955d 276
915c199f 277/* Physical Coding Sublayer */
e58bb43f
GC		 278struct rgmii_adv {
279 unsigned int pause;
280 unsigned int duplex;
281 unsigned int lp_pause;
282 unsigned int lp_duplex;
283};
284
285#define STMMAC_PCS_PAUSE 1
286#define STMMAC_PCS_ASYM_PAUSE 2
287
e7434821
GC		 288/* DMA HW capabilities */
289struct dma_features {
290 unsigned int mbps_10_100;
291 unsigned int mbps_1000;
292 unsigned int half_duplex;
293 unsigned int hash_filter;
294 unsigned int multi_addr;
295 unsigned int pcs;
296 unsigned int sma_mdio;
297 unsigned int pmt_remote_wake_up;
298 unsigned int pmt_magic_frame;
299 unsigned int rmon;
ceb69499 300 /* IEEE 1588-2002 */
e7434821 301 unsigned int time_stamp;
ceb69499 302 /* IEEE 1588-2008 */
e7434821
GC		 303 unsigned int atime_stamp;
304 /* 802.3az - Energy-Efficient Ethernet (EEE) */
305 unsigned int eee;
306 unsigned int av;
48863ce5 307 unsigned int tsoen;
e7434821
GC		 308 /* TX and RX csum */
309 unsigned int tx_coe;
48863ce5 310 unsigned int rx_coe;
e7434821
GC		 311 unsigned int rx_coe_type1;
312 unsigned int rx_coe_type2;
313 unsigned int rxfifo_over_2048;
314 /* TX and RX number of channels */
315 unsigned int number_rx_channel;
316 unsigned int number_tx_channel;
ceb69499 317 /* Alternate (enhanced) DESC mode */
e7434821
GC		 318 unsigned int enh_desc;
319};
320
aec7ff27
GC		 321/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
322#define BUF_SIZE_16KiB 16384
323#define BUF_SIZE_8KiB 8192
324#define BUF_SIZE_4KiB 4096
325#define BUF_SIZE_2KiB 2048
47dd7a54 326
aec7ff27
GC		 327/* Power Down and WOL */
328#define PMT_NOT_SUPPORTED 0
329#define PMT_SUPPORTED 1
47dd7a54 330
aec7ff27
GC		 331/* Common MAC defines */
332#define MAC_CTRL_REG 0x00000000 /* MAC Control */
333#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
334#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
47dd7a54 335
d765955d 336/* Default LPI timers */
f5351ef7 337#define STMMAC_DEFAULT_LIT_LS 0x3E8
438a62b1 338#define STMMAC_DEFAULT_TWT_LS 0x1E
d765955d 339
4a7d666a
GC		 340#define STMMAC_CHAIN_MODE 0x1
341#define STMMAC_RING_MODE 0x2
342
2618abb7
VB		 343#define JUMBO_LEN 9000
344
915c199f 345/* Descriptors helpers */
db98a0b0
GC		 346struct stmmac_desc_ops {
347 /* DMA RX descriptor ring initialization */
c24602ef
GC		 348 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
349 int end);
db98a0b0 350 /* DMA TX descriptor ring initialization */
c24602ef 351 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
47dd7a54
GC		 352
353 /* Invoked by the xmit function to prepare the tx descriptor */
354 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
be434d50 355 bool csum_flag, int mode, bool tx_own,
0e80bdc9 356 bool ls);
753a7109
AT		 357 void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
358 int len2, bool tx_own, bool ls,
359 unsigned int tcphdrlen,
360 unsigned int tcppayloadlen);
47dd7a54
GC		 361 /* Set/get the owner of the descriptor */
362 void (*set_tx_owner) (struct dma_desc *p);
363 int (*get_tx_owner) (struct dma_desc *p);
47dd7a54 364 /* Clean the tx descriptor as soon as the tx irq is received */
4a7d666a 365 void (*release_tx_desc) (struct dma_desc *p, int mode);
47dd7a54
GC		 366 /* Clear interrupt on tx frame completion. When this bit is
367 * set an interrupt happens as soon as the frame is transmitted */
0e80bdc9 368 void (*set_tx_ic)(struct dma_desc *p);
47dd7a54
GC		 369 /* Last tx segment reports the transmit status */
370 int (*get_tx_ls) (struct dma_desc *p);
371 /* Return the transmit status looking at the TDES1 */
372 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
ad01b7d4 373 struct dma_desc *p, void __iomem *ioaddr);
47dd7a54
GC		 374 /* Get the buffer size from the descriptor */
375 int (*get_tx_len) (struct dma_desc *p);
376 /* Handle extra events on specific interrupts hw dependent */
47dd7a54
GC		 377 void (*set_rx_owner) (struct dma_desc *p);
378 /* Get the receive frame size */
38912bdb 379 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
47dd7a54
GC		 380 /* Return the reception status looking at the RDES1 */
381 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
382 struct dma_desc *p);
c24602ef
GC		 383 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
384 struct dma_extended_desc *p);
891434b1
RK		 385 /* Set tx timestamp enable bit */
386 void (*enable_tx_timestamp) (struct dma_desc *p);
387 /* get tx timestamp status */
388 int (*get_tx_timestamp_status) (struct dma_desc *p);
389 /* get timestamp value */
ceb69499 390 u64(*get_timestamp) (void *desc, u32 ats);
891434b1
RK		 391 /* get rx timestamp status */
392 int (*get_rx_timestamp_status) (void *desc, u32 ats);
d0225e7d
AT		 393 /* Display ring */
394 void (*display_ring)(void *head, unsigned int size, bool rx);
753a7109
AT		 395 /* set MSS via context descriptor */
396 void (*set_mss)(struct dma_desc *p, unsigned int mss);
db98a0b0
GC		 397};
398
915af656
AS		 399extern const struct stmmac_desc_ops enh_desc_ops;
400extern const struct stmmac_desc_ops ndesc_ops;
401
915c199f 402/* Specific DMA helpers */
db98a0b0
GC		 403struct stmmac_dma_ops {
404 /* DMA core initialization */
495db273
GC		 405 int (*reset)(void __iomem *ioaddr);
406 void (*init)(void __iomem *ioaddr, int pbl, int fb, int mb,
afea0365
GC		 407 int aal, u32 dma_tx, u32 dma_rx, int atds);
408 /* Configure the AXI Bus Mode Register */
409 void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
db98a0b0 410 /* Dump DMA registers */
ad01b7d4 411 void (*dump_regs) (void __iomem *ioaddr);
db98a0b0
GC		 412 /* Set tx/rx threshold in the csr6 register
413 * An invalid value enables the store-and-forward mode */
f88203a2
VB		 414 void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
415 int rxfifosz);
db98a0b0
GC		 416 /* To track extra statistic (if supported) */
417 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
ad01b7d4
GC		 418 void __iomem *ioaddr);
419 void (*enable_dma_transmission) (void __iomem *ioaddr);
420 void (*enable_dma_irq) (void __iomem *ioaddr);
421 void (*disable_dma_irq) (void __iomem *ioaddr);
422 void (*start_tx) (void __iomem *ioaddr);
423 void (*stop_tx) (void __iomem *ioaddr);
424 void (*start_rx) (void __iomem *ioaddr);
425 void (*stop_rx) (void __iomem *ioaddr);
426 int (*dma_interrupt) (void __iomem *ioaddr,
aec7ff27 427 struct stmmac_extra_stats *x);
e7434821 428 /* If supported then get the optional core features */
f10a6a35
AT		 429 void (*get_hw_feature)(void __iomem *ioaddr,
430 struct dma_features *dma_cap);
62a2ab93
GC		 431 /* Program the HW RX Watchdog */
432 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
48863ce5
AT		 433 void (*set_tx_ring_len)(void __iomem *ioaddr, u32 len);
434 void (*set_rx_ring_len)(void __iomem *ioaddr, u32 len);
435 void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
436 void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
437 void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);
db98a0b0
GC		 438};
439
7ed24bbe
VB		 440struct mac_device_info;
441
915c199f 442/* Helpers to program the MAC core */
db98a0b0
GC		 443struct stmmac_ops {
444 /* MAC core initialization */
7ed24bbe 445 void (*core_init)(struct mac_device_info *hw, int mtu);
38912bdb 446 /* Enable and verify that the IPC module is supported */
7ed24bbe 447 int (*rx_ipc)(struct mac_device_info *hw);
db98a0b0 448 /* Dump MAC registers */
7ed24bbe 449 void (*dump_regs)(struct mac_device_info *hw);
db98a0b0 450 /* Handle extra events on specific interrupts hw dependent */
7ed24bbe
VB		 451 int (*host_irq_status)(struct mac_device_info *hw,
452 struct stmmac_extra_stats *x);
47dd7a54 453 /* Multicast filter setting */
3b57de95 454 void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
47dd7a54 455 /* Flow control setting */
7ed24bbe
VB		 456 void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
457 unsigned int fc, unsigned int pause_time);
47dd7a54 458 /* Set power management mode (e.g. magic frame) */
7ed24bbe 459 void (*pmt)(struct mac_device_info *hw, unsigned long mode);
47dd7a54 460 /* Set/Get Unicast MAC addresses */
7ed24bbe
VB		 461 void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
462 unsigned int reg_n);
463 void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
464 unsigned int reg_n);
465 void (*set_eee_mode)(struct mac_device_info *hw);
466 void (*reset_eee_mode)(struct mac_device_info *hw);
467 void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
468 void (*set_eee_pls)(struct mac_device_info *hw, int link);
469 void (*ctrl_ane)(struct mac_device_info *hw, bool restart);
470 void (*get_adv)(struct mac_device_info *hw, struct rgmii_adv *adv);
2f7a791c 471 void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x);
47dd7a54
GC		 472};
473
915c199f 474/* PTP and HW Timer helpers */
891434b1
RK		 475struct stmmac_hwtimestamp {
476 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
19d857c9 477 u32 (*config_sub_second_increment) (void __iomem *ioaddr, u32 clk_rate);
891434b1 478 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
ceb69499
GC		 479 int (*config_addend) (void __iomem *ioaddr, u32 addend);
480 int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
481 int add_sub);
482 u64(*get_systime) (void __iomem *ioaddr);
891434b1
RK		 483};
484
915af656 485extern const struct stmmac_hwtimestamp stmmac_ptp;
48863ce5 486extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
915af656 487
47dd7a54
GC		 488struct mac_link {
489 int port;
490 int duplex;
491 int speed;
492};
493
494struct mii_regs {
495 unsigned int addr; /* MII Address */
496 unsigned int data; /* MII Data */
497};
498
915c199f 499/* Helpers to manage the descriptors for chain and ring modes */
29896a67 500struct stmmac_mode_ops {
c24602ef
GC		 501 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
502 unsigned int extend_desc);
4a7d666a 503 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
362b37be 504 int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);
29896a67
GC		 505 int (*set_16kib_bfsize)(int mtu);
506 void (*init_desc3)(struct dma_desc *p);
891434b1
RK		 507 void (*refill_desc3) (void *priv, struct dma_desc *p);
508 void (*clean_desc3) (void *priv, struct dma_desc *p);
4a7d666a
GC		 509};
510
47dd7a54 511struct mac_device_info {
ceb69499
GC		 512 const struct stmmac_ops *mac;
513 const struct stmmac_desc_ops *desc;
514 const struct stmmac_dma_ops *dma;
29896a67 515 const struct stmmac_mode_ops *mode;
891434b1 516 const struct stmmac_hwtimestamp *ptp;
db98a0b0
GC		 517 struct mii_regs mii; /* MII register Addresses */
518 struct mac_link link;
7ed24bbe 519 void __iomem *pcsr; /* vpointer to device CSRs */
3b57de95
VB		 520 int multicast_filter_bins;
521 int unicast_filter_entries;
522 int mcast_bits_log2;
d2afb5bd 523 unsigned int rx_csum;
47dd7a54
GC		 524};
525
3b57de95 526struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
c623d149
AT		 527 int perfect_uc_entries,
528 int *synopsys_id);
529struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id);
530
aec7ff27 531
d6cc64ef
JP		 532void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
533 unsigned int high, unsigned int low);
534void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
535 unsigned int high, unsigned int low);
bfab27a1 536
d6cc64ef 537void stmmac_set_mac(void __iomem *ioaddr, bool enable);
bfab27a1 538
d6cc64ef 539void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
29896a67
GC		 540extern const struct stmmac_mode_ops ring_mode_ops;
541extern const struct stmmac_mode_ops chain_mode_ops;
bd4242df 542
c623d149
AT		 543/**
544 * stmmac_get_synopsys_id - return the SYINID.
545 * @priv: driver private structure
546 * Description: this simple function is to decode and return the SYINID
547 * starting from the HW core register.
548 */
549static inline u32 stmmac_get_synopsys_id(u32 hwid)
550{
551 /* Check Synopsys Id (not available on old chips) */
552 if (likely(hwid)) {
553 u32 uid = ((hwid & 0x0000ff00) >> 8);
554 u32 synid = (hwid & 0x000000ff);
555
556 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
557 uid, synid);
558
559 return synid;
560 }
561 return 0;
562}
bd4242df 563#endif /* __COMMON_H__ */
Linux 6.x block layer and io_uring tree(s)