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net: stmmac: Add hardware supported cross-timestamp
[linux-block.git] / drivers / net / ethernet / stmicro / stmmac / common.h
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4fa9c49f 1/* SPDX-License-Identifier: GPL-2.0-only */
47dd7a54
GC		 2/*******************************************************************************
3 STMMAC Common Header File
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
47dd7a54
GC		 7
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9*******************************************************************************/
10
bd4242df
RK		 11#ifndef __COMMON_H__
12#define __COMMON_H__
13
bfab27a1 14#include <linux/etherdevice.h>
5e33c791 15#include <linux/netdevice.h>
afea0365 16#include <linux/stmmac.h>
bfab27a1 17#include <linux/phy.h>
2fa4e4b7 18#include <linux/pcs/pcs-xpcs.h>
bfab27a1 19#include <linux/module.h>
12c70f30 20#if IS_ENABLED(CONFIG_VLAN_8021Q)
8f617541
GC		 21#define STMMAC_VLAN_TAG_USED
22#include <linux/if_vlan.h>
23#endif
24
56b106ae 25#include "descs.h"
42de047d 26#include "hwif.h"
1c901a46 27#include "mmc.h"
56b106ae 28
62a2ab93 29/* Synopsys Core versions */
48ae5554
JA		 30#define DWMAC_CORE_3_40 0x34
31#define DWMAC_CORE_3_50 0x35
32#define DWMAC_CORE_4_00 0x40
33#define DWMAC_CORE_4_10 0x41
34#define DWMAC_CORE_5_00 0x50
35#define DWMAC_CORE_5_10 0x51
36#define DWXGMAC_CORE_2_10 0x21
4a4ccde0
JA		 37#define DWXLGMAC_CORE_2_00 0x20
38
39/* Device ID */
40#define DWXGMAC_ID 0x76
41#define DWXLGMAC_ID 0x27
48ae5554 42
48863ce5 43#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
62a2ab93 44
aa042f60
SYS		 45/* TX and RX Descriptor Length, these need to be power of two.
46 * TX descriptor length less than 64 may cause transmit queue timed out error.
47 * RX descriptor length less than 64 may cause inconsistent Rx chain error.
48 */
49#define DMA_MIN_TX_SIZE 64
50#define DMA_MAX_TX_SIZE 1024
51#define DMA_DEFAULT_TX_SIZE 512
52#define DMA_MIN_RX_SIZE 64
53#define DMA_MAX_RX_SIZE 1024
54#define DMA_DEFAULT_RX_SIZE 512
e3ad57c9
GC		 55#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
56
56b106ae
GC		 57#undef FRAME_FILTER_DEBUG
58/* #define FRAME_FILTER_DEBUG */
47dd7a54 59
915c199f 60/* Extra statistic and debug information exposed by ethtool */
47dd7a54
GC		 61struct stmmac_extra_stats {
62 /* Transmit errors */
63 unsigned long tx_underflow ____cacheline_aligned;
64 unsigned long tx_carrier;
65 unsigned long tx_losscarrier;
3c20f72f 66 unsigned long vlan_tag;
47dd7a54
GC		 67 unsigned long tx_deferred;
68 unsigned long tx_vlan;
69 unsigned long tx_jabber;
70 unsigned long tx_frame_flushed;
71 unsigned long tx_payload_error;
72 unsigned long tx_ip_header_error;
73 /* Receive errors */
74 unsigned long rx_desc;
3c20f72f
GC		 75 unsigned long sa_filter_fail;
76 unsigned long overflow_error;
77 unsigned long ipc_csum_error;
47dd7a54 78 unsigned long rx_collision;
e0a76606 79 unsigned long rx_crc_errors;
1cc5a735 80 unsigned long dribbling_bit;
1b924032 81 unsigned long rx_length;
47dd7a54
GC		 82 unsigned long rx_mii;
83 unsigned long rx_multicast;
84 unsigned long rx_gmac_overflow;
85 unsigned long rx_watchdog;
86 unsigned long da_rx_filter_fail;
87 unsigned long sa_rx_filter_fail;
88 unsigned long rx_missed_cntr;
89 unsigned long rx_overflow_cntr;
90 unsigned long rx_vlan;
b5418e13 91 unsigned long rx_split_hdr_pkt_n;
62a2ab93 92 /* Tx/Rx IRQ error info */
47dd7a54
GC		 93 unsigned long tx_undeflow_irq;
94 unsigned long tx_process_stopped_irq;
95 unsigned long tx_jabber_irq;
96 unsigned long rx_overflow_irq;
97 unsigned long rx_buf_unav_irq;
98 unsigned long rx_process_stopped_irq;
99 unsigned long rx_watchdog_irq;
100 unsigned long tx_early_irq;
101 unsigned long fatal_bus_error_irq;
62a2ab93
GC		 102 /* Tx/Rx IRQ Events */
103 unsigned long rx_early_irq;
47dd7a54
GC		 104 unsigned long threshold;
105 unsigned long tx_pkt_n;
106 unsigned long rx_pkt_n;
47dd7a54 107 unsigned long normal_irq_n;
9125cdd1
GC		 108 unsigned long rx_normal_irq_n;
109 unsigned long napi_poll;
110 unsigned long tx_normal_irq_n;
111 unsigned long tx_clean;
0e80bdc9 112 unsigned long tx_set_ic_bit;
62a2ab93
GC		 113 unsigned long irq_receive_pmt_irq_n;
114 /* MMC info */
d765955d
GC		 115 unsigned long mmc_tx_irq_n;
116 unsigned long mmc_rx_irq_n;
117 unsigned long mmc_rx_csum_offload_irq_n;
118 /* EEE */
d765955d
GC		 119 unsigned long irq_tx_path_in_lpi_mode_n;
120 unsigned long irq_tx_path_exit_lpi_mode_n;
121 unsigned long irq_rx_path_in_lpi_mode_n;
122 unsigned long irq_rx_path_exit_lpi_mode_n;
123 unsigned long phy_eee_wakeup_error_n;
c24602ef
GC		 124 /* Extended RDES status */
125 unsigned long ip_hdr_err;
126 unsigned long ip_payload_err;
127 unsigned long ip_csum_bypassed;
128 unsigned long ipv4_pkt_rcvd;
129 unsigned long ipv6_pkt_rcvd;
ee112c12
GC		 130 unsigned long no_ptp_rx_msg_type_ext;
131 unsigned long ptp_rx_msg_type_sync;
132 unsigned long ptp_rx_msg_type_follow_up;
133 unsigned long ptp_rx_msg_type_delay_req;
134 unsigned long ptp_rx_msg_type_delay_resp;
135 unsigned long ptp_rx_msg_type_pdelay_req;
136 unsigned long ptp_rx_msg_type_pdelay_resp;
137 unsigned long ptp_rx_msg_type_pdelay_follow_up;
138 unsigned long ptp_rx_msg_type_announce;
139 unsigned long ptp_rx_msg_type_management;
140 unsigned long ptp_rx_msg_pkt_reserved_type;
c24602ef
GC		 141 unsigned long ptp_frame_type;
142 unsigned long ptp_ver;
143 unsigned long timestamp_dropped;
144 unsigned long av_pkt_rcvd;
145 unsigned long av_tagged_pkt_rcvd;
146 unsigned long vlan_tag_priority_val;
147 unsigned long l3_filter_match;
148 unsigned long l4_filter_match;
149 unsigned long l3_l4_filter_no_match;
0982a0f6
GC		 150 /* PCS */
151 unsigned long irq_pcs_ane_n;
152 unsigned long irq_pcs_link_n;
153 unsigned long irq_rgmii_n;
e58bb43f
GC		 154 unsigned long pcs_link;
155 unsigned long pcs_duplex;
156 unsigned long pcs_speed;
2f7a791c
GC		 157 /* debug register */
158 unsigned long mtl_tx_status_fifo_full;
159 unsigned long mtl_tx_fifo_not_empty;
160 unsigned long mmtl_fifo_ctrl;
161 unsigned long mtl_tx_fifo_read_ctrl_write;
162 unsigned long mtl_tx_fifo_read_ctrl_wait;
163 unsigned long mtl_tx_fifo_read_ctrl_read;
164 unsigned long mtl_tx_fifo_read_ctrl_idle;
165 unsigned long mac_tx_in_pause;
166 unsigned long mac_tx_frame_ctrl_xfer;
167 unsigned long mac_tx_frame_ctrl_idle;
168 unsigned long mac_tx_frame_ctrl_wait;
169 unsigned long mac_tx_frame_ctrl_pause;
170 unsigned long mac_gmii_tx_proto_engine;
171 unsigned long mtl_rx_fifo_fill_level_full;
172 unsigned long mtl_rx_fifo_fill_above_thresh;
173 unsigned long mtl_rx_fifo_fill_below_thresh;
174 unsigned long mtl_rx_fifo_fill_level_empty;
175 unsigned long mtl_rx_fifo_read_ctrl_flush;
176 unsigned long mtl_rx_fifo_read_ctrl_read_data;
177 unsigned long mtl_rx_fifo_read_ctrl_status;
178 unsigned long mtl_rx_fifo_read_ctrl_idle;
179 unsigned long mtl_rx_fifo_ctrl_active;
180 unsigned long mac_rx_frame_ctrl_fifo;
181 unsigned long mac_gmii_rx_proto_engine;
f748be53
AT		 182 /* TSO */
183 unsigned long tx_tso_frames;
184 unsigned long tx_tso_nfrags;
9f298959
OBL		 185 /* EST */
186 unsigned long mtl_est_cgce;
187 unsigned long mtl_est_hlbs;
188 unsigned long mtl_est_hlbf;
189 unsigned long mtl_est_btre;
190 unsigned long mtl_est_btrlm;
47dd7a54
GC		 191};
192
8bf993a5
JA		 193/* Safety Feature statistics exposed by ethtool */
194struct stmmac_safety_stats {
195 unsigned long mac_errors[32];
196 unsigned long mtl_errors[32];
197 unsigned long dma_errors[32];
198};
199
200/* Number of fields in Safety Stats */
201#define STMMAC_SAFETY_FEAT_SIZE \
202 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
203
cd7201f4
GC		 204/* CSR Frequency Access Defines*/
205#define CSR_F_35M 35000000
206#define CSR_F_60M 60000000
207#define CSR_F_100M 100000000
208#define CSR_F_150M 150000000
209#define CSR_F_250M 250000000
210#define CSR_F_300M 300000000
211
212#define MAC_CSR_H_FRQ_MASK 0x20
213
aec7ff27 214#define HASH_TABLE_SIZE 64
f88203a2 215#define PAUSE_TIME 0xffff
aec7ff27
GC		 216
217/* Flow Control defines */
218#define FLOW_OFF 0
219#define FLOW_RX 1
220#define FLOW_TX 2
221#define FLOW_AUTO (FLOW_TX | FLOW_RX)
222
e58bb43f
GC		 223/* PCS defines */
224#define STMMAC_PCS_RGMII (1 << 0)
225#define STMMAC_PCS_SGMII (1 << 1)
226#define STMMAC_PCS_TBI (1 << 2)
227#define STMMAC_PCS_RTBI (1 << 3)
228
ceb69499 229#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
aec7ff27 230
1db123fb 231/* DAM HW feature register fields */
ceb69499
GC		 232#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
233#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
234#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
235#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
236#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
237#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
238#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
239#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
240#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
241#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
242#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
243#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
244#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
245#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
246#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
247#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
248#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
249#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
250#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
251#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
252#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
253#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
254#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
255/* Timestamping with Internal System Time */
256#define DMA_HW_FEAT_INTTSEN 0x02000000
257#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
258#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
259#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
0f1f88a8 260#define DEFAULT_DMA_PBL 8
1db123fb 261
70523e63
GC		 262/* PCS status and mask defines */
263#define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
264#define PCS_LINK_IRQ BIT(1) /* PCS Link */
265#define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
266
62a2ab93
GC		 267/* Max/Min RI Watchdog Timer count value */
268#define MAX_DMA_RIWT 0xff
01d1689d 269#define MIN_DMA_RIWT 0x10
4e4337cc 270#define DEF_DMA_RIWT 0xa0
9125cdd1 271/* Tx coalesce parameters */
8fce3331 272#define STMMAC_COAL_TX_TIMER 1000
9125cdd1
GC		 273#define STMMAC_MAX_COAL_TX_TICK 100000
274#define STMMAC_TX_MAX_FRAMES 256
da202451
JA		 275#define STMMAC_TX_FRAMES 25
276#define STMMAC_RX_FRAMES 0
9125cdd1 277
abe80fdc
JP		 278/* Packets types */
279enum packets_types {
280 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
281 PACKET_PTPQ = 0x2, /* PTP Packets */
282 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
283 PACKET_UPQ = 0x4, /* Untagged Packets */
284 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
285};
286
ceb69499
GC		 287/* Rx IPC status */
288enum rx_frame_status {
c1fa3212
FG		 289 good_frame = 0x0,
290 discard_frame = 0x1,
291 csum_none = 0x2,
292 llc_snap = 0x4,
293 dma_own = 0x8,
753a7109 294 rx_not_ls = 0x10,
47dd7a54
GC		 295};
296
c363b658
FG		 297/* Tx status */
298enum tx_frame_status {
299 tx_done = 0x0,
300 tx_not_ls = 0x1,
301 tx_err = 0x2,
302 tx_dma_own = 0x4,
303};
304
9125cdd1
GC		 305enum dma_irq_status {
306 tx_hard_error = 0x1,
307 tx_hard_error_bump_tc = 0x2,
308 handle_rx = 0x4,
309 handle_tx = 0x8,
aec7ff27 310};
47dd7a54 311
915c199f 312/* EEE and LPI defines */
162fb1d6 313#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
314#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
315#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
316#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
0982a0f6 317
48863ce5 318#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
d765955d 319
915c199f 320/* Physical Coding Sublayer */
e58bb43f
GC		 321struct rgmii_adv {
322 unsigned int pause;
323 unsigned int duplex;
324 unsigned int lp_pause;
325 unsigned int lp_duplex;
326};
327
328#define STMMAC_PCS_PAUSE 1
329#define STMMAC_PCS_ASYM_PAUSE 2
330
e7434821
GC		 331/* DMA HW capabilities */
332struct dma_features {
333 unsigned int mbps_10_100;
334 unsigned int mbps_1000;
335 unsigned int half_duplex;
336 unsigned int hash_filter;
337 unsigned int multi_addr;
338 unsigned int pcs;
339 unsigned int sma_mdio;
340 unsigned int pmt_remote_wake_up;
341 unsigned int pmt_magic_frame;
342 unsigned int rmon;
ceb69499 343 /* IEEE 1588-2002 */
e7434821 344 unsigned int time_stamp;
ceb69499 345 /* IEEE 1588-2008 */
e7434821
GC		 346 unsigned int atime_stamp;
347 /* 802.3az - Energy-Efficient Ethernet (EEE) */
348 unsigned int eee;
349 unsigned int av;
b8ef7020 350 unsigned int hash_tb_sz;
48863ce5 351 unsigned int tsoen;
e7434821
GC		 352 /* TX and RX csum */
353 unsigned int tx_coe;
48863ce5 354 unsigned int rx_coe;
e7434821
GC		 355 unsigned int rx_coe_type1;
356 unsigned int rx_coe_type2;
357 unsigned int rxfifo_over_2048;
358 /* TX and RX number of channels */
359 unsigned int number_rx_channel;
360 unsigned int number_tx_channel;
9eb12474 361 /* TX and RX number of queues */
362 unsigned int number_rx_queues;
363 unsigned int number_tx_queues;
9a8a02c9
JA		 364 /* PPS output */
365 unsigned int pps_out_num;
ceb69499 366 /* Alternate (enhanced) DESC mode */
e7434821 367 unsigned int enh_desc;
11fbf811
TR		 368 /* TX and RX FIFO sizes */
369 unsigned int tx_fifo_size;
370 unsigned int rx_fifo_size;
8bf993a5
JA		 371 /* Automotive Safety Package */
372 unsigned int asp;
4dbbe8dd
JA		 373 /* RX Parser */
374 unsigned int frpsel;
375 unsigned int frpbs;
376 unsigned int frpes;
a993db88 377 unsigned int addr64;
76067459 378 unsigned int rssen;
3cd1cfcb 379 unsigned int vlhash;
67afd6d1 380 unsigned int sphen;
30d93227
JA		 381 unsigned int vlins;
382 unsigned int dvlan;
425eabdd 383 unsigned int l3l4fnum;
5904a980 384 unsigned int arpoffsel;
504723af
JA		 385 /* TSN Features */
386 unsigned int estwid;
387 unsigned int estdep;
388 unsigned int estsel;
1ac14241 389 unsigned int fpesel;
430b383c 390 unsigned int tbssel;
341f67e4
TTM		 391 /* Numbers of Auxiliary Snapshot Inputs */
392 unsigned int aux_snapshot_n;
e7434821
GC		 393};
394
86051317
JA		 395/* RX Buffer size must be multiple of 4/8/16 bytes */
396#define BUF_SIZE_16KiB 16368
8137b6ef 397#define BUF_SIZE_8KiB 8188
aec7ff27
GC		 398#define BUF_SIZE_4KiB 4096
399#define BUF_SIZE_2KiB 2048
47dd7a54 400
aec7ff27
GC		 401/* Power Down and WOL */
402#define PMT_NOT_SUPPORTED 0
403#define PMT_SUPPORTED 1
47dd7a54 404
aec7ff27
GC		 405/* Common MAC defines */
406#define MAC_CTRL_REG 0x00000000 /* MAC Control */
407#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
28089222 408#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
47dd7a54 409
d765955d 410/* Default LPI timers */
f5351ef7 411#define STMMAC_DEFAULT_LIT_LS 0x3E8
438a62b1 412#define STMMAC_DEFAULT_TWT_LS 0x1E
be1c7eae 413#define STMMAC_ET_MAX 0xFFFFF
d765955d 414
4a7d666a
GC		 415#define STMMAC_CHAIN_MODE 0x1
416#define STMMAC_RING_MODE 0x2
417
2618abb7
VB		 418#define JUMBO_LEN 9000
419
76067459
JA		 420/* Receive Side Scaling */
421#define STMMAC_RSS_HASH_KEY_SIZE 40
422#define STMMAC_RSS_MAX_TABLE_SIZE 256
423
30d93227
JA		 424/* VLAN */
425#define STMMAC_VLAN_NONE 0x0
426#define STMMAC_VLAN_REMOVE 0x1
427#define STMMAC_VLAN_INSERT 0x2
428#define STMMAC_VLAN_REPLACE 0x3
429
915af656
AS		 430extern const struct stmmac_desc_ops enh_desc_ops;
431extern const struct stmmac_desc_ops ndesc_ops;
432
7ed24bbe
VB		 433struct mac_device_info;
434
915af656 435extern const struct stmmac_hwtimestamp stmmac_ptp;
48863ce5 436extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
915af656 437
47dd7a54 438struct mac_link {
ca84dfb9
LC		 439 u32 speed_mask;
440 u32 speed10;
441 u32 speed100;
442 u32 speed1000;
2142754f 443 u32 speed2500;
ca84dfb9 444 u32 duplex;
5b0d7d7d
JA		 445 struct {
446 u32 speed2500;
447 u32 speed5000;
448 u32 speed10000;
449 } xgmii;
8a880936
JA		 450 struct {
451 u32 speed25000;
452 u32 speed40000;
453 u32 speed50000;
454 u32 speed100000;
455 } xlgmii;
47dd7a54
GC		 456};
457
458struct mii_regs {
459 unsigned int addr; /* MII Address */
460 unsigned int data; /* MII Data */
b91dce4c
LC		 461 unsigned int addr_shift; /* MII address shift */
462 unsigned int reg_shift; /* MII reg shift */
463 unsigned int addr_mask; /* MII address mask */
464 unsigned int reg_mask; /* MII reg mask */
465 unsigned int clk_csr_shift;
466 unsigned int clk_csr_mask;
47dd7a54
GC		 467};
468
47dd7a54 469struct mac_device_info {
ceb69499
GC		 470 const struct stmmac_ops *mac;
471 const struct stmmac_desc_ops *desc;
472 const struct stmmac_dma_ops *dma;
29896a67 473 const struct stmmac_mode_ops *mode;
891434b1 474 const struct stmmac_hwtimestamp *ptp;
4dbbe8dd 475 const struct stmmac_tc_ops *tc;
3b1dd2c5 476 const struct stmmac_mmc_ops *mmc;
f213bbe8
JA		 477 const struct mdio_xpcs_ops *xpcs;
478 struct mdio_xpcs_args xpcs_args;
db98a0b0
GC		 479 struct mii_regs mii; /* MII register Addresses */
480 struct mac_link link;
7ed24bbe 481 void __iomem *pcsr; /* vpointer to device CSRs */
b8ef7020
BH		 482 unsigned int multicast_filter_bins;
483 unsigned int unicast_filter_entries;
484 unsigned int mcast_bits_log2;
d2afb5bd 485 unsigned int rx_csum;
3fe5cadb
GC		 486 unsigned int pcs;
487 unsigned int pmt;
02e57b9d 488 unsigned int ps;
4a4ccde0 489 unsigned int xlgmac;
ed64639b
WVK		 490 unsigned int num_vlan;
491 u32 vlan_filter[32];
c89f44ff 492 unsigned int promisc;
e0f9956a
CKT		 493 bool vlan_fail_q_en;
494 u8 vlan_fail_q;
47dd7a54
GC		 495};
496
abe80fdc
JP		 497struct stmmac_rx_routing {
498 u32 reg_mask;
499 u32 reg_shift;
500};
501
5f0456b4
JA		 502int dwmac100_setup(struct stmmac_priv *priv);
503int dwmac1000_setup(struct stmmac_priv *priv);
504int dwmac4_setup(struct stmmac_priv *priv);
2142754f 505int dwxgmac2_setup(struct stmmac_priv *priv);
4a4ccde0 506int dwxlgmac2_setup(struct stmmac_priv *priv);
aec7ff27 507
d6cc64ef
JP		 508void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
509 unsigned int high, unsigned int low);
510void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
511 unsigned int high, unsigned int low);
d6cc64ef 512void stmmac_set_mac(void __iomem *ioaddr, bool enable);
bfab27a1 513
477286b5
AT		 514void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
515 unsigned int high, unsigned int low);
516void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
517 unsigned int high, unsigned int low);
518void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
519
d6cc64ef 520void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
70523e63 521
29896a67
GC		 522extern const struct stmmac_mode_ops ring_mode_ops;
523extern const struct stmmac_mode_ops chain_mode_ops;
f748be53 524extern const struct stmmac_desc_ops dwmac4_desc_ops;
bd4242df
RK		 525
526#endif /* __COMMON_H__ */
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