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47dd7a54 GC |
1 | /******************************************************************************* |
2 | STMMAC Common Header File | |
3 | ||
4 | Copyright (C) 2007-2009 STMicroelectronics Ltd | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
23 | *******************************************************************************/ | |
24 | ||
5e33c791 | 25 | #include <linux/netdevice.h> |
8f617541 GC |
26 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
27 | #define STMMAC_VLAN_TAG_USED | |
28 | #include <linux/if_vlan.h> | |
29 | #endif | |
30 | ||
56b106ae GC |
31 | #include "descs.h" |
32 | ||
33 | #undef CHIP_DEBUG_PRINT | |
34 | /* Turn-on extra printk debug for MAC core, dma and descriptors */ | |
35 | /* #define CHIP_DEBUG_PRINT */ | |
36 | ||
37 | #ifdef CHIP_DEBUG_PRINT | |
38 | #define CHIP_DBG(fmt, args...) printk(fmt, ## args) | |
39 | #else | |
40 | #define CHIP_DBG(fmt, args...) do { } while (0) | |
41 | #endif | |
42 | ||
43 | #undef FRAME_FILTER_DEBUG | |
44 | /* #define FRAME_FILTER_DEBUG */ | |
47dd7a54 | 45 | |
47dd7a54 GC |
46 | struct stmmac_extra_stats { |
47 | /* Transmit errors */ | |
48 | unsigned long tx_underflow ____cacheline_aligned; | |
49 | unsigned long tx_carrier; | |
50 | unsigned long tx_losscarrier; | |
51 | unsigned long tx_heartbeat; | |
52 | unsigned long tx_deferred; | |
53 | unsigned long tx_vlan; | |
54 | unsigned long tx_jabber; | |
55 | unsigned long tx_frame_flushed; | |
56 | unsigned long tx_payload_error; | |
57 | unsigned long tx_ip_header_error; | |
58 | /* Receive errors */ | |
59 | unsigned long rx_desc; | |
60 | unsigned long rx_partial; | |
61 | unsigned long rx_runt; | |
62 | unsigned long rx_toolong; | |
63 | unsigned long rx_collision; | |
64 | unsigned long rx_crc; | |
1b924032 | 65 | unsigned long rx_length; |
47dd7a54 GC |
66 | unsigned long rx_mii; |
67 | unsigned long rx_multicast; | |
68 | unsigned long rx_gmac_overflow; | |
69 | unsigned long rx_watchdog; | |
70 | unsigned long da_rx_filter_fail; | |
71 | unsigned long sa_rx_filter_fail; | |
72 | unsigned long rx_missed_cntr; | |
73 | unsigned long rx_overflow_cntr; | |
74 | unsigned long rx_vlan; | |
75 | /* Tx/Rx IRQ errors */ | |
76 | unsigned long tx_undeflow_irq; | |
77 | unsigned long tx_process_stopped_irq; | |
78 | unsigned long tx_jabber_irq; | |
79 | unsigned long rx_overflow_irq; | |
80 | unsigned long rx_buf_unav_irq; | |
81 | unsigned long rx_process_stopped_irq; | |
82 | unsigned long rx_watchdog_irq; | |
83 | unsigned long tx_early_irq; | |
84 | unsigned long fatal_bus_error_irq; | |
85 | /* Extra info */ | |
86 | unsigned long threshold; | |
87 | unsigned long tx_pkt_n; | |
88 | unsigned long rx_pkt_n; | |
89 | unsigned long poll_n; | |
90 | unsigned long sched_timer_n; | |
91 | unsigned long normal_irq_n; | |
92 | }; | |
93 | ||
aec7ff27 GC |
94 | #define HASH_TABLE_SIZE 64 |
95 | #define PAUSE_TIME 0x200 | |
96 | ||
97 | /* Flow Control defines */ | |
98 | #define FLOW_OFF 0 | |
99 | #define FLOW_RX 1 | |
100 | #define FLOW_TX 2 | |
101 | #define FLOW_AUTO (FLOW_TX | FLOW_RX) | |
102 | ||
103 | #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ | |
104 | ||
aec7ff27 | 105 | enum rx_frame_status { /* IPC status */ |
47dd7a54 GC |
106 | good_frame = 0, |
107 | discard_frame = 1, | |
108 | csum_none = 2, | |
3eeb2997 | 109 | llc_snap = 4, |
47dd7a54 GC |
110 | }; |
111 | ||
aec7ff27 GC |
112 | enum tx_dma_irq_status { |
113 | tx_hard_error = 1, | |
114 | tx_hard_error_bump_tc = 2, | |
115 | handle_tx_rx = 3, | |
116 | }; | |
47dd7a54 | 117 | |
aec7ff27 GC |
118 | /* GMAC TX FIFO is 8K, Rx FIFO is 16K */ |
119 | #define BUF_SIZE_16KiB 16384 | |
120 | #define BUF_SIZE_8KiB 8192 | |
121 | #define BUF_SIZE_4KiB 4096 | |
122 | #define BUF_SIZE_2KiB 2048 | |
47dd7a54 | 123 | |
aec7ff27 GC |
124 | /* Power Down and WOL */ |
125 | #define PMT_NOT_SUPPORTED 0 | |
126 | #define PMT_SUPPORTED 1 | |
47dd7a54 | 127 | |
aec7ff27 GC |
128 | /* Common MAC defines */ |
129 | #define MAC_CTRL_REG 0x00000000 /* MAC Control */ | |
130 | #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ | |
131 | #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */ | |
47dd7a54 | 132 | |
db98a0b0 GC |
133 | struct stmmac_desc_ops { |
134 | /* DMA RX descriptor ring initialization */ | |
47dd7a54 | 135 | void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size, |
db98a0b0 GC |
136 | int disable_rx_ic); |
137 | /* DMA TX descriptor ring initialization */ | |
47dd7a54 GC |
138 | void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size); |
139 | ||
140 | /* Invoked by the xmit function to prepare the tx descriptor */ | |
141 | void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len, | |
142 | int csum_flag); | |
143 | /* Set/get the owner of the descriptor */ | |
144 | void (*set_tx_owner) (struct dma_desc *p); | |
145 | int (*get_tx_owner) (struct dma_desc *p); | |
146 | /* Invoked by the xmit function to close the tx descriptor */ | |
147 | void (*close_tx_desc) (struct dma_desc *p); | |
148 | /* Clean the tx descriptor as soon as the tx irq is received */ | |
149 | void (*release_tx_desc) (struct dma_desc *p); | |
150 | /* Clear interrupt on tx frame completion. When this bit is | |
151 | * set an interrupt happens as soon as the frame is transmitted */ | |
152 | void (*clear_tx_ic) (struct dma_desc *p); | |
153 | /* Last tx segment reports the transmit status */ | |
154 | int (*get_tx_ls) (struct dma_desc *p); | |
155 | /* Return the transmit status looking at the TDES1 */ | |
156 | int (*tx_status) (void *data, struct stmmac_extra_stats *x, | |
ad01b7d4 | 157 | struct dma_desc *p, void __iomem *ioaddr); |
47dd7a54 GC |
158 | /* Get the buffer size from the descriptor */ |
159 | int (*get_tx_len) (struct dma_desc *p); | |
160 | /* Handle extra events on specific interrupts hw dependent */ | |
47dd7a54 GC |
161 | int (*get_rx_owner) (struct dma_desc *p); |
162 | void (*set_rx_owner) (struct dma_desc *p); | |
163 | /* Get the receive frame size */ | |
164 | int (*get_rx_frame_len) (struct dma_desc *p); | |
165 | /* Return the reception status looking at the RDES1 */ | |
166 | int (*rx_status) (void *data, struct stmmac_extra_stats *x, | |
167 | struct dma_desc *p); | |
db98a0b0 GC |
168 | }; |
169 | ||
170 | struct stmmac_dma_ops { | |
171 | /* DMA core initialization */ | |
ad01b7d4 | 172 | int (*init) (void __iomem *ioaddr, int pbl, u32 dma_tx, u32 dma_rx); |
db98a0b0 | 173 | /* Dump DMA registers */ |
ad01b7d4 | 174 | void (*dump_regs) (void __iomem *ioaddr); |
db98a0b0 GC |
175 | /* Set tx/rx threshold in the csr6 register |
176 | * An invalid value enables the store-and-forward mode */ | |
ad01b7d4 | 177 | void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode); |
db98a0b0 GC |
178 | /* To track extra statistic (if supported) */ |
179 | void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x, | |
ad01b7d4 GC |
180 | void __iomem *ioaddr); |
181 | void (*enable_dma_transmission) (void __iomem *ioaddr); | |
182 | void (*enable_dma_irq) (void __iomem *ioaddr); | |
183 | void (*disable_dma_irq) (void __iomem *ioaddr); | |
184 | void (*start_tx) (void __iomem *ioaddr); | |
185 | void (*stop_tx) (void __iomem *ioaddr); | |
186 | void (*start_rx) (void __iomem *ioaddr); | |
187 | void (*stop_rx) (void __iomem *ioaddr); | |
188 | int (*dma_interrupt) (void __iomem *ioaddr, | |
aec7ff27 | 189 | struct stmmac_extra_stats *x); |
db98a0b0 GC |
190 | }; |
191 | ||
192 | struct stmmac_ops { | |
193 | /* MAC core initialization */ | |
ad01b7d4 | 194 | void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned; |
ebbb293f GC |
195 | /* Support checksum offload engine */ |
196 | int (*rx_coe) (void __iomem *ioaddr); | |
db98a0b0 | 197 | /* Dump MAC registers */ |
ad01b7d4 | 198 | void (*dump_regs) (void __iomem *ioaddr); |
db98a0b0 | 199 | /* Handle extra events on specific interrupts hw dependent */ |
ad01b7d4 | 200 | void (*host_irq_status) (void __iomem *ioaddr); |
47dd7a54 GC |
201 | /* Multicast filter setting */ |
202 | void (*set_filter) (struct net_device *dev); | |
203 | /* Flow control setting */ | |
ad01b7d4 | 204 | void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex, |
47dd7a54 GC |
205 | unsigned int fc, unsigned int pause_time); |
206 | /* Set power management mode (e.g. magic frame) */ | |
ad01b7d4 | 207 | void (*pmt) (void __iomem *ioaddr, unsigned long mode); |
47dd7a54 | 208 | /* Set/Get Unicast MAC addresses */ |
ad01b7d4 | 209 | void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr, |
db98a0b0 | 210 | unsigned int reg_n); |
ad01b7d4 | 211 | void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr, |
db98a0b0 | 212 | unsigned int reg_n); |
47dd7a54 GC |
213 | }; |
214 | ||
215 | struct mac_link { | |
216 | int port; | |
217 | int duplex; | |
218 | int speed; | |
219 | }; | |
220 | ||
221 | struct mii_regs { | |
222 | unsigned int addr; /* MII Address */ | |
223 | unsigned int data; /* MII Data */ | |
224 | }; | |
225 | ||
47dd7a54 | 226 | struct mac_device_info { |
cadb7924 | 227 | const struct stmmac_ops *mac; |
228 | const struct stmmac_desc_ops *desc; | |
229 | const struct stmmac_dma_ops *dma; | |
db98a0b0 GC |
230 | struct mii_regs mii; /* MII register Addresses */ |
231 | struct mac_link link; | |
47dd7a54 GC |
232 | }; |
233 | ||
ad01b7d4 GC |
234 | struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr); |
235 | struct mac_device_info *dwmac100_setup(void __iomem *ioaddr); | |
aec7ff27 | 236 | |
ad01b7d4 | 237 | extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], |
aec7ff27 | 238 | unsigned int high, unsigned int low); |
ad01b7d4 | 239 | extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, |
aec7ff27 | 240 | unsigned int high, unsigned int low); |
ad01b7d4 | 241 | extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); |