[linux-block.git] / drivers / net / ethernet / stmicro / stmmac / common.h

/*******************************************************************************
  STMMAC Common Header File

  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#ifndef __COMMON_H__
#define __COMMON_H__

#include <linux/etherdevice.h>
#include <linux/netdevice.h>
#include <linux/stmmac.h>
#include <linux/phy.h>
#include <linux/module.h>
#if IS_ENABLED(CONFIG_VLAN_8021Q)
#define STMMAC_VLAN_TAG_USED
#include <linux/if_vlan.h>
#endif

#include "descs.h"
#include "hwif.h"
#include "mmc.h"

/* Synopsys Core versions */
#define	DWMAC_CORE_3_40	0x34
#define	DWMAC_CORE_3_50	0x35
#define	DWMAC_CORE_4_00	0x40
#define DWMAC_CORE_5_00 0x50
#define DWMAC_CORE_5_10 0x51
#define STMMAC_CHAN0	0	/* Always supported and default for all chips */

/* These need to be power of two, and >= 4 */
#define DMA_TX_SIZE 512
#define DMA_RX_SIZE 512
#define STMMAC_GET_ENTRY(x, size)	((x + 1) & (size - 1))

#undef FRAME_FILTER_DEBUG
/* #define FRAME_FILTER_DEBUG */

/* Extra statistic and debug information exposed by ethtool */
struct stmmac_extra_stats {
	/* Transmit errors */
	unsigned long tx_underflow ____cacheline_aligned;
	unsigned long tx_carrier;
	unsigned long tx_losscarrier;
	unsigned long vlan_tag;
	unsigned long tx_deferred;
	unsigned long tx_vlan;
	unsigned long tx_jabber;
	unsigned long tx_frame_flushed;
	unsigned long tx_payload_error;
	unsigned long tx_ip_header_error;
	/* Receive errors */
	unsigned long rx_desc;
	unsigned long sa_filter_fail;
	unsigned long overflow_error;
	unsigned long ipc_csum_error;
	unsigned long rx_collision;
	unsigned long rx_crc_errors;
	unsigned long dribbling_bit;
	unsigned long rx_length;
	unsigned long rx_mii;
	unsigned long rx_multicast;
	unsigned long rx_gmac_overflow;
	unsigned long rx_watchdog;
	unsigned long da_rx_filter_fail;
	unsigned long sa_rx_filter_fail;
	unsigned long rx_missed_cntr;
	unsigned long rx_overflow_cntr;
	unsigned long rx_vlan;
	/* Tx/Rx IRQ error info */
	unsigned long tx_undeflow_irq;
	unsigned long tx_process_stopped_irq;
	unsigned long tx_jabber_irq;
	unsigned long rx_overflow_irq;
	unsigned long rx_buf_unav_irq;
	unsigned long rx_process_stopped_irq;
	unsigned long rx_watchdog_irq;
	unsigned long tx_early_irq;
	unsigned long fatal_bus_error_irq;
	/* Tx/Rx IRQ Events */
	unsigned long rx_early_irq;
	unsigned long threshold;
	unsigned long tx_pkt_n;
	unsigned long rx_pkt_n;
	unsigned long normal_irq_n;
	unsigned long rx_normal_irq_n;
	unsigned long napi_poll;
	unsigned long tx_normal_irq_n;
	unsigned long tx_clean;
	unsigned long tx_set_ic_bit;
	unsigned long irq_receive_pmt_irq_n;
	/* MMC info */
	unsigned long mmc_tx_irq_n;
	unsigned long mmc_rx_irq_n;
	unsigned long mmc_rx_csum_offload_irq_n;
	/* EEE */
	unsigned long irq_tx_path_in_lpi_mode_n;
	unsigned long irq_tx_path_exit_lpi_mode_n;
	unsigned long irq_rx_path_in_lpi_mode_n;
	unsigned long irq_rx_path_exit_lpi_mode_n;
	unsigned long phy_eee_wakeup_error_n;
	/* Extended RDES status */
	unsigned long ip_hdr_err;
	unsigned long ip_payload_err;
	unsigned long ip_csum_bypassed;
	unsigned long ipv4_pkt_rcvd;
	unsigned long ipv6_pkt_rcvd;
	unsigned long no_ptp_rx_msg_type_ext;
	unsigned long ptp_rx_msg_type_sync;
	unsigned long ptp_rx_msg_type_follow_up;
	unsigned long ptp_rx_msg_type_delay_req;
	unsigned long ptp_rx_msg_type_delay_resp;
	unsigned long ptp_rx_msg_type_pdelay_req;
	unsigned long ptp_rx_msg_type_pdelay_resp;
	unsigned long ptp_rx_msg_type_pdelay_follow_up;
	unsigned long ptp_rx_msg_type_announce;
	unsigned long ptp_rx_msg_type_management;
	unsigned long ptp_rx_msg_pkt_reserved_type;
	unsigned long ptp_frame_type;
	unsigned long ptp_ver;
	unsigned long timestamp_dropped;
	unsigned long av_pkt_rcvd;
	unsigned long av_tagged_pkt_rcvd;
	unsigned long vlan_tag_priority_val;
	unsigned long l3_filter_match;
	unsigned long l4_filter_match;
	unsigned long l3_l4_filter_no_match;
	/* PCS */
	unsigned long irq_pcs_ane_n;
	unsigned long irq_pcs_link_n;
	unsigned long irq_rgmii_n;
	unsigned long pcs_link;
	unsigned long pcs_duplex;
	unsigned long pcs_speed;
	/* debug register */
	unsigned long mtl_tx_status_fifo_full;
	unsigned long mtl_tx_fifo_not_empty;
	unsigned long mmtl_fifo_ctrl;
	unsigned long mtl_tx_fifo_read_ctrl_write;
	unsigned long mtl_tx_fifo_read_ctrl_wait;
	unsigned long mtl_tx_fifo_read_ctrl_read;
	unsigned long mtl_tx_fifo_read_ctrl_idle;
	unsigned long mac_tx_in_pause;
	unsigned long mac_tx_frame_ctrl_xfer;
	unsigned long mac_tx_frame_ctrl_idle;
	unsigned long mac_tx_frame_ctrl_wait;
	unsigned long mac_tx_frame_ctrl_pause;
	unsigned long mac_gmii_tx_proto_engine;
	unsigned long mtl_rx_fifo_fill_level_full;
	unsigned long mtl_rx_fifo_fill_above_thresh;
	unsigned long mtl_rx_fifo_fill_below_thresh;
	unsigned long mtl_rx_fifo_fill_level_empty;
	unsigned long mtl_rx_fifo_read_ctrl_flush;
	unsigned long mtl_rx_fifo_read_ctrl_read_data;
	unsigned long mtl_rx_fifo_read_ctrl_status;
	unsigned long mtl_rx_fifo_read_ctrl_idle;
	unsigned long mtl_rx_fifo_ctrl_active;
	unsigned long mac_rx_frame_ctrl_fifo;
	unsigned long mac_gmii_rx_proto_engine;
	/* TSO */
	unsigned long tx_tso_frames;
	unsigned long tx_tso_nfrags;
};

/* Safety Feature statistics exposed by ethtool */
struct stmmac_safety_stats {
	unsigned long mac_errors[32];
	unsigned long mtl_errors[32];
	unsigned long dma_errors[32];
};

/* Number of fields in Safety Stats */
#define STMMAC_SAFETY_FEAT_SIZE	\
	(sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))

/* CSR Frequency Access Defines*/
#define CSR_F_35M	35000000
#define CSR_F_60M	60000000
#define CSR_F_100M	100000000
#define CSR_F_150M	150000000
#define CSR_F_250M	250000000
#define CSR_F_300M	300000000

#define	MAC_CSR_H_FRQ_MASK	0x20

#define HASH_TABLE_SIZE 64
#define PAUSE_TIME 0xffff

/* Flow Control defines */
#define FLOW_OFF	0
#define FLOW_RX		1
#define FLOW_TX		2
#define FLOW_AUTO	(FLOW_TX | FLOW_RX)

/* PCS defines */
#define STMMAC_PCS_RGMII	(1 << 0)
#define STMMAC_PCS_SGMII	(1 << 1)
#define STMMAC_PCS_TBI		(1 << 2)
#define STMMAC_PCS_RTBI		(1 << 3)

#define SF_DMA_MODE 1		/* DMA STORE-AND-FORWARD Operation Mode */

/* DAM HW feature register fields */
#define DMA_HW_FEAT_MIISEL	0x00000001	/* 10/100 Mbps Support */
#define DMA_HW_FEAT_GMIISEL	0x00000002	/* 1000 Mbps Support */
#define DMA_HW_FEAT_HDSEL	0x00000004	/* Half-Duplex Support */
#define DMA_HW_FEAT_EXTHASHEN	0x00000008	/* Expanded DA Hash Filter */
#define DMA_HW_FEAT_HASHSEL	0x00000010	/* HASH Filter */
#define DMA_HW_FEAT_ADDMAC	0x00000020	/* Multiple MAC Addr Reg */
#define DMA_HW_FEAT_PCSSEL	0x00000040	/* PCS registers */
#define DMA_HW_FEAT_L3L4FLTREN	0x00000080	/* Layer 3 & Layer 4 Feature */
#define DMA_HW_FEAT_SMASEL	0x00000100	/* SMA(MDIO) Interface */
#define DMA_HW_FEAT_RWKSEL	0x00000200	/* PMT Remote Wakeup */
#define DMA_HW_FEAT_MGKSEL	0x00000400	/* PMT Magic Packet */
#define DMA_HW_FEAT_MMCSEL	0x00000800	/* RMON Module */
#define DMA_HW_FEAT_TSVER1SEL	0x00001000	/* Only IEEE 1588-2002 */
#define DMA_HW_FEAT_TSVER2SEL	0x00002000	/* IEEE 1588-2008 PTPv2 */
#define DMA_HW_FEAT_EEESEL	0x00004000	/* Energy Efficient Ethernet */
#define DMA_HW_FEAT_AVSEL	0x00008000	/* AV Feature */
#define DMA_HW_FEAT_TXCOESEL	0x00010000	/* Checksum Offload in Tx */
#define DMA_HW_FEAT_RXTYP1COE	0x00020000	/* IP COE (Type 1) in Rx */
#define DMA_HW_FEAT_RXTYP2COE	0x00040000	/* IP COE (Type 2) in Rx */
#define DMA_HW_FEAT_RXFIFOSIZE	0x00080000	/* Rx FIFO > 2048 Bytes */
#define DMA_HW_FEAT_RXCHCNT	0x00300000	/* No. additional Rx Channels */
#define DMA_HW_FEAT_TXCHCNT	0x00c00000	/* No. additional Tx Channels */
#define DMA_HW_FEAT_ENHDESSEL	0x01000000	/* Alternate Descriptor */
/* Timestamping with Internal System Time */
#define DMA_HW_FEAT_INTTSEN	0x02000000
#define DMA_HW_FEAT_FLEXIPPSEN	0x04000000	/* Flexible PPS Output */
#define DMA_HW_FEAT_SAVLANINS	0x08000000	/* Source Addr or VLAN */
#define DMA_HW_FEAT_ACTPHYIF	0x70000000	/* Active/selected PHY iface */
#define DEFAULT_DMA_PBL		8

/* PCS status and mask defines */
#define	PCS_ANE_IRQ		BIT(2)	/* PCS Auto-Negotiation */
#define	PCS_LINK_IRQ		BIT(1)	/* PCS Link */
#define	PCS_RGSMIIIS_IRQ	BIT(0)	/* RGMII or SMII Interrupt */

/* Max/Min RI Watchdog Timer count value */
#define MAX_DMA_RIWT		0xff
#define MIN_DMA_RIWT		0x20
/* Tx coalesce parameters */
#define STMMAC_COAL_TX_TIMER	40000
#define STMMAC_MAX_COAL_TX_TICK	100000
#define STMMAC_TX_MAX_FRAMES	256
#define STMMAC_TX_FRAMES	64

/* Packets types */
enum packets_types {
	PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
	PACKET_PTPQ = 0x2, /* PTP Packets */
	PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
	PACKET_UPQ = 0x4, /* Untagged Packets */
	PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
};

/* Rx IPC status */
enum rx_frame_status {
	good_frame = 0x0,
	discard_frame = 0x1,
	csum_none = 0x2,
	llc_snap = 0x4,
	dma_own = 0x8,
	rx_not_ls = 0x10,
};

/* Tx status */
enum tx_frame_status {
	tx_done = 0x0,
	tx_not_ls = 0x1,
	tx_err = 0x2,
	tx_dma_own = 0x4,
};

enum dma_irq_status {
	tx_hard_error = 0x1,
	tx_hard_error_bump_tc = 0x2,
	handle_rx = 0x4,
	handle_tx = 0x8,
};

/* EEE and LPI defines */
#define	CORE_IRQ_TX_PATH_IN_LPI_MODE	(1 << 0)
#define	CORE_IRQ_TX_PATH_EXIT_LPI_MODE	(1 << 1)
#define	CORE_IRQ_RX_PATH_IN_LPI_MODE	(1 << 2)
#define	CORE_IRQ_RX_PATH_EXIT_LPI_MODE	(1 << 3)

#define CORE_IRQ_MTL_RX_OVERFLOW	BIT(8)

/* Physical Coding Sublayer */
struct rgmii_adv {
	unsigned int pause;
	unsigned int duplex;
	unsigned int lp_pause;
	unsigned int lp_duplex;
};

#define STMMAC_PCS_PAUSE	1
#define STMMAC_PCS_ASYM_PAUSE	2

/* DMA HW capabilities */
struct dma_features {
	unsigned int mbps_10_100;
	unsigned int mbps_1000;
	unsigned int half_duplex;
	unsigned int hash_filter;
	unsigned int multi_addr;
	unsigned int pcs;
	unsigned int sma_mdio;
	unsigned int pmt_remote_wake_up;
	unsigned int pmt_magic_frame;
	unsigned int rmon;
	/* IEEE 1588-2002 */
	unsigned int time_stamp;
	/* IEEE 1588-2008 */
	unsigned int atime_stamp;
	/* 802.3az - Energy-Efficient Ethernet (EEE) */
	unsigned int eee;
	unsigned int av;
	unsigned int tsoen;
	/* TX and RX csum */
	unsigned int tx_coe;
	unsigned int rx_coe;
	unsigned int rx_coe_type1;
	unsigned int rx_coe_type2;
	unsigned int rxfifo_over_2048;
	/* TX and RX number of channels */
	unsigned int number_rx_channel;
	unsigned int number_tx_channel;
	/* TX and RX number of queues */
	unsigned int number_rx_queues;
	unsigned int number_tx_queues;
	/* Alternate (enhanced) DESC mode */
	unsigned int enh_desc;
	/* TX and RX FIFO sizes */
	unsigned int tx_fifo_size;
	unsigned int rx_fifo_size;
	/* Automotive Safety Package */
	unsigned int asp;
};

/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
#define BUF_SIZE_16KiB 16384
#define BUF_SIZE_8KiB 8192
#define BUF_SIZE_4KiB 4096
#define BUF_SIZE_2KiB 2048

/* Power Down and WOL */
#define PMT_NOT_SUPPORTED 0
#define PMT_SUPPORTED 1

/* Common MAC defines */
#define MAC_CTRL_REG		0x00000000	/* MAC Control */
#define MAC_ENABLE_TX		0x00000008	/* Transmitter Enable */
#define MAC_ENABLE_RX		0x00000004	/* Receiver Enable */

/* Default LPI timers */
#define STMMAC_DEFAULT_LIT_LS	0x3E8
#define STMMAC_DEFAULT_TWT_LS	0x1E

#define STMMAC_CHAIN_MODE	0x1
#define STMMAC_RING_MODE	0x2

#define JUMBO_LEN		9000

extern const struct stmmac_desc_ops enh_desc_ops;
extern const struct stmmac_desc_ops ndesc_ops;

struct mac_device_info;

extern const struct stmmac_hwtimestamp stmmac_ptp;
extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;

struct mac_link {
	u32 speed_mask;
	u32 speed10;
	u32 speed100;
	u32 speed1000;
	u32 duplex;
};

struct mii_regs {
	unsigned int addr;	/* MII Address */
	unsigned int data;	/* MII Data */
	unsigned int addr_shift;	/* MII address shift */
	unsigned int reg_shift;		/* MII reg shift */
	unsigned int addr_mask;		/* MII address mask */
	unsigned int reg_mask;		/* MII reg mask */
	unsigned int clk_csr_shift;
	unsigned int clk_csr_mask;
};

struct mac_device_info {
	const struct stmmac_ops *mac;
	const struct stmmac_desc_ops *desc;
	const struct stmmac_dma_ops *dma;
	const struct stmmac_mode_ops *mode;
	const struct stmmac_hwtimestamp *ptp;
	struct mii_regs mii;	/* MII register Addresses */
	struct mac_link link;
	void __iomem *pcsr;     /* vpointer to device CSRs */
	int multicast_filter_bins;
	int unicast_filter_entries;
	int mcast_bits_log2;
	unsigned int rx_csum;
	unsigned int pcs;
	unsigned int pmt;
	unsigned int ps;
};

struct stmmac_rx_routing {
	u32 reg_mask;
	u32 reg_shift;
};

struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
					int perfect_uc_entries,
					int *synopsys_id);
struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id);
struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
				     int perfect_uc_entries, int *synopsys_id);

void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
			 unsigned int high, unsigned int low);
void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
			 unsigned int high, unsigned int low);
void stmmac_set_mac(void __iomem *ioaddr, bool enable);

void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
				unsigned int high, unsigned int low);
void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
				unsigned int high, unsigned int low);
void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);

void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);

extern const struct stmmac_mode_ops ring_mode_ops;
extern const struct stmmac_mode_ops chain_mode_ops;
extern const struct stmmac_desc_ops dwmac4_desc_ops;

/**
 * stmmac_get_synopsys_id - return the SYINID.
 * @priv: driver private structure
 * Description: this simple function is to decode and return the SYINID
 * starting from the HW core register.
 */
static inline u32 stmmac_get_synopsys_id(u32 hwid)
{
	/* Check Synopsys Id (not available on old chips) */
	if (likely(hwid)) {
		u32 uid = ((hwid & 0x0000ff00) >> 8);
		u32 synid = (hwid & 0x000000ff);

		pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
			uid, synid);

		return synid;
	}
	return 0;
}
#endif /* __COMMON_H__ */
Commit	Line	Data
47dd7a54 GC	1	/*******************************************************************************
	2	STMMAC Common Header File
	3
	4	Copyright (C) 2007-2009 STMicroelectronics Ltd
	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
47dd7a54 GC	15	The full GNU General Public License is included in this distribution in
	16	the file called "COPYING".
	17
	18	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	19	*******************************************************************************/
	20
bd4242df RK	21	#ifndef __COMMON_H__
	22	#define __COMMON_H__
	23
bfab27a1	24	#include <linux/etherdevice.h>
5e33c791	25	#include <linux/netdevice.h>
afea0365	26	#include <linux/stmmac.h>
bfab27a1 GC	27	#include <linux/phy.h>
bfab27a1 GC	28	#include <linux/module.h>
12c70f30	29	#if IS_ENABLED(CONFIG_VLAN_8021Q)
8f617541 GC	30	#define STMMAC_VLAN_TAG_USED
	31	#include <linux/if_vlan.h>
	32	#endif
	33
56b106ae	34	#include "descs.h"
42de047d	35	#include "hwif.h"
1c901a46	36	#include "mmc.h"
56b106ae	37
62a2ab93 GC	38	/* Synopsys Core versions */
	39	#define DWMAC_CORE_3_40 0x34
	40	#define DWMAC_CORE_3_50 0x35
48863ce5	41	#define DWMAC_CORE_4_00 0x40
8bf993a5 JA	42	#define DWMAC_CORE_5_00 0x50
8bf993a5 JA	43	#define DWMAC_CORE_5_10 0x51
48863ce5	44	#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
62a2ab93	45
22d3efe5	46	/* These need to be power of two, and >= 4 */
e3ad57c9 GC	47	#define DMA_TX_SIZE 512
	48	#define DMA_RX_SIZE 512
	49	#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
	50
56b106ae GC	51	#undef FRAME_FILTER_DEBUG
56b106ae GC	52	/* #define FRAME_FILTER_DEBUG */
47dd7a54	53
915c199f	54	/* Extra statistic and debug information exposed by ethtool */
47dd7a54 GC	55	struct stmmac_extra_stats {
	56	/* Transmit errors */
	57	unsigned long tx_underflow ____cacheline_aligned;
	58	unsigned long tx_carrier;
	59	unsigned long tx_losscarrier;
3c20f72f	60	unsigned long vlan_tag;
47dd7a54 GC	61	unsigned long tx_deferred;
	62	unsigned long tx_vlan;
	63	unsigned long tx_jabber;
	64	unsigned long tx_frame_flushed;
	65	unsigned long tx_payload_error;
	66	unsigned long tx_ip_header_error;
	67	/* Receive errors */
	68	unsigned long rx_desc;
3c20f72f GC	69	unsigned long sa_filter_fail;
	70	unsigned long overflow_error;
	71	unsigned long ipc_csum_error;
47dd7a54	72	unsigned long rx_collision;
e0a76606	73	unsigned long rx_crc_errors;
1cc5a735	74	unsigned long dribbling_bit;
1b924032	75	unsigned long rx_length;
47dd7a54 GC	76	unsigned long rx_mii;
	77	unsigned long rx_multicast;
	78	unsigned long rx_gmac_overflow;
	79	unsigned long rx_watchdog;
	80	unsigned long da_rx_filter_fail;
	81	unsigned long sa_rx_filter_fail;
	82	unsigned long rx_missed_cntr;
	83	unsigned long rx_overflow_cntr;
	84	unsigned long rx_vlan;
62a2ab93	85	/* Tx/Rx IRQ error info */
47dd7a54 GC	86	unsigned long tx_undeflow_irq;
	87	unsigned long tx_process_stopped_irq;
	88	unsigned long tx_jabber_irq;
	89	unsigned long rx_overflow_irq;
	90	unsigned long rx_buf_unav_irq;
	91	unsigned long rx_process_stopped_irq;
	92	unsigned long rx_watchdog_irq;
	93	unsigned long tx_early_irq;
	94	unsigned long fatal_bus_error_irq;
62a2ab93 GC	95	/* Tx/Rx IRQ Events */
62a2ab93 GC	96	unsigned long rx_early_irq;
47dd7a54 GC	97	unsigned long threshold;
	98	unsigned long tx_pkt_n;
	99	unsigned long rx_pkt_n;
47dd7a54	100	unsigned long normal_irq_n;
9125cdd1 GC	101	unsigned long rx_normal_irq_n;
	102	unsigned long napi_poll;
	103	unsigned long tx_normal_irq_n;
	104	unsigned long tx_clean;
0e80bdc9	105	unsigned long tx_set_ic_bit;
62a2ab93 GC	106	unsigned long irq_receive_pmt_irq_n;
62a2ab93 GC	107	/* MMC info */
d765955d GC	108	unsigned long mmc_tx_irq_n;
	109	unsigned long mmc_rx_irq_n;
	110	unsigned long mmc_rx_csum_offload_irq_n;
	111	/* EEE */
d765955d GC	112	unsigned long irq_tx_path_in_lpi_mode_n;
	113	unsigned long irq_tx_path_exit_lpi_mode_n;
	114	unsigned long irq_rx_path_in_lpi_mode_n;
	115	unsigned long irq_rx_path_exit_lpi_mode_n;
	116	unsigned long phy_eee_wakeup_error_n;
c24602ef GC	117	/* Extended RDES status */
	118	unsigned long ip_hdr_err;
	119	unsigned long ip_payload_err;
	120	unsigned long ip_csum_bypassed;
	121	unsigned long ipv4_pkt_rcvd;
	122	unsigned long ipv6_pkt_rcvd;
ee112c12 GC	123	unsigned long no_ptp_rx_msg_type_ext;
	124	unsigned long ptp_rx_msg_type_sync;
	125	unsigned long ptp_rx_msg_type_follow_up;
	126	unsigned long ptp_rx_msg_type_delay_req;
	127	unsigned long ptp_rx_msg_type_delay_resp;
	128	unsigned long ptp_rx_msg_type_pdelay_req;
	129	unsigned long ptp_rx_msg_type_pdelay_resp;
	130	unsigned long ptp_rx_msg_type_pdelay_follow_up;
	131	unsigned long ptp_rx_msg_type_announce;
	132	unsigned long ptp_rx_msg_type_management;
	133	unsigned long ptp_rx_msg_pkt_reserved_type;
c24602ef GC	134	unsigned long ptp_frame_type;
	135	unsigned long ptp_ver;
	136	unsigned long timestamp_dropped;
	137	unsigned long av_pkt_rcvd;
	138	unsigned long av_tagged_pkt_rcvd;
	139	unsigned long vlan_tag_priority_val;
	140	unsigned long l3_filter_match;
	141	unsigned long l4_filter_match;
	142	unsigned long l3_l4_filter_no_match;
0982a0f6 GC	143	/* PCS */
	144	unsigned long irq_pcs_ane_n;
	145	unsigned long irq_pcs_link_n;
	146	unsigned long irq_rgmii_n;
e58bb43f GC	147	unsigned long pcs_link;
	148	unsigned long pcs_duplex;
	149	unsigned long pcs_speed;
2f7a791c GC	150	/* debug register */
	151	unsigned long mtl_tx_status_fifo_full;
	152	unsigned long mtl_tx_fifo_not_empty;
	153	unsigned long mmtl_fifo_ctrl;
	154	unsigned long mtl_tx_fifo_read_ctrl_write;
	155	unsigned long mtl_tx_fifo_read_ctrl_wait;
	156	unsigned long mtl_tx_fifo_read_ctrl_read;
	157	unsigned long mtl_tx_fifo_read_ctrl_idle;
	158	unsigned long mac_tx_in_pause;
	159	unsigned long mac_tx_frame_ctrl_xfer;
	160	unsigned long mac_tx_frame_ctrl_idle;
	161	unsigned long mac_tx_frame_ctrl_wait;
	162	unsigned long mac_tx_frame_ctrl_pause;
	163	unsigned long mac_gmii_tx_proto_engine;
	164	unsigned long mtl_rx_fifo_fill_level_full;
	165	unsigned long mtl_rx_fifo_fill_above_thresh;
	166	unsigned long mtl_rx_fifo_fill_below_thresh;
	167	unsigned long mtl_rx_fifo_fill_level_empty;
	168	unsigned long mtl_rx_fifo_read_ctrl_flush;
	169	unsigned long mtl_rx_fifo_read_ctrl_read_data;
	170	unsigned long mtl_rx_fifo_read_ctrl_status;
	171	unsigned long mtl_rx_fifo_read_ctrl_idle;
	172	unsigned long mtl_rx_fifo_ctrl_active;
	173	unsigned long mac_rx_frame_ctrl_fifo;
	174	unsigned long mac_gmii_rx_proto_engine;
f748be53 AT	175	/* TSO */
	176	unsigned long tx_tso_frames;
	177	unsigned long tx_tso_nfrags;
47dd7a54 GC	178	};
47dd7a54 GC	179
8bf993a5 JA	180	/* Safety Feature statistics exposed by ethtool */
	181	struct stmmac_safety_stats {
	182	unsigned long mac_errors[32];
	183	unsigned long mtl_errors[32];
	184	unsigned long dma_errors[32];
	185	};
	186
	187	/* Number of fields in Safety Stats */
	188	#define STMMAC_SAFETY_FEAT_SIZE \
	189	(sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
	190
cd7201f4 GC	191	/* CSR Frequency Access Defines*/
	192	#define CSR_F_35M 35000000
	193	#define CSR_F_60M 60000000
	194	#define CSR_F_100M 100000000
	195	#define CSR_F_150M 150000000
	196	#define CSR_F_250M 250000000
	197	#define CSR_F_300M 300000000
	198
	199	#define MAC_CSR_H_FRQ_MASK 0x20
	200
aec7ff27	201	#define HASH_TABLE_SIZE 64
f88203a2	202	#define PAUSE_TIME 0xffff
aec7ff27 GC	203
	204	/* Flow Control defines */
	205	#define FLOW_OFF 0
	206	#define FLOW_RX 1
	207	#define FLOW_TX 2
	208	#define FLOW_AUTO (FLOW_TX \| FLOW_RX)
	209
e58bb43f GC	210	/* PCS defines */
	211	#define STMMAC_PCS_RGMII (1 << 0)
	212	#define STMMAC_PCS_SGMII (1 << 1)
	213	#define STMMAC_PCS_TBI (1 << 2)
	214	#define STMMAC_PCS_RTBI (1 << 3)
	215
ceb69499	216	#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
aec7ff27	217
1db123fb	218	/* DAM HW feature register fields */
ceb69499 GC	219	#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
	220	#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
	221	#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
	222	#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
	223	#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
	224	#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
	225	#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
	226	#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
	227	#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
	228	#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
	229	#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
	230	#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
	231	#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
	232	#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
	233	#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
	234	#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
	235	#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
	236	#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
	237	#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
	238	#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
	239	#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
	240	#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
	241	#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
	242	/* Timestamping with Internal System Time */
	243	#define DMA_HW_FEAT_INTTSEN 0x02000000
	244	#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
	245	#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
	246	#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
0f1f88a8	247	#define DEFAULT_DMA_PBL 8
1db123fb	248
70523e63 GC	249	/* PCS status and mask defines */
	250	#define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
	251	#define PCS_LINK_IRQ BIT(1) /* PCS Link */
	252	#define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
	253
62a2ab93 GC	254	/* Max/Min RI Watchdog Timer count value */
	255	#define MAX_DMA_RIWT 0xff
	256	#define MIN_DMA_RIWT 0x20
9125cdd1 GC	257	/* Tx coalesce parameters */
	258	#define STMMAC_COAL_TX_TIMER 40000
	259	#define STMMAC_MAX_COAL_TX_TICK 100000
	260	#define STMMAC_TX_MAX_FRAMES 256
	261	#define STMMAC_TX_FRAMES 64
	262
abe80fdc JP	263	/* Packets types */
	264	enum packets_types {
	265	PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
	266	PACKET_PTPQ = 0x2, /* PTP Packets */
	267	PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
	268	PACKET_UPQ = 0x4, /* Untagged Packets */
	269	PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
	270	};
	271
ceb69499 GC	272	/* Rx IPC status */
ceb69499 GC	273	enum rx_frame_status {
c1fa3212 FG	274	good_frame = 0x0,
	275	discard_frame = 0x1,
	276	csum_none = 0x2,
	277	llc_snap = 0x4,
	278	dma_own = 0x8,
753a7109	279	rx_not_ls = 0x10,
47dd7a54 GC	280	};
47dd7a54 GC	281
c363b658 FG	282	/* Tx status */
	283	enum tx_frame_status {
	284	tx_done = 0x0,
	285	tx_not_ls = 0x1,
	286	tx_err = 0x2,
	287	tx_dma_own = 0x4,
	288	};
	289
9125cdd1 GC	290	enum dma_irq_status {
	291	tx_hard_error = 0x1,
	292	tx_hard_error_bump_tc = 0x2,
	293	handle_rx = 0x4,
	294	handle_tx = 0x8,
aec7ff27	295	};
47dd7a54	296
915c199f	297	/* EEE and LPI defines */
162fb1d6	298	#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
	299	#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
	300	#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
	301	#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
0982a0f6	302
48863ce5	303	#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
d765955d	304
915c199f	305	/* Physical Coding Sublayer */
e58bb43f GC	306	struct rgmii_adv {
	307	unsigned int pause;
	308	unsigned int duplex;
	309	unsigned int lp_pause;
	310	unsigned int lp_duplex;
	311	};
	312
	313	#define STMMAC_PCS_PAUSE 1
	314	#define STMMAC_PCS_ASYM_PAUSE 2
	315
e7434821 GC	316	/* DMA HW capabilities */
	317	struct dma_features {
	318	unsigned int mbps_10_100;
	319	unsigned int mbps_1000;
	320	unsigned int half_duplex;
	321	unsigned int hash_filter;
	322	unsigned int multi_addr;
	323	unsigned int pcs;
	324	unsigned int sma_mdio;
	325	unsigned int pmt_remote_wake_up;
	326	unsigned int pmt_magic_frame;
	327	unsigned int rmon;
ceb69499	328	/* IEEE 1588-2002 */
e7434821	329	unsigned int time_stamp;
ceb69499	330	/* IEEE 1588-2008 */
e7434821 GC	331	unsigned int atime_stamp;
	332	/* 802.3az - Energy-Efficient Ethernet (EEE) */
	333	unsigned int eee;
	334	unsigned int av;
48863ce5	335	unsigned int tsoen;
e7434821 GC	336	/* TX and RX csum */
e7434821 GC	337	unsigned int tx_coe;
48863ce5	338	unsigned int rx_coe;
e7434821 GC	339	unsigned int rx_coe_type1;
	340	unsigned int rx_coe_type2;
	341	unsigned int rxfifo_over_2048;
	342	/* TX and RX number of channels */
	343	unsigned int number_rx_channel;
	344	unsigned int number_tx_channel;
9eb12474	345	/* TX and RX number of queues */
	346	unsigned int number_rx_queues;
	347	unsigned int number_tx_queues;
ceb69499	348	/* Alternate (enhanced) DESC mode */
e7434821	349	unsigned int enh_desc;
11fbf811 TR	350	/* TX and RX FIFO sizes */
	351	unsigned int tx_fifo_size;
	352	unsigned int rx_fifo_size;
8bf993a5 JA	353	/* Automotive Safety Package */
8bf993a5 JA	354	unsigned int asp;
e7434821 GC	355	};
e7434821 GC	356
aec7ff27 GC	357	/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
	358	#define BUF_SIZE_16KiB 16384
	359	#define BUF_SIZE_8KiB 8192
	360	#define BUF_SIZE_4KiB 4096
	361	#define BUF_SIZE_2KiB 2048
47dd7a54	362
aec7ff27 GC	363	/* Power Down and WOL */
	364	#define PMT_NOT_SUPPORTED 0
	365	#define PMT_SUPPORTED 1
47dd7a54	366
aec7ff27 GC	367	/* Common MAC defines */
	368	#define MAC_CTRL_REG 0x00000000 /* MAC Control */
	369	#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
28089222	370	#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
47dd7a54	371
d765955d	372	/* Default LPI timers */
f5351ef7	373	#define STMMAC_DEFAULT_LIT_LS 0x3E8
438a62b1	374	#define STMMAC_DEFAULT_TWT_LS 0x1E
d765955d	375
4a7d666a GC	376	#define STMMAC_CHAIN_MODE 0x1
	377	#define STMMAC_RING_MODE 0x2
	378
2618abb7 VB	379	#define JUMBO_LEN 9000
2618abb7 VB	380
915af656 AS	381	extern const struct stmmac_desc_ops enh_desc_ops;
	382	extern const struct stmmac_desc_ops ndesc_ops;
	383
7ed24bbe VB	384	struct mac_device_info;
7ed24bbe VB	385
915af656	386	extern const struct stmmac_hwtimestamp stmmac_ptp;
48863ce5	387	extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
915af656	388
47dd7a54	389	struct mac_link {
ca84dfb9 LC	390	u32 speed_mask;
	391	u32 speed10;
	392	u32 speed100;
	393	u32 speed1000;
	394	u32 duplex;
47dd7a54 GC	395	};
	396
	397	struct mii_regs {
	398	unsigned int addr; /* MII Address */
	399	unsigned int data; /* MII Data */
b91dce4c LC	400	unsigned int addr_shift; /* MII address shift */
	401	unsigned int reg_shift; /* MII reg shift */
	402	unsigned int addr_mask; /* MII address mask */
	403	unsigned int reg_mask; /* MII reg mask */
	404	unsigned int clk_csr_shift;
	405	unsigned int clk_csr_mask;
47dd7a54 GC	406	};
47dd7a54 GC	407
47dd7a54	408	struct mac_device_info {
ceb69499 GC	409	const struct stmmac_ops *mac;
	410	const struct stmmac_desc_ops *desc;
	411	const struct stmmac_dma_ops *dma;
29896a67	412	const struct stmmac_mode_ops *mode;
891434b1	413	const struct stmmac_hwtimestamp *ptp;
db98a0b0 GC	414	struct mii_regs mii; /* MII register Addresses */
db98a0b0 GC	415	struct mac_link link;
7ed24bbe	416	void __iomem pcsr; / vpointer to device CSRs */
3b57de95 VB	417	int multicast_filter_bins;
	418	int unicast_filter_entries;
	419	int mcast_bits_log2;
d2afb5bd	420	unsigned int rx_csum;
3fe5cadb GC	421	unsigned int pcs;
3fe5cadb GC	422	unsigned int pmt;
02e57b9d	423	unsigned int ps;
47dd7a54 GC	424	};
47dd7a54 GC	425
abe80fdc JP	426	struct stmmac_rx_routing {
	427	u32 reg_mask;
	428	u32 reg_shift;
	429	};
	430
3b57de95	431	struct mac_device_info dwmac1000_setup(void __iomem ioaddr, int mcbins,
c623d149 AT	432	int perfect_uc_entries,
	433	int *synopsys_id);
	434	struct mac_device_info dwmac100_setup(void __iomem ioaddr, int *synopsys_id);
477286b5 AT	435	struct mac_device_info dwmac4_setup(void __iomem ioaddr, int mcbins,
477286b5 AT	436	int perfect_uc_entries, int *synopsys_id);
aec7ff27	437
d6cc64ef JP	438	void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
	439	unsigned int high, unsigned int low);
	440	void stmmac_get_mac_addr(void __iomem ioaddr, unsigned char addr,
	441	unsigned int high, unsigned int low);
d6cc64ef	442	void stmmac_set_mac(void __iomem *ioaddr, bool enable);
bfab27a1	443
477286b5 AT	444	void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
	445	unsigned int high, unsigned int low);
	446	void stmmac_dwmac4_get_mac_addr(void __iomem ioaddr, unsigned char addr,
	447	unsigned int high, unsigned int low);
	448	void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
	449
d6cc64ef	450	void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
70523e63	451
29896a67 GC	452	extern const struct stmmac_mode_ops ring_mode_ops;
29896a67 GC	453	extern const struct stmmac_mode_ops chain_mode_ops;
f748be53	454	extern const struct stmmac_desc_ops dwmac4_desc_ops;
bd4242df	455
c623d149 AT	456	/**
	457	* stmmac_get_synopsys_id - return the SYINID.
	458	* @priv: driver private structure
	459	* Description: this simple function is to decode and return the SYINID
	460	* starting from the HW core register.
	461	*/
	462	static inline u32 stmmac_get_synopsys_id(u32 hwid)
	463	{
	464	/* Check Synopsys Id (not available on old chips) */
	465	if (likely(hwid)) {
	466	u32 uid = ((hwid & 0x0000ff00) >> 8);
	467	u32 synid = (hwid & 0x000000ff);
	468
	469	pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
	470	uid, synid);
	471
	472	return synid;
	473	}
	474	return 0;
	475	}
bd4242df	476	#endif /* __COMMON_H__ */