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net: stmmac: configuration of CBS in case of a TX AVB queue
[linux-2.6-block.git] / drivers / net / ethernet / stmicro / stmmac / common.h
CommitLineData
47dd7a54
GC		 1/*******************************************************************************
2 STMMAC Common Header File
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
47dd7a54
GC		 15 The full GNU General Public License is included in this distribution in
16 the file called "COPYING".
17
18 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
19*******************************************************************************/
20
bd4242df
RK		 21#ifndef __COMMON_H__
22#define __COMMON_H__
23
bfab27a1 24#include <linux/etherdevice.h>
5e33c791 25#include <linux/netdevice.h>
afea0365 26#include <linux/stmmac.h>
bfab27a1
GC		 27#include <linux/phy.h>
28#include <linux/module.h>
12c70f30 29#if IS_ENABLED(CONFIG_VLAN_8021Q)
8f617541
GC		 30#define STMMAC_VLAN_TAG_USED
31#include <linux/if_vlan.h>
32#endif
33
56b106ae 34#include "descs.h"
1c901a46 35#include "mmc.h"
56b106ae 36
62a2ab93
GC		 37/* Synopsys Core versions */
38#define DWMAC_CORE_3_40 0x34
39#define DWMAC_CORE_3_50 0x35
48863ce5
AT		 40#define DWMAC_CORE_4_00 0x40
41#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
62a2ab93 42
22d3efe5 43/* These need to be power of two, and >= 4 */
e3ad57c9
GC		 44#define DMA_TX_SIZE 512
45#define DMA_RX_SIZE 512
46#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
47
56b106ae
GC		 48#undef FRAME_FILTER_DEBUG
49/* #define FRAME_FILTER_DEBUG */
47dd7a54 50
915c199f 51/* Extra statistic and debug information exposed by ethtool */
47dd7a54
GC		 52struct stmmac_extra_stats {
53 /* Transmit errors */
54 unsigned long tx_underflow ____cacheline_aligned;
55 unsigned long tx_carrier;
56 unsigned long tx_losscarrier;
3c20f72f 57 unsigned long vlan_tag;
47dd7a54
GC		 58 unsigned long tx_deferred;
59 unsigned long tx_vlan;
60 unsigned long tx_jabber;
61 unsigned long tx_frame_flushed;
62 unsigned long tx_payload_error;
63 unsigned long tx_ip_header_error;
64 /* Receive errors */
65 unsigned long rx_desc;
3c20f72f
GC		 66 unsigned long sa_filter_fail;
67 unsigned long overflow_error;
68 unsigned long ipc_csum_error;
47dd7a54 69 unsigned long rx_collision;
e0a76606 70 unsigned long rx_crc_errors;
1cc5a735 71 unsigned long dribbling_bit;
1b924032 72 unsigned long rx_length;
47dd7a54
GC		 73 unsigned long rx_mii;
74 unsigned long rx_multicast;
75 unsigned long rx_gmac_overflow;
76 unsigned long rx_watchdog;
77 unsigned long da_rx_filter_fail;
78 unsigned long sa_rx_filter_fail;
79 unsigned long rx_missed_cntr;
80 unsigned long rx_overflow_cntr;
81 unsigned long rx_vlan;
62a2ab93 82 /* Tx/Rx IRQ error info */
47dd7a54
GC		 83 unsigned long tx_undeflow_irq;
84 unsigned long tx_process_stopped_irq;
85 unsigned long tx_jabber_irq;
86 unsigned long rx_overflow_irq;
87 unsigned long rx_buf_unav_irq;
88 unsigned long rx_process_stopped_irq;
89 unsigned long rx_watchdog_irq;
90 unsigned long tx_early_irq;
91 unsigned long fatal_bus_error_irq;
62a2ab93
GC		 92 /* Tx/Rx IRQ Events */
93 unsigned long rx_early_irq;
47dd7a54
GC		 94 unsigned long threshold;
95 unsigned long tx_pkt_n;
96 unsigned long rx_pkt_n;
47dd7a54 97 unsigned long normal_irq_n;
9125cdd1
GC		 98 unsigned long rx_normal_irq_n;
99 unsigned long napi_poll;
100 unsigned long tx_normal_irq_n;
101 unsigned long tx_clean;
0e80bdc9 102 unsigned long tx_set_ic_bit;
62a2ab93
GC		 103 unsigned long irq_receive_pmt_irq_n;
104 /* MMC info */
d765955d
GC		 105 unsigned long mmc_tx_irq_n;
106 unsigned long mmc_rx_irq_n;
107 unsigned long mmc_rx_csum_offload_irq_n;
108 /* EEE */
d765955d
GC		 109 unsigned long irq_tx_path_in_lpi_mode_n;
110 unsigned long irq_tx_path_exit_lpi_mode_n;
111 unsigned long irq_rx_path_in_lpi_mode_n;
112 unsigned long irq_rx_path_exit_lpi_mode_n;
113 unsigned long phy_eee_wakeup_error_n;
c24602ef
GC		 114 /* Extended RDES status */
115 unsigned long ip_hdr_err;
116 unsigned long ip_payload_err;
117 unsigned long ip_csum_bypassed;
118 unsigned long ipv4_pkt_rcvd;
119 unsigned long ipv6_pkt_rcvd;
ee112c12
GC		 120 unsigned long no_ptp_rx_msg_type_ext;
121 unsigned long ptp_rx_msg_type_sync;
122 unsigned long ptp_rx_msg_type_follow_up;
123 unsigned long ptp_rx_msg_type_delay_req;
124 unsigned long ptp_rx_msg_type_delay_resp;
125 unsigned long ptp_rx_msg_type_pdelay_req;
126 unsigned long ptp_rx_msg_type_pdelay_resp;
127 unsigned long ptp_rx_msg_type_pdelay_follow_up;
128 unsigned long ptp_rx_msg_type_announce;
129 unsigned long ptp_rx_msg_type_management;
130 unsigned long ptp_rx_msg_pkt_reserved_type;
c24602ef
GC		 131 unsigned long ptp_frame_type;
132 unsigned long ptp_ver;
133 unsigned long timestamp_dropped;
134 unsigned long av_pkt_rcvd;
135 unsigned long av_tagged_pkt_rcvd;
136 unsigned long vlan_tag_priority_val;
137 unsigned long l3_filter_match;
138 unsigned long l4_filter_match;
139 unsigned long l3_l4_filter_no_match;
0982a0f6
GC		 140 /* PCS */
141 unsigned long irq_pcs_ane_n;
142 unsigned long irq_pcs_link_n;
143 unsigned long irq_rgmii_n;
e58bb43f
GC		 144 unsigned long pcs_link;
145 unsigned long pcs_duplex;
146 unsigned long pcs_speed;
2f7a791c
GC		 147 /* debug register */
148 unsigned long mtl_tx_status_fifo_full;
149 unsigned long mtl_tx_fifo_not_empty;
150 unsigned long mmtl_fifo_ctrl;
151 unsigned long mtl_tx_fifo_read_ctrl_write;
152 unsigned long mtl_tx_fifo_read_ctrl_wait;
153 unsigned long mtl_tx_fifo_read_ctrl_read;
154 unsigned long mtl_tx_fifo_read_ctrl_idle;
155 unsigned long mac_tx_in_pause;
156 unsigned long mac_tx_frame_ctrl_xfer;
157 unsigned long mac_tx_frame_ctrl_idle;
158 unsigned long mac_tx_frame_ctrl_wait;
159 unsigned long mac_tx_frame_ctrl_pause;
160 unsigned long mac_gmii_tx_proto_engine;
161 unsigned long mtl_rx_fifo_fill_level_full;
162 unsigned long mtl_rx_fifo_fill_above_thresh;
163 unsigned long mtl_rx_fifo_fill_below_thresh;
164 unsigned long mtl_rx_fifo_fill_level_empty;
165 unsigned long mtl_rx_fifo_read_ctrl_flush;
166 unsigned long mtl_rx_fifo_read_ctrl_read_data;
167 unsigned long mtl_rx_fifo_read_ctrl_status;
168 unsigned long mtl_rx_fifo_read_ctrl_idle;
169 unsigned long mtl_rx_fifo_ctrl_active;
170 unsigned long mac_rx_frame_ctrl_fifo;
171 unsigned long mac_gmii_rx_proto_engine;
f748be53
AT		 172 /* TSO */
173 unsigned long tx_tso_frames;
174 unsigned long tx_tso_nfrags;
47dd7a54
GC		 175};
176
cd7201f4
GC		 177/* CSR Frequency Access Defines*/
178#define CSR_F_35M 35000000
179#define CSR_F_60M 60000000
180#define CSR_F_100M 100000000
181#define CSR_F_150M 150000000
182#define CSR_F_250M 250000000
183#define CSR_F_300M 300000000
184
185#define MAC_CSR_H_FRQ_MASK 0x20
186
aec7ff27 187#define HASH_TABLE_SIZE 64
f88203a2 188#define PAUSE_TIME 0xffff
aec7ff27
GC		 189
190/* Flow Control defines */
191#define FLOW_OFF 0
192#define FLOW_RX 1
193#define FLOW_TX 2
194#define FLOW_AUTO (FLOW_TX | FLOW_RX)
195
e58bb43f
GC		 196/* PCS defines */
197#define STMMAC_PCS_RGMII (1 << 0)
198#define STMMAC_PCS_SGMII (1 << 1)
199#define STMMAC_PCS_TBI (1 << 2)
200#define STMMAC_PCS_RTBI (1 << 3)
201
ceb69499 202#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
aec7ff27 203
1db123fb 204/* DAM HW feature register fields */
ceb69499
GC		 205#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
206#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
207#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
208#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
209#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
210#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
211#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
212#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
213#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
214#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
215#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
216#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
217#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
218#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
219#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
220#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
221#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
222#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
223#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
224#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
225#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
226#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
227#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
228/* Timestamping with Internal System Time */
229#define DMA_HW_FEAT_INTTSEN 0x02000000
230#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
231#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
232#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
0f1f88a8 233#define DEFAULT_DMA_PBL 8
1db123fb 234
70523e63
GC		 235/* PCS status and mask defines */
236#define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
237#define PCS_LINK_IRQ BIT(1) /* PCS Link */
238#define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
239
62a2ab93
GC		 240/* Max/Min RI Watchdog Timer count value */
241#define MAX_DMA_RIWT 0xff
242#define MIN_DMA_RIWT 0x20
9125cdd1
GC		 243/* Tx coalesce parameters */
244#define STMMAC_COAL_TX_TIMER 40000
245#define STMMAC_MAX_COAL_TX_TICK 100000
246#define STMMAC_TX_MAX_FRAMES 256
247#define STMMAC_TX_FRAMES 64
248
ceb69499
GC		 249/* Rx IPC status */
250enum rx_frame_status {
c1fa3212
FG		 251 good_frame = 0x0,
252 discard_frame = 0x1,
253 csum_none = 0x2,
254 llc_snap = 0x4,
255 dma_own = 0x8,
753a7109 256 rx_not_ls = 0x10,
47dd7a54
GC		 257};
258
c363b658
FG		 259/* Tx status */
260enum tx_frame_status {
261 tx_done = 0x0,
262 tx_not_ls = 0x1,
263 tx_err = 0x2,
264 tx_dma_own = 0x4,
265};
266
9125cdd1
GC		 267enum dma_irq_status {
268 tx_hard_error = 0x1,
269 tx_hard_error_bump_tc = 0x2,
270 handle_rx = 0x4,
271 handle_tx = 0x8,
aec7ff27 272};
47dd7a54 273
915c199f 274/* EEE and LPI defines */
162fb1d6 275#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
276#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
277#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
278#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
0982a0f6 279
48863ce5 280#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
d765955d 281
915c199f 282/* Physical Coding Sublayer */
e58bb43f
GC		 283struct rgmii_adv {
284 unsigned int pause;
285 unsigned int duplex;
286 unsigned int lp_pause;
287 unsigned int lp_duplex;
288};
289
290#define STMMAC_PCS_PAUSE 1
291#define STMMAC_PCS_ASYM_PAUSE 2
292
e7434821
GC		 293/* DMA HW capabilities */
294struct dma_features {
295 unsigned int mbps_10_100;
296 unsigned int mbps_1000;
297 unsigned int half_duplex;
298 unsigned int hash_filter;
299 unsigned int multi_addr;
300 unsigned int pcs;
301 unsigned int sma_mdio;
302 unsigned int pmt_remote_wake_up;
303 unsigned int pmt_magic_frame;
304 unsigned int rmon;
ceb69499 305 /* IEEE 1588-2002 */
e7434821 306 unsigned int time_stamp;
ceb69499 307 /* IEEE 1588-2008 */
e7434821
GC		 308 unsigned int atime_stamp;
309 /* 802.3az - Energy-Efficient Ethernet (EEE) */
310 unsigned int eee;
311 unsigned int av;
48863ce5 312 unsigned int tsoen;
e7434821
GC		 313 /* TX and RX csum */
314 unsigned int tx_coe;
48863ce5 315 unsigned int rx_coe;
e7434821
GC		 316 unsigned int rx_coe_type1;
317 unsigned int rx_coe_type2;
318 unsigned int rxfifo_over_2048;
319 /* TX and RX number of channels */
320 unsigned int number_rx_channel;
321 unsigned int number_tx_channel;
9eb12474 322 /* TX and RX number of queues */
323 unsigned int number_rx_queues;
324 unsigned int number_tx_queues;
ceb69499 325 /* Alternate (enhanced) DESC mode */
e7434821 326 unsigned int enh_desc;
11fbf811
TR		 327 /* TX and RX FIFO sizes */
328 unsigned int tx_fifo_size;
329 unsigned int rx_fifo_size;
e7434821
GC		 330};
331
aec7ff27
GC		 332/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
333#define BUF_SIZE_16KiB 16384
334#define BUF_SIZE_8KiB 8192
335#define BUF_SIZE_4KiB 4096
336#define BUF_SIZE_2KiB 2048
47dd7a54 337
aec7ff27
GC		 338/* Power Down and WOL */
339#define PMT_NOT_SUPPORTED 0
340#define PMT_SUPPORTED 1
47dd7a54 341
aec7ff27
GC		 342/* Common MAC defines */
343#define MAC_CTRL_REG 0x00000000 /* MAC Control */
344#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
28089222 345#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
47dd7a54 346
d765955d 347/* Default LPI timers */
f5351ef7 348#define STMMAC_DEFAULT_LIT_LS 0x3E8
438a62b1 349#define STMMAC_DEFAULT_TWT_LS 0x1E
d765955d 350
4a7d666a
GC		 351#define STMMAC_CHAIN_MODE 0x1
352#define STMMAC_RING_MODE 0x2
353
2618abb7
VB		 354#define JUMBO_LEN 9000
355
915c199f 356/* Descriptors helpers */
db98a0b0
GC		 357struct stmmac_desc_ops {
358 /* DMA RX descriptor ring initialization */
c24602ef
GC		 359 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
360 int end);
db98a0b0 361 /* DMA TX descriptor ring initialization */
c24602ef 362 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
47dd7a54
GC		 363
364 /* Invoked by the xmit function to prepare the tx descriptor */
365 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
be434d50 366 bool csum_flag, int mode, bool tx_own,
0e80bdc9 367 bool ls);
753a7109
AT		 368 void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
369 int len2, bool tx_own, bool ls,
370 unsigned int tcphdrlen,
371 unsigned int tcppayloadlen);
47dd7a54
GC		 372 /* Set/get the owner of the descriptor */
373 void (*set_tx_owner) (struct dma_desc *p);
374 int (*get_tx_owner) (struct dma_desc *p);
47dd7a54 375 /* Clean the tx descriptor as soon as the tx irq is received */
4a7d666a 376 void (*release_tx_desc) (struct dma_desc *p, int mode);
47dd7a54
GC		 377 /* Clear interrupt on tx frame completion. When this bit is
378 * set an interrupt happens as soon as the frame is transmitted */
0e80bdc9 379 void (*set_tx_ic)(struct dma_desc *p);
47dd7a54
GC		 380 /* Last tx segment reports the transmit status */
381 int (*get_tx_ls) (struct dma_desc *p);
382 /* Return the transmit status looking at the TDES1 */
383 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
ad01b7d4 384 struct dma_desc *p, void __iomem *ioaddr);
47dd7a54
GC		 385 /* Get the buffer size from the descriptor */
386 int (*get_tx_len) (struct dma_desc *p);
387 /* Handle extra events on specific interrupts hw dependent */
47dd7a54
GC		 388 void (*set_rx_owner) (struct dma_desc *p);
389 /* Get the receive frame size */
38912bdb 390 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
47dd7a54
GC		 391 /* Return the reception status looking at the RDES1 */
392 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
393 struct dma_desc *p);
c24602ef
GC		 394 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
395 struct dma_extended_desc *p);
891434b1
RK		 396 /* Set tx timestamp enable bit */
397 void (*enable_tx_timestamp) (struct dma_desc *p);
398 /* get tx timestamp status */
399 int (*get_tx_timestamp_status) (struct dma_desc *p);
400 /* get timestamp value */
ceb69499 401 u64(*get_timestamp) (void *desc, u32 ats);
891434b1
RK		 402 /* get rx timestamp status */
403 int (*get_rx_timestamp_status) (void *desc, u32 ats);
d0225e7d
AT		 404 /* Display ring */
405 void (*display_ring)(void *head, unsigned int size, bool rx);
753a7109
AT		 406 /* set MSS via context descriptor */
407 void (*set_mss)(struct dma_desc *p, unsigned int mss);
db98a0b0
GC		 408};
409
915af656
AS		 410extern const struct stmmac_desc_ops enh_desc_ops;
411extern const struct stmmac_desc_ops ndesc_ops;
412
915c199f 413/* Specific DMA helpers */
db98a0b0
GC		 414struct stmmac_dma_ops {
415 /* DMA core initialization */
495db273 416 int (*reset)(void __iomem *ioaddr);
50ca903a
NC		 417 void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
418 u32 dma_tx, u32 dma_rx, int atds);
afea0365
GC		 419 /* Configure the AXI Bus Mode Register */
420 void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
db98a0b0 421 /* Dump DMA registers */
fbf68229 422 void (*dump_regs)(void __iomem *ioaddr, u32 *reg_space);
db98a0b0
GC		 423 /* Set tx/rx threshold in the csr6 register
424 * An invalid value enables the store-and-forward mode */
f88203a2
VB		 425 void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
426 int rxfifosz);
db98a0b0
GC		 427 /* To track extra statistic (if supported) */
428 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
ad01b7d4
GC		 429 void __iomem *ioaddr);
430 void (*enable_dma_transmission) (void __iomem *ioaddr);
431 void (*enable_dma_irq) (void __iomem *ioaddr);
432 void (*disable_dma_irq) (void __iomem *ioaddr);
433 void (*start_tx) (void __iomem *ioaddr);
434 void (*stop_tx) (void __iomem *ioaddr);
435 void (*start_rx) (void __iomem *ioaddr);
436 void (*stop_rx) (void __iomem *ioaddr);
437 int (*dma_interrupt) (void __iomem *ioaddr,
aec7ff27 438 struct stmmac_extra_stats *x);
e7434821 439 /* If supported then get the optional core features */
f10a6a35
AT		 440 void (*get_hw_feature)(void __iomem *ioaddr,
441 struct dma_features *dma_cap);
62a2ab93
GC		 442 /* Program the HW RX Watchdog */
443 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
48863ce5
AT		 444 void (*set_tx_ring_len)(void __iomem *ioaddr, u32 len);
445 void (*set_rx_ring_len)(void __iomem *ioaddr, u32 len);
446 void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
447 void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
448 void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);
db98a0b0
GC		 449};
450
7ed24bbe
VB		 451struct mac_device_info;
452
915c199f 453/* Helpers to program the MAC core */
db98a0b0
GC		 454struct stmmac_ops {
455 /* MAC core initialization */
7ed24bbe 456 void (*core_init)(struct mac_device_info *hw, int mtu);
38912bdb 457 /* Enable and verify that the IPC module is supported */
7ed24bbe 458 int (*rx_ipc)(struct mac_device_info *hw);
9eb12474 459 /* Enable RX Queues */
4f6046f5 460 void (*rx_queue_enable)(struct mac_device_info *hw, u8 mode, u32 queue);
d0a9c9f9
JP		 461 /* Program RX Algorithms */
462 void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);
463 /* Program TX Algorithms */
464 void (*prog_mtl_tx_algorithms)(struct mac_device_info *hw, u32 tx_alg);
6a3a7193
JP		 465 /* Set MTL TX queues weight */
466 void (*set_mtl_tx_queue_weight)(struct mac_device_info *hw,
467 u32 weight, u32 queue);
d43042f4
JP		 468 /* RX MTL queue to RX dma mapping */
469 void (*map_mtl_to_dma)(struct mac_device_info *hw, u32 queue, u32 chan);
19d91873
JP		 470 /* Configure AV Algorithm */
471 void (*config_cbs)(struct mac_device_info *hw, u32 send_slope,
472 u32 idle_slope, u32 high_credit, u32 low_credit,
473 u32 queue);
db98a0b0 474 /* Dump MAC registers */
fbf68229 475 void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);
db98a0b0 476 /* Handle extra events on specific interrupts hw dependent */
7ed24bbe
VB		 477 int (*host_irq_status)(struct mac_device_info *hw,
478 struct stmmac_extra_stats *x);
8f71a88d
JP		 479 /* Handle MTL interrupts */
480 int (*host_mtl_irq_status)(struct mac_device_info *hw, u32 chan);
47dd7a54 481 /* Multicast filter setting */
3b57de95 482 void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
47dd7a54 483 /* Flow control setting */
7ed24bbe 484 void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
29feff39 485 unsigned int fc, unsigned int pause_time, u32 tx_cnt);
47dd7a54 486 /* Set power management mode (e.g. magic frame) */
7ed24bbe 487 void (*pmt)(struct mac_device_info *hw, unsigned long mode);
47dd7a54 488 /* Set/Get Unicast MAC addresses */
7ed24bbe
VB		 489 void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
490 unsigned int reg_n);
491 void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
492 unsigned int reg_n);
b4b7b772 493 void (*set_eee_mode)(struct mac_device_info *hw,
494 bool en_tx_lpi_clockgating);
7ed24bbe
VB		 495 void (*reset_eee_mode)(struct mac_device_info *hw);
496 void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
497 void (*set_eee_pls)(struct mac_device_info *hw, int link);
ad5a87d7
JP		 498 void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x,
499 u32 rx_queues, u32 tx_queues);
70523e63
GC		 500 /* PCS calls */
501 void (*pcs_ctrl_ane)(void __iomem *ioaddr, bool ane, bool srgmi_ral,
502 bool loopback);
503 void (*pcs_rane)(void __iomem *ioaddr, bool restart);
504 void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);
47dd7a54
GC		 505};
506
915c199f 507/* PTP and HW Timer helpers */
891434b1
RK		 508struct stmmac_hwtimestamp {
509 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
ba1ffd74
GC		 510 u32 (*config_sub_second_increment)(void __iomem *ioaddr, u32 ptp_clock,
511 int gmac4);
891434b1 512 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
ceb69499
GC		 513 int (*config_addend) (void __iomem *ioaddr, u32 addend);
514 int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
ba1ffd74 515 int add_sub, int gmac4);
ceb69499 516 u64(*get_systime) (void __iomem *ioaddr);
891434b1
RK		 517};
518
915af656 519extern const struct stmmac_hwtimestamp stmmac_ptp;
48863ce5 520extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
915af656 521
47dd7a54
GC		 522struct mac_link {
523 int port;
524 int duplex;
525 int speed;
526};
527
528struct mii_regs {
529 unsigned int addr; /* MII Address */
530 unsigned int data; /* MII Data */
b91dce4c
LC		 531 unsigned int addr_shift; /* MII address shift */
532 unsigned int reg_shift; /* MII reg shift */
533 unsigned int addr_mask; /* MII address mask */
534 unsigned int reg_mask; /* MII reg mask */
535 unsigned int clk_csr_shift;
536 unsigned int clk_csr_mask;
47dd7a54
GC		 537};
538
915c199f 539/* Helpers to manage the descriptors for chain and ring modes */
29896a67 540struct stmmac_mode_ops {
c24602ef
GC		 541 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
542 unsigned int extend_desc);
4a7d666a 543 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
362b37be 544 int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);
29896a67
GC		 545 int (*set_16kib_bfsize)(int mtu);
546 void (*init_desc3)(struct dma_desc *p);
891434b1
RK		 547 void (*refill_desc3) (void *priv, struct dma_desc *p);
548 void (*clean_desc3) (void *priv, struct dma_desc *p);
4a7d666a
GC		 549};
550
47dd7a54 551struct mac_device_info {
ceb69499
GC		 552 const struct stmmac_ops *mac;
553 const struct stmmac_desc_ops *desc;
554 const struct stmmac_dma_ops *dma;
29896a67 555 const struct stmmac_mode_ops *mode;
891434b1 556 const struct stmmac_hwtimestamp *ptp;
db98a0b0
GC		 557 struct mii_regs mii; /* MII register Addresses */
558 struct mac_link link;
7ed24bbe 559 void __iomem *pcsr; /* vpointer to device CSRs */
3b57de95
VB		 560 int multicast_filter_bins;
561 int unicast_filter_entries;
562 int mcast_bits_log2;
d2afb5bd 563 unsigned int rx_csum;
3fe5cadb
GC		 564 unsigned int pcs;
565 unsigned int pmt;
02e57b9d 566 unsigned int ps;
47dd7a54
GC		 567};
568
3b57de95 569struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
c623d149
AT		 570 int perfect_uc_entries,
571 int *synopsys_id);
572struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id);
477286b5
AT		 573struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
574 int perfect_uc_entries, int *synopsys_id);
aec7ff27 575
d6cc64ef
JP		 576void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
577 unsigned int high, unsigned int low);
578void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
579 unsigned int high, unsigned int low);
d6cc64ef 580void stmmac_set_mac(void __iomem *ioaddr, bool enable);
bfab27a1 581
477286b5
AT		 582void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
583 unsigned int high, unsigned int low);
584void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
585 unsigned int high, unsigned int low);
586void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
587
d6cc64ef 588void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
70523e63 589
29896a67
GC		 590extern const struct stmmac_mode_ops ring_mode_ops;
591extern const struct stmmac_mode_ops chain_mode_ops;
f748be53 592extern const struct stmmac_desc_ops dwmac4_desc_ops;
bd4242df 593
c623d149
AT		 594/**
595 * stmmac_get_synopsys_id - return the SYINID.
596 * @priv: driver private structure
597 * Description: this simple function is to decode and return the SYINID
598 * starting from the HW core register.
599 */
600static inline u32 stmmac_get_synopsys_id(u32 hwid)
601{
602 /* Check Synopsys Id (not available on old chips) */
603 if (likely(hwid)) {
604 u32 uid = ((hwid & 0x0000ff00) >> 8);
605 u32 synid = (hwid & 0x000000ff);
606
607 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
608 uid, synid);
609
610 return synid;
611 }
612 return 0;
613}
bd4242df 614#endif /* __COMMON_H__ */
Linux 6.x block layer and io_uring tree(s)